A method for manufacturing a memory device and a memory device

Abstract

This disclosure provides a method for fabricating a memory device and the memory device itself. The method includes: providing a substrate, the substrate including an array region and a peripheral region located outside the array region; forming a plurality of spaced bit line structures within the array region, the top and sidewalls of the bit line structures having isolation structures, and forming capacitor contact holes between adjacent bit line structures; forming an initial contact layer, the initial contact layer covering the capacitor contact holes, the isolation structures, and the peripheral region; patterning the initial contact layer, and using the patterned initial contact layer as a mask to etch portions of the isolation structures to form air gaps.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a method for manufacturing a memory device and the memory device itself. Background Technology

[0002] Memory typically includes storage capacitors and storage transistors connected to the storage capacitors, which store electrical charges representing stored information. As integration density increases in semiconductor fabrication processes, improving memory integration density has become a trend, leading to an increase in bit line integration density. However, as the spacing between bit lines becomes smaller, the parasitic capacitance between bit lines has a growing impact on device performance. Summary of the Invention

[0003] The disclosure section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This disclosure is not intended to limit the key features and essential technical features of the claimed technical solutions, nor is it intended to determine the scope of protection of the claimed technical solutions.

[0004] To address the shortcomings of existing technologies, this disclosure proposes a method for manufacturing a memory device and a memory device that can reduce process steps and lower parasitic capacitance between adjacent bit lines.

[0005] To overcome the existing problems, this disclosure provides a method for manufacturing a storage device, the method comprising:

[0006] A substrate is provided, the substrate including an array region and a peripheral region located outside the array region;

[0007] Multiple spaced bit line structures are formed within the array region. Isolation structures are formed on the top and sidewalls of the bit line structures, and capacitive contact holes are formed between adjacent bit line structures.

[0008] An initial contact layer is formed, which covers the capacitor contact hole, the isolation structure, and the peripheral area;

[0009] The initial contact layer is patterned, and a portion of the isolation structure is etched using the patterned initial contact layer as a mask to form an air gap.

[0010] In one embodiment of this disclosure, the isolation structure includes a first insulating layer, a second insulating layer, and a sacrificial layer, wherein the sacrificial layer is located between the first insulating layer and the second insulating layer, and has a different etching selectivity than the first insulating layer and the second insulating layer.

[0011] In one embodiment of this disclosure, the first insulating layer and the second insulating layer are made of silicon nitride, and the sacrificial layer is made of silicon oxide.

[0012] In one embodiment of this disclosure, the patterned initial contact layer includes a plurality of opening patterns that expose portions of the isolation structure.

[0013] In one embodiment of this disclosure, a portion of the isolation structure is etched using the patterned initial contact layer as a mask to form an air gap, including etching the sacrificial layer of the isolation structure through the opening pattern to form the air gap between the first insulating layer and the second insulating layer.

[0014] In one embodiment of this disclosure, the opening images are arranged in a hexagonal pattern or in parallel intervals.

[0015] In one embodiment of this disclosure, the angle between the opening pattern and the bit line structure is 10 to 30°, and the length of the opening pattern is 100 nm to 200 nm.

[0016] In one embodiment of this disclosure, the etching is dry etching, and the etching gases are NH3 and HF.

[0017] In one embodiment of this disclosure, the step of forming the initial contact layer includes depositing a first barrier layer, a second barrier layer, and a conductive layer sequentially on the surfaces of the capacitor contact hole, the isolation structure, and the peripheral region.

[0018] In one embodiment of this disclosure, the step of patterning the initial contact layer includes depositing a first photoresist layer on the surface of the initial contact layer, patterning the first photoresist layer, and etching the initial contact layer using the patterned first photoresist layer as a mask to form the opening pattern.

[0019] In one embodiment of this disclosure, the opening pattern is located in the array region.

[0020] In one embodiment of this disclosure, the method further includes forming a landing pad after forming the air gap.

[0021] In one embodiment of this disclosure, the step of forming a landing pad includes depositing a second photoresist layer on the surface of the patterned initial contact layer, patterning the second photoresist layer, and etching the patterned initial contact layer using the patterned second photoresist layer as a mask to form a landing pad.

[0022] In one embodiment of this disclosure, the landing pad includes a barrier layer and a wiring layer.

[0023] According to the method for fabricating the memory device disclosed herein, an initial contact layer is first deposited covering the capacitor structure and the bit line isolation structure, and an opening is formed in the initial contact layer to expose a portion of the isolation structure. An air gap can be etched through this opening, so that the air gap etching is completed in one exposure step before the landing pad etching, reducing the photolithography steps and lowering the process cost. At the same time, since an air gap is formed between adjacent bit line structures, the parasitic capacitance between the bit line structures is reduced.

[0024] In another aspect, this disclosure provides a storage device comprising:

[0025] The substrate includes an array region and a peripheral region located outside the array region. The substrate has a plurality of spaced bit line structures and a plurality of landing pads located in the array region, and a gate structure and a peripheral circuit contact structure located in the peripheral region.

[0026] An isolation structure, at least covering the sidewalls and top of the bit line;

[0027] An air gap structure is located within the isolation structure;

[0028] A gate isolation layer covers at least the peripheral gate sidewalls and top.

[0029] According to the memory device disclosed herein, since an air gap is formed between the bit lines of the included memory device, the dielectric constant between the bit lines is reduced, thereby reducing the parasitic capacitance. Furthermore, the air gap is fabricated using the fabrication method of this application, which reduces the number of process steps and lowers the cost. Attached Figure Description

[0030] The following drawings, which are incorporated herein by reference as part of this disclosure, are provided for understanding the disclosure. The drawings illustrate embodiments of the disclosure and their descriptions, serving to explain the principles of the disclosure.

[0031] Figure 1 A flowchart illustrating the steps of a method for manufacturing a storage device according to an embodiment of the present disclosure is shown.

[0032] Figure 2 This is a cross-sectional view of a device after forming a bit line structure, an isolation structure, and an initial contact layer on a substrate, according to an embodiment of the present disclosure.

[0033] Figure 3 This is a cross-sectional view of a device after a patterned photoresist layer has been formed on an initial contact layer, according to an embodiment of this disclosure.

[0034] Figure 4 This is a cross-sectional view of a device etched using a patterned photoresist layer as a mask, according to an embodiment of this disclosure.

[0035] Figure 5One implementation of an open graphic pattern;

[0036] Figure 6 Another implementation of the open graphic pattern;

[0037] Figure 7 This is a cross-sectional view of a device etched using a patterned initial contact layer as a mask, according to an embodiment of this disclosure.

[0038] Figure 8 This is a cross-sectional view of a device after etching the initial contact to form a landing pad and peripheral circuit contact structure, according to an embodiment of the present disclosure.

[0039] Figure 9 for Figure 8 The pattern shown is of the landing pad and peripheral circuit contact structure after the initial contact layer has been etched.

[0040] Figure 10 This is a cross-sectional view of a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring this disclosure.

[0042] It should be understood that this disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] Currently, in the fabrication of memory devices, the measure used to reduce parasitic capacitance between bit lines is to form air gaps between them. However, the current manufacturing process is quite complicated. For example, before forming the air gap, it involves forming bit line structures, isolation structures, and landing pads. There are many steps between forming the bit line structure and forming the air gap, which is complex, costly, and detrimental to improving yield and performance.

[0047] Based on this, this disclosure provides a method for manufacturing a storage device, such as... Figure 1 As shown, the manufacturing method includes:

[0048] S101: Provides a substrate, the substrate including an array region and a peripheral region located outside the array region;

[0049] S103: Multiple spaced bit line structures are formed within the listed area, and the top and sidewalls of the bit line structures are formed with isolation structures, and capacitor contact holes are formed between adjacent bit line structures.

[0050] S105: Forming an initial contact layer, which covers the capacitor contact hole, the isolation structure, and the peripheral area;

[0051] S107: Patterned initial contact layer, using the patterned initial contact layer as a mask to etch part of the isolation structure to form an air gap.

[0052] According to the method for fabricating the memory device disclosed herein, an initial contact layer is first deposited covering the capacitor structure and the bit line isolation structure, and an opening is formed in the initial contact layer to expose a portion of the isolation structure. An air gap can be etched through this opening, so that the air gap etching is completed in one exposure step before the landing pad etching, reducing the photolithography steps and lowering the process cost. At the same time, since an air gap is formed between adjacent bit line structures, the parasitic capacitance between the bit line structures is reduced.

[0053] To fully understand this disclosure, the technical solution of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0054] S101: Provides a substrate, the substrate including an array region and a peripheral region located outside the array region;

[0055] like Figure 2 As shown, a substrate 200 is provided, which includes at least an array region 200A and a peripheral region 200B located outside the array region 200A. The array region 200A is used to form memory cells, and the peripheral region 200B is used to form peripheral transistors, such as logic control transistors. An isolation region 201 is formed in the substrate 200, thereby dividing the substrate 200 into a plurality of active regions 202.

[0056] The substrate 200 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., without limitation.

[0057] The isolation region 201 can employ a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. The active region 202 of the semiconductor substrate 200 is defined by the isolation region 201.

[0058] S103: Multiple spaced bit line structures are formed in the array area. The top and sidewalls of the bit line structures are formed with isolation structures, and capacitor contact holes are formed between adjacent bit line structures.

[0059] like Figure 2 As shown, multiple spaced bit line structures 203 are formed on the array region 200A. Isolation structures 208 are formed on the top and sidewalls of the bit line structures 203, and capacitor contact holes (not shown in the figure) are formed between adjacent bit line structures 203. A peripheral region gate structure 218 and a peripheral circuit contact structure 220 are formed in the peripheral region 200B. A gate isolation layer 219 is formed on the top of the sidewall of the peripheral region gate structure 218. The structure and composition of the peripheral region gate structure 218 can be formed simultaneously with the bit line structures 203. The gate isolation layer 219 can adopt a NON structure, that is, it includes a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer.

[0060] The capacitor contact hole also includes a capacitor contact plug 212, and the conductive layer 216 is connected to the active region 202 through the capacitor contact plug 212. In some embodiments, the capacitor contact plug 212 may be made of polycrystalline silicon.

[0061] Bit line structure 203 includes contact structure 204, isolation layer 205, metal layer 206, and insulating layer 207. Contact structure 204 may be made of polysilicon and is used to connect metal layer 206 and active region 202. Isolation layer 205 may be made of titanium or titanium nitride and is used to prevent metal diffusion from metal layer 206 to contact structure 204. Metal layer 206 may be made of tungsten or other materials. Insulating layer 207 may be made of silicon nitride or silicon oxynitride and is used to isolate metal layer 206 from conductive layer 216.

[0062] The isolation structure 208 includes a first insulating layer 209, a sacrificial layer 210, and a second insulating layer 211 arranged sequentially from the array region 200A toward the peripheral region 200B, with the sacrificial layer 210 located between the first insulating layer 209 and the second insulating layer 211. The first insulating layer 209 and the second insulating layer 211 have etch selectivity relative to the sacrificial layer 210, meaning that the etch selectivity ratio of the sacrificial layer 210 is different from that of the first insulating layer 209 and the second insulating layer 211. In some embodiments, the first insulating layer 209 and the second insulating layer 211 may be made of silicon nitride, and the sacrificial layer 210 may be made of silicon oxide.

[0063] S105: Forming an initial contact layer, which covers the capacitor contact hole, the isolation structure, and the peripheral area;

[0064] like Figure 2 As shown, an initial contact layer 213 is formed on the substrate 200, which covers the capacitor contact hole, the isolation structure 208 and the peripheral region 200B.

[0065] The initial contact layer 213 includes a first barrier layer 214, a second barrier layer 215, and a conductive layer 216. In some embodiments, the conductive layer 216 is made of tungsten, and the first barrier layer 214 is made of titanium, which improves the interfacial contact performance between the conductive layer 216 and the second barrier layer 215 and prevents structural defects at the interface. The second barrier layer 215 is made of titanium nitride, which prevents the metal of the conductive layer 216 from diffusing to the adjacent bit line structure 203 and the capacitor contact plug 212. Furthermore, the number of layers of the first barrier layer 214 and the second barrier layer 215 can be one or more, which is not limited here.

[0066] The initial contact layer 213 formation step includes: sequentially depositing a first barrier layer 214, a second barrier layer 215 and a conductive layer 216 on the surfaces of the capacitor contact hole, the isolation structure 208 and the peripheral region 200B.

[0067] In some embodiments, a metal silicide layer 217 is also formed between the capacitor contact plug 212 and the initial contact layer 213. Since the resistance of the metal silicide is less than that of polysilicon, the contact resistance of the capacitor can be further reduced by forming a metal silicide above the capacitor contact plug 212. The material of the metal silicide can be titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi2).

[0068] The process structure in the above embodiments can be formed using etching, deposition, or other processes. The etching process can be dry etching or wet etching; specifically, dry etching can be one or more of plasma etching, reactive ion etching, or ion milling. The gas used in dry etching can be one or more of trifluoromethane, carbon tetrafluoride, difluoromethane, hydrobromic acid, chlorine, or sulfur hexafluoride; wet etching can use hot phosphoric acid or hydrofluoric acid as the etching solution. The deposition process can be one or more of chemical vapor deposition, physical vapor deposition, low-temperature chemical vapor deposition, low-pressure chemical vapor deposition, thermal chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, spin coating, or coating processes.

[0069] S107: Patterned initial contact layer, using the patterned initial contact layer as a mask to etch part of the isolation structure to form an air gap.

[0070] In some embodiments, such as Figure 3 As shown, a first photoresist layer (not shown) is deposited on the surface of the initial contact layer 213, and the first photoresist layer is patterned by a photolithography process, which includes operations such as exposure and development. The projection of the opening of the patterned first photoresist layer 221 coincides with the projection of the isolation structure 208 and the capacitor contact hole.

[0071] like Figure 4 As shown, the initial contact layer 213 is etched using the patterned first photoresist layer 221 as a mask, so as to form a pattern in the initial contact layer 213 as shown in the figure. Figure 4 The opening pattern 222 is shown. The etching process used in the above method can be a dry etching process, including but not limited to reactive ion etching, ion beam etching, plasma etching, or laser cutting. In this embodiment, plasma etching is used, and the etching gas includes nitrogen trifluoride (NF3) and chlorine (CL2). After etching is completed, the patterned first photoresist layer 218 is removed. The removal process can be, but is not limited to, using a suitable solvent or an ashing method.

[0072] In some embodiments, the patterned initial contact layer 213 includes a plurality of opening patterns 222 located above the array region 200A and exposing a portion of the isolation structure 208.

[0073] In some embodiments, such as Figure 5 and Figure 6As shown, the arrangement of the opening pattern 222 can be hexagonal or parallel spaced. On the one hand, the initial contact layer 213 can be etched using the existing photomask process, saving costs and improving production efficiency. On the other hand, while ensuring that the formed opening pattern 222 can expose part of the isolation structure 208 and capacitor contact hole, the number of openings can be minimized to save etching time, that is, the complete formation of the air gap can be achieved with a limited number of openings.

[0074] In some embodiments, the length of the opening pattern 222 ranges from 100 nm to 200 nm, the distance between adjacent opening patterns 222 ranges from 100 nm to 200 nm, and the angle between the opening pattern 222 and the bit line structure 203 is 10 to 30°. For example, the distance between the opening patterns can be 150 nm, the spacing can be 155 nm or 160 nm, and the angle between the opening pattern 222 and the bit line structure 203 is 20°. When the length of the opening pattern 222 is greater than 200 nm, the opening pattern 222 will become a continuous pattern, causing over-etching of the isolation structure 208, which will lead to structural defects in the bit line structure 203; if the length is less than 100 nm, the sacrificial layer 210 portion in the isolation structure 208 cannot be completely removed, and thus a complete air gap structure cannot be formed.

[0075] Meanwhile, if the distance between adjacent opening patterns 222 is less than 100 nm, the area etched into the conductive layer 216 will increase, making it impossible to form a complete landing pad 213A in subsequent processes; if the distance is greater than 200 nm, the formation of a complete air gap structure cannot be guaranteed. Furthermore, if the angle between the opening pattern 222 and the bit line structure 203 is less than 10° or greater than 30°, the opening pattern 222 cannot effectively expose the isolation structure 208, thus preventing the formation of a complete air gap structure.

[0076] like Figure 4 and Figure 7 As shown, the patterned initial contact layer 213 is used as a mask to etch a portion of the isolation structure 208 to form an air gap 223. Specifically, the sacrificial layer 210 of the isolation structure 208 can be etched through the opening pattern 222 to form an air gap 223 between the first insulating layer 209 and the second insulating layer 211, thereby reducing the dielectric constant between adjacent bit line structures 203 and thus reducing the parasitic capacitance between the bit line structures.

[0077] In some embodiments, the materials of the first insulating layer 209 and the second insulating layer 211 in the isolation structure 208 may be silicon nitride, and the material of the sacrificial layer 210 may be silicon oxide.

[0078] In some embodiments, the etching process used for the sacrificial layer in the etched isolation structure is dry etching. The dry etching process includes, but is not limited to, reactive ion etching, ion beam etching, plasma etching, or laser cutting. In this embodiment, plasma is used for dry etching at an etching temperature greater than 100°C. The etching gases include NH3 and HF, with flow rates of 50 sccm–500 sccm and 10 sccm–100 sccm, respectively, and pressures of 2 mTorr–50 mTorr for both. Here, sccm represents cubic centimeters per minute, and mTorr represents Howot.

[0079] The etching principle is as follows: reaction: SiO2 + 4HF + 4NH3 → (NH4)2SiF6;

[0080] Dissociation: (NH4)2SiF6 → SiO2 + 4HF + 4NH3;

[0081] In some embodiments, such as Figure 8 and Figure 9 As shown, after the air gap 223 is formed, the patterned initial contact layer 213 is etched to form a landing pad 213A in the array region 200A and a peripheral circuit contact structure 213B in the peripheral region 200B.

[0082] In some embodiments, such as Figure 8 and Figure 9 As shown, a second photoresist layer (not shown) is deposited on the surface of the patterned initial contact layer 213, the second photoresist layer is patterned, and the patterned initial contact layer 213 is etched using the patterned second photoresist layer as a mask to form a landing pad 213A and a peripheral circuit contact structure 213B.

[0083] While forming the landing pad 213A and the peripheral circuit contact structure 213B, an insulating opening 224 is also formed between adjacent landing pads 213A. An insulating material layer can then be filled into this opening to insulate adjacent landing pads 213A from each other. The depth of the insulating opening 224 can be set as needed. It should be understood that the depth of the insulating opening 224 can be consistent with the depth of the opening pattern 222, that is, the etching depth when etching with the patterned first photoresist layer 218 as a mask is consistent with the etching depth when etching the patterned initial contact layer. In some embodiments, the etching process used is dry etching. Etching the patterned initial contact layer 213 can be divided into two steps: main etching and over-etching. In some embodiments, the flow rate ratio of the etching gas NF3 / CL2 used in the main etching process is greater than 1, and the flow rate ratio of the etching gas NF3 / CL2 used in the over-etching process is less than 1, to ensure uniform etching and avoid structural defects in the formed landing pad 213.

[0084] In some embodiments, the landing pad 213A and the peripheral circuit contact structure 213B include a barrier layer (not shown in the figure), which is composed of a portion of a first barrier layer 214, a second barrier layer 215, and a wiring layer (composed of a portion of a conductive layer 216).

[0085] Thus, the process steps implemented according to the method of this disclosure embodiment are completed. It is understood that the storage device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0086] According to the method for fabricating the memory device disclosed herein, an initial contact layer is first deposited covering the capacitor structure and the bit line isolation structure, and an opening is formed in the initial contact layer to expose a portion of the isolation structure. An air gap can be etched through this opening, so that the air gap etching is completed in one exposure step before the landing pad etching, reducing the photolithography steps and lowering the process cost. At the same time, since an air gap is formed between adjacent bit line structures, the parasitic capacitance between the bit line structures is reduced.

[0087] This disclosure also provides a storage device, such as Figure 10 As shown, in some embodiments, the memory device includes: a substrate 300, which includes an array region 300A and a peripheral region 300B located outside the array region 300A. The substrate 300 has a plurality of spaced bit line structures 303 and a plurality of landing pads 313A located in the array region 300A, and a gate structure 318 and a peripheral circuit contact structure 313B located in the peripheral region 300B; an isolation structure 308, which at least covers the sidewalls and top of the bit line structures 303; an air gap structure 310 located within the isolation structure 308; and a gate isolation layer 319, which at least covers the sidewalls and top of the peripheral gate 318.

[0088] The substrate material includes, but is not limited to, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, as well as multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Devices, such as NMOS and / or PMOS, can also be formed on the substrate. Similarly, conductive components can also be formed in the substrate, which can be the gate, source, or drain of a transistor, or a metal interconnect structure electrically connected to the transistor.

[0089] The isolation region 301 can employ a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. The active region 302 of the semiconductor substrate 300 is defined by the isolation region 301.

[0090] The wiring structure 303 includes a contact structure 304, an isolation layer 305, a metal layer 306, and an insulating layer 307. The isolation structure 308 includes a first insulating layer 309 and a second insulating layer 311. The air gap structure 310 is located between the first insulating layer 309 and the second insulating layer 311. The landing pad 313A includes a barrier layer (not shown) and a wiring layer 316 located above the barrier layer. The barrier layer is composed of a first barrier layer 314 and a second barrier layer 315.

[0091] A capacitive contact plug 312 is also formed between adjacent bit line structures 303, and the wiring layer 316 is connected to the active region 302 through the capacitive contact plug 312. In some embodiments, the material of the capacitive contact plug 312 may be polysilicon. A metal silicide layer 317 is also formed between the capacitive contact plug 312 and the landing pad 313A.

[0092] According to the memory device of this embodiment, since an air gap is formed between the bit lines of the included memory device, the dielectric constant between the bit lines is reduced, thereby reducing the parasitic capacitance. Furthermore, the air gap is fabricated using the fabrication method of this application, which reduces the number of process steps and lowers the cost.

[0093] Since the foregoing method embodiments correspond to this embodiment, the relevant technical details mentioned in the foregoing method embodiments remain valid in this embodiment, and the technical effects achievable in the foregoing method embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the method embodiments.

[0094] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A method of fabricating a memory device, comprising: include: A substrate is provided, the substrate including an array region and a peripheral region located outside the array region; Multiple spaced bit line structures are formed within the array region. Isolation structures are formed on the top and sidewalls of the bit line structures, and capacitive contact holes are formed between adjacent bit line structures. An initial contact layer is formed, which covers the capacitor contact hole, the isolation structure, and the peripheral area; The initial contact layer is patterned, and a portion of the isolation structure is etched using the patterned initial contact layer as a mask to form an air gap; The patterned initial contact layer is etched to form a landing pad for the capacitor.

2. The method of producing a memory device according to claim 1, wherein The isolation structure includes a first insulating layer, a second insulating layer, and a sacrificial layer, wherein the sacrificial layer is located between the first insulating layer and the second insulating layer, and has a different etching selectivity than the first insulating layer and the second insulating layer.

3. The method for manufacturing a storage device according to claim 2, characterized in that, The first insulating layer and the second insulating layer are made of silicon nitride, and the sacrificial layer is made of silicon oxide.

4. The method for manufacturing a storage device according to claim 2, characterized in that, The patterned initial contact layer includes multiple opening patterns that expose portions of the isolation structure.

5. The method for manufacturing a storage device according to claim 4, characterized in that, Using the patterned initial contact layer as a mask, a portion of the isolation structure is etched to form an air gap, including etching the sacrificial layer of the isolation structure through the opening pattern to form the air gap between the first insulating layer and the second insulating layer.

6. The method for manufacturing a storage device according to claim 5, characterized in that, The opening pattern is either hexagonal or arranged in parallel intervals.

7. The method for manufacturing a storage device according to claim 6, characterized in that, The angle between the opening pattern and the bit line structure is 10 to 30°, and the length of the opening pattern is 100 nm to 200 nm.

8. The method for manufacturing a storage device according to claim 1, characterized in that, The etching is a dry etching process, and the etching gases are NH3 and HF.

9. The method for manufacturing a storage device according to claim 1, characterized in that, The step of forming the initial contact layer includes depositing a first barrier layer, a second barrier layer, and a conductive layer sequentially on the surfaces of the capacitor contact hole, the isolation structure, and the peripheral area.

10. The method for manufacturing a storage device according to claim 4, characterized in that, The step of patterning the initial contact layer includes depositing a first photoresist layer on the surface of the initial contact layer, patterning the first photoresist layer, and etching the initial contact layer using the patterned first photoresist layer as a mask to form the opening pattern.

11. The method for manufacturing a storage device according to claim 10, characterized in that, The opening pattern is located in the array region.

12. The method for manufacturing a storage device according to claim 1, characterized in that, The step of forming the landing pad includes depositing a second photoresist layer on the surface of the patterned initial contact layer, patterning the second photoresist layer, and etching the patterned initial contact layer using the patterned second photoresist layer as a mask to form the landing pad.

13. The method for manufacturing a storage device according to claim 12, characterized in that, The landing pad includes a barrier layer and a wiring layer.

14. A storage device, characterized in that, The memory is manufactured by the method of any one of claims 1 to 13, comprising: The substrate includes an array region and a peripheral region located outside the array region. The substrate has a plurality of spaced bit line structures and a plurality of landing pads located in the array region, and a gate structure and a peripheral circuit contact structure located in the peripheral region. An isolation structure, at least covering the sidewalls and top of the bit line; An air gap structure is located within the isolation structure; A gate isolation layer covers at least the sidewalls and top of the gate structure.

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