A semiconductor memory device and its fabrication method
By adding a pad layer and a spacer wall to the outside of the bit line contacts of the DRAM, the structural defects caused by over-etching are solved, improving the reliability of the memory device and the stability of the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-04-23
- Publication Date
- 2026-07-03
AI Technical Summary
Existing technologies for increasing the density of dynamic random access memory (DRAM) cells have problems such as structural defects and increased manufacturing process complexity, especially at bit line contacts where excessive etching can easily lead to aperture expansion.
An additional padding layer is provided on the outside of the bit line contact, the opening diameter of the bit line contact is reduced, and a gap wall is provided between the bit line and the padding layer to form a semiconductor memory device with better component reliability.
This effectively avoids structural defects caused by increased memory cell density, improves the component reliability of semiconductor memory devices, and ensures the smooth progress of subsequent manufacturing processes.
Smart Images
Figure CN116761425B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor device technology, and in particular to a semiconductor memory device and a method for manufacturing the same. Background Technology
[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor memory devices must also meet the requirements of high aggregation and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, it has gradually replaced DRAM with only planar gate structures as the current mainstream development trend. Generally, DRAM with a recessed gate structure consists of a large number of memory cells clustered into an array to store information. Each memory cell can be composed of a transistor assembly connected in series with a memory assembly to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies still need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention
[0003] One objective of this invention is to provide a semiconductor memory device and its fabrication method, which involves additionally providing a padding layer on the outside of the bit line contacts to reduce the diameter of the bit line contact opening. Thus, the fabrication method of this invention enables the formation of a semiconductor memory device with improved component reliability, effectively avoiding structural defects that may arise from the continuous increase in memory cell density.
[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor memory device, comprising:
[0005] A substrate, wherein the substrate includes a plurality of active regions and shallow trench isolation between two adjacent active regions;
[0006] Multiple bit lines are arranged on the substrate, spaced apart from each other;
[0007] Bit line contacts are located below the bit line and partially extend into the active region;
[0008] A gap wall is provided on the sidewall of the bit line and the bit line contact;
[0009] A padding layer extends outward from the bit line contact in a direction away from the substrate, wherein the padding layer includes a first portion embedded in the bit line, the first portion being disposed opposite to each other on both sides of the bit line contact in the direction of extension of the bit line.
[0010] Optionally, it further includes: storage node plugs, disposed on each of the active regions and alternately disposed with respect to the bit lines;
[0011] The liner layer includes a second portion disposed between the bit line contact and the storage node plug.
[0012] Optionally, a portion of the gap wall is disposed on the second portion.
[0013] Optionally, the padding layer is isolated from the shallow trench within the substrate.
[0014] Optionally, it also includes:
[0015] A dielectric layer is located between the bit line and the substrate, wherein the pad layer is in contact with the surface of the dielectric layer.
[0016] Optionally, the padding layer is disposed around the bit line contact and includes an insulating material different from that used for shallow trench isolation.
[0017] Optionally, it also includes:
[0018] Multiple word lines are arranged separately within the substrate; and
[0019] Multiple word line isolation layers are disposed on the substrate and corresponding to the word lines, wherein the second portion of the pad layer is located between adjacent word line isolation layers and comprises the same material as the word line isolation layers.
[0020] Optionally, each of the bit lines includes a metal bit line.
[0021] To achieve the above objectives, another embodiment of the present invention provides a semiconductor memory device, comprising:
[0022] A substrate, wherein the substrate includes a plurality of active regions and shallow trench isolation between two adjacent active regions;
[0023] Multiple bit lines are disposed on the substrate, spaced apart from each other. Each bit line includes a conductive layer and a capping layer stacked sequentially from bottom to top, and the top of the capping layer has multiple protrusions.
[0024] Bit line contacts are disposed below the bit line and partially extend into the active region, wherein each of the protrusions is disposed around each of the bit line contacts in a direction perpendicular to the substrate.
[0025] Optionally, it also includes:
[0026] Multiple pad layers extend along the outside of the bit line contacts in a direction away from the substrate;
[0027] Wherein, each of the protrusions overlaps with each of the pad layers in a direction perpendicular to the substrate.
[0028] Optionally, each of the aforementioned padding layers is partially embedded within the positioning line.
[0029] Optionally, it further includes: a gap wall disposed on the sidewall of the bit line and the bit line contact; and a storage node plug disposed on each of the active regions and alternately disposed with the bit line.
[0030] Each of the aforementioned padding layers is sandwiched between the gap wall on the bit line contact and the storage node plug.
[0031] To achieve the above objectives, another embodiment of the present invention provides a method for manufacturing a semiconductor memory device, comprising:
[0032] A substrate is provided, the substrate including a plurality of active regions and shallow trench isolation between two adjacent active regions;
[0033] Multiple bit lines are formed on the substrate, and the bit lines are arranged apart from each other;
[0034] A bit line contact is formed below the bit line, and a portion of the bit line contact extends into the active region;
[0035] A gap wall is formed on the sidewall of the bit line and the bit line contact;
[0036] A pad layer is formed on the substrate, the pad layer extending away from the substrate along the outer side of the bit line contact, wherein the pad layer includes a first portion embedded within the bit line, the first portion being disposed opposite to each other on both sides of the bit line contact along the direction of extension of the bit line; and
[0037] Storage node plugs are formed on each of the active regions, and the storage node plugs and the bit lines are alternately arranged.
[0038] Optionally, the liner layer further includes a second portion formed between the bit line contact and the storage node plug, and a portion of the gap wall is formed on the second portion.
[0039] Optionally, it also includes:
[0040] A dielectric layer is formed on the substrate;
[0041] A sacrificial layer is formed on the dielectric layer, and an opening is formed in the sacrificial layer;
[0042] A padding material layer is formed on the substrate to cover the surfaces of the sacrificial layer and the opening, and,
[0043] Partial removal of the dielectric layer and the substrate, forming a contact opening within the substrate; and
[0044] Partially remove the padding material layer to form the padding layer.
[0045] Optionally, the padding material layer is formed after partially removing the dielectric layer.
[0046] Optionally, the padding material layer is formed before partially removing the dielectric layer.
[0047] Optionally, it also includes:
[0048] A dielectric material layer is formed on the substrate and filled between each bit line;
[0049] Partial removal of the dielectric material layer forms multiple plug openings, exposing each of the active regions; and
[0050] The storage node plug is formed within each of the plug openings.
[0051] Optionally, the liner material layer includes a second portion formed between the bit line contact and the storage node plug;
[0052] Forming a pad layer on the substrate includes:
[0053] When forming the plug opening, the second portion of the liner layer formed between the bit line contact and the storage node plug is removed to obtain the liner layer;
[0054] The liner layer comprises the same material as the shallow trench isolation.
[0055] Optionally, it also includes:
[0056] Multiple word lines are formed within the substrate; and
[0057] A plurality of word line isolation layers are formed on the substrate, each corresponding to a word line, wherein the second portion of the pad layer is formed between adjacent word line isolation layers and includes the same material as the word line isolation layers. Attached Figure Description
[0058] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.
[0059] Figures 1 to 16 The diagram illustrates the structure of a semiconductor memory device during its fabrication process according to a first embodiment of the present invention, wherein:
[0060] Figure 1 This is a top view of a semiconductor memory device after the mask structure has been formed.
[0061] Figure 2 for Figure 1 A cross-sectional view along tangent A-A';
[0062] Figure 3 This is a schematic cross-sectional view of a semiconductor memory device after the formation of a pad material layer.
[0063] Figure 4 This is a top view of a semiconductor memory device after the contact openings have been formed.
[0064] Figure 5 for Figure 4 A cross-sectional view along tangent A-A';
[0065] Figure 6 This is a cross-sectional view of a semiconductor memory device after bit line contacts have been formed.
[0066] Figure 7 This is a top view of a semiconductor memory device after the capping layer has been formed.
[0067] Figure 8 for Figure 7 A cross-sectional view along tangent A-A';
[0068] Figure 9 for Figure 7 A schematic cross-sectional view along the tangent B-B';
[0069] Figure 10 This is a top view of a semiconductor memory device after bit lines have been formed.
[0070] Figure 11 for Figure 10 A cross-sectional view along tangent A-A';
[0071] Figure 12 For Figure 10 A schematic cross-sectional view along the tangent B-B';
[0072] Figure 13 This is a top view of a semiconductor memory device after the spacer walls have been formed.
[0073] Figure 14 for Figure 13 A cross-sectional view along tangent A-A';
[0074] Figure 15 This is a top view of a semiconductor memory device after contact formation; and
[0075] Figure 16 for Figure 15 A cross-sectional view along tangent A-A';
[0076] Figures 17 to 18 The diagram illustrates the structure of a semiconductor memory device during its fabrication process according to a second embodiment of the present invention, wherein:
[0077] Figure 17 This is a top view of a semiconductor memory device after contact formation; and
[0078] Figure 18 for Figure 17 A cross-sectional view along tangent A-A';
[0079] Figure 19 The diagram shown is a cross-sectional structural schematic of a semiconductor memory device during the fabrication process according to a third embodiment of the present invention.
[0080] The reference numerals in the attached figures are explained as follows:
[0081] 100 / 200 / 300 - Semiconductor memory device; 110 - Substrate; 112 - Shallow trench isolation; 114 - Active region; 120 - Gate structure; 130 - Dielectric layer; 132 - Oxide layer; 134 / 136 - Nitride layer; 138 - Bottom semiconductor layer; 140 - Mask structure; 142 - Sacrificial layer; 144 - Silicon-containing hard mask layer; 146 - Patterned photoresist layer; 148 - Pattern; 150 / 350 - Opening; 150a - Contact opening; 152 / 352 - Gasket material layer; 154 / 254 - Gasket layer; 154a - First part; 154b - Second part; 160 - Bit line; 161 - Bit line contact; 162 - Semiconductor layer; 164 - Barrier layer; 166 - Conductive layer; 168 - Cap layer; 168a - Protrusion; 170 - Spacer wall; 172 - Memory node plug; D1 - First direction; x / y - Direction. Detailed Implementation
[0082] To enable those skilled in the art to further understand the embodiments of the present invention, preferred embodiments of the present invention are described below in conjunction with the accompanying drawings, detailing the composition and desired effects of the embodiments. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments to complete other embodiments without departing from the spirit of the present invention.
[0083] Please refer to the following first. Figures 1 to 16 The illustration is a structural diagram of the semiconductor memory device 100 during the fabrication process in the first embodiment of the present invention, wherein... Figure 1 , Figure 4 , Figure 7 , Figure 10 , Figure 13 and Figure 15 This is a top view of the semiconductor memory device 100 during its fabrication process, while the other figures are cross-sectional views of the semiconductor memory device 100 during its fabrication process. Figure 1 and Figure 2 As shown, the semiconductor memory device 100 includes, for example, a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator (SOI) substrate. At least one shallow trench isolation (STI) 112 is provided within the substrate 110 to define a plurality of active areas 114 on the substrate 110. That is, the shallow trench isolation 112 surrounds the active areas 114 and is disposed outside the active areas 114.
[0084] In detail, the active regions 114 extend parallel to each other and spaced apart toward the first direction D1, and have the same length (not shown) in the first direction D1, so as to present a specific arrangement as a whole, for example, Figure 1The array arrangement shown is an example, but not limited to. In one embodiment, the active region 114 can be formed using, but is not limited to, the following fabrication process. First, a bulk silicon substrate (not shown) is provided, and a mask layer (not shown) is formed on the bulk substrate. The mask layer includes a pattern that can be used to define the active region 114. The bulk substrate is partially covered by the mask layer and an etching process is performed to partially remove the bulk substrate to form the active region 114 and at least one shallow trench (not shown) surrounding the active region 114. Then, an insulating material (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, is filled into the shallow trench to form a shallow trench isolation 112. Thus, the fabrication of the substrate 110 is completed, and the shallow trench isolation 112 with its top surface flush with the surface of the substrate 110 and the active region 114 are formed within the substrate 110. In another embodiment, a patterned mask (not shown) defining the active region 114 can be formed using a self-aligned double patterning (SADP) fabrication process or a self-aligned reverse patterning (SARP) fabrication process, but is not limited thereto.
[0085] For example Figure 1As shown, the semiconductor memory device 100 also includes a plurality of buried gate structures 120 embedded in the substrate 110. The gate structures 120 extend parallel to each other in the y-direction and intersect with the active region 114 and the shallow trench isolation 112. In detail, each gate structure 120 includes a dielectric layer (not shown), a gate dielectric layer (not shown), a gate (not shown), and a capping layer (not shown) stacked sequentially from bottom to top. The surface of the capping layer is flush with the top surface of the substrate 110, so that the gate structure 120 can serve as a plurality of buried word lines (WL) of the semiconductor memory device 100 to switch transistor components (not shown) formed in the substrate 110 in subsequent fabrication processes to receive voltage signals from memory cells (not shown) formed in subsequent fabrication processes. In one embodiment, the gate structure 120 may be formed by, but is not limited to, the following fabrication process: First, a plurality of trenches (not shown) are formed in the substrate 110. Then, a dielectric layer covering the entire surface of the trench, a gate dielectric material layer (not shown), and a gate layer filling the trench are sequentially formed in each of the trenches. After the gate layer and the gate dielectric material layer are etched back, a gate dielectric layer covering the lower half surface of each of the trenches and a gate filling the lower half of each of the trenches are formed. Then, a capping layer filling the upper half of the trenches is formed.
[0086] In addition, such as Figure 2 As shown, the semiconductor memory device 100 also includes a dielectric layer 130 disposed on the substrate 110, directly covering each of the word lines (i.e., the gate structure 120). Figure 2 The top surface (not shown). In one embodiment, the dielectric layer 130 preferably has a composite layer structure, such as comprising an oxide layer 132-nitride layer 134-oxide layer 136 (oxide-nitride-oxide, ONO) structure stacked sequentially from bottom to top, but not limited thereto. Then, a bottom semiconductor layer 138 and a mask structure 140 are sequentially formed on the substrate 110 to form within the substrate 110... Figures 4 to 6The multiple contact openings 150a are shown. In detail, the mask structure 140 includes, for example, a sacrificial layer (e.g., containing an organic dielectric material) 142, a silicon-containing hard mask (SBH) layer 144, and a patterned photoresist layer 146 sequentially stacked above the dielectric layer 130, wherein the patterned photoresist layer 146 has at least one pattern 148 that can be used to define at least one contact opening 150a. In one embodiment, the bottom semiconductor layer 138 includes, for example, a semiconductor material, preferably including a material with a significant etch selectivity to the sacrificial layer 142, such as doped polycrystalline silicon, doped amorphous silicon, or other silicon-containing materials, but is not limited thereto.
[0087] Then, an etching process is performed on the patterned photoresist layer 146 to sequentially transfer the pattern 148 of the patterned photoresist layer 146 into the underlying silicon-containing hard mask layer 144, sacrificial layer 142, bottom semiconductor layer 138, and dielectric layer 130, forming a pattern as shown below. Figure 3 The multiple openings 150 shown are respectively aligned with each active region 114. Furthermore, after the openings 150 are formed, the patterned photoresist layer 146 and the silicon-containing hard mask layer 144 are completely removed. Then, as shown... Figure 3 As shown, a pad material layer 152 is formed on the substrate 110, conformally covering the remaining sacrificial layer 142, the bottom semiconductor layer 138, and the exposed surfaces of the opening 150. In one embodiment, the pad material layer 152 comprises, for example, a material such as silicon oxide or silicon oxynitride, preferably a material similar to, but not limited to, the shallow trench isolation 112. In another embodiment, the pad material layer 152 may also be selected to comprise an insulating material different from that of the shallow trench isolation 112, such as silicon nitride or silicon carbonitride.
[0088] Perform another etching process, through, for example Figure 3 The outline of the opening 150 shown is etched downwards into the pad material layer 152 and a portion of the substrate 110 to form a plurality of contact openings 150a, as shown. Figure 4 and Figure 5 As shown. Simultaneously, the sacrificial layer 142, whose material is adjacent to the pad material layer 152, is also removed in the other etching process, exposing the underlying bottom semiconductor layer 138. Each contact opening 150a is formed, for example, between adjacent two word lines (i.e., gate structure 120), such that a portion of each active region 114 (i.e., substrate 110) is exposed from the bottom of each contact opening 150a. It should be noted that in the other etching process, the material covering the top surface of the sacrificial layer 142 and the substrate layer 138 are completely removed. Figure 3The padding material layer 152 on the bottom surface of the opening 150 is shown, and the padding material layer 152 covering the sidewalls of the opening 150 is partially removed to form a plurality of padding layers 154. Thus, the padding layers 154 are formed directly on the substrate 110 and cover the opposite sidewalls of each contact opening 150a, wherein the lower half of the sidewall of the padding layer 154 is partially covered by the bottom semiconductor layer 138, while the upper half of the sidewall of the padding layer 154 is completely exposed. In other words, each padding layer 154 is formed as shown in the figure. Figure 4 In the top view shown, the padding layer 154 is arranged around the sidewall of each contact opening 150a. Therefore, the diameter of each contact opening 150a can be effectively controlled by the padding layer 154, avoiding problems such as widening caused by over-etching in the aforementioned etching process.
[0089] like Figure 6 As shown, bit line contacts (BLCs) 161 are formed within each contact opening 150a. The top surface of the bit line contact 161 is lower than the top surface of the pad layer 154, and preferably flush with the top surface of the bottom semiconductor layer 138, but is not limited thereto. In other embodiments, bit line contacts (not shown) with top surfaces lower than or higher than the top surface of the bottom semiconductor layer 138 may be selectively formed, depending on the actual device requirements. The bit line contact 161 may include conductive materials such as silicon-phosphorus (SiP), preferably including phosphorus with a high doping concentration, but is not limited thereto. The bit line contact 161 can be formed by, but is not limited to, the following fabrication process: First, a chemical vapor deposition (CVD) fabrication process is performed to form a conductive material layer (e.g., a conductive material including silicon phosphate) in the contact opening 150a, at least filling the contact opening 150a. Then, an etching process, such as a dry etching process, is performed to partially remove the conductive material layer to the position where the contact opening 150a is partially filled, so as to serve as the bit line contact 161.
[0090] like Figures 7 to 9 As shown, a semiconductor layer 162 (e.g., containing polysilicon, doped silicon, doped phosphorus, or silicon-phosphorus materials), a barrier layer 164 (e.g., containing titanium and / or titanium nitride), a conductive layer 166 (e.g., containing low-resistivity metals such as tungsten, aluminum, or copper), and a capping layer 168 (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride) are sequentially formed on a substrate 110, covering the bottom semiconductor layer 138, the pad layer 154, and the bit line contacts 161. A portion of the semiconductor layer 162 can fill the contact openings 150a. It should be noted that because a pad layer 154 protruding from the surface of the substrate 110 is additionally provided around each contact opening 150a, the semiconductor layer 162, barrier layer 164, conductive layer 166, and capping layer 168, which are sequentially stacked above the pad layer 154, also form corresponding protrusions. This results in multiple upwardly protruding protrusions 168a forming on the top surface of the capping layer 168. Figure 7 The top view shown presents a ring-like shape, for example. Furthermore, the protrusions 168a are aligned with the pad layers 154 in the direction perpendicular to the substrate 110 to surround each contact opening 150a, as shown... Figures 8 to 9 As shown.
[0091] like Figures 10 to 12 As shown, a patterning fabrication process is performed, in which a bottom semiconductor layer 138, a semiconductor layer 162, a barrier layer 164, a conductive layer 166, and a capping layer 168 are sequentially stacked above the dielectric layer 130, forming multiple bit lines 160. These bit lines extend parallel to each other and spaced apart along the x-direction, intersecting with the active region 114 and the gate structure 120, respectively. Some of the bit lines 160 have bit line contacts 161 below them, which can extend into and directly contact portions of the active region 114, thereby electrically connecting to the transistor assembly formed within the substrate 110 to receive or transmit voltage signals from the memory cells formed in subsequent fabrication processes.
[0092] It should be noted that when forming the bit line 160, the first portion 154a of the pad layer 154 is partially buried within the bottom semiconductor layer 138 of the bit line 160 and partially buried within the semiconductor layer 162 of the bit line 160, such that the first portion 154a is located between the bit line contact 161 and the bit line 160 in the direction of extension of the bit line 160 (i.e., the x-direction), and is positioned above each active region 114 in the direction perpendicular to the substrate 110, as shown below. Figure 10 and Figure 12 As shown. On the other hand, the second portion 154b of the pad layer 154 is exposed after the patterned bottom semiconductor layer 138, semiconductor layer 162, barrier layer 164, conductive layer 166 and capping layer 168, such that the second portion 154b is positioned on the sidewall of each bit line 160 in the direction perpendicular to the bit line 160 (i.e., the y-direction), and does not directly contact the sidewall of the bit line 160 but instead forms a gap (not shown) between them, such as... Figure 10 and Figure 11 As shown. Furthermore, the second portion 154b is positioned above the shallow trench isolation 112 in a direction perpendicular to the substrate 110. In embodiments where the pad layer 154 and the shallow trench isolation 112 are made of the same material, the second portion 154b can be considered as an extension of the shallow trench isolation 112 extending onto the surface of the substrate 110, but is not limited thereto.
[0093] Then, as Figure 13 and Figure 14 As shown, a deposition and etch-back fabrication process is performed to form spacer walls 170 on the sidewalls of bit lines 160, bit line contacts 161, and the second portion 154b. These spacer walls may be made of materials such as silicon oxide, silicon nitride, silicon oxynitride, or carbonitride. The spacer walls 170 may selectively have the following characteristics: Figure 14The single-layer structure shown may be a composite layer structure (not shown), which may include, for example, a first spacer wall (not shown, containing silicon nitride), a second spacer wall (not shown, containing silicon oxide), and a third spacer wall (not shown, containing silicon nitride) sequentially stacked on the sidewalls of each bit line 160, but is not limited thereto. It should be noted that in this embodiment, the spacer wall 170 preferably fills the gap between each bit line 160 and the second portion 154b, but is not limited thereto. In another embodiment, the operating conditions of the deposition and etch-back fabrication process may be adjusted such that the spacer wall 170 partially fills the gap between each bit line 160 and the second portion 154b to form a void (not shown), or does not fill the gap between each bit line 160 and the second portion 154b to form an air gap (not shown), to further electrically isolate the bit lines 160 from conductive components subsequently formed between adjacent bit lines 160. On the other hand, the first portion 154a of the pad layer 154 is still partially embedded in the bottom semiconductor layer 138 of the bit line 160, and partially embedded in the semiconductor layer 162 of the bit line 160, as described above. Figure 12 As shown.
[0094] Subsequently, such as Figure 15 and Figure 16 As shown, multiple contacts 172 are formed on the substrate 110, alternately disposed with bit lines 160, and the contacts 172 and bit lines 160 are electrically isolated from each other by spacers 170 disposed therebetween. Each contact 172 passes through a dielectric layer 130 and directly contacts each active region 114 within the substrate 110, serving as a storage node contact. In one embodiment, the contacts 172 may include, for example, a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, but are not limited thereto. Furthermore, the contacts 172 can be formed using, but are not limited to, the following fabrication process: First, a dielectric material layer (not shown, for example, including silicon oxide, silicon oxynitride, etc.) is filled between the bit lines 160. Next, using another mask layer (not shown) formed on the substrate 110, the dielectric material layer and dielectric layer 130 are partially removed to form a plurality of plug openings (not shown) between each bit line, exposing the two ends of each active region 114 within the substrate 110. Then, a deposition process and an etch-back process are performed sequentially to form contacts 172 extending into each plug opening, such that the top surface of each contact 172 can be flush with the top surface of each bit line 160 and the spacer wall 172, but is not limited thereto.
[0095] It should be noted that in this embodiment, when the plug opening is formed, the second portion 154b of the liner layer 154 and the gap wall 170 covering it are not additionally etched, so that after the contact 172 is formed, the second portion 154b of the liner layer 154 is sandwiched between each contact 172 and each line 160 in the y direction. Figure 16 As shown. On the other hand, the first portion 154a of the pad layer 154 is still partially buried within the bottom semiconductor layer 138 of the bit line 160, and partially buried within the semiconductor layer 162 of the bit line 160, as described above. Figure 12 As shown. In another embodiment, the contact 172 can also be fabricated using a self-aligned double patterning process or a self-aligned reverse patterning process, but is not limited thereto. Furthermore, it should be noted that in this embodiment, before the plug opening is formed, multiple word line isolation layers (not shown, but including materials such as silicon nitride and silicon carbonitride) can be formed on the substrate 110, corresponding to the word lines (i.e., gate structure 120) within the substrate 110, such that the second portion 154b of the pad layer 154 is positioned between adjacent word line isolation layers in the x-direction. In one embodiment, the word line isolation layer may include, for example, the same material as the pad layer 154, but is not limited thereto.
[0096] Thus, the fabrication of the semiconductor memory device 100 in the first embodiment of the present invention is completed. According to the fabrication method of this embodiment, additionally, as... Figure 5 A padding layer 154 is provided on the sidewall of the contact opening 150a, reducing the diameter of the contact opening 150a to improve problems such as the diameter expansion of the contact opening 150a caused by over-etching. Furthermore, since the bit line 160 and the bit line contact 161 are formed after the padding layer 154 is formed, at least a portion (i.e., the first portion 154a) of the padding layer 154 is embedded within the bit line 160, effectively protecting the bit line contact 161 when patterning the bit line 160. Specifically, as described above... Figure 12 As shown, the first portion 154a embedded in the bit line 160 is located between the bit line contact 161 and the bit line 160 in the direction of extension of the bit line 160 (i.e., the x-direction), and as previously mentioned... Figure 16As shown, the pad layer 154 also includes a second portion 154b, which is exposed after the patterned bit line 160 and is positioned between the bit line 160 and the contact 172 in the direction perpendicular to the bit line 160 (i.e., the y-direction). Thus, the fabrication method of this embodiment allows for the continued formation of memory components in subsequent fabrication processes, and the memory components and the transistor components together constitute a dynamic random access memory (DRAM) device, but this is not a limitation. The semiconductor memory device of this embodiment has components such as the bit line contact 161 with good structural reliability, which can effectively avoid structural defects that may arise from the continuous increase in memory cell density formed in subsequent fabrication processes.
[0097] However, those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor memory devices and their fabrication processes of the present invention may have other forms or be achieved by other means, and are not limited to the foregoing. For example, in one embodiment, bit line 160 may also optionally include a metal bit line. Other embodiments or variations of the semiconductor memory devices and their fabrication processes in the present invention will be further described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same points. Furthermore, the same components in the embodiments of the present invention are designated by the same reference numerals to facilitate comparison between the embodiments.
[0098] Please refer to Figures 17 to 18 As shown, it illustrates a structural schematic diagram of the semiconductor memory device 200 during the fabrication process in the second embodiment of the present invention, wherein, Figure 17 This is a top view schematic diagram of the semiconductor memory device 200 during its fabrication process. Figure 18 This is a cross-sectional schematic diagram of the semiconductor memory device 200 during its fabrication process. The initial steps of this embodiment are largely the same as those of the first embodiment described above, such as... Figures 1 to 16 As shown, it will not be described again here. The main difference between the manufacturing process of this embodiment and the first embodiment is that the padding layer 254 in this embodiment only includes the first part 154a embedded in each line 160.
[0099] In detail, such as Figures 17 to 18 As shown, when forming contact 172 in this embodiment, the second portion 154b (as described in the previous embodiment) is removed along with the dielectric material layer and dielectric layer 130 during partial removal. Figures 10 to 11As shown in the figure, the spacer wall 170 covering it forms a plurality of plug openings (not shown). On the other hand, the first portion 154a is still partially embedded in the bottom semiconductor layer 138 of the bit line 160 and partially embedded in the semiconductor layer 162 of the bit line 160, as in the aforementioned embodiment. Figure 12 As shown. Thus, only a gap wall 170 is provided between each of the plug openings and each position line 160, and similarly, after the contact 172 is formed, only a gap wall 170 is provided between each contact 172 and each position line 160, as... Figure 18 As shown.
[0100] Thus, the fabrication of the semiconductor memory device 200 in the second embodiment of the present invention is completed. According to the fabrication method of this embodiment, although the pad layer 254 only includes the first portion 154a embedded within each bit line 160, it can still be reduced in size as... Figure 5 The aperture of the contact opening 150a shown improves the problem of aperture expansion of the contact opening 150a caused by over-etching, while effectively protecting the bit line contacts 161 when patterning the bit lines 160. Thus, the fabrication method of this embodiment can still form memory components in subsequent fabrication processes, and the memory components and the transistor components together form a dynamic random access memory device, but this is not a limitation. The semiconductor memory device 200 of this embodiment also has components such as the bit line contacts 161 with good structural reliability, which can effectively avoid structural defects that may arise from the continuous increase in memory cell density formed in subsequent fabrication processes.
[0101] Please refer to Figure 19 The diagram illustrates a cross-sectional view of the semiconductor memory device during fabrication in the third embodiment of the present invention. The steps of this embodiment are largely the same as those of the first embodiment described above, and the similarities will not be repeated here. The main difference between the fabrication process of this embodiment and the first embodiment is that the pad layer (not shown) in this embodiment is formed on the surface of the dielectric layer 130, and does not directly contact the shallow trench isolation 112 within the substrate 110.
[0102] In detail, such as Figure 19 As shown, this embodiment, through, as Figure 1 and Figure 2 When the patterned photoresist layer 146 shown is subjected to the etching process, the pattern 148 of the patterned photoresist layer 146 is sequentially transferred into the underlying silicon-containing hard mask layer 144, sacrificial layer 142, and bottom semiconductor layer 138 to form a pattern as shown. Figure 19 The multiple openings 350 shown are respectively aligned with each active region 114. Furthermore, after the openings 350 are formed, the patterned photoresist layer 146 and the silicon-containing hard mask layer 144 are completely removed. Then, as shown... Figure 19As shown, a pad material layer 352 is formed on the substrate 110, conformally covering the remaining sacrificial layer 142, the bottom semiconductor layer 138, and the exposed surface of the opening 350. Under this operation, subsequent fabrication processes (as described in the first embodiment above) are performed... Figures 4 to 16 The various manufacturing processes shown can form the pad layer that directly contacts the surface of the dielectric layer 130, and it is also provided as described above. Figure 6 The outer side of the bit line contact 161 shown, wherein the pad layer may simultaneously include the first portion 154a and the second portion 154b as described in the first embodiment above, or may only include the first portion 154a as described in the second embodiment above.
[0103] Thus, the fabrication of the semiconductor memory device 300 in the third embodiment of the present invention is completed. According to the fabrication method of this embodiment, although the pad layer is disposed on the dielectric layer 130, it can still be reduced in size as shown in the figure. Figure 5 The diameter of the contact opening 150a shown improves the problem of the increased diameter of the contact opening 150a caused by over-etching, while also... Figures 10 to 12 The patterned bit line 160 effectively protects the bit line contacts 161. The fabrication method of this embodiment allows for the continued formation of memory components in subsequent fabrication processes, and the memory components and transistor components together constitute a dynamic random access memory device, but this is not a limitation. The semiconductor memory device 300 of this embodiment also has components such as the bit line contacts 161 with good structural reliability, effectively avoiding structural defects that may arise from the continuous increase in memory cell density formed in subsequent fabrication processes.
[0104] Overall, the fabrication method of this embodiment of the invention additionally provides a padding layer on the sidewall of the contact opening to reduce the diameter of the contact opening, thereby improving problems such as the increase in the diameter of the contact opening caused by excessive etching. Furthermore, since the bit lines and bit line contacts are formed after the padding layer is formed, the padding layer effectively protects the bit line contacts when the bit lines are patterned. Thus, the fabrication method of this embodiment of the invention can form a semiconductor memory device with better component reliability, resulting in bit line contacts with optimized structural reliability, effectively avoiding structural defects that may arise from the continuous increase in memory cell density formed in subsequent fabrication processes.
[0105] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A semiconductor memory device, characterized in that, include: A substrate, wherein the substrate includes a plurality of active regions and shallow trench isolation between two adjacent active regions; Multiple bit lines are arranged on the substrate, extending along the x-direction and spaced apart from each other along the y-direction, wherein the x-direction is perpendicular to the y-direction; Multiple word lines extend along the y-direction and are arranged in the substrate with spacing between them along the x-direction; Bit line contacts are disposed below the bit lines and partially extend into the active region, and the bit line contacts are disposed between adjacent word lines; A gap wall is provided on the sidewall of the bit line and the bit line contact; A pad layer extends outward from the bit line contact in a direction away from the substrate, wherein the pad layer includes a first portion embedded in the bit line, the first portion being disposed opposite to each other on both sides of the bit line contact along the x-direction, the first portion being located between the bit line contact and the word line.
2. The semiconductor memory device according to claim 1, characterized in that, It also includes: storage node plugs, which are disposed on each of the active regions and alternately disposed with respect to the bit lines; The liner layer includes a second portion disposed between the bit line contact and the storage node plug.
3. The semiconductor memory device according to claim 2, characterized in that, The gap wall is partially disposed on the second part.
4. The semiconductor memory device according to claim 1, characterized in that, The padding layer is in isolated contact with the shallow trench in the substrate.
5. The semiconductor memory device according to claim 1, characterized in that, Also includes: A dielectric layer is located between the bit line and the substrate, wherein the pad layer is in contact with the surface of the dielectric layer.
6. The semiconductor memory device according to claim 2, characterized in that, The padding layer is disposed around the bit line contact and includes an insulating material different from that of the shallow trench isolation.
7. The semiconductor memory device according to claim 6, characterized in that, Also includes: Multiple character lines are arranged in the substrate, spaced apart from each other; as well as Multiple word line isolation layers are disposed on the substrate and corresponding to the word lines, wherein the second portion of the pad layer is located between adjacent word line isolation layers and comprises the same material as the word line isolation layers.
8. The semiconductor memory device according to claim 1, characterized in that, Each of the bit lines mentioned includes a metal bit line.
9. A method for manufacturing a semiconductor memory device, characterized in that, include: A substrate is provided, the substrate including a plurality of active regions and shallow trench isolation between two adjacent active regions; Multiple word lines are formed within the substrate, the word lines extending along the y-direction and arranged to be spaced apart from each other along the x-direction; Multiple bit lines are formed on the substrate, the bit lines extending along the x-direction and arranged separately from each other along the y-direction, the x-direction being perpendicular to the y-direction; A bit line contact is formed below the bit line, and a portion of the bit line contact extends into the active region; A gap wall is formed on the sidewall of the bit line and the bit line contact; A pad layer is formed on the substrate, the pad layer extending away from the substrate along the outside of the bit line contact, wherein the pad layer includes a first portion embedded in the bit line, the first portion being disposed opposite to the bit line contact along the x-direction; as well as Storage node plugs are formed on each of the active regions, and the storage node plugs and the bit lines are alternately arranged.
10. A method for manufacturing a semiconductor memory device according to claim 9, characterized in that, The liner layer also includes a second portion formed between the bit line contact and the storage node plug, and a portion of the gap wall is formed on the second portion.
11. A method for manufacturing a semiconductor memory device according to claim 9, characterized in that, Also includes: A dielectric layer is formed on the substrate; A sacrificial layer is formed on the dielectric layer, and an opening is formed in the sacrificial layer; A pad material layer is formed on the substrate to cover the surface of the sacrificial layer and the opening, and the dielectric layer and the substrate are partially removed to form a contact opening within the substrate; as well as Partially remove the padding material layer to form the padding layer.
12. A method for manufacturing a semiconductor memory device according to claim 11, characterized in that, The padding material layer is formed after the dielectric layer is partially removed.
13. A method for manufacturing a semiconductor memory device according to claim 11, characterized in that, The padding material layer is formed before the dielectric layer is partially removed.
14. A method for manufacturing a semiconductor memory device according to claim 11, characterized in that, Also includes: A dielectric material layer is formed on the substrate and filled between each bit line; Partial removal of the dielectric material layer forms multiple plug openings, exposing each of the active regions; as well as The storage node plug is formed within each of the plug openings.
15. A method for manufacturing a semiconductor memory device according to claim 14, characterized in that, The liner material layer includes a second portion formed between the bit line contact and the storage node plug; Forming a pad layer on the substrate includes: When forming the plug opening, the second portion of the liner layer formed between the bit line contact and the storage node plug is removed to obtain the liner layer; The liner layer comprises the same material as the shallow trench isolation.
16. A method for manufacturing a semiconductor memory device according to claim 10, characterized in that, Also includes: Multiple word line isolation layers are formed on the substrate, each corresponding to a word line, wherein the second portion of the pad layer is formed between adjacent word line isolation layers and includes the same material as the word line isolation layers.