Small single-pulse radar signal processing system based on single-chip platform

Abstract

The application provides a small single-pulse radar signal processing system based on a single-chip platform, which is integrated on a single chip, adopts an integrated scheme of waveform generation+antenna control+signal collection+signal processing, and concentrates small phased array antenna signal generation and the like into completion in the single chip, completes single-pulse radar signal fixed-point and floating-point operation based on a ZYNQ-7000 series chip, completes signal collection and fixed-point operation tasks by an FPGA in the chip, and an ARM core completes system control and floating-point data processing tasks, so that the real-time requirement and the processing precision requirement of signal processing can be met at the same time, and the problems of complex structure, high power consumption, high cost, difficulty in miniaturization and integration and the like of existing single-pulse radar signal processing and control components are effectively solved.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically relating to a small single-pulse radar signal processing system based on a single-chip platform. Background Technology

[0002] A monopulse radar is a type of precision tracking radar. With each pulse emitted, the antenna simultaneously forms several beams. By comparing the amplitude and phase of the echo signals from each beam, when the target is on the antenna axis, the amplitude and phase of the echo signals from each beam are equal, resulting in zero signal difference. When the target is not on the antenna axis, the amplitude and phase of the echo signals from each beam are unequal, generating a signal difference that drives the antenna to turn towards the target until the antenna axis is aligned with the target. This allows the measurement of the target's elevation and azimuth angles. The sum of the signals received from each beam can be used to determine the target's distance, enabling both distance measurement and angle tracking.

[0003] Existing monopulse radar systems typically employ a cascaded FPGA+DSP (FPGA: Field Programmable Gate Array; DSP: Digital Signal Processor) architecture to complete signal acquisition and processing tasks. Generally, the design uses an FPGA chip for signal acquisition and fixed-point computation, and a DSP chip for floating-point computation and system control.

[0004] In summary, the existing technology has the following drawbacks:

[0005] a) Existing monopulse radars use a multi-chip architecture to complete signal processing and antenna control tasks. Their structure is complex, power consumption is high, reliability is low, and they are difficult to miniaturize and integrate.

[0006] b) When using a multi-chip architecture, data transmission between chips relies on hardware links, which results in high software development and maintenance costs. Once the hardware design is completed, the adjustability is limited, and the flexibility is greatly reduced.

[0007] c) When existing multi-chip architectures are applied to small monopulse radars, they cannot fully utilize their computing power, resulting in losses in various aspects, including cost, size, and power consumption. Summary of the Invention

[0008] To address the aforementioned problems in the prior art, this invention provides a small-scale monopulse radar signal processing system based on a single-chip platform. The technical problem to be solved by this invention is achieved through the following technical solution:

[0009] This invention provides a small monopulse radar signal processing system based on a single-chip platform. The system is integrated onto a single chip and communicates with a phased array antenna and an ADC acquisition unit via I / O ports. The system includes:

[0010] The waveform generation module is used to generate intermediate frequency linear frequency modulated signals of two waveforms and transmit them to the phased array antenna.

[0011] The signal acquisition module is used to receive three serial data outputs from the ADC acquisition unit and convert the three serial data into parallel data.

[0012] The serial data is obtained by the ADC acquisition unit by acquiring the intermediate frequency linear frequency modulated signals of the sum path, azimuth difference path, and elevation difference path output by the phased array antenna;

[0013] The antenna control module is used to generate timing waveforms to control the transmit and receive timing of the phased array antenna and to generate phase-shift codes to control the beam direction of the phased array antenna.

[0014] The signal processing module is used to complete the fixed-point processing and floating-point processing of the parallel data converted by the signal acquisition module;

[0015] Beneficial effects:

[0016] (1) The present invention adopts an integrated solution of waveform generation + antenna control + signal acquisition + signal processing, which integrates the signal generation process of small phased array antenna into a single chip. Based on the ZYNQ-7000 series chip, the fixed-point and floating-point operations of the single pulse radar signal are completed. The FPGA in the chip completes the signal acquisition and fixed-point operation tasks, and the ARM core completes the system control and floating-point data processing tasks. It can simultaneously meet the real-time requirements and processing accuracy requirements of signal processing, and effectively solves the problems of complex structure, high power consumption, high cost, and difficulty in miniaturization and integration of existing single pulse radar signal processing and control components.

[0017] (2) The present invention uses a single chip for signal acquisition and processing, and uses the standard interface inside the chip for data transmission and interaction. The interface functions and rates can be flexibly configured by software, which effectively avoids the problems of reliability and maintainability of data transmission links between chips.

[0018] (3) This invention provides an overall plan and specific implementation of the single-pulse radar signal processing flow. For key points in the implementation process, it proposes using asynchronous FIFO to perform multi-bit data across clock domains and designs different data interaction schemes between PL and PS.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a small monopulse radar signal processing system based on a single-chip platform provided by the present invention;

[0021] Figure 2 This is a schematic diagram of the working process of the waveform generation module provided by the present invention;

[0022] Figure 3 This is a schematic diagram of the dual-line ADC output timing provided by the present invention;

[0023] Figure 4 This is a schematic diagram of the ADC data composition provided by the present invention;

[0024] Figure 5 This is a schematic diagram of the workflow of the timing control module provided by the present invention;

[0025] Figure 6 This is a schematic diagram of the output waveform of the timing control module provided by the present invention;

[0026] Figure 7 This is a schematic diagram of the working process of the beam direction control module provided by the present invention;

[0027] Figure 8 This is a schematic diagram of the signal processing flow provided by the present invention;

[0028] Figure 9 This is a schematic diagram of the two-dimensional time-domain data matrix provided by the present invention;

[0029] Figure 10 This is a schematic diagram of the reference unit and protection unit provided by the present invention;

[0030] Figure 11 This is a schematic diagram of the state transition provided by the present invention;

[0031] Figure 12 This is a schematic diagram of the overall workflow provided by the present invention. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0033] This invention provides a small monopulse radar signal processing system based on a single-chip platform. The system is integrated onto a single chip and communicates with a phased array antenna and an ADC acquisition unit via I / O ports. The single chip is a ZYNQ-7000 series chip, divided into a PL (Programmable Logic) section and a PS (Processing System) section. The PL and PS sections utilize custom IP and exchange control parameters via a GP (General Pointer Interface); signal data exchange is completed through HP (Hypertext Transfer Interface), DDR (DDR Memory), and AMBA (Automatic Bus Interface).

[0034] The PS section includes a system control module and a signal processing floating-point arithmetic module. The functions of the waveform generation module, signal acquisition module, antenna control module, and signal processing fixed-point arithmetic module are implemented by the PL section.

[0035] This invention utilizes the ZYNQ-7000 series chip to process small-scale monopulse radar signals. The ZYNQ-7000 series chip is divided into a PL (programmable logic) section and a PS (processor system), interconnected via an AXI (Advanced Extensible Interface) bus. The PL section consists of a Xilinx 7-series FPGA, programmable via a hardware description language. The PS section includes an APU (Application Processing Unit), peripheral interfaces, cache memory, memory interfaces, interconnect interfaces, and a clock generation circuit. The APU consists of two ARM cores and an associated computing unit. The PS section primarily handles interface control and floating-point operations, and is programmable via software.

[0036] refer to Figure 1 As shown, this invention completes waveform generation, signal acquisition, antenna control, and signal processing for a small monopulse radar based on a single chip. The small monopulse radar signal processing system based on the single-chip platform includes:

[0037] The waveform generation module is used to generate intermediate frequency linear frequency modulated signals of two waveforms and transmit them to the phased array antenna.

[0038] The waveform generation module mainly generates intermediate frequency linear frequency modulation signals. This function is a fixed timing process. In this invention, the waveform generation is completed at the PL end.

[0039] The signal acquisition module is used to receive three serial data outputs from the ADC acquisition unit and convert the three serial data into parallel data.

[0040] The signal acquisition module mainly converts the three serial data output by the ADC (Analog to Digital Converter) chip into parallel data used in signal processing. This is also a fixed-timing process and is completed at the PL terminal.

[0041] The serial data is obtained by the ADC acquisition unit by acquiring the intermediate frequency linear frequency modulated signals of the sum path, azimuth difference path, and elevation difference path output by the phased array antenna;

[0042] The antenna control module is used to generate timing waveforms to control the transmit and receive timing of the phased array antenna and to generate phase-shift codes to control the beam direction of the phased array antenna.

[0043] The antenna control module is mainly divided into a transmit / receive timing control module and a beam direction control module. The transmit / receive timing control module outputs timing waveforms at specific IO (Input / Output) ports on the PL terminal according to preset parameters to control the transmit / receive timing of the phased array antenna. The beam direction control module calculates the phase shift code corresponding to the beam angle sent from the PS terminal according to the phase shift code calculation rules defined for the phased array antenna, and outputs it to the antenna phase shifter through specific IO ports on the PL terminal to complete the beam direction control of the phased array antenna. The antenna control module is set on the PL terminal.

[0044] The signal processing module is used to complete the fixed-point processing and floating-point processing of the parallel data converted by the signal acquisition module;

[0045] The fixed-point processing and floating-point processing are implemented by different parts of a single chip.

[0046] The signal processing module consists of two parts: a fixed-point data processing module and a floating-point data processing module. The fixed-point data processing module mainly performs tasks such as digital down-conversion and pulse compression of the parallel data output by the signal acquisition module. This operation processes fixed-point data, with a simple processing flow, logic, and fixed timing, and is completed at the PL end. The floating-point data processing module mainly performs target detection, target association, target tracking, state transition, and system control. It processes floating-point data, has a larger computational load, and more complex logic, so the floating-point data processing module is executed at the PS end.

[0047] Furthermore, since the PL is responsible for generating some control data and control waveforms, such as phase-shift codes and timing waveforms, while the PS is responsible for outputting the beam direction, transmit / receive timing definitions, waveform parameters, and other control parameters required by the PL to complete the overall system control, there is data interaction between the PL and PS. Considering that signal processing is performed at the PL end (fixed-point arithmetic) and the PS end (floating-point arithmetic), data interaction between the PL and PS also needs to be implemented. Therefore, the data interaction between the PL and PS includes two parts: control parameter interaction and signal data interaction. The control parameters have a fixed format and small data volume; therefore, this invention uses a custom IP to complete the control parameter interaction through the GP (General Purpose AXI Ports) interface between the PL and PS. However, the signal data volume is larger; therefore, this invention uses the higher-speed HP (High Performance AXI Ports) interface, DDR (Double Data Rate) synchronous dynamic random access memory, and AMBA (Advanced Microcontroller Bus Architecture) bus interface to complete the signal data interaction.

[0048] This invention utilizes a single chip to complete the entire single-pulse signal processing flow, resulting in higher integration, significantly reduced costs, and the ability to meet the signal processing requirements of small-scale single-pulse radar. Furthermore, this invention employs a standard on-chip interface, leading to higher reliability, higher development efficiency, and enhanced maintainability.

[0049] Based on the chip structure and the above description, the module setup and functional division of the present invention are shown in the figure below. The data output by the ADC includes three channels: sum, pitch difference, and azimuth difference. Unless otherwise specified, the signal processing mentioned below uses the same processing method for the three channels.

[0050] Combination Figure 1 as well as Figure 2 The system control module in the PS section transmits waveform parameters to the waveform generation module in the PL section through the GP interface;

[0051] The transmitted waveform parameters include waveform timing parameters and waveform selection parameters. The waveform timing parameters include pulse trigger time and pulse repetition frequency.

[0052] The waveform generation module is used to read the pre-stored waveform file from the ROM according to the address based on the waveform timing parameters and waveform selection parameters, generate intermediate frequency linear frequency modulation signals of two predetermined timing and waveforms, and output the intermediate frequency linear frequency modulation signals to the phased array antenna through the IO interface.

[0053] According to the actual needs of the present invention, the waveform generation module generates two waveforms, and their parameters are shown in the table below:

[0054] Table 1 Waveform parameters generated by this invention

[0055] waveform 1µs linear frequency modulation signal 10µs linear frequency modulation signal bandwidth 10MHz 10MHz Time width 1us 10us Repetition frequency 10kHz 10kHz amplitude Quantified to 8192 Quantified to 8192 clock frequency 320MHz 320MHz

[0056] The two waveforms differ only in duration. This invention uses the generation of a 10µs linear frequency modulated signal as an example to illustrate the waveform generation method of this invention.

[0057] The workflow of the waveform generation module is as follows: Figure 2 As shown, the waveform generation module in this invention uses a clock frequency of 320MHz, which contains 3200 sampling points within a 10µs time period. First, MATLAB (Matrix Laboratory, a mathematical analysis tool) is used to simulate and generate the 10µs linear frequency modulated signal shown in the table above, setting the sampling rate to 320MHz and the amplitude to 1. Then, the simulated signal with an amplitude of 1 is quantized according to the quantization rules. In this invention, the output waveform is represented by a 14-bit signed number. Therefore, the waveform data is quantized using 1 sign bit and 13 decimal bits, and the quantization result is stored as a .coe file according to a specific format defined by Xilinx. The .coe file is stored in a specific ROM (Read-Only Memory). After responding to the waveform output command, the waveform generation module reads the .coe file from the ROM in address order and outputs the ROM output result to the phased array antenna through the I / O interface, completing the waveform generation function.

[0058] Each of the three serial data streams consists of 14 bits. The frame clock FCLK is synchronized with each complete 14-bit data stream, and the bit clock DCLK is synchronized with each bit.

[0059] The signal acquisition module converts the serial data output by the ADC into parallel data. Each bit of data output by the ADC consists of 14 bits, including 1 sign bit and 13 data bits. The 14-bit data is transmitted to the PL using a two-wire serial method, and its timing is as follows: Figure 3 As shown.

[0060] FCLK is the frame clock, synchronized with each 14-bit complete data segment, while DCLK is the bit clock, synchronized with each bit. A single complete data segment can be represented as follows: Figure 4 As shown, the signal acquisition module converts serial data into... under the drive of the FCLK clock. Figure 4 The parallel data shown is output sequentially to subsequent processing flows.

[0061] refer to Figures 5 to 7The antenna control module includes: a transmit / receive timing control module and a beam direction control module;

[0062] The transmit / receive timing control module is used to generate transmit / receive timing waveforms based on the timing parameters output by the system control module, and output them to the phased array antenna through the corresponding IO port of the PL section to control the transmit / receive timing of the phased array antenna.

[0063] The beam direction control module is used to calculate the phase shift code corresponding to the beam angle sent by the PS part according to the phase shift code calculation rules defined by the phase array antenna, and output it to the antenna phase shifter through the IO port of the PL part to control the beam direction control of the phase array antenna.

[0064] The timing parameters output by the system control module include the rising and falling edge times of the T timing, R timing, TRPLUS timing, and LFM timing.

[0065] The transmit / receive timing waveforms include: T timing, R timing, TRPLUS timing, and LFM timing, which are output to the phased array antenna through the corresponding IO ports; the transmit / receive timing waveforms are active at high level.

[0066] The beam direction control module is used to calculate the ROM address based on the beam direction parameters sent by the PS, and read the phase shift code at the corresponding position of the ROM according to the ROM address; then it outputs the code to the phased array antenna through IO.

[0067] The antenna transmit / receive timing waveforms include T timing, R timing, TRPLUS timing, and LFM timing, which are output to the phased array antenna at the corresponding I / O ports. These are active high. The transmit / receive timing period is fixed in this invention; therefore, the timing parameters output by the system control module only need to include the rising and falling edge times of the waveform. The timing control module can obtain the low-level timing of the high-level waveform by parsing these parameters. The timing control module operates at a clock frequency of 50MHz, and includes 5000 rising edges within one pulse repetition period. A schematic diagram of the output waveform of the timing control module is shown below. Figure 6 As shown.

[0068] Where Clock is the clock frequency of 50MHz, PRT represents the pulse repetition period of 100us, and its count value under Clock drive is in a period of 5000, with a value range of [0,4999]. The rise and fall times of the waveforms below are all based on this count value. The phased array antenna adopts a transmit and receive separation mechanism, and the T waveform and R waveform are not high at the same time. In the figure above, t1 represents the high level duration of the T waveform, t2 represents the low level duration of the R waveform, t3 represents the high level duration of the TRPLUS waveform, and t4 represents the high level duration of the LFM waveform. Their numerical relationship is: t2>t3>t1>t4. Taking a 10us linear frequency modulation signal as the intermediate frequency signal output as an example, the count values ​​corresponding to the level change edges on both sides are: T, [120,630]; R, [112,636]; TRPLUS, [116,633]; LFM, [125,625].

[0069] refer to Figure 7 The beam direction control module uses a lookup table method to calculate the phase shift code. The phase shift code is pre-stored as a .coe file in the ROM. The ROM address is calculated based on the beam direction parameters sent by the PS. The phase shift code at the corresponding position in the ROM is read out and output to the phased array antenna through IO.

[0070] Combination Figure 8 as well as Figure 12 The signal processing module is the core of this invention, mainly comprising two modules: a fixed-point data processing module and a floating-point data processing module. The fixed-point data processing module performs digital down-conversion and pulse compression of the parallel data output from the signal acquisition module at the PL terminal. The floating-point data processing module performs target detection, target association, target tracking, state transitions, and system control at the PS terminal. The main workflow of the signal processing module is described below. Figure 8 The overall workflow is as follows Figure 12 As shown.

[0071] The fixed-point data processing module is used to process the parallel data output by the signal acquisition module in the PL section to complete the fixed-point processing process, specifically including:

[0072] S11, the digital down-conversion module in the fixed-point data processing module mixes the intermediate frequency signal to obtain I and Q data, and then performs low-pass filtering to remove high-frequency components to obtain the original baseband echo data;

[0073] The intermediate frequency signal is acquired by the ADC from the phased array antenna. This intermediate frequency signal is input to the signal acquisition module at the PL terminal, and the signal acquisition module converts the serial data into parallel data.

[0074] S12 performs frequency domain pulse compression on the original baseband echo data;

[0075] S13, the pulse compression results of multiple pulses are accumulated to form a two-dimensional time domain matrix;

[0076] It is worth noting that: the intermediate frequency (IF) data sampled by the ADC is first input to the signal acquisition module at the PL end. The signal acquisition module converts the serial data into parallel data and then outputs it to the digital down-conversion module. The digital down-conversion module mixes the IF signal to obtain I and Q data, then performs low-pass filtering to remove high-frequency components, obtaining the original baseband echo data. Next, frequency domain pulse compression is performed on the baseband data. First, the data undergoes FFT (Fast Fourier Transform) to obtain frequency domain data, then multiplies it by a frequency domain reference function, and finally performs IFFT (Inverse Fast Fourier Transform) to obtain the pulse-compressed data. At this point, the fixed-point data processing process at the PL end is complete. This invention performs target detection after accumulating several pulses, such as... Figure 9 As shown, the pulse compression results of several pulses form a two-dimensional time-domain matrix.

[0077] The floating-point data processing module is used to complete the floating-point processing process based on parallel data in the PS section, specifically including:

[0078] S21, Target detection is performed based on the pulse compression data;

[0079] S21 includes:

[0080] S211, arrange the time-domain pulse data in the two-dimensional time-domain matrix continuously according to the frequency dimension, and perform frequency-dimensional FFT to obtain two-dimensional time-frequency domain data;

[0081] S212, calculate the amplitude mean value in the two-dimensional time-frequency domain to obtain the basis noise;

[0082] S213, traverse the entire two-dimensional time-frequency domain data matrix, record the coordinate information of matrix elements with amplitudes greater than the first threshold, identify suspected targets, and then calculate the average amplitude of noise within the reference cell before and after the suspected target, as the noise amplitude.

[0083] S214, calculate the signal-to-noise ratio of the target amplitude to the noise amplitude. If the signal-to-noise ratio is greater than the second threshold and the suspected target is a local maximum, then the suspected target is determined to be the final target.

[0084] S215 sorts the target information of the final target in descending order of magnitude and stores it in DDR.

[0085] It is worth noting that this invention performs range-dimensional target detection in the two-dimensional time-frequency domain of the signal. Since the pulse-compressed data is time-domain data, the time-domain pulse data is first arranged continuously according to the frequency dimension, and a frequency-dimensional FFT is performed to obtain two-dimensional time-frequency domain data. Then, the average amplitude of the two-dimensional time-frequency domain is calculated to obtain the basis noise. A first threshold is determined based on the basis noise, and a second threshold is set empirically. The first threshold is the amplitude threshold. The entire two-dimensional time-frequency data matrix is ​​traversed, and the coordinate information of matrix elements with amplitudes greater than the first threshold is recorded to identify suspected targets. Then, the average amplitude of the noise within the reference cells before and after the suspected target is calculated as the noise amplitude. The reference cells are defined as follows: Figure 10 As shown,

[0086] exist Figure 10 In the matrix, T represents the range gate position of the suspected target. The protection unit is divided into an upper protection unit and a lower protection unit; these units are set up to reduce the impact of target sidebands on noise calculation. The reference unit is divided into an upper reference unit and a lower reference unit. The second threshold is the signal-to-noise ratio (SNR) threshold. The amplitude of the suspected target is used as the signal amplitude, and its SNR is calculated relative to the mean of the reference units, i.e., the noise amplitude. If the SNR is greater than the second threshold, and the suspected target is a local maximum, then the suspected target is considered the final target. This invention protects elements at the boundaries, calculating only their single-sided reference units or discarding them directly. The suspected targets in the matrix are traversed to obtain all final target information. The target information mainly includes the target's range gate position, frequency gate position, amplitude, and SNR. The target information is sorted in descending order of amplitude and stored in DDR.

[0087] S22, perform target association based on target information;

[0088] S22 includes:

[0089] S221, Select the three largest targets in amplitude in the current frame and the previous two frames as the associated objects, and traverse all target combinations between different frames;

[0090] S222, when the absolute value of the distance threshold difference between the target in the previous two frames and the target in the current frame is less than the absolute difference threshold, calculate and store the sum of the distance threshold differences between the target in the previous two frames and the target in the current frame, as well as the target sequence number information.

[0091] S223, repeat S221 to S222 until the traversal is complete, and take the target with the smallest sum of association differences as the valid association result;

[0092] S224, record the current frame target sequence number of the valid association result.

[0093] It's worth noting that target association is performed after obtaining target information. The target association module calculates the correlation between the target in the current frame and the targets in the previous two frames, treating targets that meet the association requirements as the same target. Specifically, it selects the three largest amplitude targets in the current frame and the previous two frames as association objects, traversing all target combinations across different frames. When the absolute value of the distance threshold difference between the targets in the previous two frames and the target in the current frame is less than a set threshold, it calculates and stores the sum of the distance threshold differences between the targets in the previous two frames and the target in the current frame, along with the target sequence number. After completing the traversal, the target with the smallest sum of correlation differences is taken as the association result, and the target sequence number in the current frame from the association result is used as input to the target tracking module for target information calculation. At this point, the association result is valid. If no target meets the requirements, the association is considered to have failed, the association result is invalid, and target tracking is not performed.

[0094] S23, target tracking is performed based on target association, and state transitions and system control are performed based on the tracking results.

[0095] S23 of the present invention includes:

[0096] S231, calculate the angle difference, velocity, and distance of the target corresponding to the target sequence number in the current frame recorded in S224;

[0097] S232 tracks based on angle difference, speed, and distance;

[0098] The target tracking module primarily calculates target information and tracks target distance and angle. This target information mainly includes the target's angular error, velocity, and distance. The target angular error is calculated using the following formula:

[0099]

[0100]

[0101] in, These represent the azimuth and elevation errors, respectively, which are determined based on the antenna array; (λ1, λ2) are the slope parameters of the angle error and angle determined based on the antenna pattern; (T1, T2) are the time constants, which are related to the frame period; (E ΣI E ΣQ (E) represents the I and Q information of the target in the path; AI E AQ (E) represents the azimuth difference I and Q information corresponding to the target; PI E PQ () represents the pitch difference I and Q information corresponding to the target.

[0102] The formula for calculating the target speed is:

[0103]

[0104] Where PRF is the pulse repetition period, I dop λ is the target frequency dimension index, λ is the wavelength, and PLSNUM is the number of pulses.

[0105] The formula for calculating the target distance is:

[0106]

[0107] Among them, I ran Let C be the distance dimension index of the target, C be the speed of light, and F be the distance dimension index. s The sampling rate.

[0108] S233, switch between search state, tracking state and memory state according to the tracking situation;

[0109] In the search state, the system scans for targets according to a preset beam direction. When the association result is valid, the state changes to the tracking state. When the association result is invalid, the system changes to the memory state, maintains the memory state, and expands the association range until the dwell requirement is met. If a valid association result appears during the expansion of the association range, the state changes back to the tracking state.

[0110] S234, the system control module controls the waveform, transmit / receive timing, and beam direction according to different states.

[0111] It's worth noting that the state transition module determines the program state based on the target association status of the current frame. Upon power-up, the system initially remains in the search state, where the beam scans according to a preset beam direction. The program performs target detection and association on the data accumulated in each frame. When the association result is valid, the state transitions to tracking. At this point, the system control module performs beam pointing integration based on the target's angular error information; that is, the beam pointing of the current frame plus the current frame's angular error becomes the new beam pointing for the next frame. When target tracking is lost, i.e., the association result is invalid, the system transitions to the memory state. The memory state lasts for a maximum of 10 frames. During this time, the beam pointing remains unchanged, and the association module expands the association range frame by frame. If a valid association result appears within a certain number of frames, the state transition module switches the program state back to tracking; otherwise, it switches to the search state. This process is repeated continuously. Figure 11 As shown.

[0112] The system control module primarily controls waveform, transmit / receive timing, and beam direction. The beam direction is controlled differently depending on the three states: in search mode, it scans according to a preset waveform map; in tracking mode, it integrates the beam direction based on the angular error; and in memory mode, it maintains the beam direction unchanged. Other control items are not detailed here.

[0113] The following mainly describes the present invention. Figure 12The first and second level FIFOs, HP interface, AMBA bus, GP interface and IO interface are explained.

[0114] The insertion of first-level and second-level FIFOs between processing modules is to solve the problem of multi-bit data crossing clock domains.

[0115] FIFO stands for First In First Out, a first-in-first-out storage device. In this invention, a first-level FIFO is used for parallel data transmission across clock domains from an ADC. The parallel ADC data includes the sampling results from three ADC channels. To verify the correctness of data transmission, a counter data channel is added in addition to the ADC data, and it is written to and read from the first-level FIFO along with the ADC data. The input clock of the first-level FIFO is the ADC's accompanying clock, and the output clock is the system clock. Since they have the same frequency but different sources, direct data transmission can lead to metastability and data transmission errors. Therefore, a first-level FIFO is inserted between the two clock domains as a buffer. Because the two clock domains have the same frequency, the depth of the first-level FIFO does not need to be large, and data writing and reading are continuous and simultaneous. The write clock for the secondary FIFO is the system clock, and the read clock is the HP interface clock. The HP interface clock rate is four times that of the system clock. Therefore, the secondary FIFO cannot always be read and written simultaneously. This invention sets a FIFO full flag. Data is continuously written to the secondary FIFO under the drive of the system clock. After a certain amount of data is written, the FIFO full flag is automatically set to 1, triggering the FIFO read process. The FIFO read process reads a fixed amount of data each time to ensure that the secondary FIFO is not emptied. After the read process is completed, it enters a waiting state to prepare for the next trigger. This realizes the function of transferring data from the slow clock domain to the fast clock domain.

[0116] HP interface stands for High Performance AXI Ports, a high-performance AXI interface. AXI primarily describes the data transmission method between master and slave devices and is an interface protocol. HP interface is a high-performance, high-bandwidth, low-latency interface; this invention uses HP interface to transmit large amounts of ADC data. AMBA bus stands for Advanced Microcontroller Bus Architecture, an advanced microcontroller bus architecture. In the ZYNQ-7000 series chips, DDR access is performed via the AMBA bus. GP interface stands for General Purpose AXI Ports, a general-purpose AXI interface. Its speed is slower than HP interface; therefore, this invention uses GP interface to transmit small amounts of parameter data. IO (Input / Output) interface is a custom input / output interface; this invention uses IO interface to complete ADC data input, waveform output, and antenna control output.

[0117] This invention uses a forwarding target simulator to simulate a moving target with an initial distance of 9 kilometers and a speed of 400 m / s. Using the processing and control flow in this invention, angle and distance tracking can be stably completed, and the frame processing cycle is within 40 ms, which verifies the effectiveness and real-time performance of this invention.

[0118] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0119] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0120] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A small single-pulse radar signal processing system based on a single-chip platform, characterized by, The small single-pulse radar signal processing system based on a single-chip platform is integrated on a single chip and communicates with a phased array antenna and an ADC acquisition unit through an IO port. The waveform generation module is configured to generate intermediate frequency linear frequency modulation signals of two waveforms and transmit the intermediate frequency linear frequency modulation signals to the phased array antenna. The signal acquisition module is configured to receive three-way serial data output by the ADC acquisition unit and convert the three-way serial data into parallel data. The serial data is obtained by the ADC acquisition unit through acquisition of intermediate frequency linear frequency modulation signals output by the sum channel, the azimuth difference channel and the elevation difference channel of the phased array antenna. The antenna control module is configured to generate a timing waveform to control the transmission timing of the phased array antenna and generate a phase shift code to control the beam direction of the phased array antenna. The signal processing module is configured to complete a fixed-point processing process and a floating-point processing process of the parallel data converted by the signal acquisition module. The fixed-point processing process and the floating-point processing process are implemented by different parts of the single chip. The single chip is a ZYNQ-7000 series chip, which is divided into a PL programmable logic part and a PS processing system part. The PL part and the PS part use a self-defined IP to interact with control parameters through a GP interface and complete signal data interaction through an HP interface, a DDR and an AMBA bus interface.

2. The small single-pulse radar signal processing system based on a single-chip platform of claim 1, wherein, The PS part includes a system control module, and the functions of the waveform generation module, the signal acquisition module, the antenna control module and the signal processing module are implemented by the PL part. The system control module of the PS part transmits generation parameters to the waveform generation module in the PL part through the GP interface. The generation parameters include waveform timing parameters and waveform selection parameters, and the waveform timing parameters include pulse trigger time and pulse repetition frequency.

3. The small single-pulse radar signal processing system based on a single-chip platform of claim 1, wherein, The waveform generation module is configured to read a pre-stored waveform file from a ROM according to an address to generate intermediate frequency linear frequency modulation signals of two predetermined waveforms with predetermined timing based on the waveform timing parameters and the waveform selection parameters, and output the intermediate frequency linear frequency modulation signals to the phased array antenna through an IO interface.

4. The small single-pulse radar signal processing system based on a single-chip platform of claim 1, wherein, Each piece of the three-way serial data is composed of 14 bits, a frame clock FCLK is synchronized with each 14-bit complete data, and a bit clock DCLK is synchronized with a bit. The antenna control module includes a transmission timing control module and a beam direction control module. The transmission timing control module is configured to generate a transmission timing waveform based on timing parameters output by the system control module and output the transmission timing waveform to the phased array antenna through a corresponding IO port of the PL part to control the transmission timing of the phased array antenna.

5. The small single-pulse radar signal processing system based on a single-chip platform of claim 4, wherein, The beam direction control module is configured to calculate a phase shift code corresponding to a beam angle sent by the PS part according to a phase shift code calculation rule defined by the phased array antenna and output the phase shift code to an antenna phase shifter through an IO port of the PL part to control the beam direction of the phased array antenna. The timing parameters output by the system control module include rising edge and falling edge times of T timing, R timing, TRPLUS timing and LFM timing. The transceiving timing waveform includes T timing, R timing, TRPLUS timing and LFM timing, and is output to the phased array antenna through a corresponding IO port; the transceiving timing waveform is effective at a high level; The beam direction control module is configured to calculate a ROM address according to the beam direction parameter sent by the PS, and read out the phase shift code at the corresponding position of the ROM according to the ROM address, and then output the phase shift code to the phased array antenna through the IO.

6. The small single-pulse radar signal processing system based on a single-chip platform of claim 1, wherein, The signal processing module includes a fixed-point data processing module and a floating-point data processing module; The fixed-point data processing module is configured to process the parallel data output by the signal acquisition module in the PL part to complete a fixed-point processing process, and specifically includes: S11, a digital down-conversion module in the fixed-point data processing module mixes the intermediate frequency signal to obtain I and Q two-way data, and then performs low-pass filtering to filter out high-frequency components to obtain original baseband echo data; wherein the intermediate frequency signal is collected by the ADC on the phased array antenna, and the intermediate frequency signal is input to the signal acquisition module in the PL part, and the signal acquisition module converts the serial data into parallel data; S12, the original baseband echo data is pulse compressed in the frequency domain; S13, the pulse compression results of multiple pulses are accumulated to form a two-dimensional time domain matrix; The floating-point data processing module is configured to process the parallel data in the PS part to complete a floating-point processing process, and specifically includes: S21, target detection is performed according to the pulse compressed data; S22, target association is performed according to target information; S23, target tracking is performed according to target association, and state conversion and system control are performed according to the tracking result.

7. The small single-pulse radar signal processing system based on a single-chip platform of claim 6, wherein, S21 includes: S211, time domain pulse data in the two-dimensional time domain matrix is arranged continuously according to the frequency dimension, and two-dimensional time-frequency domain data is obtained by performing frequency dimension FFT; S212, the amplitude mean value of the two-dimensional time-frequency domain is calculated to obtain the base noise; S213, the entire two-dimensional time-frequency domain matrix is traversed, the matrix element coordinate information of the amplitude greater than the first threshold is recorded to determine the suspected target, and the average amplitude of the noise amplitude in the distance gate reference unit before and after the suspected target is calculated as the noise amplitude; S214, the signal-to-noise ratio of the target amplitude and the noise amplitude is calculated, and if the signal-to-noise ratio is greater than the second threshold and the suspected target is a local maximum value, the suspected target is determined as a final target; S215, the target information of the final target is sorted in descending order of amplitude, and stored in the DDR.

8. The small single-pulse radar signal processing system based on a single-chip platform of claim 7, wherein, S22 includes: S221, the three largest amplitude targets in the current frame and the previous two frames are selected as the association objects, and all target combinations between different frames are traversed; S222, when the absolute value of the distance gate difference between the targets in the previous two frames and the current frame is less than the absolute difference threshold, the sum of the distance gate differences between the targets in the previous two frames and the current frame and the target serial number information are calculated and stored; S223, S221 to S222 are repeated until the traversal is completed, and the target with the smallest association difference sum is taken as the effective association result; S224, the target serial number of the current frame of the effective association result is recorded.

9. The small single-pulse radar signal processing system based on a single-chip platform of claim 7, wherein, S23 includes: S231, the angle difference, speed and distance of the target corresponding to the target serial number recorded in S224 are calculated; S232, tracking is performed according to the angle difference, speed and distance; S233, transition between the searching state, the tracking state and the memory state according to the tracking situation; Wherein, the target is scanned according to the preset beam direction in the searching state; the state is transferred to the tracking state when the association result is valid; the system state is transferred to the memory state when the association result is invalid, the memory state is maintained and the association range is expanded until the stay requirement is reached; if the valid association result appears during the expansion of the association range, the state is transferred to the tracking state; S234, the system control module controls the waveform, the transceiving timing and the beam direction according to different states.

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