A processor for channel estimation

Abstract

The application discloses a processor for channel estimation. It comprises a hardware message management module for processing serial instructions in a channel estimation special instruction set and configuring execution parameters of parallel instructions in the channel estimation special instruction set; a cache management subsystem for moving vector data according to the execution parameters; an arithmetic logic unit for performing vector operation on the vector data according to the execution parameters and returning the operation result to the cache management subsystem; and an arbitrator for accessing corresponding cache data according to the vector data moved by the target channel of the cache management subsystem. The processor for channel estimation can be compatible with various channel estimation algorithms, provide customized operation and processing, and has a relatively simple instruction set, so that the energy consumption and complexity are relatively low.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more particularly to a processor for channel estimation. Background Technology

[0002] Currently, algorithms that primarily implement vector operations such as channel estimation are mainly based on digital signal processing (DSP) solutions or application-specific integrated circuit (ASIC) circuit solutions.

[0003] DSP computation can be implemented in software, resulting in high flexibility, but also leading to high energy consumption and complexity. Furthermore, DSPs are generally compatible with most algorithms, lacking specific instructions tailored for channel estimation, thus resulting in lower performance in channel estimation. ASIC circuit solutions, on the other hand, are custom-designed circuits based on channel estimation algorithms, achieving very high performance, but lack flexibility and incompatibility with various different channel estimation algorithms. Summary of the Invention

[0004] This invention provides a processor for channel estimation, which has an instruction set and hardware architecture specifically designed for channel estimation, is compatible with different channel estimation algorithms, and is flexibly configurable.

[0005] This invention provides a processor for channel estimation, comprising: The Hardware Message Management (HMM) module is used to process serial instructions in the channel estimation dedicated instruction set and configure the execution parameters of parallel instructions in the channel estimation dedicated instruction set. The Memory Management Subsystem (MMS) is used to move vector data according to the execution parameters. The Arithmetic and Logic Unit (ALU) is used to perform vector operations on the vector data according to the execution parameters, and to send the operation results back to the cache management subsystem. An arbitrator is used to access the corresponding cached data based on the vector data moved by the target channel of the cache management subsystem.

[0006] Optionally, the hardware message management module (HMM) includes: The instruction random access memory (IRAM) module is used to store the serial instructions and the parallel instructions; The vector parameter configuration module is used to configure the execution parameters of the parallel instructions and transmit the execution parameters to the cache management subsystem and the arithmetic logic unit respectively. An instruction processing module is used to process the serial instructions.

[0007] Optionally, during the execution of the first parallel instruction by the cache management subsystem and the arithmetic logic unit, the hardware message management module parses and executes the serial instruction, and parses the second parallel instruction; After parsing the second parallel instruction, if the cache management subsystem and the arithmetic logic unit have completed the first parallel instruction, the hardware message management module configures the execution parameters of the second parallel instruction; otherwise, it waits for the first parallel instruction to complete before configuring the execution parameters of the second parallel instruction.

[0008] Optionally, the vector parameter configuration module includes a first vector parameter register group and a second vector parameter register group; The value of the first vector parameter register group is updated in real time according to the currently parsed channel estimation dedicated instruction; The value of the second vector parameter register group is synchronized with the value of the first vector parameter register group when the execution parameters are configured.

[0009] Optionally, the MMS is specifically used for: The vector data is interleaved according to the operation mode of the arithmetic logic unit and then transmitted to the arithmetic logic unit. The calculation result is interleaved according to the operation mode of the arithmetic logic unit (ALU) and then transmitted to the arbitrator.

[0010] Optionally, the MMS is also used for: Extract vector data based on the starting address, length, jump step size, and number of repetitions.

[0011] Optionally, the MMS is specifically used for: During each extraction process, determine the starting address of the current extraction, the starting address of the next extraction, and the current extraction count; If, based on the currently extracted starting address, the jump address corresponding to the jump step size does not exceed the range indicated by the length, then vector data is extracted from the jump address; Repeat the above extraction process until the current extraction count reaches the set number.

[0012] Optionally, the ALU includes an adder, a multiplier, and a selector, wherein the adder, the multiplier, and the selector are used to provide multiple operation modes.

[0013] Optionally, the ALU includes an operation mode that combines butterfly operations and complex multiplication.

[0014] Optionally, the arithmetic logic unit further includes a flip-flop for storing the real part (RE) and imaginary part (IM) of the butterfly factor.

[0015] This invention provides a processor for channel estimation, comprising: a hardware message management module for processing serial instructions in a dedicated channel estimation instruction set and configuring execution parameters for parallel instructions in the dedicated channel estimation instruction set; a cache management subsystem for moving vector data according to the execution parameters; an arithmetic logic unit for performing vector operations on the vector data according to the execution parameters and sending the operation results back to the cache management subsystem; and an arbitrator for accessing corresponding cached data according to the vector data moved by the target channel in the cache management subsystem. The processor for channel estimation of this invention is customized for channel estimation algorithms, and its performance is significantly better than DSP-based solutions. Furthermore, it incorporates many customized operations and processing, resulting in a simpler instruction set, thus lower power consumption and complexity compared to DSPs.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a processor for channel estimation provided according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a processor for channel estimation provided according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the execution order of serial and parallel instructions according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the internal structure of an HMM provided according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a 32-point radix-4 butterfly operation according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a radix-4 butterfly operation with a mechanism for repeated jump data acquisition and interleaving provided by an embodiment of the present invention; Figure 7 This is a flowchart of a request address acquisition process provided by an embodiment of the present invention; Figure 8 This is a schematic diagram of a radix-4 butterfly arithmetic mode provided according to an embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the flow of input data within the ALU in the radix-4 butterfly operation mode provided by an embodiment of the present invention; Figure 10 This is a schematic diagram of the data flow in a complex number multiplication operation mode provided by an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of an ALU provided according to an embodiment of the present invention; Figure 12 This is a schematic diagram of an ALU mode specifically designed for FFT algorithm, which handles radix-4 butterfly and complex multiplication, according to an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1This diagram illustrates a processor for channel estimation according to an embodiment of the present invention. The processor is suitable for channel estimation, and the present invention belongs to the ASIP class of implementation schemes, such as... Figure 1 As shown, the processor for channel estimation includes: The hardware message management module (HMM) 10 is used to process serial instructions in the channel estimation dedicated instruction set and configure the execution parameters of parallel instructions in the channel estimation dedicated instruction set; the buffer management subsystem (MMS) 11 is used to move vector data according to the execution parameters; the arithmetic logic unit (ALU) 12 is used to perform vector operations on the vector data according to the execution parameters and return the operation results to the buffer management subsystem (MMS) 11; and the arbitrator 13 is used to access the corresponding buffer data according to the vector data moved by the target channel of the MMS 11.

[0022] Specifically, the entire ASIP architecture can be viewed as a combination of a scalar processor and some vector processing and arithmetic units. The instruction set of the processor used for channel estimation can be divided into two categories: serial instructions and parallel instructions. Serial instructions are mainly used to complete operations such as assigning values ​​to register sets, accessing memory, and branching, all of which are scalar processing. Parallel instructions are mainly used to indicate the channel information that requires data transfer in vector operations and the mode of vector operations. The vector processing and arithmetic units will complete the operations of reading the source data stream, vector operations, and outputting the result data stream based on this information and the parameters of each channel.

[0023] HMM 10 can process serial instructions in the channel estimation instruction set. Specifically, HMM 10 can fetch and decode all instructions, and complete the execution and write-back operations of serial instructions. For parallel instructions, after decoding, it configures the execution parameters of the parallel instructions in the channel estimation instruction set, such as which operation mode to use, data fetching parameters, interleaving parameters, and the number of channels. MMS 11 is mainly used to move vector data in memory. Depending on the needs of ALU 12, it may perform interleaving processing on the data or transmit the single-shot data to ALU 12 by dividing it into multiple fields and transmitting them one shot at a time. At the same time, this module is also responsible for processing the output data of ALU 12 and moving it to memory. ALU 12 mainly performs ALU operations on the input data in the corresponding mode, supporting operations between vectors, between vectors and scalars, and between scalars. The specific calculation process is determined according to the ALU operation mode (also called ALU mode), and the calculation result is sent back to MMS 11. Arbitrator 13 can select one of the channels from MMS 11 as the target channel and access the corresponding cached data (MEMORY) based on the vector data moved by the target channel.

[0024] The present invention provides a processor for channel estimation, which has some instructions dedicated to channel estimation and a dedicated hardware implementation structure, including data transfer and internal connections of ALU 12, while retaining some general computing modes, which can improve the flexibility of algorithm modification and realize channel estimation.

[0025] In one embodiment, HMM 10 includes: IRAM for storing serial instructions and parallel instructions; a vector parameter configuration module for configuring the execution parameters of parallel instructions and transmitting the execution parameters to MMS 11 and ALU 12 respectively; and an instruction processing module 22 for processing serial instructions.

[0026] Figure 2 A schematic diagram of a processor for channel estimation provided in an embodiment of the present invention is shown below. Figure 2 As shown, the processor for channel estimation includes an HMM 10, which further includes an instruction cache module (IRAM) 20, a vector parameter configuration module 21, and an instruction processing module 22; the processor for channel estimation also includes an MMS 11, which further includes multiple channels (CH) 23. Figure 2 Taking four channels as an example, denoted as CH0, CH1, CH2, and CH3 respectively; each channel has a corresponding First In, First Out (FIFO) memory, denoted as FIFO0, FIFO1, FIFO2, and FIFO3 respectively; the processor used for channel estimation also includes ALU 12, arbitrator 13, and multiple memory ports. When different channels are used as target channels, the processor may access cached data through different memory ports.

[0027] CH 23 can be used for reading, writing, and moving data. MEMORY: cache, memory for storing data. Arbitrator 13 can select one of the four CH 23 read / write requests, respond to the request, and access the MEMORY according to the request. FIFO can represent first-in-first-out, i.e., a pipelined data storage structure, where data written first is retrieved first during reading. HMM10 can fetch and decode all instructions, and complete the execution and write-back operations of serial instructions; for parallel instructions, after decoding, the vector parameter configuration module 21 configures the relevant information of vector operations to MMS 11 and ALU 12.

[0028] In one embodiment, during the execution of the first parallel instruction by MMS 11 and ALU 12, HMM 10 parses and executes the serial instruction and parses the second parallel instruction; after HMM 10 parses the second parallel instruction, if MMS 11 and ALU 12 have completed the first parallel instruction, then HMM 10 configures the execution parameters of the second parallel instruction; otherwise, it waits for the first parallel instruction to be completed before configuring the execution parameters of the second parallel instruction.

[0029] Specifically, in related technologies, each vector operation requires the execution of a serial instruction before configuring the relevant parameters to complete the execution of parallel instructions. This means that the next vector operation not only waits for the current operation to complete but also for the execution of the serial instruction corresponding to its required parameters. This results in significant idle time and low efficiency in vector operations. However, in this embodiment of the invention, while MMS 11 and ALU 12 are executing the first parallel instruction, HMM 10 can parse and execute the serial instruction and parse the second parallel instruction. That is, it can parse one instruction while executing another. Compared with related technologies, this not only saves vector operation time but also improves computational efficiency.

[0030] Figure 3 This is a schematic diagram illustrating the execution order of serial and parallel instructions provided in an embodiment of the present invention. Figure 3 As shown, P1-Pn represent parallel instructions, and S1-Sn represent serial instructions.

[0031] During the execution of P1 by MMS 11 and ALU 12, HMM 10 parses and executes S2. After parsing P2, if P1 has already been completed, HMM 10 configures the execution parameters for P2; otherwise, it waits for P1 to complete before configuring the execution parameters for P2, and so on. This process continues thereafter. Figure 3 The order shown is used to execute Pn and Sn. Figure 3 The instructions in the program execute smoothly and can process Pn and Sn in parallel, which not only saves time in vector operations but also improves computational efficiency.

[0032] In one embodiment, the vector parameter configuration module 21 includes a first vector parameter register group and a second vector parameter register group; the value of the first vector parameter register group is updated in real time according to the currently parsed channel estimation dedicated instruction; the value of the second vector parameter register group is synchronized with the value of the first vector parameter register group when configuring the execution parameters.

[0033] Figure 4 This is a schematic diagram of the internal structure of an HMM provided in an embodiment of the present invention, such as... Figure 4As shown, in the vector parameter configuration module 21, there are two vector parameter register groups: vector parameter register group 1 and vector parameter register group 2. This invention employs... Figure 4 This processing structure executes both serial and parallel instructions. Vector parameter register group 1 updates its internal values ​​in real time based on the currently parsed instruction. Vector parameter register group 2 serves as the interface between HMM 10 and the vector processing and arithmetic units; it only needs to obtain the current value of register group 1 synchronously when configuring vector operations. This approach can overcome some of the problems existing in related technologies and improve instruction execution efficiency.

[0034] Combination Figure 3 The execution process of serial and parallel instructions specifically includes the following: After parsing P1 and configuring the start of the vector processing and arithmetic unit, vector parameter register group 2 synchronously obtains the current value of vector register group 1 and assists in completing vector operations as an interface. During the P1 execution phase, HMM 10 continues to parse and execute S2 and updates the value of vector parameter register group 1. Since the value of register group 2 does not change during this period, it does not affect the normal execution of P1. At the same time, P2 continues to be parsed. After P2 is parsed, the status of the vector processing and arithmetic unit needs to be judged. If P1 has been completed, the parameters for the second vector operation can be configured; otherwise, wait for P1 to be completed.

[0035] It should be noted that there may be situations where the execution of S2 depends on the execution result of P1. In this case, we can only wait for P1 to finish executing before parsing and executing S2. However, this situation can be avoided as much as possible during the software instruction writing stage.

[0036] It should be noted that, Figure 4 Vector processing in MMS 11 refers to the MMS 11. CH0, CH1, CH2, and CH3 in MMS 11 need to receive parameters to correctly complete data transfer. The arithmetic unit refers to the ALU, which needs mode parameters to obtain the type of operation to be performed.

[0037] In one embodiment, MMS 11 is specifically used for: interleaving vector data according to the operation mode of ALU 12 and transmitting it to ALU 12; and interleaving the operation result according to the operation mode of ALU 12 and transmitting it to arbitrator 13.

[0038] MMS 11 is primarily used for processing and moving data from memory to ALU 12 and back from ALU 12 to memory. As an ASIP dedicated to channel estimation, support for Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) is essential.

[0039] Therefore, in addition to the basic continuous reading based on address and length, MMS 11 also implements some dedicated addressing methods according to the needs of the channel estimation algorithm. Figure 5 This is a schematic diagram of a 32-point radix-4 butterfly operation provided in the embodiments of the present invention, as shown below. Figure 5 As shown, it is assumed that a single cycle of the current MMS 11 channel can read 4 complex points. Figure 5 The ALU 12 shown can not be fed data using the continuous addressing mode. Instead, the method of using a step size of 8 complex points and an effective length of 1 complex point requires 4 cycles to combine the points for one radix-4 butterfly operation, which is inefficient.

[0040] Therefore, ASIP has designed a mechanism for repeated jump data retrieval and interleaving specifically for radix-4 butterfly data transfer and processing to improve the data processing efficiency of radix-4 butterfly. Figure 6 A schematic diagram of a radix-4 butterfly operation, which incorporates a mechanism for repeated jumps and interleaving, is provided for embodiments of the present invention. Figure 6 As shown, the vector data can be repeatedly skipped and retrieved according to the operation mode of ALU 12, then interleaved and transmitted to ALU 12, and the operation result can be interleaved and transmitted to the arbitrator according to the operation mode of ALU 12.

[0041] In one embodiment, MMS 11 is also used to extract vector data based on the starting address, length, jump step size, and number of repetitions.

[0042] The starting address and the jump step size together determine the jump address, and the length determines the range of data to be retrieved in this repeated jump. If the jump address for extracting vector data is within the range of data to be retrieved in this repeated jump, the vector data can be extracted from that jump address; otherwise, the next repeated jump will be performed.

[0043] In one embodiment, MMS 11 is specifically used for: During each extraction process, the starting address of the current extraction, the starting address of the next extraction, and the current extraction count are determined. If the jump address corresponding to the jump step size does not exceed the range of the length indicator based on the starting address of the current extraction, vector data is extracted from the jump address. The above extraction process is repeated until the current extraction count reaches the set number.

[0044] Specifically, to support the function of repeatedly jumping to retrieve data, in addition to the starting address (Source_addr) and length (Data_length), the jump step size (Jump_addr) and the number of repetitions (Rep_cnt) are also introduced.

[0045] For example, Figure 7 A flowchart for obtaining a request address is provided in an embodiment of the present invention, as follows: Figure 7 As shown, the specific steps include: S10. Req_addr=Source_addr; Rep_source_addr=Source_addr+C_len; Rep_cnt_c=0.

[0046] Specifically, the address of the first request (i.e., Req_addr) is the starting address (i.e., Source_addr), that is, Req_addr = Source_addr. At the same time, Source_addr is used to calculate the initial address of the next round of value retrieval (i.e., Rep_source_addr). C_len is the length of 4 complex points, and Rep_cnt_c indicates which round of value retrieval is being performed.

[0047] S11. Determine whether Req_addr + Jump_step exceeds the range of Source_addr + Data_length. If yes, execute S12; otherwise, execute S13.

[0048] S12. Determine if Rep_cnt_c is less than the value of Rep_cnt. If yes, execute S14; otherwise, end the process.

[0049] Specifically, determine whether the current round number (Rep_cnt_c) is less than the number of repetitions (Rep_cnt). S13, Req_addr = Req_addr + Jump_step.

[0050] S14. Req_addr=Req_source_addr; Req_source_addr=Req_source_addr+C_len; Rep_cnt_c=Rep_cnt_c+1.

[0051] Specifically, it determines whether the requested address and jump step size exceed the range of the starting address and length. If they do not exceed the range, it continues to jump. If they do exceed the range, it determines whether there is another round. If so, it enters the next round of jump address retrieval; otherwise, the current relocation task has been completed.

[0052] In one embodiment, ALU 12 includes an adder, a multiplier, and a selector, which are used to provide multiple operation modes.

[0053] Specifically, the ALU 12 primarily selects the path of input data within the module based on the currently configured operation mode to complete the corresponding operation. For example, assuming the ALU 12 has one adder and one multiplier, and three input data a, b, and c; first, a and b are input to the adder via a selector, and then the output of the adder and c are input to the multiplier, thus completing (a+b)*c; if a and b are input to the multiplier first, and then c is input to the adder, then a*b+c is achieved. By using selectors to choose the path of input data between the internal computation units of the ALU 12, various operations can be implemented.

[0054] For example, Figure 8 This is a schematic diagram of a radix-4 butterfly arithmetic mode provided in an embodiment of the present invention, as shown below. Figure 8 As shown, A0~A3 represent the input of the radix-4 butterfly operation formula, C0~C3 represent the output of the radix-4 butterfly operation formula, and T0~T3 represent the intermediate calculation results of the radix-4 butterfly operation formula. Specifically, the following formula is used to calculate C0~C3 through A0~A3.

[0055] Based on the above calculation formula, a schematic diagram of the flow of input data within ALU 12 in radix-4 butterfly operation mode can be drawn.

[0056] Figure 9 This is a schematic diagram illustrating the flow of input data within the ALU 12 in the radix-4 butterfly operation mode provided in an embodiment of the present invention, as shown below. Figure 9As shown, the general form of a complex number is a + b * i, where Re represents the real part (a in complex numbers) and Im represents the imaginary part (b in complex numbers). The radix-4 butterfly arithmetic mode requires 16 adders (ADD_0~ADD_15). In addition to the necessary clock and reset signals, each adder module has three input interfaces: two data interfaces and one parameter configuration interface. The adder will perform addition (parameter value 0) or subtraction (parameter value 1) operations on the two input data based on this parameter.

[0057] In one embodiment, the operation mode includes an operation mode that combines butterfly operations and complex number multiplication.

[0058] Figure 10 This diagram illustrates the data flow of a complex number multiplication operation mode provided in an embodiment of the present invention. This operation mode is complex number multiplication, meaning that both Ai and Bi are complex numbers, and it is a general mode. Based on the representation of complex numbers: Ai and Bi are the inputs for complex number multiplication, and Ci is the output. = = Then compare the representation of the complex number Ci, that is Since ASIP has two input channels, each channel can input 4 complex numbers. Therefore, the ALU mode for complex number multiplication can perform 4 complex number multiplication operations. Thus, the value of i can be 0, 1, 2, or 3. This mode requires 16 multipliers and 8 adders.

[0059] Figure 9 and Figure 10 Both ALU modes utilize adders numbered 0-7, and the data sources for the adders differ between the two modes. ALU 12's ability to reconstruct these two modes primarily relies on... Figure 11 The structure shown, Figure 11 This is a schematic diagram of the structure of an ALU provided in an embodiment of the present invention. Figure 11Taking adder number 5 (ADD_5) as an example, its parameters and two data interfaces are connected to MUXs. These MUXs select the corresponding signals as inputs to the adders through selection signals generated by the ALU mode. For example, when the mode is complex multiplication, the two data input MUXs select the output signals of multipliers numbered 10 and 11 respectively, and the parameter selects the constant 0, indicating that the current adder is performing an addition operation.

[0060] These MUXs allow the computational units (adders, multipliers, etc.) inside the ALU to be reused as much as possible in different ALU modes, saving area.

[0061] Furthermore, since ASIP is dedicated to channel estimation algorithm processing, a dedicated hardware connection path for channel estimation can be designed within the ALU. Taking the 4096-point FFT algorithm as an example, if each stage of the operation is completed using one radix-4 butterfly pattern plus one complex multiplication, then completing the entire algorithm requires six radix-4 butterfly patterns and five complex multiplication patterns. Assuming that each pattern requires n cycles from reading, calculation to writing, the FFT algorithm requires 11n cycles to complete.

[0062] In one embodiment, the arithmetic logic unit further includes a flip-flop for storing the real and imaginary parts of the butterfly factor.

[0063] Figure 12 This invention provides a schematic diagram of an ALU mode specifically designed for FFT algorithms, which combines radix-4 butterfly multiplication and complex multiplication. Figure 12 As shown, the ellipsis of complex multiplication contains four complex multiplication structures (i.e. Figure 10 Therefore, there will be 16 multipliers and 8 adders. Figure 11 In this model, radix-4 butterfly, complex multiplication, and CDFF all work simultaneously, forming a collaborative processing mode, so they need to be performed concurrently.

[0064] in, Figure 12 In the diagram, A0~A3 are the input data before each stage of butterfly operation, and B0~B3 are the corresponding butterfly factors. To synchronize the output of the radix-4 butterfly operation with the complex multiplication stage, two stages of complex D flip-flops (D Flip-flops) are needed for the butterfly factors. Since B0~B3 are all complex numbers, a complex flip-flop is added, indicating that both the real and imaginary parts need to be registered using DFFs. Therefore, the newly added dedicated mode requires 16 multipliers, 24 adders, and 16 D flip-flops.

[0065] Compared to the previous separate processing, the dedicated mode, although it adds 8 adders and 16 D flip-flops, reduces the time to implement the 4096-point FFT algorithm to 6n cycles, achieving a performance improvement of nearly 2 times. The additional adders and D flip-flops can also be used to customize dedicated ALU modes for other channel estimation algorithms, essentially avoiding resource waste.

[0066] Therefore, ASIP will have some instructions specifically for channel estimation, as well as dedicated hardware implementation structures, including data transfer and internal connections of the ALU, while retaining some general computation patterns to provide some flexibility for algorithm modification.

[0067] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

[0068] Generally, various embodiments of the present invention can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while others may be implemented in firmware or software (which may be executed by a controller, microprocessor, or other computing device), although the invention is not limited thereto.

[0069] Embodiments of the present invention can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0070] Any block diagram of logical flow in the accompanying drawings of this invention may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored in memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Video Disc (DVD) or Compact Disk (CD), etc.). Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and processors based on multi-core processor architectures.

[0071] A detailed description of exemplary embodiments of the invention has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of the invention. Therefore, the proper scope of the invention will be determined by the claims.

[0072] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A processor for channel estimation, characterized in that, include: The hardware message management module is used to process serial instructions in the channel estimation dedicated instruction set and configure the execution parameters of parallel instructions in the channel estimation dedicated instruction set. The cache management subsystem is used to move vector data according to the execution parameters; An arithmetic logic unit is used to perform vector operations on the vector data according to the execution parameters, and to send the operation results back to the cache management subsystem; An arbitrator is used to access the corresponding cached data based on the vector data moved by the target channel of the cache management subsystem; During the execution of the first parallel instruction by the cache management subsystem and the arithmetic logic unit, the hardware message management module parses and executes the serial instruction, and parses the second parallel instruction. After parsing the second parallel instruction, if the cache management subsystem and the arithmetic logic unit have completed the first parallel instruction, the hardware message management module configures the execution parameters of the second parallel instruction; otherwise, it waits for the first parallel instruction to be completed before configuring the execution parameters of the second parallel instruction. The cache management subsystem is also used to extract vector data based on the starting address, length, jump step size, and number of repetitions.

2. The processor according to claim 1, characterized in that, The hardware message management module includes: An instruction cache module is used to store the serial instructions and the parallel instructions; The vector parameter configuration module is used to configure the execution parameters of the parallel instructions and transmit the execution parameters to the cache management subsystem and the arithmetic logic unit respectively. An instruction processing module is used to process the serial instructions.

3. The processor according to claim 2, characterized in that, The vector parameter configuration module includes a first vector parameter register group and a second vector parameter register group; The value of the first vector parameter register group is updated in real time according to the currently parsed channel estimation dedicated instruction; The value of the second vector parameter register group is synchronized with the value of the first vector parameter register group when the execution parameters are configured.

4. The processor according to claim 1, characterized in that, The cache management subsystem is specifically used for: The vector data is interleaved according to the operation mode of the arithmetic logic unit and then transmitted to the arithmetic logic unit. The calculation result is interleaved according to the operation mode of the arithmetic logic unit and then transmitted to the arbitrator.

5. The processor according to claim 1, characterized in that, The cache management subsystem is specifically used for: During each extraction process, determine the starting address of the current extraction, the starting address of the next extraction, and the current extraction count; If, based on the currently extracted starting address, the jump address corresponding to the jump step size does not exceed the range indicated by the length, then vector data is extracted from the jump address; Repeat the above extraction process until the current extraction count reaches the set number.

6. The processor according to claim 1, characterized in that, The arithmetic logic unit includes an adder, a multiplier, and a selector, which are used to provide multiple operation modes.

7. The processor according to claim 6, characterized in that, The operation mode includes both butterfly operation and complex number multiplication.

8. The processor according to claim 7, characterized in that, The arithmetic logic unit also includes flip-flops for storing the real and imaginary parts of the butterfly factor.

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