A method and apparatus for switching the execution state of a process.

Abstract

A method and apparatus for switching the execution state of a process are disclosed, used to switch a process running in a slave logical core to run in the master logical core when the master logical core and slave logical core are decoupled. In this application, the method includes: if a process running in the slave logical core satisfies a first condition, pausing the process in the slave logical core and recording the pause position of the process, the pause position being used to determine the execution position the next time the process runs in the slave logical core, wherein the first condition indicates that the process is to perform a target operation, and the target operation can be executed when the process's execution state is in the privileged state of the master logical core; switching the process's execution state from the user state of the slave logical core to the privileged state of the master logical core; and running the process in the master logical core for the process to execute the target operation.

Description

Technical Field

[0001] This application relates to the field of processors, and more particularly to a method and apparatus for switching the execution state of a process. Background Technology

[0002] Faced with increasingly complex computing demands, modern computers can no longer meet the needs of business operations with a single architecture of central processing unit (CPU). Many solutions opt for heterogeneous computing. Heterogeneous computing combines computing units with different process architectures, instruction sets, and functions, such as CPUs, digital signal processing (DSPs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs), to form a hybrid computing system.

[0003] Taking the ARMv8-A architecture as an example, the CPU physical cores include ARM64 logical cores and ARM32 logical cores. The ARM64 logical core can execute privilege levels EL0 to EL4, while the ARM32 logical core can execute privilege level EL0, with EL0 being the lowest privilege level. When an ARM32 process runs in the ARMv8-A architecture, it specifically runs within the ARM32 logical core. However, when the ARM32 process needs to perform a high-privilege operation (such as a system call), an exception is triggered, causing the ARM32 process's execution state to transition from privilege level EL0 to privilege level EL1, thus executing the high-privilege operation within the ARM64 logical core. Subsequently, the ARM32 process's execution state returns from privilege level EL1 to privilege level EL0, continuing execution within the ARM32 logical core.

[0004] In this approach, the ARM64 logic core and the ARM32 logic core need to be tightly coupled. For example, the ARM64 logic core needs to add new registers and vector table entries to support the ARM32 logic core. These two logic cores cannot evolve independently. Summary of the Invention

[0005] This application provides a method and apparatus for switching the execution state of a process, which decouples two logical cores while flexibly switching the execution states of the two logical cores, thereby allowing one of the logical cores to evolve independently.

[0006] In a first aspect, this application provides a method for switching the execution state of a process, applied in a CPU, the CPU including physical cores, the physical cores including a master logical core and a slave logical core, the method including: if a process running on a slave logical core satisfies a first condition, suspending the process running in the slave logical core and recording the pause position of the process, the pause position can be used to determine the execution position when the process runs in the slave logical core again, wherein the first condition is used to indicate that the process is to perform a target operation, and the target operation can be executed when the process's execution state is in the privileged state of the master logical core; switching the execution state of the process from the user state of the slave logical core to the privileged state of the master logical core; running the process in the master logical core so that the process can perform the target operation.

[0007] In the above technical solution, when a process is running in the slave logic core and the process needs to perform a target operation, the pause position of the process is recorded by the slave logic core. This pause position can be used to determine the execution position when the process runs in the slave logic core again. In this way, the master logic core and the slave logic core do not need to share registers. It is possible to decouple the two logic cores while flexibly switching the execution states of the two logic cores, so that one of the logic cores can evolve independently.

[0008] In one possible implementation, recording the pause position of the process includes: writing the pause position information into a configuration space from the main logical core. This configuration space is used for information exchange between the main and slave logical cores. By configuring a configuration space in the physical core for information exchange between the main and slave logical cores, decoupling the main and slave logical cores is achieved. This allows the main and slave logical cores to evolve independently, enabling independent evolution of the instruction set corresponding to the slave logical core without disrupting the architectural semantics / instruction space of the main logical core.

[0009] In one possible implementation, the method further includes: switching the execution state of the process from the privileged state of the main logical core to the user state of the slave logical core; reading the pause position information from the configuration space through the slave logical core; and resuming the process execution from the pause position in the slave logical core. Thus, after the main logical core completes the target operation, the slave logical core can be started to continue running the process. Since the slave logical core previously recorded the pause position, it can continue running from that pause position, thereby enabling the process to switch between the two logical cores without interruption.

[0010] In one possible implementation, the first condition includes the process triggering a first type of exception, which includes exceptions other than reliability exceptions, availability exceptions, and serviceability RAS exceptions; switching the execution state of the process from the user mode of the slave logic kernel to the privileged mode of the master logic kernel, including: triggering the master logic kernel to run the process to switch the execution state of the process from the user mode of the slave logic kernel to the user mode of the master logic kernel; determining the target privilege level corresponding to the first type of exception from multiple privilege levels of the privileged mode of the master logic kernel; and switching the execution state of the process from the user mode of the master logic kernel to the target privilege level of the master logic kernel's privileged mode.

[0011] In one possible implementation, before switching the execution state of the process from the user mode of the main logic core to the target privilege level of the main logic core's privileged mode, the following steps are included: obtaining the virtual memory address corresponding to the target privilege level; and determining that the virtual memory address has not been mapped to the physical memory address.

[0012] In the above technical solution, the main logical kernel accesses the virtual memory address corresponding to the target privilege level. If it is determined that the virtual memory address does not have a mapping relationship with the physical memory address, a page fault is triggered. Based on the triggered page fault, the main logical kernel can transfer the process's execution state from the user mode of the main logical kernel to the target privilege level of the main logical kernel's privileged mode. In this way, by constructing a special exception (i.e., a page fault), the process's execution state is transferred from the user mode of the main logical kernel to the target privilege level of the main logical kernel's privileged mode, reducing the complexity of the process entering the privileged mode for execution.

[0013] In one possible implementation, the first condition includes the process receiving an interrupt or the process triggering a RAS exception. Since interrupts or RAS exceptions are asynchronous events and need to be processed quickly, when a process running on a secondary logical core receives an interrupt or triggers a RAS exception, the execution state of the process can be switched from the user mode of the secondary logical core to the target privilege level of the privileged state of the primary logical core through a hardware unit (or hardware part) in the CPU physical core.

[0014] In one possible implementation, the method further includes: starting the process in the main logical core; if the process's instruction set belongs to the instruction set executed by the slave logical core, recording the process's starting position and triggering the slave logical core to enter the running state; and in the slave logical core, starting the process from the starting position. In the above technical solution, some processes (such as MySQL processes, graph computation processes, or encryption / decryption operators) need to run in the slave logical core. When these processes are started in the main logical core, it can be determined that these processes need to run in the slave logical core. Therefore, the main logical core records the process's starting position and triggers the slave logical core to enter the running state, so that the slave logical core reads the starting position and runs the process at that starting position.

[0015] In one possible implementation, the method further includes: releasing the physical core hardware resources occupied by the main logic core while running processes; wherein the hardware resources include memory resources and / or input / output resources. In this way, the released hardware resources can be reused to run other processes, helping to make full use of hardware resources.

[0016] In one possible implementation, the method further includes recording one or more of the following information from the logical kernel: the reason for suspending the running process on the logical kernel, the execution parameters corresponding to the target operation, the environment information when the running process was suspended, or privilege level information; wherein the privilege level information is used to indicate the privilege level of the main logical kernel when the process executes the target operation. In this way, the main logical kernel can correctly process the target operation based on these parameters.

[0017] In one possible implementation, an acceleration engine and algorithms, such as a MySQL process, a graph computation process, or one or more encryption / decryption operators, can be run from the logic core, which can improve the computing speed compared to running these processes on the main logic core.

[0018] Secondly, this application provides a process execution state switching device, which may be a CPU.

[0019] The device includes a processor and a memory; the memory stores a computer program; the processor calls the computer program stored in the memory to perform the following steps: if a process running on a slave logical core satisfies a first condition, suspend the process running on the slave logical core and record the pause position of the process, the pause position being used to determine the execution position the next time the process runs on the slave logical core, wherein the first condition is used to indicate that the process is to perform a target operation, and the target operation can be executed when the process's execution state is in the privileged state of the master logical core; switch the process's execution state from the user state of the slave logical core to the privileged state of the master logical core; run the process on the master logical core so that the process can perform the target operation.

[0020] In one possible implementation, when the processor records the pause position of the process, it specifically writes the pause position information to the configuration space through the slave logic core. The configuration space is used for information exchange between the master logic core and the slave logic core.

[0021] In one possible implementation, the processor is also used to: switch the execution state of the process from the privileged state of the main logical core to the user state of the slave logical core; read the pause position information from the configuration space through the slave logical core; and resume the process from the pause position in the slave logical core.

[0022] In one possible implementation, the first condition includes the process triggering a first type of exception, which includes exceptions other than reliability exceptions, availability exceptions, and serviceability RAS exceptions. When the processor switches the execution state of the process from the user mode of the slave logic core to the privileged mode of the master logic core, it specifically performs the following: triggers the master logic core to run the process to switch the execution state of the process from the user mode of the slave logic core to the user mode of the master logic core; determines the target privilege level corresponding to the first type of exception from multiple privilege levels of the privileged mode of the master logic core; and switches the execution state of the process from the user mode of the master logic core to the target privilege level of the privileged mode of the master logic core.

[0023] In one possible implementation, before the processor switches the execution state of the process from the user mode of the main logic core to the target privilege level of the privileged mode of the main logic core, it also performs the following: obtains the virtual memory address corresponding to the target privilege level; and determines that the virtual memory address has not been mapped to the physical memory address.

[0024] In one possible implementation, the first condition includes the process being interrupted or triggering a RAS exception.

[0025] In one possible implementation, the processor is also used to: start a process in the main logical core; if the process's instruction set belongs to the instruction set executed by the slave logical core, record the process's starting position and trigger the slave logical core to enter the running state; and in the slave logical core, start running the process from the starting position.

[0026] In one possible implementation, the processor is also used to: release the hardware resources of the physical core occupied by the main logic core when running a process; wherein the hardware resources include memory resources and / or input / output resources.

[0027] In one possible implementation, the processor is further configured to: record from the logical core one or more of the following information: the reason for suspending the running process on the logical core, the execution parameters corresponding to the target operation, the environment information when the running process is suspended, or, privilege level information; wherein the privilege level information is used to indicate the privilege level of the privilege state of the main logical core when the process is executing the target operation.

[0028] Thirdly, this application provides a process execution state switching device, which may be a CPU.

[0029] The device includes a main logic core module and a slave logic core module. The slave logic core module is used to pause the running process when a first condition is met, and records the pause position of the process. The pause position is used to determine the execution position when the process runs in the slave logic core module next time. The first condition is used to indicate that the process is to perform a target operation, and the target operation can be executed when the process's execution state is in the privileged state of the main logic core module. The slave logic core module is also used to switch the execution state of the process from the user state of the slave logic core module to the privileged state of the main logic core module. The main logic core module is used to run the process so that the process can perform the target operation.

[0030] In one possible implementation, when the slave logic core module records the pause position of the process, it specifically writes the pause position information into the configuration space, which is used for information exchange between the master logic core module and the slave logic core module.

[0031] In one possible implementation, the main logic kernel module is also used to switch the execution state of the process from the privileged state of the main logic kernel module to the user state of the slave logic kernel module; the slave logic kernel module is also used to read the pause position information from the configuration space and continue running the process from the pause position.

[0032] In one possible implementation, the first condition includes the process triggering a first type of exception, which includes exceptions other than reliability exceptions, availability exceptions, and serviceability RAS exceptions; the slave logic core module is specifically used to trigger the main logic core module to run the process, so as to switch the execution state of the process from the user mode of the slave logic core module to the user mode of the main logic core module; the main logic core module is specifically used to determine the target privilege level corresponding to the first type of exception from multiple privilege levels of the privileged state of the main logic core module, and to switch the execution state of the process from the user mode of the main logic core module to the target privilege level of the privileged state of the main logic core module.

[0033] In one possible implementation, before the main logic core module switches the execution state of the process from the user mode of the main logic core module to the target privilege level of the privileged mode of the main logic core module, it also obtains the virtual memory address corresponding to the target privilege level and determines that the virtual memory address has not been mapped to the physical memory address.

[0034] In one possible implementation, the first condition includes the process being interrupted or triggering a RAS exception.

[0035] In one possible implementation, the main logic core module is also used to start a process. If the process's instruction set belongs to the instruction set that the slave logic core runs, the starting position of the process is recorded, and the slave logic core module is triggered to enter the running state. The slave logic core module is also used to start running the process from the starting position.

[0036] In one possible implementation, the main logic core module releases the hardware resources of the physical core occupied during the running process; wherein, the hardware resources include memory resources and / or input / output resources.

[0037] In one possible implementation, the slave logic core module is also used to record one or more of the following information: the reason for suspending the running process on the slave logic core, the execution parameters corresponding to the target operation, the environment information when the running process is suspended, or, privilege level information; wherein, the privilege level information is used to indicate the privilege level of the privilege state of the master logic core when the process is executing the target operation.

[0038] Fourthly, embodiments of this application provide a chip system, including: a processor and a memory, wherein the processor is coupled to the memory, and the memory is used to store programs or instructions, wherein when the programs or instructions are executed by the processor, the chip system implements the methods in the first aspect or any possible implementation of the first aspect.

[0039] Fifthly, this application provides a computer program product, which includes a computer program or instructions that, when executed by a device, implement the method in the first aspect or any possible implementation of the first aspect.

[0040] In a sixth aspect, this application provides a computer-readable storage medium storing a computer program or instructions that, when executed by a computing device, implement the method in the first aspect or any possible implementation thereof.

[0041] In a seventh aspect, this application provides a computing device including a processor connected to a memory for storing a computer program, and the processor for executing the computer program stored in the memory to cause the computing device to perform the method in the first aspect or any possible implementation thereof.

[0042] The technical effects that can be achieved by any of the second to seventh aspects mentioned above can be referred to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of an ARMv8-A architecture;

[0044] Figure 2 This is a schematic diagram illustrating the process of switching between two execution states, AArch64 and AArch32.

[0045] Figure 3 A schematic diagram of a chip system architecture is provided for this application;

[0046] Figure 4 A schematic diagram of the running processes in a Master logic core and a Slave logic core provided in this application;

[0047] Figure 5 A flowchart illustrating a method for switching execution states provided in this application;

[0048] Figure 6 A schematic diagram of a startup process provided in this application;

[0049] Figure 7 A schematic diagram illustrating a method for switching the execution state of a process provided in this application;

[0050] Figure 8 A schematic diagram illustrating how a Master logic core traps a process to a target privilege level, as provided in this application;

[0051] Figure 9 A schematic diagram illustrating another method for switching the execution state of a process provided in this application;

[0052] Figure 10 A schematic diagram illustrating yet another method for switching the execution state of a process provided in this application;

[0053] Figure 11 A flowchart illustrating another method for switching execution states provided in this application. Detailed Implementation

[0054] To better explain the embodiments of this application, the relevant terms or technologies used in this application will be explained first:

[0055] (1) Programs and processes

[0056] A program is an ordered set of instructions; it is simply a static entity.

[0057] A process is the execution of a program on a specific dataset. A process is a dynamic entity with its own lifecycle. A process is created, runs due to scheduling, remains in a waiting state while awaiting resources or events, and is terminated upon completing its task. A process reflects the entire dynamic process of a program running on a given dataset.

[0058] (2) User mode and kernel mode

[0059] When a process is executing user code, it is in the user running state (also known as user mode). When a process is trapped in kernel code execution due to a system call, it is in the kernel running state (also known as kernel mode). The executed kernel code uses the current process's kernel stack; each process has its own kernel stack.

[0060] When a user runs a program, the process created by that program initially runs its own code in user mode. When the process needs to perform file operations, send network data, or perform other operations, it uses system calls such as `write` and `send` to invoke kernel code. The process then enters the kernel address space to execute the kernel code to complete the corresponding operation. After the kernel-mode process finishes executing, it returns to user mode. User-mode processes cannot arbitrarily manipulate the kernel address space.

[0061] (3) CPU, physical core, logic core

[0062] CPU is not the same as physical core, much less logical core.

[0063] A physical core (processor) is a visible, real CPU core. A physical core has independent circuitry and L1 and L2 caches, and can execute instructions independently.

[0064] Logical core (LCPU): A core at the logical level within the same physical core.

[0065] A CPU can have multiple physical cores. A physical core can be divided into multiple logical cores.

[0066] (4) Real-time operating system (kernel) refers to the core part of most operating systems. It consists of the parts of the operating system used to manage memory, files, peripherals and system resources.

[0067] (5) Executable and Linkable Format (ELF) files refer to object files on Unix and x86-64 Linux. Object files are computer files used to store object code. Object files may contain machine code, data used by the code during runtime, debugging information, etc., and are intermediate products in the process of generating program files from source code files.

[0068] (6) Synchronous and asynchronous operations

[0069] Synchronous operation refers to a process where the caller must wait for the call to return a result before continuing execution.

[0070] Asynchronous operations, as opposed to synchronous operations, do not require the caller to wait for the result after issuing the call. Instead, the callee continues to perform subsequent operations. The callee notifies the caller through its status or handles the call through a callback function.

[0071] (7) Reliability, availability, and serviceability (RAS)

[0072] Reliability refers to the system's ability to operate reliably for as long as possible, preventing unexpected crashes, restarts, or even physical damage. Availability refers to the system's ability to remain online for as long as possible, ensuring that minor issues do not disrupt its normal operation. Serviceability refers to the system's ability to provide convenient diagnostic functions, such as system logs and dynamic monitoring, to facilitate system diagnosis and maintenance by administrators, enabling early detection and repair of errors. RAS, as a whole, aims to ensure the entire system operates reliably for as long as possible without going offline, and possesses a sufficiently robust fault tolerance mechanism.

[0073] (8) Firmware is generally stored in electrically erasable programmable ROM (EEPROM) or FLASH chip in the device. For example, firmware is the basic input / output system (BIOS) on the computer motherboard.

[0074] (9) Registers are components within the Central Processing Unit (CPU). Registers are high-speed storage devices with limited capacity, used to temporarily store instructions, data, and addresses. The saved program status register (SPSR) is used to save the state of the current program status register (CPSR) so that the operating state at the time of the exception can be restored after an exception return. When a specific exception interrupt occurs, this register is used to store the contents of the current program status register. The SPSR can be used to restore the CPSR when exiting the exception interrupt.

[0075] Based on the above-mentioned terms or technical explanations, the following explanations illustrate the scenarios to which this application applies.

[0076] A CPU physical core can include a master logical core and slave logical cores. A CPU physical core can run multiple processes, which can run on either the master or slave logical core. For example, if the master logical core is an ARM64 logical core and the slave logical core is an ARM32 logical core, then an ARM64 process can run on the ARM64 logical core, and an ARM32 process can run on the ARM32 logical core. Normally, regardless of which logical core a process runs on, it can be started by the master logical core. If the master logical core determines that a process needs to run on a slave logical core, it can call the slave logical core to make the process run on the slave logical core.

[0077] The following example illustrates how an ARM64 logic core can start an ARM32 process and run the ARM32 process within the ARM32 logic core, using an ARM64 logic core as the Master logic core and an ARM32 logic core as the Slave logic core.

[0078] For example, in the ARMv8 architecture, both AArch32 (or ARM32) and AArch64 (or ARM64) execution states can be supported simultaneously. The AArch64 execution state supports the A64 instruction set and can run ARM64 processes. The AArch32 execution state supports the T32 and A32 instruction sets and can run ARM32 processes.

[0079] In ARMv8-A, the concept of privilege level is called exception level (EL), which is a logical division of the privilege level at which a program runs. Exception levels are divided into the following four types:

[0080] EL0: Normal user program;

[0081] EL1: Operating system kernel;

[0082] EL2: Virtual Machine Monitor;

[0083] EL3: Low-level firmware, including Security Monitor.

[0084] The higher the privilege level number, the higher the privilege level. Typically, a piece of software, such as an application, operating system kernel, or virtual machine monitor, occupies only one privilege level.

[0085] For the ARMv8-A architecture, please refer to [link / reference]. Figure 1As shown, the execution state of the ARM32 logic core is AARCH32, and the execution state of the ARM64 logic core is AARCH64. AARCH32 corresponds to the EL0 privilege level, and AARCH64 corresponds to both the EL0 and EL1 privilege levels. Alternatively, it can be understood that at the EL0 privilege level, user-mode processes can run in both the AARCH64 and AARCH32 execution states; at the EL1 privilege level, kernel-mode processes can run in the AARCH64 execution state.

[0086] Furthermore, the ARMv8-A architecture may have the following characteristics:

[0087] (1) The A32 and T32 instruction sets supported by AArch32, and the A64 instruction set supported by AArch64, can be encapsulated through execution state.

[0088] (2) The CPU must be in either AArch32 or AArch64 execution state at any time. When switching between the two execution states, the CPU needs to enter a higher privilege level through an exception.

[0089] (3) AArch32 and AArch64 are tightly coupled and can share registers.

[0090] (4) AArch32 and AArch64 cannot call each other (e.g., functions of the A64 instruction set cannot call functions of the A32 or T32 instruction sets), and AArch32 and AArch64 cannot be used as extensions of each other.

[0091] (5) To enable AArch64 to support AArch32 exception handling, a set of ARM32EL0 exception handling entries is added to the exception vector table. For example, the exception vector table includes the correspondence between exceptions and exception handlers. When an exception occurs, AArch32 needs to trap from a low privilege level to a high privilege level. When AArch64 is at a high privilege level, it accesses the exception vector table to determine the exception handler that needs to be scheduled.

[0092] like Figure 2 This application provides an example of a process for switching between two execution states, AArch64 and AArch32. Specifically, in the AArch64 execution state, an ARM32 executable program (which may be simply referred to as a program) is run.

[0093] Step 201: In the AArch64 execution state, the ARM32 process loaded in the EL0 user mode will enter the EL1 kernel mode. In the EL1 kernel, the ELF file format is parsed and it is found that the program to be run in the EL0 user mode is an A32 instruction set program. Therefore, when returning to the EL0 user mode, the execution state will be switched to the AArch32 execution state by setting SPSR, that is, the execution state is switched from AArch64 to AArch32.

[0094] Step 202: When an ARM32 process running in the AArch32 execution state needs to handle an exception, it needs to trap into the EL1 kernel mode, meaning the execution state switches back from AArch32 to AArch64. After handling the exception, the EL1 kernel mode returns to the AArch32 execution state in EL0 as needed. Alternatively, after the ARM32 process running in the AArch32 execution state finishes running, it needs to trap into the EL1 kernel mode to complete the task.

[0095] Therefore, the logic cores running in an ARM32 process need to frequently switch between ARM64 and ARM32 logic cores, requiring significant hardware work for this switching. Switching between ARM64 and ARM32 logic cores relies on exceptions recorded in an exception vector table and their corresponding handlers. This exception vector table is stored in registers and requires a large amount of register space. Since the ARM64 and ARM32 logic cores share registers, they are tightly coupled and cannot evolve independently.

[0096] This application provides a method and apparatus for switching the execution state of a process, which decouples two logical cores while flexibly switching the execution states of the two logical cores, thereby allowing one of the logical cores to evolve independently.

[0097] To facilitate the description of the switching method in this application, the system architecture to which this application applies will be explained first. For example... Figure 3 This is a schematic diagram of the architecture of a chip system, which includes multiple CPU physical cores. Each CPU physical core may include two logical cores, which can be represented as a Master logical core and a Slave logical core, respectively.

[0098] The Master logic core is used to execute privileged-mode operations, while the Slave logic core is used to execute user-mode operations. In privileged-mode, multiple privilege levels are higher than those in user-mode. For example, if the Master logic core is ARM64, the privileged modes implemented by the Master logic core correspond to three privilege levels: EL1, EL2, and EL3. The Slave logic core implements the user-mode privilege levels, where EL1, EL2, and EL3 are all higher than the user-mode privilege levels.

[0099] Furthermore, the Master logic core can also be used to execute user-mode operations, thus implementing user-mode privilege levels. Continuing with the example of an ARM64 Master logic core, the user-mode implemented by the Master logic core includes the EL0 privilege level. The user-mode privilege level implemented by the Master logic core can be the same as the user-mode privilege level implemented by the Slave logic core.

[0100] For example, user-mode programs can run on either the Master or Slave logical core, depending on their instruction set. System software (such as kernel / hypervisor / firmware) can only run on the Master logical core.

[0101] Furthermore, the Master and Slave logical cores use different instruction sets. The Master logical core can use mainstream instruction sets such as x86 or ARM, while the Slave logical core can use a custom-developed instruction set. The computing power of the Slave logical core can be higher than that of the Master logical core.

[0102] The process running on the Slave logic core (hereinafter referred to as the process) includes an executable code segment, which can be divided into two main parts: the trampoline code segment and the main code segment.

[0103] The jumper code segment runs on the Master logical core and is used to call the Slave logical core to run the process. It can be understood that since process loading occurs on the Master logical core, while process execution occurs on the Slave logical core, the jumper code segment in the Master logical core is needed to switch the process from running on the Master logical core to running on the Slave logical core.

[0104] The main code segment runs on the Slave logic core, where the main code segment is the main code of the running process.

[0105] Between the Master and Slave logical cores lies a configuration space, which can be understood as the interaction interface between the two logical cores. This configuration space can be a register set or a special memory space. This configuration space is used for information exchange between the Master and Slave logical cores. For example, when the Master logical core starts a process, it can determine that the process needs to run on the Slave logical core. Therefore, it writes the relevant parameters for the Slave logical core to the configuration space. The Slave logical core reads these parameters from the configuration space and starts executing the process based on the read parameters.

[0106] Each CPU physical core corresponds to an off-core resource, such as a cache or a memory management unit (MMU).

[0107] Multiple CPU physical cores and their corresponding external resources can be packaged together in a single chip system, which can be connected to memory and peripherals.

[0108] Taking the ARM64 logic core as an example, this explains the processes running in the Master and Slave logic cores. The Master instruction set in the ARM64 logic core is also known as the A64 instruction set, and processes running on the ARM64 logic core are also called A64 processes. For example... Figure 4 In this chip system, there are user mode, privileged mode, and hardware components. User-mode processes and system software (such as Kernel / Hypervisor / Firmware) of the A64 instruction set run on the ARM64 logical core, while user-mode processes (i.e., processes) of the Slave instruction set run on the Slave logical core.

[0109] The following explains the method for switching the execution state of a process in this application. This method can be found in [reference needed]. Figure 5 The flowchart shown.

[0110] Step 501: Start the process on the Master logical core, and ensure that the process needs to run on the Slave logical core. Start the Slave logical core so that it can run the process. When running the process on the Slave logical core, the process can only perform user-mode operations.

[0111] Step 502: When it is determined that the process needs to perform privileged operations, the execution state of the process is switched from user mode to privileged mode. Accordingly, the process needs to be switched to run in the Master logical core.

[0112] Step 503: After the process in the Master logical core has finished processing the privileged state operation, the execution state of the process can be switched back from privileged state to user state. Accordingly, the process is switched back to the Slave logical core to run.

[0113] When the execution state of the above process switches from privileged mode to user mode, or from user mode to privileged mode, the Master logical core and the Slave logical core can exchange information with each other through the configuration space.

[0114] Figure 6This is a schematic diagram illustrating the boot process of a Master logic core, provided as an example of this application. (Refer to...) Figure 6 The explanation of step 501 above is as follows: the text in the dashed box can represent the action performed by the Master logic core or the Slave logic core.

[0115] The Master logical core starts the running process in user mode and then transitions the process from user mode to privileged mode. The Master logical core loads the process's data from memory.

[0116] The data of a process includes its code segment / text segment, data segment, and executable file. The code segment typically stores the program's executable code in memory. The data segment usually stores initialized global variables within the program. Executable files are, for example, ELF files.

[0117] For example, the executable file of a process contains an identifier indicating whether the process needs to run on a Slave logical core. Accordingly, the Master logical core determines whether the process needs to run on a Slave logical core based on this identifier.

[0118] For another example, the Master logic core determines, based on the code segment, that the instruction set executed by the process belongs to the instruction set run by the Slave logic core, and thus determines that the process needs to run on the Slave logic core.

[0119] If the Master logical core determines that a process needs to run on the Slave logical core, it can return the process from privileged mode to the Slave logical core's user mode, allowing the Slave logical core to execute the process in user mode. Specifically, when the Master logical core returns the process from privileged mode to the Slave logical core's user mode, it can return the process to the entry point of the jump code segment in the Master logical core and write the process's entry point to the configuration space through the jump code segment, thereby triggering the Slave logical core to start executing the process from that entry point.

[0120] Specifically, the Master logic core can write the process's starting position (or starting position information) into the configuration space via a jump code segment. Then, the Master logic core manipulates the configuration space through the jump code segment to trigger a startup instruction (also known as a slave call instruction), thereby starting the Slave logic core via the slave call instruction. Correspondingly, the Slave logic core reads the starting position from the configuration space and starts the process based on the read starting position.

[0121] Furthermore, after invoking the slave call instruction, the Master logical core can release the physical core hardware resources occupied by the Master logical core while running a process. These hardware resources may include one or more of the following: memory resources and input / output (I / O) resources. In this way, the released hardware resources can be reused to execute other processes, helping to make full use of hardware resources.

[0122] Furthermore, the Master logic core writes the location of the next instruction after the slave call instruction (this location can be denoted as master.pc) into the configuration space. This master.pc can be used by the Master logic core to know from which position to start execution when it needs to execute the process again. This implementation method can be found in the description of step 502 in the following embodiments. For ease of description, the next instruction after the slave call instruction can be referred to as the master.pc instruction.

[0123] When a process is executed on the Slave logical core, there may be a situation where the process meets a first condition. This first condition indicates that the process needs to perform a privileged operation, which can be referred to as the target operation. Furthermore, the Slave logical core needs to pause the process currently running on it and then switch the process to be run by the Master logical core. In this way, the process running on the Master logical core can execute the target operation.

[0124] Furthermore, based on the different types of target operations, the pauses triggered by the target operation can be divided into exceptions and interruptions.

[0125] An exception refers to an event originating from within the CPU's execution of instructions. Exceptions can be further divided into Category I exceptions and Category II exceptions. Category I exceptions can be ordinary exceptions, while Category II exceptions can be RAS (Related Aspects of Memory) exceptions. Examples of RAS exceptions include physical corruption of memory pages. Ordinary exceptions are all exceptions other than RAS exceptions, such as system calls (or syscalls), page faults, and instruction faults.

[0126] An interrupt refers to an event that occurs outside of the CPU's instruction execution, such as a clock interrupt, serial port interrupt, network interrupt, or I / O interrupt. Taking a clock interrupt as an example, a clock interrupt indicates that a fixed time slice has elapsed, prompting the CPU to handle timing tasks, start timed tasks, etc.

[0127] The following explains step 502 based on three scenarios: normal exception, interruption, and RAS exception.

[0128] I. Common Abnormalities

[0129] Figure 7 This diagram illustrates a method for switching the execution state of a process when it triggers a common exception. The text within the dashed boxes represents the actions performed by either the Master or Slave logical cores.

[0130] During the execution of a process on the Slave logical core, a common exception is triggered because the process needs to perform a target operation. The Slave logical core needs to write the process's execution context (or common exception information) into the configuration space.

[0131] Ordinary exception information may include one or more of the following: privilege level information, the location of the instruction that triggered the exception, the cause of the exception, the address where the exception occurred, exception parameters, register information, etc.

[0132] The privilege level information indicates the privilege level corresponding to the target operation (also known as the target privilege level), that is, which privilege level the Master logic core needs to use to handle this exception. For example, if the target operation is a system call, then the target privilege level is EL1.

[0133] The instruction that triggered the exception can be considered the point where the process was interrupted, and can be denoted as slave.pc. When the slave logical core resumes execution, it can continue execution from that point slave.pc. The instruction corresponding to the point slave.pc can be called the slave.pc instruction.

[0134] The exception cause indicates the reason for suspending the running process from the logical core, or the reason that caused the exception, such as a system call, page fault, instruction failure, etc.

[0135] The address where the exception occurred, such as the location in memory that was accessed.

[0136] Exceptional parameters, such as parameters that need to be passed in a system call.

[0137] Register information indicates the runtime environment of the slave core when a process is paused in the slave core. This runtime environment information can be used by the slave core to resume process execution. Register information such as SPSR information is another example.

[0138] Correspondingly, the hardware resources corresponding to the Slave logical core can be retired at the instruction location that triggers the target operation. The Slave hardware unit then switches the process from running on the Slave logical core to running on the Master logical core. The Master logical core then reads the location master.pc in the configuration space and, based on that location master.pc, continues execution from the instruction following the slave call instruction in the jump code segment (i.e., the master.pc instruction).

[0139] It can be understood that the process's execution state switched from the user mode of the Slave logical core to the user mode of the Master logical core. The Master logical core needs to further switch the process from its user mode to its privileged mode. Specifically, the Master logical core can also read the process's common exception information in the configuration space and, based on this information, transfer the process's execution state from its user mode to its privileged mode. The Master logical core can determine the target privilege level to which the process will be transferred based on the privilege level information within the common exception information.

[0140] After the process gets stuck in the target privilege level, the Master logic core further executes the target operation, that is, handles the ordinary exception, based on the exception cause, exception address, exception parameters and other information in the ordinary exception information.

[0141] The following examples illustrate common exceptions, namely system call and page fault.

[0142] 1. System call

[0143] Furthermore, the exception parameters may include the system call identifier (syscall id) and system call input parameters.

[0144] The Master core can read the system call identifier and system call parameters from the ordinary exception information in the configuration space. Based on these two parameters, it constructs a system call and then issues it. In other words, the Master core in privileged mode sees this transformed system call. After the system call is executed, the Master core can write the return value of the system call to the configuration space, allowing the Slave core to read the return value from the configuration space.

[0145] For example, the Master logic core can construct the system call according to the application binary interface (ABI) rules of the architecture corresponding to the Master logic core, thus making it applicable to different CPUs. Correspondingly, the Master logic core still writes the return value of the system call to the configuration space according to the same ABI rules.

[0146] 2. Page error

[0147] Furthermore, the exception parameters may include the virtual page address corresponding to the page error.

[0148] The Master logical core can read virtual page addresses from ordinary exception information in the configuration space, allocate physical page addresses for those virtual page addresses, establish a mapping relationship between the virtual page addresses and physical page addresses, and update the page table. The virtual page address is also known as the virtual memory address, and the physical page address is also known as the physical memory address.

[0149] It should be noted that, due to the large number of common exceptions caused by processes, this application can determine the privilege level corresponding to different common exceptions. It can be understood that one privilege level can correspond to multiple common exceptions; for example, the EL1 privilege level corresponds to system calls, page faults, instruction failures, etc. When such exceptions occur, the Master logical core can trap the process to the EL1 privilege level for processing.

[0150] In one possible implementation, the Master kernel transfers the process's execution state from the user mode of the Master kernel to the target privilege level of the Master kernel's privileged mode. This can be achieved by constructing a special exception. See [link to details]. Figure 8 The trapping method is shown.

[0151] It should be noted beforehand that two virtual page addresses can be added to a real-time operating system. These two virtual page addresses correspond to two privilege levels in privileged mode (specifically, kernel mode). For example, the two privilege levels in kernel mode are EL1 and EL2, where virtual page address 1 corresponds to EL1 and virtual page address 2 corresponds to EL2. Furthermore, these two virtual page addresses are not mapped to physical page addresses.

[0152] Accordingly, the Master kernel can select the target privilege level corresponding to the common exception triggered by the Slave kernel from multiple privilege levels corresponding to privileged mode. Then, it determines the virtual page address corresponding to the target privilege level from multiple virtual page addresses. The Master kernel accesses the virtual page address corresponding to the target privilege level by executing a page access instruction. If it determines that the virtual page address does not have a mapping relationship with the physical page address, it will trigger an exception (i.e., a page fault). Subsequently, the Master kernel enters the target privilege level from user mode.

[0153] For example, the Master kernel determines that the exception triggered by the process is a system call. Based on the system call, the Master kernel determines that the process needs to be trapped in the EL1 privilege level. The Master kernel accesses virtual page address 1 and determines that the current virtual page address 1 does not correspond to a physical page address, i.e., virtual page address 1 access error. Subsequently, the Master kernel triggers a page fault exception and traps the process in the EL1 privilege level. In this way, the process runs in the EL1 privilege level of the Master kernel, and the Master kernel can perform the target operation, i.e., handle the system call.

[0154] Here, there is no need to perform page fault handling for the page fault triggered by the Master logical core accessing the virtual page address. In this way, the Master logical core can repeatedly trigger the page fault exception, thereby changing the execution state of the process from the user mode of the Master logical core to the target privilege level of the privileged mode of the Master logical core.

[0155] Furthermore, the page fault here is used to transfer the execution state of the process from the user mode of the Master logical core to the target privilege level of the privileged mode of the Master logical core. This page fault is different from the page fault triggered when the Slave logical core is running the process, the latter being the actual exception that needs to be handled during process execution.

[0156] After the Master logical core completes the target operation in privileged mode (or handles a normal exception), it can return to the jump code segment. Specifically, the Master logical core can return to the page access instruction in the jump code segment. After the page access instruction, the Master logical core continues to execute the slave call instruction, thereby triggering the Slave logical core to run. The Slave logical core then resumes execution from the interrupted location, slave.pc. Furthermore, the Slave logical core can read register information from the normal exception information in the configuration space and, based on the read register information, restore the runtime environment information of the process before the Slave logical core triggered the exception.

[0157] II. Interruption

[0158] Figure 9 This diagram illustrates a method for switching the execution state of a process when it receives an interrupt. The text within the dashed boxes represents the actions performed by either the Master or Slave logical cores.

[0159] If a process is interrupted during the execution of a Slave logical core, the Slave logical core needs to write the process's execution context (or interrupt information) into the configuration space.

[0160] Interrupt information may include one or more of the following: privilege level information, the location of the instruction that received the interrupt, the interrupt cause, the interrupt address, interrupt parameters, and register information. The privilege level information, interrupt parameters, register information, and interrupt address can all be found in the description of the runtime context in the above-mentioned general exceptions.

[0161] The location where the interrupted instruction was received can also be recorded as slave.pc. When the slave logic core resumes execution, it can continue execution from that location slave.pc.

[0162] Interrupt reason indicates the cause of the interrupt, such as clock interrupt, serial port interrupt, network interrupt, etc.

[0163] Since interrupts are asynchronous events and need to be processed quickly, the hardware unit of the Slave logic core can trap the execution state of the process into a privileged state. Here, the hardware unit of the Slave logic core can also determine which privilege level the process should be trapped into, such as EL1 or EL2, depending on the type of interrupt.

[0164] From the perspective of the Master core, the interrupt occurs in master.pc. This means that many operations occur during the execution of the slave core's `salve.call` instruction, such as the Master core going to sleep and the slave core triggering the execution of instructions. For the Master core, the interrupt occurs during the execution of `salve.call`, and the Master core responds to the interrupt after `salve.call` has finished executing but before the next instruction (i.e., the `master.pc` instruction) is executed.

[0165] After the Master logic core completes the target operation (or handles the interrupt) in privileged mode, it returns to master.pc in the jumper code segment. Subsequently, the Master logic core continues to execute the slave call instruction to trigger the Slave logic core to run, and the Slave logic core resumes execution from the interrupted position slave.pc.

[0166] III. RAS Abnormalities

[0167] Figure 10 This diagram illustrates a method for switching the execution state of a process when it triggers a RAS (Real-Time Analysis) exception. The text within the dashed boxes represents the actions performed by either the Master or Slave logical cores.

[0168] RAS exceptions can be further divided into synchronous aborts (SErrors) and asynchronous aborts (SEI).

[0169] SErrors are related to instruction execution. The return address maintained by SErrors when entering an exception state precisely reflects the instruction that caused the exception, which could occur at any step in the instruction execution process. For example, it could fail during the instruction fetch phase, the decode phase, or the instruction execution phase. Similar to ordinary exceptions, SErrors are synchronous events.

[0170] SEI is independent of the executed instructions. SEI originates from the external memory system or from errors on the bus, such as unrecoverable error correcting code errors (ECC errors). Similar to interrupts, SEI is an asynchronous event.

[0171] During the execution of a process on the Slave logical core, a RAS exception is triggered because the process needs to perform a target operation. The Slave logical core needs to write the process's execution context (or RAS exception information) into the configuration space.

[0172] The RAS exception information may include one or more of the following: privilege level information, the instruction location that triggered the RAS exception, the cause of the RAS exception, the address where the RAS exception occurred, the RAS exception parameters, register information, etc.

[0173] Privilege level information, RAS exception parameters, register information, and the address where the RAS exception occurred can all be found in the description of the runtime context in the above-mentioned ordinary exceptions.

[0174] The instruction that triggered the RAS exception can also be recorded as slave.pc. When the slave logical core resumes execution, it can continue execution from that slave.pc.

[0175] The RAS anomaly cause indicates the reason for the RAS anomaly, such as an error correction code error.

[0176] The hardware unit of the Slave logical core can transfer the execution state of a process from user mode to privileged mode. Specifically, privileged mode can be firmware mode, for example, corresponding to the EL3 privilege level. Accordingly, the hardware unit of the Slave logical core can transfer the execution state of a process to the EL3 privilege level. In RAS exceptions, user mode can also be referred to as the EL0 privilege level within privileged modes, which is lower than other privilege levels within privileged modes.

[0177] From the perspective of the privileged state of the Master core, the RAS exception occurs in master.pc. This can be explained by the fact that many operations occur during the execution of the slave core's `salve.call` instruction, such as the Master core going to sleep and the slave core triggering the execution of instructions. For the Master core, the RAS exception occurs during the execution of `salve.call`, and the Master core responds to the RAS exception after the `salve.call` instruction has finished executing and before the next instruction (i.e., the `master.pc` instruction) is executed.

[0178] The Master logical core handles RAS exceptions in EL3 privilege level and obtains the RAS exception handling result. The RAS exception handling result can be used to indicate whether the RAS exception is recoverable. The Master logical core returns from EL3 privilege level to EL1 privilege level, or in other words, from firmware mode to kernel mode.

[0179] Correspondingly, the Master logical core obtains the handling result of the RAS exception at the EL1 privilege level. If the RAS exception is determined to be recoverable based on the handling result, the Master logical core executes the target operation at the EL1 privilege level and returns to the instruction corresponding to the master.pc location recorded in the configuration space (i.e., the master.pc instruction). If the RAS exception is determined to be unrecoverable based on the handling result, the Master logical core executes panic kernel processing at the EL1 privilege level.

[0180] In one possible approach, when the Master logical core handles RAS exceptions in the EL3 privilege level, specifically, the Master logical core's firmware may perform the following steps (a) to (c):

[0181] (a) Save the user-mode context and restore the EL3 privileged context.

[0182] (b) Read the RAS exception information in the configuration space and handle the RAS exception according to the RAS exception information, such as trying to repair the memory pages.

[0183] (c) Save the EL3 privilege level context, restore the user mode context, and set the ESR_EL1, FAR_EL1, SPSR_EL1 and other registers. Since the EL1 privilege level obtains some statuses of exceptions through these registers, the purpose of setting these registers is to make the EL1 privilege level think that the source of the exception is user mode. After the EL1 privilege level handles the exception, it returns to user mode through the ERET instruction, instead of returning to the Fireware corresponding to the EL3 privilege level.

[0184] After the Master logic core completes the privileged processing of the target operation, it returns to the master.pc instruction in the jumper code segment. Subsequently, the Master logic core continues to execute the slave call instruction, triggering the Slave logic core to run. The Slave logic core then resumes execution from the interrupted point, slave.pc.

[0185] It should be noted that the aforementioned ordinary exception information, interrupt information, and RAS exception information can all be collectively referred to as the process's execution context. Specifically, the exception cause, interrupt cause, and RAS exception cause can all be referred to as the reason for suspending the process on the Slave logical core, i.e., the process's suspension reason. Exception parameters, interrupt parameters, and RAS exception parameters can all be referred to as the execution parameters corresponding to the process's target operation. The instruction location that triggered the exception, the instruction location that received the interrupt, and the instruction location that triggered the RAS exception can all be referred to as the location where the process was interrupted, or the process's suspension location (slave.pc), or information about the process's suspension location. Alternatively, the process's execution context can be understood to include one or more of the following: the suspension location of the process suspended on the Slave logical core, the suspension reason for the process suspended on the Slave logical core, the execution parameters corresponding to the target operation, register information (i.e., the environment information when the process was suspended), or privilege level information.

[0186] In addition, it should be added that the above Figures 6 to 10 The main steps in the relevant embodiments are marked, and the step numbers in each figure only indicate the order of the actions in the figure in which they are located.

[0187] To better illustrate the execution locations of the Master and Slave logical cores under normal exception, interruption, or RAS exception conditions in the embodiments of this application, refer to... Figure 11 The following example further illustrates this point. Figure 11 The code segment on the left can be considered as the jump board code segment contained in the Master logic core.

[0188] The Slave kernel runs the process and determines that the process has triggered a normal exception. The Slave kernel then switches the process's execution state from its user mode to the Master kernel's user mode. The Master kernel begins execution from the instructions at master.pc (i.e., the master.pc instructions) and, based on the normal exception, determines that it needs to be handled at the EL1 privilege level. Therefore, it accesses the virtual page address 1 corresponding to the EL1 privilege level. Figure 11 (Represented as page1). Subsequently, after the Master logical core triggers the page fault exception corresponding to page1, it traps the process execution state to the EL1 privilege level to execute the target operation. After completing the target operation, the Master logical core returns to the instruction that accessed page1 (i.e., the page access instruction), and then returns to instruction 1. Further, the Master logical core calls the slave.call instruction, triggering the Slave logical core to run, and the Slave logical core continues execution from the interrupted position slave.pc.

[0189] The slave kernel runs the process and determines that the process has been interrupted. The slave kernel's hardware unit directly transfers the process's execution state from the slave kernel's user mode to the master kernel's privileged state (e.g., EL1 privilege level). The master kernel then runs the process to execute the target operation. After the process completes the target operation, it returns to the instruction at the master.pc location (i.e., the master.pc instruction), and then returns to instruction 1. Further, the master kernel calls the slave.call instruction, triggering the slave kernel to run, and the slave kernel resumes execution from the interrupted location at slave.pc.

[0190] The slave kernel runs the process and determines that the process has triggered a RAS exception. The slave kernel's hardware unit directly transfers the process's execution state from the slave kernel's user mode to the master kernel's privileged mode (e.g., EL3 privilege level). The master kernel runs the process to execute the target operation. After the process completes the target operation, it returns to the instruction at master.pc (i.e., the master.pc instruction), and then returns to instruction 1. The master kernel calls the slave.call instruction, triggering the slave kernel to run, and the slave kernel resumes execution from the interrupted position at slave.pc.

[0191] In the above technical solution, the Master and Slave logical cores interact through a configuration space, achieving decoupling between them. This allows the Master and Slave logical cores to evolve independently; that is, without disrupting the architecture semantics / instruction space of the Master logical core, the instruction set of the Slave logical core can evolve independently. Consequently, the Slave logical core can run acceleration engines and algorithms, such as MySQL processes, graph computation processes, or one or more encryption / decryption operators, resulting in increased computational speed compared to the Master logical core.

[0192] Furthermore, when a process running on a Slave logical core needs to execute a target operation, the Slave logical core can write the process's execution context to the configuration space. This execution context includes the pause position corresponding to the paused execution of the process by the Slave logical core. Correspondingly, after the Master logical core completes the target operation for the process, it can start the Slave logical core to continue running the process. Subsequently, the Slave logical core can read the pause position from the configuration space and continue executing the process from that pause position. In this way, the running state of a process can be switched between the Master and Slave logical cores.

[0193] It should be added that, in this application, the relationship between the logical core, the process, and the target operation can be understood as follows: the process runs in the logical core (Slave logical core or Master logical core), and the process executes the target operation, which is the logical core (such as the Master logical core) in which it runs executes the target operation.

[0194] Based on the above content and the same concept, this application provides a computer program product, which includes a computer program or instructions that, when executed by a device, implement the method in the above method embodiments.

[0195] Based on the above content and the same concept, this application provides a computer-readable storage medium storing a computer program or instructions, which, when executed by a computing device, implements the method in the above method embodiments.

[0196] Based on the above content and the same concept, this application provides a computing device, including a processor connected to a memory for storing computer programs, and the processor for executing the computer programs stored in the memory, so that the computing device implements the methods in the above method embodiments.

[0197] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

[0198] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for switching the execution state of a process, characterized in that, Applied to a central processing unit (CPU), the CPU comprising physical cores, the physical cores including a master logical core and slave logical cores, the method comprising: If the process running on the slave logic core meets the first condition, the process is paused in the slave logic core and the pause position of the process is recorded. The pause position is used to determine the execution position when the process runs on the slave logic core next time. The first condition is used to indicate that the process is to perform a target operation, and the target operation can be executed when the execution state of the process is in the privileged state of the master logic core. Switch the execution state of the process from the user mode of the slave logic core to the privileged mode of the master logic core; The process runs in the main logic core so that the process can perform the target operation.

2. The method as described in claim 1, characterized in that, The recording of the pause position of the process includes: The pause position information is written into the configuration space by the slave logic core, and the configuration space is used for information interaction between the master logic core and the slave logic core.

3. The method as described in claim 2, characterized in that, The method further includes: Switch the execution state of the process from the privileged state of the main logic core to the user state of the slave logic core; The pause position information is read from the configuration space from the logic core; In the logic core, the process resumes execution from the paused position.

4. The method as described in claim 1, characterized in that, The first condition includes the process triggering a first type of exception, which includes exceptions other than reliability exceptions, availability exceptions, and serviceability RAS exceptions. Switching the execution state of the process from the user mode of the slave logic core to the privileged mode of the master logic core includes: The main logic core is triggered to run the process, so as to switch the execution state of the process from the user mode of the slave logic core to the user mode of the main logic core; The target privilege level corresponding to the first type of exception is determined from multiple privilege levels of the privileged state of the main logic core; The execution state of the process is switched from the user mode of the main logic core to the target privilege level of the privileged mode of the main logic core.

5. The method as described in claim 4, characterized in that, Before switching the execution state of the process from the user mode of the main logic core to the target privilege level of the privileged mode of the main logic core, the method further includes: Obtain the virtual memory address corresponding to the target privilege level; It was determined that the virtual memory address was not mapped to the physical memory address.

6. The method as described in claim 1, characterized in that, The first condition includes the process being interrupted or the process triggering a RAS exception.

7. The method as described in claim 1, characterized in that, The method further includes: The process is started in the main logic core; If the instruction set of the process belongs to the instruction set executed by the slave logical core, record the starting position of the process and trigger the slave logical core to enter the running state; In the logical core, the process starts running from the starting position.

8. The method as described in claim 1, characterized in that, The method further includes: Release the hardware resources of the physical core occupied by the main logic core when running the process; The hardware resources include memory resources and / or input / output resources.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: The following information is recorded from the logic core: The reasons for suspending the process on the main logic core, the execution parameters corresponding to the target operation, the environment information when suspending the process, or the privilege level information; wherein, the privilege level information is used to indicate the privilege level of the main logic core when the process executes the target operation.

10. A switching device for an execution state, characterized in that, Including processor and memory; The memory is used to store computer programs; The processor is used to invoke the computer program stored in the memory to perform the following steps: If a process running on a slave logical core meets a first condition, the process is paused in the slave logical core, and the pause position of the process is recorded. The pause position is used to determine the execution position when the process runs on the slave logical core next time. The first condition is used to indicate that the process is to perform a target operation, and the target operation can be executed when the process's execution state is in the privileged state of the main logical core. Switch the execution state of the process from the user mode of the slave logic core to the privileged mode of the master logic core; The process runs in the main logic core so that the process can perform the target operation.

11. The apparatus as claimed in claim 10, characterized in that, When the processor records the pause position of the process, it is specifically used to: write the pause position information into the configuration space through the slave logic core, the configuration space being used for information interaction between the master logic core and the slave logic core.

12. The apparatus as claimed in claim 11, characterized in that, The processor is also used for: Switch the execution state of the process from the privileged state of the main logic core to the user state of the slave logic core; The pause position information is read from the configuration space from the logic core; In the logic core, the process resumes execution from the paused position.

13. The apparatus as claimed in claim 10, characterized in that, The first condition includes the process triggering a first type of exception, which includes exceptions other than reliability exceptions, availability exceptions, and serviceability RAS exceptions. When the processor switches the execution state of the process from the user mode of the slave logic core to the privileged mode of the master logic core, it specifically performs the following operations: The main logic core is triggered to run the process, so as to switch the execution state of the process from the user mode of the slave logic core to the user mode of the main logic core; The target privilege level corresponding to the first type of exception is determined from multiple privilege levels of the privileged state of the main logic core; The execution state of the process is switched from the user mode of the main logic core to the target privilege level of the privileged mode of the main logic core.

14. The apparatus as claimed in claim 13, characterized in that, Before switching the execution state of the process from the user mode of the main logic core to the target privilege level of the privileged mode of the main logic core, the processor is further configured to: Obtain the virtual memory address corresponding to the target privilege level; It was determined that the virtual memory address was not mapped to the physical memory address.

15. The apparatus as claimed in claim 10, characterized in that, The first condition includes the process being interrupted or the process triggering a RAS exception.

16. The apparatus as claimed in claim 10, characterized in that, The processor is also used for: The process is started in the main logic core; If the instruction set of the process belongs to the instruction set executed by the slave logical core, record the starting position of the process and trigger the slave logical core to enter the running state; In the logical core, the process starts running from the starting position.

17. The apparatus as claimed in claim 10, characterized in that, The processor is also used for: Release the physical core hardware resources occupied by the main logic core when running the process; The hardware resources include memory resources and / or input / output resources.

18. The apparatus as claimed in any one of claims 10 to 17, characterized in that, The processor is also used for: The following information is recorded from the logic core: The reasons for suspending the process on the main logic core, the execution parameters corresponding to the target operation, the environment information when suspending the process, or the privilege level information; wherein, the privilege level information is used to indicate the privilege level of the main logic core when the process executes the target operation.

19. A computer program product, characterized in that, The computer program product includes a computer program or instructions that, when executed by a device, implement the method as described in any one of claims 1 to 9.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed by a computing device, implement the method as described in any one of claims 1 to 9.

21. A computing device, characterized in that, The device includes a processor connected to a memory for storing computer programs, and the processor is configured to execute the computer programs stored in the memory to cause the computing device to perform the method as described in any one of claims 1 to 9.

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