Configurable imaging resolution Multi-spectral TDI-CMOS image sensor

Abstract

The present invention discloses a multi-spectral TDI-CMOS image sensor with configurable imaging resolution, comprising: a multi-spectral pixel array, a timing drive circuit, a digital binning readout circuit and a configuration circuit; wherein the multi-spectral pixel array converts an optical signal into an image electrical signal, and transmits the image electrical signal to the digital binning readout circuit; the digital binning readout circuit receives the image electrical signal, performs digital quantization and horizontal digital binning operations on the image electrical signal, and outputs a processed digital image; the timing drive circuit provides the multi-spectral pixel array with a timing sequence for normal operation; the configuration circuit sets the working modes of the timing drive circuit and the digital binning readout circuit, and detects the working state of the circuit at the same time. The present invention meets the system's requirements for resolution and signal-to-noise ratio, and reduces the resource occupation of off-chip data storage and data processing.

Description

Technical Field

[0001] The invention belongs to the technical field of TDI CMOS image sensors, and in particular relates to a multi-spectral TDI-CMOS image sensor with configurable imaging resolution. Background Art

[0002] TDI (Time Delay Integration) technology uses a time delay integration method, which is suitable for imaging high-speed moving objects. It accumulates signals by repeatedly observing the target in multiple pixels along the direction of motion in a spatial domain image, and transforms it into a series of image electrical signals distributed in the time domain. Based on multiple exposures of the same target, the TDI image detector chip increases the collection of light energy exponentially according to the integration series through the delayed integration method. Compared with general single-line array CCD and CMOS image detector chips, it has the advantages of high imaging sensitivity, high responsiveness, and wide dynamic range. It can also output high signal-to-noise ratio signals in dark places, which can greatly improve the disadvantage of low signal-to-noise ratio caused by poor lighting conditions, which makes it difficult to see the target.

[0003] Traditional TDI detectors are implemented using an independent CCD process, which is incompatible with advanced CMOS technology, resulting in low CCD device integration, high power consumption, and complex peripheral circuit structure. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a multi-spectral TDI-CMOS image sensor with configurable imaging resolution, to meet the system's requirements for resolution and signal-to-noise ratio, and to reduce the resource occupation of off-chip data storage and data processing.

[0005] The object of the present invention is achieved through the following technical solutions: a multi-spectral TDI-CMOS image sensor with configurable imaging resolution, comprising: a multi-spectral pixel array, a timing drive circuit, a digital binning readout circuit and a configuration circuit; wherein the multi-spectral pixel array converts an optical signal into an image electrical signal, and transmits the image electrical signal to the digital binning readout circuit; the digital binning readout circuit receives the image electrical signal, performs digital quantization and horizontal digital binning operations on the image electrical signal, and outputs a processed digital image; the timing drive circuit provides the multi-spectral pixel array with a timing for normal operation; the configuration circuit sets the working mode of the timing drive circuit and the digital binning readout circuit, and detects the working state of the circuit at the same time.

[0006] In the above-mentioned imaging resolution configurable multi-spectral TDI-CMOS image sensor, the multi-spectral pixel array includes multiple spectral partitions; wherein each pixel in each spectral partition has the same structure, each pixel in each spectral partition has an equal size, and the pixel spacing in each spectral partition is equal.

[0007] In the above-mentioned imaging resolution configurable multi-spectral band TDI-CMOS image sensor, each spectral band partition is a rectangular area, wherein the number of pixels in the horizontal direction of the rectangular area determines the maximum resolution n of the image sensor in the non-binning mode, and the number of pixels in the vertical direction of the rectangular area determines the maximum TDI level m of the image sensor in the non-binning mode.

[0008] In the above-mentioned imaging resolution configurable multi-spectral band TDI-CMOS image sensor, the timing drive circuit includes multiple sub-timing drive circuits, wherein the number of sub-timing drive circuits is equal to the number of spectral band partitions; each sub-timing drive circuit provides normal working timing to the spectral band partition corresponding to each sub-timing drive circuit.

[0009] In the above-mentioned imaging resolution configurable multi-spectral band TDI-CMOS image sensor, the digital binning readout circuit includes a programmable gain amplifier, an analog-to-digital converter, a horizontal digital domain binning unit, a data processing circuit and an image interface circuit; wherein the programmable gain amplifier amplifies the image electrical signal to obtain an amplified image electrical signal, and transmits the amplified image electrical signal to the analog-to-digital converter; the analog-to-digital converter receives the amplified image electrical signal, converts the amplified image electrical signal into an image digital signal, and transmits the image digital signal to the horizontal digital domain binning unit; the horizontal digital domain binning unit receives the image digital signal, performs a horizontal digital binning operation on the image digital signal according to the working mode of the data processing circuit, obtains a processed digital image, and transmits the processed digital image to the image interface circuit.

[0010] In the above-mentioned imaging resolution configurable multi-spectral TDI-CMOS image sensor, the mode selection bit 1 and the mode selection bit 0 of the working mode of the data processing circuit are assigned a value of "X0" to represent a non-binning output mode, wherein X represents any value of 0 or 1, a value of "01" to represent a horizontal × 2 binning output mode, and a value of "11" to represent a horizontal × 4 binning output mode.

[0011] In the above-mentioned imaging resolution configurable multi-spectral band TDI-CMOS image sensor, the horizontal digital domain binning unit includes a first-level dual-channel data selection circuit, a second-level dual-channel data selection circuit, a first-level adder, a second-level adder, and a saturation judgment circuit; wherein, the analog-to-digital converter is four-channel; the image digital signals of the four-channel analog-to-digital converter pass through the first-level dual-channel data selection circuit, when the mode selection bit 0 is set to "0", the four-channel image digital signals are directly output, when the mode selection bit 0 is set to "1", the first two-channel four-channel image digital signals and the last two-channel four-channel image digital signals of the four-channel image digital signals are respectively input into the first-level adder for addition, and the summation result is input into the second-level dual-channel data selection circuit; when the mode selection bit 1 is set to "0", the two addition results pass through the saturation judgment circuit, if the result is saturated, the saturation flag bit will be set; when the mode selection bit 1 is set to "1", the two addition results are input into the second-level adder for summation, the summation passes through the saturation judgment circuit, if the result is saturated, the saturation flag bit will be set.

[0012] In the imaging resolution configurable multi-spectral band TDI-CMOS image sensor, the pixels in the spectral band partitions adopt the CCD working principle, and each pixel has multiple transfer electrodes, which are divided into two-phase CCD, three-phase CCD and four-phase CCD.

[0013] In the above imaging resolution configurable multi-spectral TDI-CMOS image sensor, the pixel is a two-phase CCD, and the TDI level is 32 levels, wherein the level 1 pixel of the pixels from level 2 to level 32 outputs a signal to the pixel output circuit through the TX gate signal of the control transmission tube TG, and the charge signal is converted into an analog voltage signal output through the pixel circuit.

[0014] In the above-mentioned imaging resolution configurable multi-spectral TDI-CMOS image sensor, the digital binning readout circuit includes a top digital binning readout circuit and a bottom digital binning readout circuit; wherein the top digital binning readout circuit is located at the top of the multi-spectral pixel array, and the bottom digital binning readout circuit is located at the bottom of the multi-spectral pixel array.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] (1) The present invention can be applied to the field of multi-spectral remote sensing imaging of the aerospace industry. Different scenes can be imaged with different resolutions to improve the signal-to-noise ratio of the system and reduce the pressure of processing massive amounts of data outside the chip.

[0017] (2) The present invention implements pixel binning within the image sensor chip, reducing the off-chip data processing pressure of the massive image sensor. There is no need to perform off-chip binning operations on the data within the peripheral FPGA. On-chip processing reduces the amount of output data and reduces the off-chip storage and processing resource usage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0019] Figure 1 It is a structural block diagram of a multi-spectral TDI-CMOS image sensor with configurable imaging resolution provided by an embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of the direction definition of a spectral band region in a pixel array provided by an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a single-column pixel array circuit provided by an embodiment of the present invention;

[0022] Figure 4 is a diagram of a digital binning readout circuit architecture provided by an embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of a horizontal digital domain binning unit provided by an embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of five binning modes provided by an embodiment of the present invention;

[0025] Figure 7 It is a cross-sectional diagram of a two-phase CCD pixel and a pixel output circuit and a vertical × 2 binning timing diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] With the continuous advancement of semiconductor process technology, CMOS image sensors have completely replaced CCD in the civilian field, and TDI-CMOS image sensors have also begun to gradually replace TDI-CCD in the high-end field.

[0028] The technical routes to realize TDI include charge domain accumulation, analog domain accumulation and digital domain accumulation. The charge domain accumulation process does not introduce additional noise and has a fast accumulation speed, so it is the most mainstream technology. The analog accumulation op amp introduces noise and the circuit layout area is large, so it only appears in academic research. Digital domain accumulation has high requirements for data storage and processing resources, and digital TDI is mainly realized by digital domain accumulation in area array CMOS.

[0029] The most typical application of TDI technology is in the field of aerospace remote sensing. To obtain richer information about the scene, it is necessary to select a specific spectrum and resolution based on the characteristics of the scene. Different scenes have different reflectivities and different application scenarios, which places specific requirements on the number of spectral bands, imaging spatial resolution, and signal-to-noise ratio. Currently, there is no TDI-CMOS image sensor with multiple spectral bands and imaging resolution that can be configured according to the application. If there are scenes with high signal-to-noise ratio requirements, off-chip digital binning operations are required, which takes up a lot of storage and processing resources of the off-chip processor.

[0030] Figure 1 : is a structural block diagram of a multi-spectral TDI-CMOS image sensor with configurable imaging resolution provided by an embodiment of the present invention. Figure 1 As shown, the imaging resolution configurable multi-spectral TDI-CMOS image sensor includes a multi-spectral pixel array, a timing drive circuit, a digital binning (merging) readout circuit and a configuration circuit; wherein,

[0031] The multi-spectral pixel array converts the optical signal into an image electrical signal, and transmits the image electrical signal to the digital binning readout circuit; the digital binning readout circuit receives the image electrical signal, performs digital quantization and horizontal digital binning operations on the image electrical signal, and outputs the processed digital image; the timing drive circuit provides the multi-spectral pixel array with a timing sequence for normal operation; the configuration circuit sets the working mode of the timing drive circuit and the digital binning readout circuit, and detects the working status of the circuit at the same time.

[0032] The multi-spectral pixel array consists of multiple spectral partitions. The number of spectral partitions can be designed according to application requirements and manufacturing costs. The pixel structure, pixel size and pixel spacing of each spectral partition are equal. Its function is to convert optical signals into electrical signals.

[0033] The pixels in the spectral partition adopt the CCD working principle. The charge signal after photoelectric conversion is subjected to vertical charge transfer and charge accumulation under the action of electrode timing.

[0034] The timing driving circuit includes a plurality of sub-timing driving circuits, each of which is identical, and the number of sub-circuits is consistent with the number of spectrum partitions in the multi-spectral pixel array. The timing driving circuit is used to provide a timing for the multi-spectral pixel array to work normally. Each sub-timing driving circuit provides a timing for the spectrum partition corresponding to each sub-timing driving circuit to work normally.

[0035] like Figure 4 As shown, the digital binning readout circuit includes a programmable gain amplifier, an analog-to-digital converter, a horizontal digital domain binning unit, a data processing circuit and an image interface circuit; wherein,

[0036] The programmable gain amplifier amplifies the image electrical signal to obtain an amplified image electrical signal, and transmits the amplified image electrical signal to the analog-to-digital converter; the analog-to-digital converter receives the amplified image electrical signal, converts the amplified image electrical signal into an image digital signal, and transmits the image digital signal to the horizontal digital domain binning unit; the horizontal digital domain binning unit receives the image digital signal, performs a horizontal digital binning operation on the image digital signal according to the working mode of the data processing circuit, obtains a processed digital image, and transmits the processed digital image to the image interface circuit.

[0037] The configuration circuit includes a register and a bus configuration circuit, which is used to set the working mode of the timing drive circuit and the readout circuit, and detect the working status of the circuit.

[0038] The configuration circuit is connected to the timing driving circuit and the digital binning readout circuit, and can respectively configure the working modes of each sub-timing circuit in the timing circuit and configure the working modes of all digital binning readout circuits.

[0039] The timing drive circuit is located on the left side of the pixel, and the output drive signal is connected to the corresponding spectral partition of the multi-spectral pixel array, providing vertical transfer and readout timing signals for the pixel.

[0040] The digital binning readout circuit is located at the top and bottom of the multi-spectral pixel array and is connected to each spectral partition. The analog image signal output by the pixel is input to the PGA circuit in the digital binning readout circuit.

[0041] The configurable imaging resolution function is achieved through on-chip hybrid domain binning technology, which is implemented through vertical charge domain binning technology and horizontal digital domain binning technology. It can realize binning modes such as 1×1, 1×2, 2×2, 2×3, and 4×4.

[0042] The vertical charge domain binning technology is switched by configuring the timing drive circuit working mode.

[0043] The horizontal digital domain binning technology is implemented by configuring the horizontal digital domain binning unit in the readout circuit and the working mode of the data processing circuit.

[0044] Each spectral band of a multi-spectral pixel array is a rectangular area, such as Figure 2 As shown, the number of pixels in the horizontal direction determines the maximum resolution n of the image sensor in non-binning mode, the vertical direction is the TDI direction of the TDI type image sensor, and the number of pixels in the vertical direction determines the maximum TDI level m of the image sensor in non-binning mode.

[0045] Figure 3 It is a single-column pixel array, in which the pixel structure is a two-phase CCD, the TDI level is m, and the 1st-level pixel outputs the signal to the pixel output circuit through the transmission tube TG. The charge signal is converted into an analog voltage signal output through the pixel circuit.

[0046] The digital binning readout circuit receives analog image data output by the pixel, and the signal is converted into digital image data through PGA, ADC, horizontal digital domain binning unit, data processing circuit and image interface circuit in sequence. The digital binning readout circuit can perform horizontal digital domain binning operation on the data.

[0047] The horizontal digital domain binning unit can process the 4-channel ADC output data. The configuration circuit selects the working mode by assigning the mode selection bit. The horizontal digital domain binning unit can output non-binning data, horizontal × 2 binning data and horizontal × 4 binning data. The unit can judge whether the data after binning is saturated and output the saturation flag bit.

[0048] Figure 6 As shown in the figure, 1×1 means no binning operation is performed, 1×2 means binning operation is performed on two pixels in one vertical column and two horizontal rows, 2×2 means binning operation is performed on four pixels in two vertical columns and two horizontal rows, 2×3 means binning operation is performed on 6 pixels in two vertical columns and three horizontal rows, and 4×4 means binning operation is performed on 16 pixels in four vertical columns and four horizontal rows.

[0049] Figure 7The vertical × 2 binning implementation is illustrated by a cross-sectional diagram of the pixel structure. By applying a driving signal to the two-phase CCD pixel electrodes PH1 and PH2, the driving charge signal is transferred between the pixels. Finally, the two pixel charge signals enter the FD capacitor through the TX gate signal of the control transmission tube TG, and are converted into analog voltage signals through the pixel output circuit. After the signal is read out, the FD capacitor signal is cleared through the RST signal, waiting for the next packet of charge to enter.

[0050] Specifically, for a multi-spectral TDI-CMOS image sensor with configurable imaging resolution, the number of spectral bands should be determined based on a trade-off between application requirements, manufacturing costs, operating frequency and other factors. The implementation plan is illustrated using an example with four spectral bands, a pixel size of 9μm, a maximum resolution of 3072, and a maximum TDI level of 32.

[0051] A multi-spectral TDI-CMOS image sensor with configurable imaging resolution, characterized by comprising a multi-spectral pixel array, a timing drive circuit, a digital binning readout circuit, and a configuration circuit.

[0052] The multi-spectral pixel array consists of four spectral partitions, which are defined as P, B1, B2, B3, and B4. The pixel structure of each spectral partition is 9 μm in size and 9 μm in spacing. The direction of each spectral region is defined as follows: Figure 2 As shown in the figure, the number of pixels in the horizontal direction determines the maximum resolution of the image sensor in non-binning mode, which is 3072. The vertical direction is the TDI direction of the TDI type image sensor. The number of pixels in the vertical direction determines the maximum TDI level of the image sensor in non-binning mode, which is 32. The maximum resolution value is generally required to be a multiple of 4, and the level value is generally required to be a multiple of 8. The function of the multi-spectral pixel array is to convert optical signals into electrical signals.

[0053] The pixels in the spectrum partition adopt the CCD working principle. Each pixel has multiple transfer electrodes, which are generally divided into two-phase CCD, three-phase CCD and four-phase CCD. The two-phase CCD has two transfer electrodes. This implementation scheme takes the two-phase CCD as an example for explanation. Figure 3 As shown, each pixel has two electrodes, PH1 and PH2. The charge signal after photoelectric conversion is transferred and accumulated in the vertical direction under the timing of the CCD electrodes.

[0054] The single-column pixel array in the spectral band partition is as follows Figure 3 As shown, the pixel structure is a two-phase CCD, and the TDI level is 32. The 1st level pixel of the pixels from level 2 to level 32 outputs the signal to the pixel output circuit through the TX gate signal of the control transmission tube TG, and the charge signal is converted into an analog voltage signal output through the pixel circuit.

[0055] The timing drive circuit includes multiple sub-timing drive circuits, each of which is identical, and the number of sub-circuits is consistent with the number of spectrum partitions in the multi-spectral pixel array. The timing drive circuit is used to provide a timing sequence for the multi-spectral pixel array to work normally.

[0056] The digital binning readout circuit includes a programmable gain amplifier (PGA), an analog-to-digital converter (ADC), a horizontal digital domain binning unit, a data processing circuit, and an image interface circuit, such as Figure 4 The function of the digital binning readout circuit is to digitally quantize the image signal, perform digital binning operations in the horizontal direction, and output the processed digital image.

[0057] The configuration circuit includes a register and a bus configuration circuit, which is used to set the working mode of the timing drive circuit and the digital binning readout circuit, and detect the working status of the circuit.

[0058] The configuration circuit is connected to the timing driving circuit and the digital binning readout circuit, and can respectively configure the working modes of each sub-timing circuit in the timing circuit and configure the working modes of all digital binning readout circuits.

[0059] The sub-timing circuit is located on the left side of the pixel, and the output driving signal is connected to the corresponding spectral partition of the multi-spectral pixel array, providing vertical transfer and readout timing signals for the pixel.

[0060] The digital binning readout circuit is located at the top and bottom of the multi-spectral pixel array. The top digital binning readout circuit processes the P spectral band and B1 spectral band image data, and the bottom digital binning readout circuit processes the B2 spectral band and B3 spectral band image data. The analog image signal output by the pixel is input into the PGA circuit in the digital binning readout circuit.

[0061] The imaging resolution can be configured through on-chip hybrid domain binning technology, which is realized by vertical charge domain binning technology and horizontal digital domain binning technology, and can realize 1×1, 1×2, 2×2, 2×3, 4×4 and other binning modes. Figure 6 As shown in the figure, 1×1 means no binning operation is performed, 1×2 means binning operation is performed on two pixels in one vertical column and two horizontal rows, 2×2 means binning operation is performed on four pixels in two vertical columns and two horizontal rows, 2×3 means binning operation is performed on 6 pixels in two vertical columns and three horizontal rows, and 4×4 means binning operation is performed on 16 pixels in four vertical columns and four horizontal rows.

[0062] The vertical charge domain binning technology switches by configuring the timing drive circuit working mode. Take vertical × 2 binning as an example. Figure 7 As shown, by applying a driving signal to the two-phase CCD pixel electrodes PH1 and PH2, the charge signal is transferred between the pixels, and finally the two pixel charges enter the FD capacitor through the transmission tube TG, and are converted into an analog voltage signal through the pixel output circuit. After the signal is read out, the FD capacitor signal is cleared through RST.

[0063] The horizontal digital domain binning technology is implemented by configuring the horizontal digital domain binning unit in the digital binning readout circuit and the working mode of the data processing circuit, such as Figure 5 As shown, mode selection bit 1 and mode selection bit 0 are assigned the value "X0" to represent a non-binning output mode, where X represents any value of 0 or 1, and the value "01" represents a horizontal × 2 binning output mode, and the value "11" represents a horizontal × 4 binning output mode.

[0064] Horizontal digital domain binning unit, such as Figure 5 As shown, it includes a dual-channel data selection circuit (MUX2), a 1st-level adder, a 2nd-level adder, and a saturation judgment circuit. The signals quantized by the four-channel ADC first pass through MUX2. When the mode selection bit 0 is set to "0", the four-channel data is directly output to the unit circuit. When the mode selection bit 0 is set to "1", the first two channels and the last two channels of the four-channel data are respectively input to the 1st-level adder for addition, and the summation result is input to the second-level MUX2; when the mode selection bit 1 is set to "0", the two summation results pass through the saturation judgment output unit. If the result is saturated, the saturation flag will be set; when the mode selection bit 1 is set to "1", the two summation results are input to the 2nd-level adder for summation, and the summation passes through the saturation judgment output unit. If the result is saturated, the saturation flag will be set. The saturation flag will be fed back to the PGA, and the device can be selected to automatically adjust the PGA gain, or it can be adjusted by the image sensor external controller program.

[0065] Take an example to illustrate the workflow of imaging resolution configuration. It is required that among the four spectral bands, the resolution of the P spectral band is 3072, the resolution of the B1 spectral band is 1536, and the resolution of the B2 and B3 spectral bands is 768. According to the resolution requirements, the P spectral band does not perform binning, the B1 spectral band performs 2×2 binning, and the B2 and B3 spectral bands perform 4×4 binning. Sub-timing circuit 1 is configured not to perform vertical charge domain binning, sub-timing circuit 2 performs ×2 vertical charge domain binning, and sub-timing circuits 3 and 4 perform ×4 vertical charge domain binning. Configure the top digital binning readout circuit, the P spectral band corresponds to the digital binning readout circuit configuration mode selection bit amplitude "00", the B1 spectral band corresponds to the digital binning readout circuit configuration mode selection bit amplitude "01", and the B2 and B3 spectral bands correspond to the digital binning readout circuit configuration mode selection bit amplitude "11". After the configuration is completed, TDI imaging can be performed.

[0066] This embodiment brings a new model to imaging system design and payload application. For the same imaging system, this embodiment can configure different spectral bands of the device to have different imaging resolutions according to different imaging scene characteristics and spectral reflectance characteristics to meet the requirements of system resolution and signal-to-noise ratio.

[0067] In this embodiment, since the imaging resolution can be flexibly configured, the same imaging electronics system can be used as a mature product in different imaging systems, avoiding the need to develop a separate imaging electronics system for one imaging system, thus saving development costs. In this embodiment, pixel binning is implemented on the image sensor chip, reducing the pressure of processing massive off-chip data of the image sensor. There is no need to perform off-chip binning operations on the data in the peripheral FPGA. On-chip processing reduces the amount of output data and reduces the use of off-chip storage and processing resources. In this embodiment, the device operating mode can be configured to meet the requirements of non-square pixel size requirements, without the need for repeated design, saving development costs and development cycles.

[0068] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A multi-spectral TDI-CMOS image sensor with configurable imaging resolution, characterized in that include: Multi-spectral pixel array, timing drive circuit, digital binning readout circuit and configuration circuit; wherein, The multi-spectral pixel array converts the optical signal into an image electrical signal, and transmits the image electrical signal to the digital binning readout circuit; The digital binning readout circuit receives the image electrical signal, performs digital quantization and horizontal digital binning operations on the image electrical signal, and outputs the processed digital image; The timing driving circuit provides the multi-spectral pixel array with a timing sequence for normal operation; The configuration circuit sets the working mode of the timing driving circuit and the digital binning readout circuit; The digital binning readout circuit includes a programmable gain amplifier, an analog-to-digital converter, a horizontal digital domain binning unit, a data processing circuit and an image interface circuit; wherein, The programmable gain amplifier amplifies the image electrical signal to obtain an amplified image electrical signal, and transmits the amplified image electrical signal to the analog-to-digital converter; The analog-to-digital converter receives the amplified image electrical signal, converts the amplified image electrical signal into an image digital signal, and transmits the image digital signal to the horizontal digital domain binning unit; The horizontal digital domain binning unit receives the image digital signal, performs a horizontal digital binning operation on the image digital signal according to the working mode of the data processing circuit, obtains a processed digital image, and transmits the processed digital image to the image interface circuit; The mode selection bit 1 and the mode selection bit 0 of the working mode of the data processing circuit are assigned a value of "X0" to represent a non-binning output mode, wherein X represents any value of 0 or 1, a value of "01" to represent a horizontal × 2 binning output mode, and a value of "11" to represent a horizontal × 4 binning output mode; The horizontal digital domain binning unit includes a first-level dual-channel data selection circuit, a second-level dual-channel data selection circuit, a first-level adder, a second-level adder, and a saturation judgment circuit; wherein, The analog-to-digital converter is four-channel; The image digital signals of the four-channel analog-to-digital converter pass through a first-level dual-channel data selection circuit. When the mode selection bit 0 is set to "0", the four-channel image digital signals are directly output. When the mode selection bit 0 is set to "1", the first two channels of the four-channel image digital signals and the last two channels of the four-channel image digital signals are respectively input into the first-level adder for addition, and the summation result is input into the second-level dual-channel data selection circuit; when the mode selection bit 1 is set to "0", the two addition results pass through the saturation judgment circuit. If the result is saturated, the saturation flag will be set; when the mode selection bit 1 is set to "1", the two addition results are input into the second-level adder for summation. The summation passes through the saturation judgment circuit. If the result is saturated, the saturation flag will be set.

2. The imaging resolution configurable multi-spectral TDI-CMOS image sensor according to claim 1, characterized in that: The multi-spectral pixel array includes a plurality of spectral partitions; wherein each pixel in each spectral partition has the same structure, each pixel in each spectral partition has the same size, and the pixel spacing in each spectral partition is equal.

3. The imaging resolution configurable multi-spectral TDI-CMOS image sensor according to claim 2, characterized in that: Each spectral partition is a rectangular area, where the number of pixels in the horizontal direction of the rectangular area determines the maximum resolution n of the image sensor in non-binning mode, and the number of pixels in the vertical direction of the rectangular area determines the maximum TDI level m of the image sensor in non-binning mode.

4. The imaging resolution configurable multi-spectral TDI-CMOS image sensor according to claim 2, characterized in that: The timing driving circuit comprises a plurality of sub-timing driving circuits, wherein the number of the sub-timing driving circuits is equal to the number of spectrum partitions; Each sub-timing driving circuit provides a timing sequence for normal operation to the spectrum partition corresponding to each sub-timing driving circuit.

5. The imaging resolution configurable multi-spectral TDI-CMOS image sensor according to claim 2, characterized in that: The picture elements in the spectrum partition adopt the CCD working principle, and each picture element has multiple transfer electrodes, which are divided into two-phase CCD, three-phase CCD and four-phase CCD.

6. The imaging resolution configurable multi-spectral TDI-CMOS image sensor according to claim 1, characterized in that: The pixel is a two-phase CCD, and the TDI level is 32. Among them, the 1st level pixel of the 2nd to 32nd level outputs the signal to the pixel output circuit through the TX gate signal of the control transmission tube TG, and the charge signal is converted into an analog voltage signal output through the pixel circuit.

7. The imaging resolution configurable multi-spectral TDI-CMOS image sensor according to claim 1, characterized in that: The digital binning readout circuit includes a top digital binning readout circuit and a bottom digital binning readout circuit; wherein the top digital binning readout circuit is located at the top of the multi-spectral pixel array, and the bottom digital binning readout circuit is located at the bottom of the multi-spectral pixel array.

Images