Quantum Chip, Quantum Computer, and Manufacturing Method

Abstract

The present disclosure provides a quantum chip, a quantum computer and a manufacturing method, relating to the field of computers, and particularly to the technical fields of quantum chips and quantum computers. The specific implementation scheme is as follows: at least one qubit; wherein, the configuration of the qubit includes: a first metal plate located in a first plane, wherein the first metal plate is in a "V" shape; a second metal plate located in the first plane, wherein the second metal plate is in a three-way shape; a connection component located between the first metal plate and the second metal plate for coupling the first metal plate and the second metal plate.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and particularly to the fields of quantum chips and quantum computer technologies. Background Art

[0002] As a logical necessity for chip size to break through the classical physical limit and also a landmark technology in the post-Moore era, quantum computing has received great attention. Nowadays, quantum computing has developed very rapidly in terms of application level, algorithm level, and hardware level. It is particularly worth noting that the implementation of quantum algorithms and applications highly depends on the development and progress of quantum hardware. Benefiting from good scalability and mature semiconductor manufacturing processes, superconducting quantum circuits are considered to be one of the most promising technical routes. In recent years, with the development of superconducting quantum computing technical solutions and micro-nano processing technologies, the number of qubits integrated on superconducting quantum chips has been increasing, and the chip structure has thus become more abundant and comprehensive. However, finding a configuration of a quantum chip with excellent performance is a very important topic. Summary of the Invention

[0003] The present disclosure provides a quantum chip, a quantum computer, and a manufacturing method.

[0004] According to one aspect of the present disclosure, there is provided a quantum chip, including:

[0005] At least one qubit;

[0006] Wherein, the configuration of the qubit includes:

[0007] A first metal plate located in a first plane, wherein the first metal plate is in a "V" shape;

[0008] A second metal plate located in the first plane, wherein the second metal plate is in a three-way shape;

[0009] A connection component located between the first metal plate and the second metal plate for coupling the first metal plate and the second metal plate.

[0010] According to another aspect of the present disclosure, there is provided a quantum computer, including at least the above-mentioned quantum chip and an external control system connected to the quantum chip.

[0011] According to still another aspect of the present disclosure, there is provided a manufacturing method of a quantum chip, including:

[0012] Forming a base material layer;

[0013] Forming a metal layer on the base material layer;

[0014] Perform an etching process to etch away at least part of the metal layer and expose at least part of the base material layer to form the configuration of the qubit as described above;

[0015] Set up a connection component to couple the first metal plate and the second metal plate included in the qubit configuration.

[0016] In this way, compared with the common design solutions in the industry, the solution of the present disclosure shows significant advantages in connectivity. Moreover, the quantum chip described in the solution of the present disclosure has good scalability. Especially when the number of qubits scales up, the advantages of the quantum chip of the solution of the present disclosure will be further highlighted. Furthermore, benefiting from the configuration of the quantum chip of the solution of the present disclosure, it is expected to achieve stronger chip performance. Therefore, the configuration of the quantum chip of the solution of the present disclosure has important guiding significance and value for the research and development of quantum chips.

[0017] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understandable through the following description. Brief Description of the Drawings

[0018] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:

[0019] Figure 1 is a schematic structural diagram of a qubit in a quantum chip according to an embodiment of the present disclosure;

[0020] Figure 2 is a schematic structural diagram of a chip obtained by the manufacturing method of a quantum chip according to an embodiment of the present disclosure;

[0021] FIG. 3(a) is a specific schematic diagram of a "V" - shaped structure in a quantum chip according to an embodiment of the present disclosure;

[0022] FIG. 3(b) is a specific schematic diagram of a three - pronged structure in a quantum chip according to an embodiment of the present disclosure;

[0023] FIG. 3(c) is a schematic diagram of the overall structure of a qubit in a quantum chip according to an embodiment of the present disclosure;

[0024] Figure 4 and Figure 5 is a schematic diagram of the coupling between qubits in a quantum chip according to an embodiment of the present disclosure;

[0025] Figure 6 is a schematic structural diagram of a two - dimensional tiling unit in a quantum chip according to an embodiment of the present disclosure;

[0026] FIG. 7(a) and FIG. 7(b) are schematic diagrams of a two - dimensional tiling structure in a quantum chip according to an embodiment of the present disclosure;

[0027] Figure 8 It is a schematic diagram of the geometric parameters of qubits in a specific example according to an embodiment of the present disclosure;

[0028] Figures 9(a) and 9(b) are schematic diagrams of the two-dimensional tiling structure of a quantum chip in a specific application example according to an embodiment of the present disclosure;

[0029] Figures 10(a) to 10(d) It is a schematic diagram of the structure of a common quantum chip in the industry. Detailed implementation manners

[0030] The following makes an explanation of exemplary embodiments of the present disclosure with reference to the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0031] The term "and / or" in this document is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The term "at least one" in this document means any one of multiple or any combination of at least two of multiple. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set composed of A, B, and C. The terms "first" and "second" in this document represent referring to multiple similar technical terms and distinguishing them, and do not mean to limit the order, or limit to only two. For example, the first feature and the second feature refer to two categories / two features. The first feature can be one or more, and the second feature can also be one or more.

[0032] In addition, for a better explanation of the present disclosure, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail to highlight the gist of the present disclosure.

[0033] As a logical necessity for chip size to break through the classical physical limits and also a landmark technology in the post-Moore era, quantum computing has received great attention. Nowadays, quantum computing has developed rapidly in terms of application level, algorithm level, and hardware level. It is particularly noteworthy that the implementation of quantum algorithms and applications highly depends on the development and progress of quantum hardware. In the implementation of quantum hardware, there are various technical solutions for quantum computing, such as superconducting quantum circuits, ion traps, optical quantum systems, etc. Benefiting from good scalability and mature semiconductor manufacturing processes, superconducting quantum circuits are considered to be one of the most promising technical routes at present. In recent years, with the development of superconducting quantum computing technical solutions and micro-nano processing technologies, the number of qubits integrated on superconducting quantum chips has been increasing, and the chip structure has become more abundant and comprehensive.

[0034] In practical applications, there are many factors to measure the performance of quantum chips (such as superconducting quantum chips), and connectivity is one of the key indicators. Here, the so-called connectivity refers to the degree of connection between one qubit and the remaining other qubits in a quantum chip (such as a superconducting quantum chip). Taking superconducting quantum chips as an example, different from ion trap quantum computing, in superconducting quantum circuits, superconducting qubits can only be coupled with adjacent superconducting qubits. Restricted by this, two-qubit gates are also limited to be implemented between adjacent superconducting qubits. However, in practice, to implement quantum gate operations between any two superconducting qubits, the coupling between non-adjacent superconducting qubits is required. Based on this, mapping the quantum circuit at the algorithm level (i.e., the logical quantum circuit) to the quantum circuit at the physical level that meets the physical limitations of superconducting quantum chips becomes a very important topic. Although this mapping solves the problem to some extent, the price is that a large number of two-qubit gates (such as two-superconducting-qubit gates) need to be introduced additionally, which undoubtedly greatly reduces the computing efficiency and accuracy.

[0035] Therefore, finding the configuration of qubits with high connectivity and then obtaining quantum chips with high connectivity becomes a very important topic.

[0036] Based on this, the present disclosure proposes a specific configuration of a quantum chip to achieve strong connectivity between qubits.

[0037] Figure 1 is a schematic structural diagram of qubits in a quantum chip according to an embodiment of the present disclosure; as Figure 1 shown, the quantum chip includes:

[0038] at least one qubit;

[0039] Further, the configuration of the qubit includes:

[0040] The first metal electrode plate 111 located on the first plane, wherein the first metal electrode plate is in a "V" shape;

[0041] The second metal electrode plate 112 located on the first plane, wherein the second metal electrode plate is in a three-way shape;

[0042] The connection component 113 located between the first metal electrode plate and the second metal electrode plate, which is used to couple the first metal electrode plate and the second metal electrode plate.

[0043] Here, it should be pointed out that the first metal electrode plate and the second metal electrode plate are two metal plates in the same plane, rather than an integrated structure. In this way, it provides a configuration support for forming a floating-type qubit.

[0044] Furthermore, it should be pointed out that the first metal plate and the second metal plate are asymmetric. In other words, the configuration of the qubit is an asymmetric structure.

[0045] In this way, compared with the common design schemes in the industry, the scheme of the present disclosure shows significant advantages in connectivity. Moreover, the quantum chip described in the scheme of the present disclosure has good scalability and high integration. Especially when the number of qubits scales up, the advantages of the quantum chip of the present disclosure will be further highlighted. Furthermore, benefiting from the configuration of the qubit (or the configuration of the quantum chip) of the present disclosure, it is expected to achieve stronger chip performance. Therefore, the configuration of the quantum chip of the present disclosure has important guiding significance and value for the research and development of quantum chips.

[0046] In a specific example of the scheme of the present disclosure, the quantum chip is a superconducting quantum chip.

[0047] It should be noted that the superconducting quantum chip described in the scheme of the present disclosure refers to a quantum chip prepared from superconducting materials. For example, all the components used in the superconducting quantum chip are prepared from superconducting materials. Further, the qubits in the superconducting quantum chip are superconducting qubits. In this way, it provides a configuration support for the performance research of superconducting quantum chips and the superconducting quantum chips with stronger chip performance.

[0048] In a specific example, the following process flow can be adopted to obtain the configuration of the qubits in the quantum chip, as Figure 2 shown, the manufacturing method of the quantum chip includes:

[0049] Form a base material layer. For example, sapphire is used as the base material;

[0050] Form a metal layer on the base material layer. For example, form a superconducting metal layer;

[0051] Perform an etching process to etch away at least part of the metal layer and expose at least part of the substrate material layer to form the above-described qubit configuration;

[0052] Set the above-described connection components in at least part of the qubit configuration to couple the first metal plate and the second metal plate included in the qubit configuration.

[0053] In this way, the quantum chip described in the present disclosure is obtained. Moreover, the quantum chip described in the present disclosure has good scalability and high integration. Especially when the number of qubits scales up, the advantages of the quantum chip in the present disclosure will be further highlighted. Furthermore, benefiting from the qubit configuration (or the quantum chip configuration) of the present disclosure, stronger chip performance is expected to be achieved. Therefore, the qubit configuration of the quantum chip in the present disclosure has important guiding significance and value for the research and development of quantum chips.

[0054] It can be understood that the above process flow is an exemplary process flow for a quantum chip containing one qubit. In practical applications, multiple qubits of the above configuration can be formed in one process flow, and the present disclosure does not limit this.

[0055] In a specific example of the present disclosure, the bottom of the "V" shape of the first metal plate and the bottom of the three-fork shape of the second metal plate are arranged at intervals, so that the two branches of the "V" shape and the three branches of the three-fork shape extend in different directions. For example, as Figure 1 shown, the two branches of the "V" shape extend respectively towards two different directions associated with the first direction, and the three branches of the three-fork shape extend respectively towards three different directions associated with the second direction. In this way, it is convenient to couple with other qubits using different branches. For example, coupling with other qubits using five branches to form a two-dimensional close-packed structure, which lays a configuration foundation for achieving high connectivity.

[0056] Here, it should be noted that the qubits coupled by different branches are different.

[0057] Further, in an example, the connection component is placed in the interval region between the bottom of the "V" shape of the first metal plate and the bottom of the three-fork shape of the second metal plate. In this way, it provides configuration support for forming a floating-type qubit.

[0058] Further, in an example, at least one of the regions where the connection component, the first metal plate, and the second metal plate are located is a non-grounding region. For example, in a specific example, as Figure 1As shown, the areas where the connection component, the first metal plate, and the second metal plate are located are all non-grounded areas, thus providing configuration support for forming a floating quantum bit.

[0059] Furthermore, in a specific example, the qubit is a floating qubit. The floating qubit refers to a connection component that couples two metal plates (i.e., the first metal plate and the second metal plate) and is not directly grounded. In this way, since the connection component is not grounded, the floating qubit is less affected by the fluctuation of the charge, has better robustness to the environment, and is more conducive to the design of a three-dimensional flip-chip quantum chip, thereby providing a configuration basis for designing a quantum chip with stronger performance.

[0060] In a specific example of the disclosed solution, the connection component is a superconducting quantum interference device. Further, in one example, the superconducting quantum interference device includes two or more Josephson junctions. For example, in a specific example, the superconducting quantum interference device includes two parallel Josephson junctions. In this way, a configuration of a quantum bit that is easy to implement is provided to enhance the practicality of the disclosed solution. At the same time, it is also convenient to use a superconducting quantum interference device to nonlinearize the energy level of the quantum bit.

[0061] Furthermore, in one example, two or more Josephson junctions are placed in two parallel lines, and the number of Josephson junctions contained in each of the two lines is the same or different. In other words, multiple Josephson junctions are placed in two different lines, and the two lines are connected in parallel. At this time, a Josephson junction ring can be formed; here, it should be noted that each line is provided with at least one Josephson junction, and the number of Josephson junctions provided in different lines can be the same or different, and the disclosed solution does not limit this. In this way, it is convenient to use a superconducting quantum interference device to nonlinearize the energy level of the quantum bit.

[0062] In a specific example of the disclosed solution, the configuration of the quantum bit also satisfies at least one of the following conditions:

[0063] Condition 1: the angle between the two branches of the “V” shape is a first angle; the first angle is an acute angle;

[0064] Condition 2: the angle between two adjacent branches of the three branches of the three-branch type is a second angle; the second angle is an acute angle;

[0065] Condition 3: The first branch of the two branches of the "V" shape is adjacent to the second branch of the three branches of the three-way shape, and the included angle between the adjacent first branch and the second branch is the third angle, and the third angle is an obtuse angle, an acute angle or a right angle.

[0066] It can be understood that in practical applications, the configuration of the quantum bit can satisfy one of the above conditions, or satisfy two of the above three conditions, or satisfy all three conditions. The solution of the present disclosure does not limit this.

[0067] In this way, the solution of the present disclosure provides a specific configuration solution for the quantum bit. Thus, it provides a configuration reference for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the solution of the present disclosure has good scalability and is convenient for forming a two-dimensional close-packed structure, and further lays a configuration foundation for realizing high connectivity.

[0068] Further, in a specific example, for Condition 2, the second angles formed by any two adjacent branches of the three branches of the three-way shape are the same or different. For example Figure 1 As shown, the two second angles can be respectively denoted as the second angle -1 and the second angle -2. At this time, the second angle -1 and the second angle -2 are the same or different.

[0069] Further, in a specific example, the first angle and the second angle are the same. For example, in an example, the second angles formed by any two adjacent branches of the three branches of the three-way shape are the same. For example, as Figure 1 shown, the second angle -1 and the second angle -2 are the same. Further, the second angle is also the same as the first angle, that is, the second angle -1, the second angle -2, and the first angle are all the same. Thus, it provides a configuration reference for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the solution of the present disclosure has good scalability and is convenient for forming a two-dimensional close-packed structure, and further lays a configuration foundation for realizing high connectivity.

[0070] Further, in a specific example, the first angle is about 60 degrees. Thus, it provides configuration support for forming a two-dimensional close-packed structure, and further lays a configuration foundation for realizing high connectivity.

[0071] In some specific examples, the first angle is 54 degrees, or in some other specific examples, the first angle is 66 degrees, or in still some other specific examples, the first angle is 60 degrees.

[0072] Further, in a specific example, the second angle is about 60 degrees. Thus, it provides configuration support for forming a two-dimensional close-packed structure, and further lays a configuration foundation for realizing high connectivity.

[0073] In some specific examples, the second angle is 54 degrees, or, in some other specific examples, the second angle is 66 degrees, or, in still some other specific examples, the second angle is 60 degrees.

[0074] Further, in a specific example, the third angle is about 90 degrees. Thus, it provides configuration support for forming a two-dimensional close-packed structure, and further lays a configuration foundation for further realizing high connectivity.

[0075] In some specific examples, the third angle is 81 degrees, or, in some other specific examples, the third angle is 99 degrees, or, in still some other specific examples, the third angle is 90 degrees.

[0076] In a specific example of the present disclosure solution, the periphery of the first metal electrode plate is a first etching region, and the first etching region is formed after etching at least a part of the region in the metal layer used to form the first metal plate; for example, as Figure 2 shown, the first etching region surrounds the bottom of the first metal electrode plate 111 and surrounds the two branches of the first metal electrode plate 111 to expose at least a part of the region of the substrate material.

[0077] And / or, in a specific example of the present disclosure solution, the periphery of the second metal electrode plate is a second etching region, and the second etching region is formed after etching at least a part of the region in the metal layer used to form the second metal plate. For example, as Figure 2 shown, the second etching region surrounds the bottom of the second metal electrode plate 112 and surrounds the three branches of the second metal electrode plate 112 to expose at least a part of the region of the substrate material.

[0078] Further, in a specific example, at least a part of the etching region at the bottom of the "V" shape of the first metal electrode plate in the first etching region and at least a part of the etching region at the bottom of the three-fork shape of the second metal electrode plate in the second etching region at least partially overlap to form a spaced region at the bottom of the "V" shape of the first metal electrode plate and at the bottom of the three-fork shape of the second metal electrode plate; further, the connection component is located in the spaced region, that is, located in the at least partially overlapping region, to couple the first metal electrode plate and the second metal electrode plate arranged at intervals.

[0079] In this way, the present disclosure solution further refines the configuration structure of the qubit, and thus provides configuration support for forming a floating-type qubit.

[0080] In a specific example of the present disclosure solution, as shown in FIG. 3(a), the dimensions of each part in the "V" shape satisfy at least one of the following conditions:

[0081] Condition 4: The height of the first branch in the two branches of the "V" shape is about 250 microns;

[0082] Condition 5: The width of the bottom of the "V" shape is about 135 microns;

[0083] Condition 6: In the first etching region, the width of at least part of the etching region around the first branch in the two branches of the "V" shape is about 12 microns - about 15 microns.

[0084] For Condition 4, in some specific examples, the height of the first branch in the two branches of the "V" shape is 225 microns, or, in some other specific examples, the height of the first branch in the two branches of the "V" shape is 275 microns, or, in still some other specific examples, the height of the first branch in the two branches of the "V" shape is 250 microns.

[0085] For Condition 5, in some specific examples, the width of the bottom of the "V" shape is 121.5 microns, or, in some other specific examples, the width of the bottom of the "V" shape is 148.5 microns, or, in still some other specific examples, the width of the bottom of the "V" shape is 135 microns.

[0086] For Condition 6, the width of at least part of the etching region around the first branch in the first etching region is about 12 microns. Or, in some other specific examples, the width of at least part of the etching region around the first branch in the first etching region is about 15 microns. Or, in still some other specific examples, the width of at least part of the etching region around the first branch in the first etching region is about 13 microns.

[0087] Furthermore, in a specific example, as shown in Fig. 3(a), the width of the partial etching region around the first branch of the "V" shape in the first etching region in the first longitudinal direction is about 15 microns; or, the width of at least part of the etching region around the first branch of the "V" shape in the first etching region in the first transverse direction is about 12 microns. Thus, it provides a configuration reference for realizing a quantum chip with stronger performance; moreover, the configuration scheme described in the present disclosure has good scalability and is convenient for forming a two-dimensional close-packed structure, thereby further laying a configuration foundation for realizing high connectivity.

[0088] In some specific examples, the width of a partial etching region around the first branch of the "V" shape in the first etching region in the first longitudinal direction is 13.5 micrometers; or, in some other specific examples, the width of a partial etching region around the first branch of the "V" shape in the first etching region in the first longitudinal direction is 16.5 micrometers; or, in still some other specific examples, the width of a partial etching region around the first branch of the "V" shape in the first etching region in the first longitudinal direction is 15 micrometers;

[0089] Further, in some specific examples, the width of at least a partial etching region around the first branch of the "V" shape in the first etching region in the first transverse direction is 10.8 micrometers, and in some other specific examples, the width of at least a partial etching region around the first branch of the "V" shape in the first etching region in the first transverse direction is 13.2 micrometers; or, in still some other specific examples, the width of at least a partial etching region around the first branch of the "V" shape in the first etching region in the first transverse direction is 12 micrometers.

[0090] It can be understood that in practical applications, the dimensions of each part in the "V" shape can meet one of the above conditions, or meet two of the above three conditions, or all three conditions are met. The solution of the present disclosure does not limit this.

[0091] In this way, the solution of the present disclosure provides a specific configuration solution for qubits, thus providing a configuration reference for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the solution of the present disclosure has good scalability and is convenient for forming a two-dimensional close-packed structure, and further lays a configuration foundation for realizing high connectivity.

[0092] Further, in a specific example, the "V" shape is a symmetric figure. For example, it is an axisymmetric figure. As shown in FIG. 3(a), it is symmetric along the axis of symmetry A-A', thus providing a configuration reference for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the solution of the present disclosure has good scalability and is convenient for forming a two-dimensional close-packed structure, and further lays a configuration foundation for realizing high connectivity.

[0093] In a specific example of the solution of the present disclosure, as shown in FIG. 3(b), the dimensions of each part in the three-way shape meet at least one of the following conditions:

[0094] Condition seven: The height of the second branch among the three branches of the three-way shape is about 245 micrometers;

[0095] Condition eight: The width of the bottom of the three-way shape is about 160 micrometers;

[0096] Condition nine: The width of at least a partial etching region around the second branch among the three branches of the three-way shape in the second etching region is about 12 micrometers - about 15 micrometers.

[0097] For condition seven, in some specific examples, the height of the second branch of the three branches of the three-forked type is 220.5 microns; or, in other specific examples, the height of the second branch of the three branches of the three-forked type is 269.5 microns; or, in some other specific examples, the height of the second branch of the three branches of the three-forked type is 245 microns.

[0098] For condition eight, in some specific examples, the width of the bottom of the three-pronged shape is 144 microns; or, in other specific examples, the width of the bottom of the three-pronged shape is 176 microns; or, in still other specific examples, the width of the bottom of the three-pronged shape is 160 microns.

[0099] For condition nine, the width of at least a portion of the etched region surrounding the second branch of the three branches of the three-forked type in the second etched region is about 12 microns. Alternatively, in other specific examples, the width of at least a portion of the etched region surrounding the second branch of the three branches of the three-forked type in the second etched region is about 15 microns. Alternatively, in still other specific examples, the width of at least a portion of the etched region surrounding the second branch of the three branches of the three-forked type in the second etched region is about 13 microns.

[0100] It is understandable that in actual applications, the size of each part of the three-pronged type can meet one of the above conditions, or meet two of the above three conditions, or meet all three conditions, and the present disclosure does not limit this.

[0101] In this way, the disclosed scheme provides a specific quantum bit configuration scheme, thereby providing a configuration reference for realizing a quantum chip with stronger performance; moreover, the configuration scheme described in the disclosed scheme has good scalability and is convenient for forming a two-dimensional densely packed structure, thereby further laying a configuration foundation for realizing high connectivity.

[0102] Further, in a specific example, the three-pronged shape is a symmetrical figure. For example, it is an axisymmetric figure, as shown in FIG3(b), symmetrical along the symmetry axis B-B'. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance; moreover, the configuration scheme described in the disclosed scheme has good scalability, which is convenient for forming a two-dimensional densely packed structure, and further lays a configuration foundation for realizing high connectivity.

[0103] Further, in a specific example, as shown in FIG3(b), the width of at least a portion of the etched area surrounding the second branch of the three-pronged shape in the second etched area in the second longitudinal direction is about 15 microns; or, the width of at least a portion of the etched area surrounding the second branch of the three-pronged shape in the second etched area in the second transverse direction is about 12 microns. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance; moreover, the configuration scheme described in the disclosed scheme has good scalability, which is convenient for forming a two-dimensional densely packed structure, and further lays a configuration foundation for realizing high connectivity.

[0104] In some specific examples, the width of at least a portion of the etched region surrounding the second branch of the three-pronged fork in the second etched region in the second longitudinal direction is 13.5 micrometers; or, in other specific examples, the width of at least a portion of the etched region surrounding the second branch of the three-pronged fork in the second etched region in the second longitudinal direction is 16.5 micrometers; or, in still other specific examples, the width of at least a portion of the etched region surrounding the second branch of the three-pronged fork in the second etched region in the second longitudinal direction is 15 micrometers;

[0105] Further, in some specific examples, at least a portion of the etched area surrounding the second branch of the three-pronged fork in the second etched region has a width of 10.8 microns in the second horizontal direction; or, in other specific examples, at least a portion of the etched area surrounding the second branch of the three-pronged fork in the second etched region has a width of 13.2 microns in the second horizontal direction; or, in still other specific examples, at least a portion of the etched area surrounding the second branch of the three-pronged fork in the second etched region has a width of 12 microns in the second horizontal direction.

[0106] In a specific example of the disclosed solution, as shown in FIG3( c ), the configuration of the qubit further satisfies at least one of the following conditions:

[0107] Condition 10: The height of the quantum bit is about 619 microns;

[0108] Condition 11: The distance between the bottom of the "V" shape of the first metal electrode plate and the bottom of the triangular shape of the second metal electrode plate is about 15 micrometers.

[0109] For condition ten, in some specific examples, the height of the quantum bit is 557.1 microns; or, in other specific examples, the height of the quantum bit is 680.9 microns; or, in still other specific examples, the height of the quantum bit is 619 microns.

[0110] For Condition 11, in some specific examples, the distance between the bottom of the "V" shape of the first metal plate and the bottom of the three-way shape of the second metal plate is 13.5 micrometers; or, in some other specific examples, the distance between the bottom of the "V" shape of the first metal plate and the bottom of the three-way shape of the second metal plate is 16.5 micrometers; or, in still some other specific examples, the distance between the bottom of the "V" shape of the first metal plate and the bottom of the three-way shape of the second metal plate is 15 micrometers.

[0111] It can be understood that in practical applications, the configuration of the qubit can meet one of the above conditions, or both conditions are met. The solution of the present disclosure does not limit this.

[0112] As shown in FIG. 3(c), in a specific example, the effective length of the first etching region in the first branch direction from the starting point to the inflection point is about 240 micrometers. For example, in some specific examples, the effective length of the first etching region in the first branch direction from the starting point to the inflection point is 216 micrometers; or, in some specific examples, the effective length of the first etching region in the first branch direction from the starting point to the inflection point is 240 micrometers; or, in some specific examples, the effective length of the first etching region in the first branch direction from the starting point to the inflection point is 246 micrometers.

[0113] Furthermore, in another specific example, the effective length of the second etching region in the second branch direction from the starting point to the inflection point is about 240 micrometers. For example, in some specific examples, the effective length of the second etching region in the second branch direction from the starting point to the inflection point is 216 micrometers; or, in some specific examples, the effective length of the second etching region in the second branch direction from the starting point to the inflection point is 240 micrometers; or, in some specific examples, the effective length of the second etching region in the second branch direction from the starting point to the inflection point is 246 micrometers.

[0114] In this way, the solution of the present disclosure provides a specific configuration solution for the qubit, thus providing a configuration reference for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the solution of the present disclosure has good scalability and is convenient for forming a two-dimensional close-packed structure, thereby further laying a configuration foundation for realizing high connectivity.

[0115] In a specific example of the present disclosure solution, when the quantum chip includes two or more qubits, two adjacent qubits are coupled through the branches of the qubits; wherein, the branches of the qubits are any one of the following: two branches of a "V" shape, and three branches of a three-way shape. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the present disclosure solution has good scalability and is convenient for forming a two-dimensional close-packed structure, thereby further laying a configuration foundation for realizing high connectivity.

[0116] Further, in a specific example, the number of other qubits that are proximally coupled to the qubit is less than or equal to 5. It can be understood that since the qubit has five branches, the qubit can be proximally coupled to different other qubits through at most five branches, that is, the same qubit can be proximally coupled to at most five qubits. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the present disclosure solution has good scalability and is convenient for forming a two-dimensional close-packed structure, thereby further laying a configuration foundation for realizing high connectivity.

[0117] Further, in a specific example, the distance between the branches for proximally coupling two qubits is 5 - 20 micrometers.

[0118] In some specific examples, the distance between the branches for proximally coupling two qubits is 5 micrometers; or, in some other specific examples, the distance between the branches for proximally coupling two qubits is 10 micrometers; or, in still some other specific examples, the distance between the branches for proximally coupling two qubits is 15 micrometers; or, in still some other specific examples, the distance between the branches for proximally coupling two qubits is 20 micrometers.

[0119] For example, as Figure 4 and Figure 5 shown, the distance between the branches for proximally coupling two qubits is 10 micrometers.

[0120] In this way, a configuration reference is provided for realizing a quantum chip with stronger performance; moreover, the configuration solution described in the present disclosure solution has good scalability and is convenient for forming a two-dimensional close-packed structure, thereby further laying a configuration foundation for realizing high connectivity.

[0121] Further, in a specific example, when the number of other qubits that are proximally coupled to the qubit is 2 or more, the qubit in the middle can serve as a coupling device for regulating the coupling strength between the two qubits coupled by the coupling device. As Figure 5As shown, the qubit Q2 is proximally coupled to the qubit Q1 and the qubit Q3 respectively through its different branches. The qubit Q2 is equivalent to the middle qubit. At this time, the qubit Q2 can be used as a coupling device, and then the coupling strength between the coupled qubits Q1 and Q3 can be regulated through the qubit Q2. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance; moreover, the configuration scheme described in the present disclosure has good scalability and is convenient for forming a two-dimensional close-packed structure, thereby further laying a configuration foundation for realizing high connectivity.

[0122] In a specific example of the present disclosure, when the quantum chip includes five or more qubits, the five or more qubits can form a two-dimensional close-packed unit on the first plane; as Figure 6 shown, five qubits form a two-dimensional close-packed unit on the first plane; further, the figures enclosed by the branches of the qubits in the two-dimensional close-packed unit include: quadrilaterals and triangles.

[0123] In this way, the present disclosure provides a specific expansion method, which is simple and convenient for forming a two-dimensional close-packed structure. Moreover, the entire space of the quantum chip is fully utilized. When the number of qubits is scaled up, the advantages of this expansion method will be further highlighted. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance, thereby further laying a configuration foundation for realizing high connectivity.

[0124] In addition, since the space between the qubits in the two-dimensional close-packed unit is relatively large, sufficient design space is provided for the follow-up, for example, it is convenient for adding wiring such as read lines and measurement and control lines in the follow-up. Benefiting from this, the quantum chip based on the present disclosure is expected to achieve stronger performance and larger scale.

[0125] Further, in a specific example, the quadrilateral is a square; and / or the triangle is an equilateral triangle. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance, thereby further laying a configuration foundation for realizing high connectivity.

[0126] Further, in a specific example, the quantum chip can form a two-dimensional close-packed structure that satisfies the two-dimensional close-packed condition; wherein, the two-dimensional close-packed structure includes at least one two-dimensional close-packed unit. In this way, a configuration reference is provided for realizing a quantum chip with stronger performance, thereby further laying a configuration foundation for realizing high connectivity.

[0127] Here, in a specific example, the two-dimensional close-packed condition includes: an integer multiple of the interior angle of a regular polygon is 360 degrees.

[0128] Further, in a specific example, the maximum connectivity of the two-dimensional tiling structure formed by the quantum chip is less than 0.57; the maximum connectivity represents the connectivity of the quantum chip when the number of qubits of the quantum chip is infinite.

[0129] In this way, the solution of the present disclosure adopts a special construction of qubits, and moreover, its mathematically abstract topological structure is proven to have strong connectivity. Benefiting from the strong connectivity, it lays a configuration foundation for further developing high-performance quantum chips.

[0130] In a specific example of the solution of the present disclosure, the quantum chip further includes:

[0131] A control line, one end of the control line is used to connect to the control port of the qubit, and the other end of the qubit control line is used to connect to the first pin to connect to an external control system through the first pin;

[0132] And / or,

[0133] A read line, one end of the read line is used to connect to the read port of the qubit, and the qubit read line is used to connect to the second pin to connect to an external control system through the second pin.

[0134] In this way, since the space between the qubits in the quantum chip provided by the solution of the present disclosure is large, sufficient wiring space is provided, so that the crosstalk problem caused by the proximity of the control lines is effectively avoided.

[0135] The solution of the present disclosure also provides a quantum computer, which at least includes the above-mentioned quantum chip and an external control system connected to the quantum chip. In this way, the average cost of performing a two-qubit gate between any two qubits in the quantum chip of the quantum computer can be effectively reduced.

[0136] In summary, the solution of the present disclosure provides a configuration of qubits with good scalability and superior performance. At the same time, it also provides a quantum chip obtained by expanding the above-mentioned qubits, and the quantum chip has high connectivity. Since the coupling strength between two adjacent qubits in the solution of the present disclosure is strong, the solution of the present disclosure can effectively reduce the average cost of performing a two-qubit gate between any two qubits in the quantum chip, so that it lays a configuration foundation for further developing high-performance quantum chips.

[0137] In addition, the space between the qubits in the quantum chip provided by the solution of the present disclosure is large, so that sufficient design space is provided for the follow-up, for example, it provides convenience for subsequent wiring such as adding read lines and measurement and control lines. Benefiting from this, the quantum chip based on the solution of the present disclosure is expected to achieve stronger performance and larger scale.

[0138] The following further elaborates on the solution of the present disclosure with specific examples; the solution of the present disclosure proposes a structure of a superconducting quantum chip and provides a structure of a qubit. The structure of this qubit has good scalability and can form a two-dimensional close-packed structure (for example, form a two-dimensional close-packed network). Moreover, the superconducting quantum chip obtained based on the configuration of the qubit provided by the solution of the present disclosure has high connectivity and excellent performance.

[0139] It should be noted that the superconducting quantum chip described in the solution of the present disclosure refers to a quantum chip prepared from superconducting materials. For example, all components used in the superconducting quantum chip are prepared from superconducting materials. Further, the qubits in the superconducting quantum chip are superconducting qubits.

[0140] The solution of the present disclosure will be elaborated in detail in two parts. The first part introduces the specific configuration of a new type of qubit and demonstrates the configuration characteristics of this qubit; the second part elaborates on the performance parameters of the configuration of the new type of qubit, such as the coupling strength between qubits and the connectivity of the topological structure obtained based on the configuration of this qubit.

[0141] First part, the configuration of the qubit

[0142] In one example, as Figure 2 shown, sapphire is used as the substrate material, and a superconducting metal layer is formed on the substrate material. After etching away some regions in the superconducting metal layer, the configuration of the qubit as shown in Figure 2 is formed. Among them, the configuration of the qubit includes at least three parts, which are respectively:

[0143] First part, the metal plate region, including: the first metal plate 111 in a "V" shape and the second metal plate 112 in an inverted "3" shape (or can be called a three-fork shape). Here, both the first metal plate 111 and the second metal plate 112 are located in the first plane. Further, in some specific examples, the bottom of the "V" shape of the first metal plate and the bottom of the three-fork shape of the second metal plate are arranged at intervals, so that the two branches of the "V" shape and the three branches of the three-fork shape extend in different directions. For example, the two branches of the "V" shape extend respectively towards two different directions associated with the first direction, and the three branches of the three-fork shape extend respectively towards three different directions associated with the second direction. In this way, it is convenient to couple with other qubits using different branches. For example, five branches are used to couple with other qubits to form a two-dimensional close-packed structure. Here, it should be pointed out that the qubits coupled by different branches are different.

[0144] The second part is the etching area, which surrounds the metal electrode plate area. This etching area is formed after etching away the superconducting metal layer to expose at least part of the area in the base material. Here, for the convenience of description, the etching area is divided into two parts. The first part is called the first etching area, and the second part is called the second etching area. Among them, the first etching area is formed after etching away at least part of the superconducting metal layer used to form the first metal plate 111. Then, after etching away at least part of the superconducting metal layer, at least part of the base material is exposed to form a "V" shape. The second etching area is formed after etching away at least part of the superconducting metal layer used to form the second metal plate 112. Then, after etching away at least part of the superconducting metal layer, at least part of the base material is exposed to form a three-way shape.

[0145] Furthermore, this etching area (that is, the first etching area and the second etching area) surrounds the first metal electrode plate 111 and the second metal electrode plate 112. For example, the first etching area surrounds the bottom of the first metal electrode plate 111 and the two branches of the first metal electrode plate 111. The second etching area surrounds the bottom of the second metal electrode plate 112 and the three branches of the second metal electrode plate 112. Moreover, there is at least a partial overlapping area between the first etching area and the second etching area. For example, at least part of the etching area at the bottom of the "V" shape of the first metal electrode plate in the first etching area overlaps at least part of the etching area at the bottom of the three-way shape of the second metal electrode plate in the second etching area. In this way, an interval area is formed at the bottom of the "V" shape of the first metal electrode plate and the bottom of the three-way shape of the second metal electrode plate, providing a configuration support for forming a floating-type qubit.

[0146] The third part is the connection area, which overlaps with at least part of the etching area and is used to couple the first metal electrode plate 111 and the second metal electrode plate 112. For example, a connection component 113 is arranged in the interval area between the bottom of the "V" shape of the first metal electrode plate 111 and the bottom of the inverted "3" shape of the second metal electrode plate 112. For example, a Superconducting Quantum Interference Device (SQUID) 113 is arranged to couple the first metal electrode plate 111 and the second metal electrode plate 112. In this way, it is convenient to non-linearize the energy levels of the qubit.

[0147] In a specific example, the superconducting quantum interference device 113 includes a plurality (two or more) of Josephson junctions; further, the plurality of Josephson junctions are disposed in two different lines, and the two lines are connected in parallel. At this time, a Josephson junction loop can be formed; here, it should be noted that each line is provided with at least one Josephson junction, and moreover, the number of Josephson junctions provided in different lines can be the same or different, and the solution of the present disclosure does not limit this. For example, in one example, two Josephson junctions connected in parallel are provided in the connection region, and the first metal plate 111 and the second metal plate 112 arranged at intervals are coupled through the two Josephson junctions connected in parallel.

[0148] In addition, it can be pointed out that the superconducting metal layer outside the qubit configuration is a grounded metal, that is to say, other regions of the superconducting metal layer except for the qubit configuration are used for grounding.

[0149] It should be noted that in this example, the qubit is a floating type qubit; here, the floating type qubit refers to a connection component that couples two metal plates, such as a SQUID that is not directly grounded. In this way, since the connection component is not grounded, the floating type qubit is less affected by charge fluctuations, has better robustness to the environment, is more conducive to the design of a quantum chip of a three-dimensional flip-chip, and is also more conducive to the structural expansion and research and development of a superconducting quantum chip that needs to meet the following requirements. At the same time, it is of great benefit to wiring and crosstalk mitigation in the superconducting quantum chip. Here, the requirements that the superconducting quantum chip needs to meet are: containing a coupler, and the distance between adjacent qubits in the superconducting quantum chip is relatively far.

[0150] Here, it should be noted that for the superconducting quantum chip obtained by using the qubit solution of the present disclosure, since the effective interval between two adjacent qubits can be relatively far, it is more conducive to wiring, thereby providing a configuration support for effectively mitigating crosstalk. Moreover, since the effective interval between two adjacent qubits can be relatively far, it also provides a configuration support for meeting the following requirements: the coupling strength between two adjacent qubits is preferably large, and the coupling strength between next-nearest neighbor qubits is preferably small.

[0151] In one example, as Figure 1 or shown in Fig. 3(a), the included angle between the two branches of the "V" shape in the first metal plate 111 is a first angle, and the first angle is an acute angle. For example, in a specific example, the first angle is about 60 degrees. Further, in some specific examples, the first angle is 54 degrees; or, in other specific examples, the first angle is 60 degrees; or, in still other specific examples, the first angle is 66 degrees.

[0152] Furthermore, in one example, the first metal plate 111 is a symmetric figure, for example, an axisymmetric figure; as shown in FIG. 3(a), the first metal plate 111 is symmetric along the axis of symmetry A - A'.

[0153] Furthermore, in another example, as Figure 1 shown in FIG. 3(b) or the like, the included angle between two adjacent branches among the three branches of the second metal plate 112 is a second angle, and the second angle is an acute angle. For example, in a specific example, the second angle is about 60 degrees. Furthermore, in some specific examples, the second angle is 54 degrees; or, in other specific examples, the second angle is 60 degrees; or, in still other specific examples, the second angle is 66 degrees.

[0154] Here, it should be noted that the second angles formed by any two adjacent branches among the three branches of the second metal plate 112, for example, the degrees of the second angle - 1 and the second angle - 2, may be the same or different, and the solution of the present disclosure does not limit this. For example, in some specific examples, the second angle - 1 and the second angle - 2 are the same; furthermore, in some specific examples, both the second angle - 1 and the second angle - 2 are 60 degrees.

[0155] Furthermore, in one example, the second metal plate 112 is a symmetric figure, for example, an axisymmetric figure; as shown in FIG. 3(b), the second metal plate 112 is symmetric along the axis of symmetry B - B'.

[0156] Furthermore, in a specific example, the first angle, the second angle - 1, and the second angle - 2 are the same, for example, all 60 degrees.

[0157] Furthermore, in another example, as Figure 1 shown, the first branch (for example, denoted as b1) of the two branches of the "V" - shaped part is adjacent to the second branch (for example, denoted as b2) of the three branches of the three - branch part, and the included angle between the adjacent first branch and the second branch is a third angle, and the third angle is an obtuse angle, an acute angle, or a right angle.

[0158] Furthermore, in a specific example, the third angle is about 90 degrees. For example, in some specific examples, the third angle is 99 degrees; or, in other specific examples, the third angle is 90 degrees; or, in still other specific examples, the third angle is 81 degrees.

[0159] It should be noted that the third angles formed by any two adjacent first branch and second branch may be the same or different. For example, as Figure 1 shown, denote the two branches of the "V" - shaped part as the first branch b 11and the first branch b 12 , and the three branches of the three-way type are respectively denoted as the second branch b 21 , the second branch b 22 , and the second branch b 23 ; at this time, the first branch b 11 is adjacent to the second branch b 21 , and the included angle between the adjacent first branch b 11 and the second branch b 21 is the third angle; correspondingly, the first branch b 12 is adjacent to the second branch b 23 , and the included angle between the adjacent first branch b 12 and the second branch b 23 is also the third angle. Here, for the sake of distinction, the included angle formed by the adjacent first branch b 11 and the second branch b 21 is denoted as the third angle - 11, and the included angle formed by the adjacent first branch b 12 and the second branch b 23 is denoted as the third angle - 23. At this time, the third angle - 11 and the third angle - 23 can be the same or different, and the present disclosure scheme does not limit this.

[0160] Further, in one example, the third angle 11 is the same as the third angle 23, for example, both are 90 degrees.

[0161] In a specific example, as shown in FIG. 3(a), the dimensions of each part of the "V" shape in the configuration of the qubit need to satisfy at least one of the following:

[0162] The height of the first branch (for example, the first branch b 11 , or the first branch b 12 ) in the two branches of the "V" shape of the qubit is about 250 micrometers;

[0163] The bottom width of the "V" shape of the qubit is about 135 micrometers;

[0164] The width of the etching area around the first branch of the "V" shape of the qubit is about 12 micrometers - about 15 micrometers; for example, the height (which can also be called the width) of the etching area around the first branch of the "V" shape of the qubit in the first longitudinal direction is about 15 micrometers; the width of the etching area around the first branch of the "V" shape of the qubit in the first transverse direction is about 12 micrometers.

[0165] Here, it should be noted that the dimensions of different first branches can be the same or different, and the present disclosure scheme does not make specific limitations on this.

[0166] In another specific example, as shown in FIG. 3(b), the dimensions of each part of the three-way type in the configuration of the qubit need to satisfy at least one of the following:

[0167] The height of the second branch (for example, the second branch b 21 , or the second branch b 22 , or the second branch b 23 ) in the three branches of the three-way type of the qubit is about 245 micrometers;

[0168] The bottom width of the three-way type of the qubit is about 160 micrometers;

[0169] The width of the etching region around the second branch of the three-way type of the qubit is about 12 micrometers - about 15 micrometers; for example, the height (which can also be called the width) of the etching region around the second branch of the three-way type of the qubit in the second longitudinal direction is about 15 micrometers; the width of the etching region around the second branch of the three-way type of the qubit in the second transverse direction is about 12 micrometers.

[0170] In yet another specific example, as shown in FIG. 3(c), the configuration of the qubit further satisfies at least one of the following conditions:

[0171] The height of the qubit is about 619 micrometers;

[0172] The interval between the bottom of the "V" shape of the first metal plate and the bottom of the three-way type of the second metal plate is about 15 micrometers;

[0173] The effective length from the starting point to the inflection point in the first branch direction in the first etching region is about 240 micrometers.

[0174] Furthermore, in a specific example, the height of the qubit is 619 micrometers; furthermore, the interval between the bottom of the "V" shape of the first metal plate and the bottom of the three-way type of the second metal plate is 15 micrometers. Furthermore, the length from the starting point to the inflection point along the direction of the first branch in the first etching region is about 240 micrometers.

[0175] Here, it should be noted that the combined use of the term "about" and a numerical value is intended to indicate that the value is within ten percent (10%) of the recited numerical value, that is, within plus or minus ten percent of the recited numerical value.

[0176] It can be understood that the above-mentioned specific dimensions are only an example, and in actual applications, the specific dimensions can be adjusted according to actual needs; in other words, the core of the present disclosure mainly lies in providing a configuration of a qubit, and the selection of the substrate material and the adjustment of the specific dimensions can be set according to the actual situation.

[0177] Furthermore, with Figure 1Expand the configuration of the qubits shown as a unit to obtain Figure 6 the two-dimensional tiling unit shown; as Figure 6 shown, the two-dimensional tiling unit includes 5 qubits; among them, during the expansion process, each qubit can form nearest-neighbor coupling with other qubits through its own branches. It can be understood that since there are five branches for the qubit, so, the other qubits that are nearest-neighbor coupled to the qubit are 5 in total.

[0178] Further, the effective spacing between two nearest-neighbor coupled qubits in the two-dimensional tiling unit is 5 - 20 microns. For example, as Figure 4 or 5 shows, the spacing between the two branches used to make two qubits have nearest-neighbor coupling is 5 - 20 microns. For example, in some specific examples, the spacing between the two branches used to make two qubits have nearest-neighbor coupling in the two-dimensional tiling unit is 5 microns; or, in some other specific examples, the spacing between the two branches used to make two qubits have nearest-neighbor coupling in the two-dimensional tiling unit is 15 microns; or, in still some other specific examples, the spacing between the two branches used to make two qubits have nearest-neighbor coupling in the two-dimensional tiling unit is 20 microns.

[0179] It should be noted that the nearest-neighbor coupling described in the present disclosure scheme refers to the coupling between adjacent quantum devices; for example, as Figure 5 shown, qubit Q1 and qubit Q2 are two adjacent qubits. At this time, the coupling between qubit Q1 and qubit Q2 is nearest-neighbor coupling; similarly, qubit Q2 and qubit Q3 are two adjacent qubits. At this time, the coupling between qubit Q2 and qubit Q3 is also nearest-neighbor coupling.

[0180] It should be noted that qubit Q1 and qubit Q3 are two non-adjacent qubits. At this time, the coupling between qubit Q1 and qubit Q3 can be called next-nearest-neighbor coupling.

[0181] It should be noted that during the design process of the superconducting quantum chip, it is expected that the coupling strength between nearest-neighbor coupled qubits is as large as possible. In this way, it is convenient to implement quantum gates with higher fidelity, and at the same time, it is also convenient to implement quantum gates faster. For example, in the scenario of implementing a two-qubit gate based on two adjacent qubits, if the coupling strength between the two adjacent qubits is stronger, a two-qubit gate with higher fidelity can be implemented, and at the same time, the two-qubit gate can also be implemented faster. And the coupling strength of next-nearest-neighbor coupling is as small as possible. In this way, it is convenient to reduce the crosstalk caused by next-nearest-neighbor coupling.

[0182] Further, in one example, the figure enclosed by the branches of the qubits in the two-dimensional tiling unit (for example, 6 branches among three qubits) includes:

[0183] Quadrilateral, for example, a quadrilateral formed by 8 branches among four qubits;

[0184] Triangle, for example, a triangle formed by 6 branches among three qubits.

[0185] Further, in a specific example, the quadrilateral can be a square, for example, with an area of 536×536 square microns).

[0186] Or, in another specific example, the triangle can be an equilateral triangle.

[0187] In this way, other quantum devices in the superconducting quantum chip can be placed flexibly, such as quantum devices necessary for the design of superconducting quantum chips like readout cavities, filters, etc.

[0188] Further, in a specific example, as shown in Fig. 7(a), based on the two-dimensional tiling unit, expanding in the two-dimensional plane, for example, on the first plane where the first metal plate and the second metal plate are located, a superconducting quantum chip including multiple two-dimensional tiling units can be obtained. At this time, the superconducting quantum chip can be called a two-dimensional tiling structure satisfying the two-dimensional tiling condition.

[0189] It should be noted that the two-dimensional tiling structure can also be represented by the topological graph shown in Fig. 7(b), that is, Fig. 7(b) is the topological graph of Fig. 7(a). Among them, in this topological graph, points represent qubits in Fig. 7(a), and edges represent the coupling relationship between two adjacent qubits.

[0190] Therefore, the configuration of the qubits described in the present disclosure scheme is conducive to the large-scale expansion of qubits and has strong flexibility. For example, in practical applications, a coupling device (such as a coupler, qubit) for realizing the coupling function can also be inserted between two adjacent qubits to realize the design of the "Q-C-Q" quantum chip structure. At the same time, this design is compatible with the 3D flip-chip bonding process, and qubits, other quantum devices, and wiring can be distributed on different substrates (i.e., 3D flip-chip bonding substrates chip) to maximize the performance of the quantum chip.

[0191] It should be noted that, in a specific example, the configuration of the inserted coupling device is also the same as the configuration of the above-mentioned qubits. At this time, it can be understood that: when the number of other qubits that are closely coupled to the qubit is 2 or more, the qubit in the middle can be used as a coupling device to regulate the coupling strength between the two qubits coupled by the coupling device; as Figure 5 shown, the qubit Q2 can be used as a coupling device.

[0192] Part Two, Performance Analysis

[0193] (1) Basic Parameters of Quantum Bits

[0194] In this example, before performing the following performance analysis, the following parameters are fixed. For example, the substrate material is sapphire, the relative dielectric constant is set to 10, and the size (length × width × height) of the substrate material is: 2 mm × 2 mm × 0.4 mm. As Figure 8 shown, the specific parameters included in the configuration of the quantum bit are as follows:

[0195] The first angle, the second angle - 1, and the second angle - 2 are all 60 degrees;

[0196] The third angle - 11 and the third angle - 23 are both 90 degrees;

[0197] The "V" shape is an axisymmetric structure, and for each branch in the two branches of the "V" shape, for example, the first branch b 11 and the first branch b 12 have a height of 250 microns;

[0198] The bottom width of the "V" shape is 135 microns;

[0199] The etching area around the branch of the "V" shape (such as the first branch b 11 and the first branch b 12 ) has a height of 15 microns in the first longitudinal direction;

[0200] The etching area around the branch of the "V" shape (such as the first branch b 11 and the first branch b 12 ) has a width of 12 microns in the first transverse direction;

[0201] For each branch in the three branches of the three - branch shape (such as the second branch b 21 , or the second branch b 22 , or the second branch b 23 ) has a height of 245 microns;

[0202] The bottom width of the three - branch shape is 160 microns

[0203] The height of the quantum bit is 619 microns;

[0204] The interval between the bottom of the "V" shape and the bottom of the three - branch shape is 15 microns.

[0205] (1) Anharmonicity of Quantum Bits

[0206] For Figure 8 the shown quantum bit, electromagnetic simulation is performed, and the anharmonicity strength of the quantum bit is obtained as 220 MHz.

[0207] Here, the anharmonicity strength of the qubit refers to the difference between two energy differences; here, one of the two energy differences is the difference between the ground state energy and the first excited state energy of the qubit, and the other of the two energy differences is the difference between the first excited state energy and the second excited state energy. Generally, the anharmonicity strength of the qubit is between 200 - 300 MHz.

[0208] In addition, the capacitance of the qubit is related to the distance between the metal plate of the qubit and the grounded metal plate. For example, the closer the distance, the larger the capacitance. Further, the capacitance of the qubit can be controlled by adjusting the geometric parameters of the qubit, and thus the anharmonicity strength of the qubit can be controlled.

[0209] Further, denoting the anharmonicity strength of the qubit as α, the anharmonicity strength α of this qubit can be expressed by the following formula:

[0210]

[0211] Here, e represents the unit elementary charge, h represents the Planck constant, C 12 represents the mutual capacitance between the first metal plate 111 and the second metal plate 112, C 1g represents the mutual capacitance between the first metal plate 111 and the ground, C 2g represents the mutual capacitance between the second metal plate 112 and the ground.

[0212] (2) Frequency of the qubit

[0213] The frequency of the qubit can be adjusted by adjusting the current in the Z - line. For example, by applying a current to the Z - line to control the magnetic flux through the SQUID of the qubit, and thus the frequency of the qubit can be regulated; generally, the frequency of the qubit is 4 - 8 GHz.

[0214] (II) Coupling strength

[0215] Two - qubit gates are a necessary basis for realizing quantum computing. And realizing the quantum operation of two - qubit gates requires a coupling between two qubits. For example, by performing quantum operations on two adjacent qubits to realize two - qubit gates. At this time, the operation time of the quantum operation for realizing two - qubit gates can be determined by the coupling strength between two adjacent qubits.

[0216] This example takes gate as an example, and the operation time of the quantum operation for realizing two - qubit gate is Here, g represents the value used to realize this two - qubit The coupling strength between two qubits of the gate. Here, the geometric parameters of each qubit in two qubits with nearest-neighbor coupling are as Figure 8 shown, and the substrate material is sapphire with a relative dielectric constant of 10, and the effective interval between adjacent qubits is set to 10 microns. At this time, electromagnetic simulation is performed on two qubits with nearest-neighbor coupling, and the coupling strength g between the two qubits is obtained as 14.3 MHz.

[0217] Furthermore, taking the coupling strength g between two qubits as 14.3 MHz as an example, the operation time t of the two-qubit gate is calculated, that is, the operation time t for executing a gate is 8.7 ns. Thus, it can be seen that the coupling strength between two qubits formed by the novel qubit configuration in the present disclosure scheme is relatively strong, and higher-fidelity and faster two-qubit gates can be achieved.

[0218] Furthermore, as Figure 5 shown, the geometric parameters of each qubit in two qubits with next-nearest-neighbor coupling are as Figure 8 shown, and the effective interval between adjacent qubits is set to 10 microns. At this time, the next-nearest-neighbor coupling strength between qubit Q1 and qubit Q3 is simulated to be 0.165 MHz. Thus, it can be seen that the next-nearest-neighbor coupling strength is relatively small. In this way, based on the qubit configuration described in the present disclosure scheme, it is convenient to design a superconducting quantum chip with more excellent performance.

[0219] (III) Connectivity

[0220] In this example, based on the above two-dimensional tiling unit, two-dimensional tiling structures as shown in FIGS. 9(a) and 9(b) can be obtained; the two-dimensional tiling structure corresponding to FIG. 9(a) is a twisted square topological structure, which can be denoted as S = {S1, S2, S3,...}, where the specific structure shown in FIG. 9(a) is the structure of S4; further, the two-dimensional tiling structure corresponding to FIG. 9(b) is a 45° skew twisted square topological structure, which can be denoted as X = {X1, X2, X3,...}, where the specific structure shown in FIG. 9(b) is the structure of X3.

[0221] Compared with common quantum chips in the industry, for example, the one-dimensional chain superconducting quantum chip shown in FIG. 10(a), the 54-qubit quantum chip shown in FIG. 10(b), the 80-qubit quantum chip shown in FIG. 10(c), and the 127-qubit quantum chip shown in FIG. 10(d), S4 and X3 obtained from the quantum chip based on the present disclosure scheme have significant advantages in the connectivity of the planar configuration, as shown in Table 1 below:

[0222] Table 1

[0223]

[0224] The comparison results of the superconducting quantum chip obtained from the qubits described in the present disclosure solution and the existing superconducting quantum chips in terms of the connectivity of the planar configuration are shown in Table 2 below:

[0225] Table 2

[0226]

[0227] As can be seen from the above table, except for being slightly inferior to the regular triangular tiling network arranged in a regular hexagon, the connectivity of the present disclosure solution is far better than other solutions.

[0228] It should be noted that each qubit in the regular triangular tiling network is adjacent to at most 6 qubits, while the qubits in the present disclosure solution are adjacent to at most 5 qubits. Since the reduction in the number of adjacent qubits will reduce the crosstalk between qubits, therefore, compared with the existing regular triangular tiling network, the present disclosure solution can improve the fidelity of quantum gate operations. Thus, it is sufficient to compromise the slight disadvantage in connectivity.

[0229] In summary, the present disclosure solution provides a configuration of qubits with good scalability and excellent performance. At the same time, it also provides a superconducting quantum chip obtained by expanding the above qubits. Since the coupling strength between two adjacent qubits in this superconducting quantum chip is relatively strong, therefore, it can effectively reduce the average cost of performing a two-qubit gate between any two qubits in the superconducting quantum chip. Moreover, the connectivity of this superconducting quantum chip is high.

[0230] In addition, the space between qubits in the superconducting quantum chip provided by the present disclosure solution is relatively large. Thus, it provides sufficient design space for subsequent use, for example, it provides convenience for subsequent wiring such as adding readout cavities and measurement and control lines. Benefiting from this, the superconducting quantum chip based on the present disclosure solution is expected to achieve stronger performance and larger scale.

[0231] The specific features are summarized as follows:

[0232] I. High connectivity. The present disclosure solution adopts a special pentagon structure, and its mathematically abstract topological structure is proven to have strong connectivity. Benefiting from the strong connectivity, it is expected to further develop high-performance quantum chips. Further analysis shows that its connectivity is better than most existing design solutions in the industry;

[0233] II. Good scalability. In the process of tiling into a quantum chip, the present disclosure solution makes full use of the entire space of the chip. When the number of qubits scales up, its advantages will be further highlighted;

[0234] Third, the design of the readout cavity and the measurement and control lines is more convenient. In the design of the present disclosure solution, the intervals between the centers of each bit are very large. This makes the design of the readout cavity and the measurement and control lines convenient. In addition, due to the large intervals between the bits, it can prevent the problem of mutual crosstalk. This makes this structure very suitable for use in applications that require high-precision readout and control;

[0235] Fourth, the coupling strength of the next-nearest neighbors is low. In the present disclosure solution, the intervals between the qubits are large, so that the coupling strength between the next-nearest neighbor qubits is low. In this way, unnecessary parasitic coupling can be suppressed to the greatest extent.

[0236] The above specific implementation manners do not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A quantum chip, comprising: At least one qubit; Wherein, the configuration of the qubit includes: A first metal plate located in a first plane, wherein the first metal plate is in a "V" shape; A second metal plate located in the first plane, wherein the second metal plate is in a three-way shape; A connection component located between the first metal plate and the second metal plate for coupling the first metal plate and the second metal plate; The qubit includes five branches, namely two branches of the "V" shape and three branches of the three-way shape, wherein each branch can be coupled with other qubits; When the quantum chip contains five or more qubits, the five or more qubits can form a two-dimensional close-packed unit on the first plane; The figures enclosed by the branches of the qubits in the two-dimensional close-packed unit include: quadrilaterals and triangles.

2. The quantum chip according to claim 1, wherein, The bottom of the "V" shape of the first metal plate and the bottom of the three-way shape of the second metal plate are arranged at intervals, so that the two branches of the "V" shape and the three branches of the three-way shape extend in different directions.

3. The quantum chip according to claim 2, wherein, The connection component is placed in the interval area between the bottom of the "V" shape of the first metal plate and the bottom of the three-way shape of the second metal plate.

4. The quantum chip according to claim 3, wherein, At least one of the areas where the connection component, the first metal plate, and the second metal plate are located is a non-grounding area.

5. The quantum chip according to claim 1, wherein, The qubit is a floating-ground qubit.

6. The quantum chip according to any one of claims 1-5, wherein, The connection component is a superconducting quantum interference device.

7. The quantum chip according to claim 6, wherein, The superconducting quantum interference device contains two or more Josephson junctions.

8. The quantum chip according to claim 7, wherein Two or more Josephson junctions are placed in two parallel lines, and the number of Josephson junctions contained in each line in the two lines is the same or different.

9. The quantum chip according to claim 6, wherein The superconducting quantum interference device contains two parallel Josephson junctions.

10. The quantum chip according to any one of claims 1-5, wherein, The configuration of the qubit also satisfies at least one of the following conditions: The included angle between the two branches of the "V" shape is a first angle; the first angle is an acute angle; The included angle between two adjacent branches among the three branches of the three-way shape is a second angle; the second angle is an acute angle; The first branch among the two branches of the "V" shape is adjacent to the second branch among the three branches of the three-way shape, and the included angle between the adjacent first branch and the second branch is a third angle, and the third angle is an obtuse angle, an acute angle or a right angle.

11. The quantum chip according to claim 10, wherein, The first angle and the second angle are the same.

12. The quantum chip according to claim 10, wherein, The first angle is about 60 degrees; Wherein, about: means that the value is within ten percent of the numerical value.

13. The quantum chip according to claim 10, wherein, The second angle is about 60 degrees; wherein, about: means that the value is within ten percent of the numerical value.

14. The quantum chip according to claim 10, wherein, The third angle is about 90 degrees, Wherein, about: means that the value is within ten percent of the numerical value.

15. The quantum chip according to any one of claims 1-5, wherein, The periphery of the first metal plate is a first etching area, and the first etching area is formed after etching at least part of the area of the metal layer used to form the first metal plate; Or, The periphery of the second metal plate is a second etching area, and the second etching area is formed after etching at least part of the area of the metal layer used to form the second metal plate.

16. The quantum chip according to claim 15, wherein, The dimensions of each part in the "V" shape satisfy at least one of the following conditions: The height of the first branch in the two branches of the "V" shape is about 250 micrometers; The width of the bottom of the "V" shape is about 135 micrometers; The width of at least part of the etching area around the first branch in the two branches of the "V" shape in the first etching area is about 12 micrometers - about 15 micrometers; Herein, "about" means that the value is within ten percent of the numerical value.

17. The quantum chip according to claim 16, wherein, The "V" shape is a symmetric figure.

18. The quantum chip according to claim 16, wherein, The width of the partial etching area around the first branch of the "V" shape in the first etching area in the first longitudinal direction is about 15 micrometers; Or, The width of at least part of the etching area around the first branch of the "V" shape in the first etching area in the first transverse direction is about 12 micrometers; Herein, "about" means that the value is within ten percent of the numerical value.

19. The quantum chip according to claim 15, wherein, The dimensions of each part in the three-branch shape satisfy at least one of the following conditions: The height of the second branch in the three branches of the three-branch shape is about 245 micrometers; The width of the bottom of the three-branch shape is about 160 micrometers; The width of at least part of the etching area around the second branch in the three branches of the three-branch shape in the second etching area is about 12 micrometers - about 15 micrometers; Herein, "about" means that the value is within ten percent of the numerical value.

20. The quantum chip according to claim 19, wherein, The three-branch shape is a symmetric figure.

21. The quantum chip according to claim 19, wherein, The width of at least part of the etching area around the second branch of the three-branch shape in the second etching area in the second longitudinal direction is about 15 micrometers; Or, The width of at least part of the etching area around the second branch of the three-branch shape in the second etching area in the second transverse direction is about 12 micrometers; Herein, "about" means that the value is within ten percent of the numerical value.

22. The quantum chip according to any one of claims 2-5, wherein, The configuration of the quantum bit also satisfies at least one of the following conditions: The height of the quantum bit is about 619 micrometers; The interval between the bottom of the "V" shape of the first metal plate and the bottom of the three-branch shape of the second metal plate is about 15 micrometers; Herein, "about" means that the value is within ten percent of the numerical value.

23. The quantum chip according to any one of claims 1-5, wherein, When the quantum chip includes two or more quantum bits, two adjacent quantum bits are coupled through the branches of the quantum bit; Herein, the branches of the quantum bit are any one of the following: the two branches of the "V" shape, and the three branches of the three-branch shape.

24. The quantum chip according to claim 23, wherein The number of other quantum bits that are proximally coupled to the quantum bit is less than or equal to 5.

25. The quantum chip according to claim 23, wherein, When the number of other quantum bits that are proximally coupled to the quantum bit is 2 or more, the quantum bit in the middle can be used as a coupling device to regulate the coupling strength between the two quantum bits coupled by the coupling device.

26. The quantum chip according to claim 23, wherein The interval between the branches for proximally coupling two quantum bits is 5 - 20 micrometers.

27. The quantum chip according to any one of claims 1 - 5, wherein the quadrilateral is a square; and / or, the triangle is an equilateral triangle.

28. The quantum chip according to any one of claims 1-5, wherein, The quantum chip can form a two-dimensional close-packing structure that satisfies the two-dimensional close-packing condition; wherein, the two-dimensional close-packing structure includes at least one two-dimensional close-packing unit.

29. The quantum chip according to claim 28, wherein, The maximum connectivity of the two-dimensional close-packing structure formed by the quantum chip is less than 0.57; The maximum connectivity represents the connectivity of the quantum chip when the number of quantum bits of the quantum chip is infinite.

30. The quantum chip according to any one of claims 1-5, wherein, The quantum chip further includes: A control line, one end of the control line is used to connect to the control port of the qubit, and the other end of the control line of the qubit is used to connect to the first pin to connect to an external control system through the first pin; and / or A read line, one end of the read line is used to connect to the read port of the qubit, and the read line of the qubit is used to connect to the second pin to connect to an external control system through the second pin.

31. The quantum chip according to any one of claims 1-5, wherein, The quantum chip is a superconducting quantum chip.

32. A quantum computer, comprising at least the quantum chip according to any one of claims 1 to 31, and an external control system connected to the quantum chip.

33. A method for manufacturing a quantum chip, comprising: Forming a base material layer; Forming a metal layer on the base material layer; Performing an etching process to etch away at least part of the metal layer and expose at least part of the base material layer to form the configuration of the qubit according to any one of claims 1 to 31; Setting up connection components to couple the first metal plate and the second metal plate included in the qubit configuration.

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