Method of forming a semiconductor structure
By forming a shielding layer in the semiconductor structure and selectively removing the sidewall layer, the problem of not being able to form AIM overlay alignment marks in the prior art is solved, thereby improving the overlay accuracy and reducing the cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-07-03
- Publication Date
- 2026-07-03
AI Technical Summary
Existing semiconductor structure formation methods cannot form advanced image measurement alignment marks (AIM), resulting in reduced alignment accuracy and affecting semiconductor process.
By forming a masking layer on the substrate, the sidewall layer and mask layer are selectively removed to form an integral overlay alignment mark without sub-patterns. The masking layer is used to selectively remove the patterns in the array area and the alignment mark area, thereby improving the overlay accuracy.
By employing self-aligned dual imaging technology to form the target pattern, the accuracy of overlay alignment marks is improved, and manufacturing costs are reduced.
Smart Images
Figure CN116798924B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuits, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] In semiconductor manufacturing, the pattern after exposure and development (i.e., the current layer) must be aligned with the existing pattern on the wafer substrate (i.e., the previous layer) to ensure correct interconnection between devices. The relative position between the current layer and the previous layer of the exposed pattern is called overlay error. Excessive overlay error will cause short circuits or open circuits in devices, affecting product yield. Through measurement and analysis of alignment marks, the photolithography system can pre-compensate for some of the overlay errors caused by previous processes on the wafer.
[0003] Image-based overlay (IBO) is a primary overlay alignment marker used for overlay value measurement. Advanced imaging metrology (AIM) is a type of IBO. AIM often has a stronger marker signal, significantly improving overlay accuracy. However, current semiconductor fabrication methods cannot form AIM; for example, self-aligned double-patterning (SADP) technology cannot form AIM, which reduces the accuracy of overlay in semiconductor processes. Summary of the Invention
[0004] The technical problem to be solved by this disclosure is to provide a method for forming a semiconductor structure that can form standard alignment marks, thereby greatly improving the accuracy of stacking in semiconductor processes.
[0005] To address the aforementioned problems, this disclosure provides a method for forming a semiconductor structure, comprising:
[0006] A substrate is provided, the substrate including an array region and an alignment mark region, a mask layer, a pattern layer and a sidewall layer are disposed on the substrate, the pattern layer having a first pattern in the array region, the pattern layer having a second pattern in the alignment mark region, and the sidewall layer covering the sidewalls and top surface of the first pattern and the second pattern, and covering the exposed surface of the mask layer.
[0007] A shielding layer is formed in the array area, where the shielding layer fills the gaps in the sidewall layer and exposes the top surface of the sidewall layer; in the alignment mark area, the shielding layer fills the gaps in the sidewall layer and covers the top surface of the sidewall layer.
[0008] Using the shielding layer as a shield, a portion of the sidewall layer is removed to expose the top surface of the first pattern;
[0009] Remove the shielding layer and part of the sidewall layer, and retain the sidewall layer of the first and second graphic sidewalls as sidewalls;
[0010] The graphic layer is removed from the array region, and the sidewalls form a third graphic.
[0011] In the array area, the third pattern is used as a mask, and in the alignment mark area, the second pattern and the sidewalls are used as masks to remove part of the mask layer to form a mask pattern.
[0012] The mask pattern is transferred into the substrate to form the target pattern in the array region and to form overlay alignment marks in the alignment mark region.
[0013] In one embodiment, the step of forming the shielding layer includes:
[0014] A shielding material layer is formed, which fills the gaps in the sidewall layer and covers the top surface of the sidewall layer. In the array area, the top surface of the shielding material layer has a first height to the top surface of the sidewall layer. In the alignment mark area, the top surface of the shielding material layer has a second height to the top surface of the sidewall layer, and the second height is greater than the first height.
[0015] The shielding material layer is thinned to form the shielding layer.
[0016] In one embodiment, in the step of providing a substrate, the pattern density of the first pattern is greater than the pattern density of the second pattern, and in the step of forming a shielding material layer, the initial amount of shielding material layer deposited in the array region and the alignment mark region is the same.
[0017] In one embodiment, the substrate further includes a peripheral region, and the step of providing a substrate includes:
[0018] A mask layer and a pattern material layer are formed on the substrate, and the pattern material layer is patterned to form the first pattern in the array region, the second pattern in the alignment mark region, and the pattern material layer located in the peripheral region is retained;
[0019] Form the sidewall layer;
[0020] In the step of forming the shielding material layer, in the peripheral area, the top surface of the shielding material layer to the top surface of the sidewall layer has a third height, which is greater than the second height;
[0021] In the step of thinning the shielding material layer to form the shielding layer, the shielding layer also covers the top surface of the sidewall layer of the peripheral area.
[0022] In one embodiment, the third height is 1.5 to 2.5 times the height of the first graphic.
[0023] In one embodiment, the height of the sidewall layer located on the top surface of the first graphic is less than the difference between the second height and the first height.
[0024] In one embodiment, during the step of removing a portion of the sidewall layer while using the shielding layer as a shield, the shielding layer of the alignment marking area is thinned and the sidewall layer is not exposed.
[0025] In one embodiment, the pattern layer includes a first sub-pattern layer and a second sub-pattern layer stacked together; in the step of removing the occlusion layer and part of the sidewall layer, the sidewall layer is etched using an etching process, and the etching rate of the etching material on the sidewall layer is greater than the etching rate on the second sub-pattern layer.
[0026] In one embodiment, the width of the gap between adjacent second patterns is greater than the critical dimension of the overlay alignment mark.
[0027] In one embodiment, in the steps of transferring a mask pattern into the substrate to form a target pattern in the array region and forming an overlay alignment mark in the alignment mark region, the critical dimension of the target pattern is smaller than the critical dimension of the overlay alignment mark.
[0028] In the formation method provided in this disclosure, the shielding layer is used to selectively remove the patterns of the array region and the alignment mark region in the same step. This allows for the formation of an integral overlay alignment mark without sub-patterns in the alignment mark region, i.e., the formation of a standard overlay alignment mark, significantly improving the accuracy of overlay in semiconductor processes. Furthermore, the formation method provided in this disclosure can simultaneously form an integral overlay alignment mark without sub-patterns in the alignment mark region using SADP technology while forming the target pattern in the array region, reducing manufacturing costs. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of an overlay alignment mark;
[0030] Figure 2 yes Figure 1 Enlarged schematic diagram of graphic 101A;
[0031] Figure 3 This is a schematic diagram of the steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
[0032] Figures 4A to 4I This is a schematic diagram of a semiconductor structure formed by the main steps of a formation method provided in an embodiment of the present disclosure. Detailed Implementation
[0033] The specific implementation of the semiconductor structure formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0034] Figure 1 This is a schematic diagram of an overlay alignment mark; please refer to [link / reference]. Figure 1 The overlay alignment mark is AIM. Both the previous layer overlay alignment mark and the current layer overlay alignment mark of the AIM are composed of corresponding lines. Figure 1 In this process, the previous layer overlay alignment marks are formed by the lines corresponding to mark 101, and the current layer overlay alignment marks are formed by the lines in the region corresponding to mark 102. In actual manufacturing, the previous layer overlay alignment marks are formed in the previous lithography process, and the current layer overlay alignment marks are formed in the current lithography process. The overlay error is obtained by measuring the positional relationship between the previous layer overlay alignment marks and the current layer overlay alignment marks. AIM often has stronger marking signals, which can accurately obtain the previous layer overlay alignment marks and the current layer overlay alignment marks, and thus accurately obtain the positional relationship between them, greatly improving the accuracy of stacking in semiconductor processes.
[0035] However, in some semiconductor structure formation methods, the alignment marks are formed simultaneously with the functional structure of the array region (e.g., bit line structure), which can lead to the inability to form standard alignment marks. Specifically, in some semiconductor structure formation methods, self-aligned double patterning (SADP) is used to form the bit line structure of the array region, and the alignment marks are also formed simultaneously using this SADP technique. This results in each pattern in the formed alignment marks consisting of multiple spaced sub-patterns, such as... Figure 2 As shown, it is Figure 1 The enlarged schematic diagram of pattern 101A shows that pattern 101A is composed of multiple sub-patterns 201, rather than a single monolithic structure without sub-patterns. This reduces the signal strength of the alignment mark during overlay, thus decreasing the accuracy of overlay in the semiconductor process. If the spacing between adjacent sub-patterns 201 is too large, each sub-pattern 201 will be identified as an independent pattern, failing to form a valid pattern 101A. This further leads to the inability to effectively capture the alignment mark in the semiconductor process, affecting the semiconductor process.
[0036] In view of this, the present disclosure provides a method for forming a semiconductor structure, which can form standard overlay alignment marks, greatly improving the accuracy of overlay in semiconductor processes. Furthermore, while forming the target pattern in the array region using SADP process, an integral overlay alignment mark without sub-patterns is formed in the alignment mark region, reducing manufacturing costs.
[0037] Figure 3 This is a schematic diagram illustrating the steps of a method for forming a semiconductor structure according to an embodiment of this disclosure. Please refer to [link / reference Figure 3 The forming method includes: step S30, providing a substrate, the substrate including an array region and an alignment mark region, a mask layer, a pattern layer and a sidewall layer disposed on the substrate, the pattern layer in the array region having a first pattern, the pattern layer in the alignment mark region having a second pattern, the sidewall layer covering the sidewalls and top surface of the first pattern and the second pattern, and covering the exposed surface of the mask layer; step S31, forming a shielding layer, the shielding layer in the array region filling the gaps in the sidewall layer and exposing the top surface of the sidewall layer, the shielding layer in the alignment mark region filling the gaps in the sidewall layer and covering the top surface of the sidewall layer; step S32, to shield... Step S33: Remove the shielding layer and part of the sidewall layer to expose the top surface of the first pattern; Step S34: Remove the shielding layer and part of the sidewall layer, and retain the sidewall layers of the first and second patterns as sidewalls; Step S35: Remove the pattern layer in the array area, and the sidewalls form the third pattern; Step S36: Use the third pattern as a shield in the array area and the second pattern and sidewalls as shields in the alignment mark area to remove part of the mask layer to form a mask pattern; Step S37: Transfer the mask pattern to the substrate to form the target pattern in the array area and to form overlay alignment marks in the alignment mark area.
[0038] In the formation method provided in the embodiments of this disclosure, the patterns of the array area and the alignment mark area are selectively removed in the same step by using a shielding layer, thereby forming an integral overlay alignment mark without sub-patterns in the alignment mark area, that is, forming a standard overlay alignment mark, which greatly improves the accuracy of stacking in semiconductor process.
[0039] Figures 4A to 4I This is a schematic diagram of a semiconductor structure formed by the main steps of a formation method provided in an embodiment of the present disclosure.
[0040] Please see Figure 3 and Figure 4B , among which, Figure 4B In the diagram, (a) is a schematic diagram of the array region AA, (b) is a schematic diagram of the alignment mark region MA, and (c) is a schematic diagram of the peripheral region PA. In step S30, a substrate 400 is provided. The substrate 400 includes the array region AA and the alignment mark region MA. A mask layer 410, a pattern layer 420, and a sidewall layer 430 are disposed on the substrate 400. The pattern layer 420 of the array region AA has a first pattern 421, and the pattern layer 420 of the alignment mark region MA has a second pattern 422. The sidewall layer 430 covers the sidewalls and top surface of the first pattern 421 and the second pattern 422, and also covers the exposed surface of the mask layer 410.
[0041] The substrate 400 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 400 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 400 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 400 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed within the substrate 400. In this embodiment, the substrate 400 is a silicon substrate, and it may also include other device structures, such as transistor structures, metal wiring structures, etc.
[0042] The alignment mark region MA is a region used to form alignment marks, such as a dicing track on a wafer. The array region AA may include multiple sub-array regions, and the alignment mark region MA may be located between adjacent sub-array regions or on the periphery of the array region AA. In some embodiments, the substrate 400 further includes a peripheral region PA located on the periphery of the array region AA.
[0043] The mask layer 410 covers the surface of the substrate 400 and is located in the array region AA, the alignment mark region MA, and the peripheral region PA. In some embodiments, the mask layer 410 is a composite film structure composed of multiple film layers. For example, the mask layer 410 is a composite film structure composed of at least two of a hard mask layer, a polysilicon layer, and a nitride layer. In other embodiments, the mask layer 410 may also be a single film layer. In this embodiment, an example is given of a composite film structure composed of a hard mask layer 411, a polysilicon layer 412, and a nitride layer 413.
[0044] A pattern layer 420 is disposed on the surface of the mask layer 410. Specifically, in this embodiment, the pattern layer 420 is disposed on the surface of the nitride layer. In the array region AA, the pattern layer 420 has a first pattern 421, and the gap between adjacent first patterns 421 exposes the surface of the mask layer 410; in the alignment mark region MA, the pattern layer 420 has a second pattern 422, and the gap between adjacent second patterns 422 exposes the surface of the mask layer 410; in the peripheral region PA, the pattern layer 420 does not have a pattern, that is, in the peripheral region PA, the pattern layer 420 covers the entire surface of the mask layer 410, and the mask layer 410 is not exposed.
[0045] In some embodiments, the gap 4221 between adjacent second patterns 422 (see...) Figure 4AThe critical dimensions of the overlay alignment mark 471 can be set according to the required dimensions. In this embodiment, a sidewall layer 430 is also provided between the second patterns 422. Therefore, in order to form an overlay alignment mark 471 with a set size, the width W1 of the gap 4221 between adjacent second patterns 422 is greater than the critical dimension CD2 of the overlay alignment mark 471 (see...). Figure 4I ).
[0046] The key dimensions of the first graphic 421 and the second graphic 422 may be the same or different. For example, in this embodiment, the key dimension of the first graphic 421 is smaller than the key dimension of the second graphic 422. In other embodiments, the key dimensions of the first graphic 421 may be the same as the key dimensions of the second graphic 422.
[0047] In some embodiments, such as Figure 4A As shown, the patterning layer 420 includes a first sub-patterning layer 420A and a second sub-patterning layer 420B stacked together. The first sub-patterning layer 420A is disposed on the surface of the mask layer 410, and the second sub-patterning layer 420B is disposed on the surface of the first sub-patterning layer 420A. In the direction perpendicular to the surface of the substrate 400 (as shown by the Z direction in the figure), the thickness of the first sub-patterning layer 420A is greater than the thickness of the second sub-patterning layer 420B. In this embodiment, the first sub-patterning layer 420A is a polysilicon layer and the second sub-patterning layer 420B is a silicon nitride layer as an example for explanation.
[0048] The sidewall layer 430 covers the exposed surfaces of the pattern layer 420 and the mask layer 410 along the contour of the pattern layer 420. In some embodiments, the sidewall layer 430 is an oxide layer; in this embodiment, a silicon oxide layer is used as an example. The sidewall layer 430 is relatively thin and does not fill the gaps between adjacent first patterns 421 and adjacent second patterns 422. In the direction parallel to the surface of the substrate 400 (as shown by the X direction in the figure), the sidewall layer 430 has gaps 4301 and 4302 in the array region AA and the alignment mark region MA. In the peripheral region PA, since the pattern layer 420 does not have a pattern, the sidewall layer 430 also does not have a pattern and covers the entire surface of the pattern layer 420.
[0049] As an example, the steps of providing a substrate 400 include:
[0050] Please see Figure 4A , among which, Figure 4AIn the diagram, (a) is a schematic diagram of the array region AA, (b) is a schematic diagram of the alignment mark region MA, and (c) is a schematic diagram of the peripheral region PA. A mask layer 410 and a patterned material layer are formed on the substrate 400, and the patterned material layer is patterned to form a first pattern 421 in the array region AA and a second pattern 422 in the alignment mark region MA. The patterned material layer in the peripheral region PA is retained. In this step, the patterned material layer in the peripheral region PA is not patterned and has a flat surface. The patterned patterned material layer is referred to as the pattern layer 420.
[0051] Please see Figure 4B The sidewall layer 430 is formed. In this step, chemical vapor deposition, atomic layer deposition, or other processes can be used to form the sidewall layer 430.
[0052] Please see Figure 3 and Figure 4D , among which, Figure 4D In the diagram, (a) is a schematic diagram of the array region AA, (b) is a schematic diagram of the alignment mark region MA, and (c) is a schematic diagram of the peripheral region PA. In step S31, a shielding layer 440 is formed. In the array region AA, the shielding layer 440 fills the gaps 4301 of the sidewall layer 430 and exposes the top surface of the sidewall layer 430. In the alignment mark region MA, the shielding layer 440 fills the gaps 4302 of the sidewall layer 430 and covers the top surface of the sidewall layer 430. In some embodiments, in the peripheral region PA, the shielding layer 440 also covers the top surface of the sidewall layer 430.
[0053] This disclosure provides a method for forming a shielding layer 440. The method includes:
[0054] Please see Figure 4C , among which, Figure 4C In the diagram, (a) is a schematic diagram of the array region AA, (b) is a schematic diagram of the alignment mark region MA, and (c) is a schematic diagram of the peripheral region PA. A shielding material layer 441 is formed, which fills the gaps 4301 and 4302 in the sidewall layer 430 and covers the top surface of the sidewall layer 430. In the array region AA, the top surface of the shielding material layer 441 to the top surface of the sidewall layer 430 has a first height H1. In the alignment mark region MA, the top surface of the shielding material layer 441 to the top surface of the sidewall layer 430 has a second height H2. The second height H2 is greater than the first height H1. Therefore, in the subsequent step of thinning the shielding material layer 441, the top surface of the sidewall layer 430 in the array region AA can be exposed, and the top surface of the sidewall layer 430 in the alignment mark region MA can be covered by the shielding layer 440.
[0055] In one embodiment, the difference in pattern density between the first pattern 421 and the second pattern 422 in the pattern layer 420 makes the second height H2 greater than the first height H1. Specifically, in the step of forming the shielding material layer 441, the initial amount of shielding material layer 441 deposited in the array region AA and the alignment mark region MA is the same, that is, the amount of deposits provided in the array region AA and the alignment mark region MA for forming the shielding material layer 441 is the same. When the pattern density of the first pattern 421 is greater than the pattern density of the second pattern 422, there are fewer voids in the alignment mark region MA, and more deposits are deposited on the top surface of the alignment mark region MA, thereby making the second height H2 greater than the first height H1.
[0056] In this embodiment, in the peripheral region PA, the shielding material layer 441 also covers the top surface of the sidewall layer 430. The top surface of the shielding material layer 441 to the top surface of the sidewall layer 430 has a third height H3, which is greater than the second height H2. Since the patterned layer 420 in the peripheral region PA has no pattern, the height of the shielding material layer 441 formed in the peripheral region PA is the largest when the amount of deposit used to form the shielding material layer 441 is the same.
[0057] In some embodiments, the height of the shielding material layer 441 of the peripheral region PA can be controlled to ensure that the top surface of the sidewall layer 430 of the array region AA can be exposed after the shielding material layer 441 is thinned, and the top surface of the sidewall layer 430 of the alignment mark region MA can be covered by the shielding layer 440. For example, in some embodiments, the third height H3 is set to 1.5 to 2.5 times the height H4 of the first pattern 421. If the third height H3 is less than 1.5 times the height H4 of the first pattern 421, the top surface of the sidewall layer 430 of the alignment mark region MA may be exposed after the shielding material layer 441 is thinned. If the third height H3 is greater than 2.5 times the height H4 of the first pattern 421, although it can be ensured that the top surface of the sidewall layer 430 of the alignment mark region MA is covered by the shielding layer 440 after the shielding material layer 441 is thinned, it will lead to increased costs.
[0058] Furthermore, in some embodiments, the height of the sidewall layer 430 located on the top surface of the first pattern 421 is less than the difference between the second height H2 and the first height H1, so as to further ensure that after the shielding material layer 441 is thinned, the top surface of the sidewall layer 430 of the array area AA can be exposed, and the top surface of the sidewall layer 430 of the alignment mark area MA can be covered by the shielding layer 440.
[0059] Please see Figure 4DThe shielding material layer 441 is thinned to form a shielding layer 440. In some embodiments, the shielding material layer 441 can be thinned by processes such as back etching. In this step, the shielding material layer 441 located in the array region AA is thinned to expose the top surface of the sidewall layer 430, that is, the shielding layer 440 does not cover the top surface of the sidewall layer 430; in the alignment mark region MA, after the shielding material layer 441 is thinned, the remaining shielding material layer 441 serves as the shielding layer 440, and its top surface is a distance from the top surface of the sidewall layer 430, so the top surface of the sidewall layer 430 is not exposed; in the peripheral region PA, the remaining shielding material layer 441 serves as the shielding layer 440, and its top surface is another distance from the top surface of the sidewall layer 430, and the distance from the top surface of the shielding layer 440 to the top surface of the sidewall layer 430 is the largest in the peripheral region PA.
[0060] In the above embodiments, the thickness of the shielding material layer 441 formed by depositing the same initial amount of deposition material in different areas in the same step is different to achieve the difference in shielding of the pattern in different areas, so as to facilitate the subsequent process.
[0061] Please see Figure 3 and Figure 4E , among which, Figure 4E In the diagram, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the alignment mark area MA, and (c) is a schematic diagram of the peripheral area PA. In step S32, using the occlusion layer 440 as an occlusion, part of the sidewall layer 430 is removed to expose the top surface of the first pattern 421.
[0062] In some embodiments, the top surface of the sidewall layer 430 located in the array region AA is exposed to the shielding layer 440, and the top surface of the sidewall layer 430 located in the alignment mark region MA and the peripheral region PA is covered by the shielding layer 440. In this step, only the sidewall layer 430 of the array region AA is partially removed until the top surface of the first pattern 421 is exposed, while the shielding layer 440 of the alignment mark region MA and the peripheral region PA is thinned and the top surface of the sidewall layer 430 is not exposed. In some embodiments, the shielding layer 440 of the array region AA is also thinned to below the top surface of the sidewall layer 430.
[0063] In some embodiments, an etching process is used to etch the sidewall layer 430, wherein the etching rate of the etching material on the sidewall layer 430 is greater than the etching rate on the shielding layer 440, so that the shielding layer 440 is avoided as much as possible when removing the sidewall layer 430, thereby avoiding the removal of the sidewall layer 430 of the alignment mark area MA and the peripheral area PA.
[0064] Please see Figure 3 and Figure 4F , among which, Figure 4FIn the diagram, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the alignment mark area MA, and (c) is a schematic diagram of the peripheral area PA. In step S33, the obscuring layer 440 and part of the sidewall layer 430 are removed. The sidewall layer 430 of the sidewalls of the first pattern 421 and the second pattern 422 is retained and used as the sidewall 450.
[0065] In this step, after removing the masking layer 440, the sidewall layer 430 on the surface of the mask layer 410 is exposed. Then, the sidewall layer 430 on the surface of the mask layer 410 is removed, and the mask layer 410 is exposed. The sidewall layer 430 of the sidewalls of the first pattern 421 and the second pattern 422 is retained, and the retained sidewall layer 430 serves as the sidewall 450.
[0066] In some embodiments, in the array region AA, the top surface of the first pattern 421 does not cover the sidewall layer 430. Therefore, when the sidewall layer 430 is removed, the first pattern 421 is thinned; for example, the second sub-pattern layer 420B in the first pattern 421 is thinned. In this embodiment, the second sub-pattern layer 420B is completely removed, exposing the first sub-pattern layer 420A in the pattern layer 420 of the array region AA, and exposing the second sub-pattern layer 420B in the pattern layer 420 of the alignment mark region MA and the peripheral region PA.
[0067] In some embodiments, an etching process is used when removing the sidewall layer 430, and the etching rate of the etching material on the sidewall layer 430 is greater than the etching rate on the pattern layer 420. For example, the etching rate of the etching material on the sidewall layer 430 is greater than the etching rate on the second sub-pattern layer 420B, so as to avoid thinning of the pattern layer 420 as much as possible. In addition, the pattern layer 420 can also be used as an etching stop layer in the alignment mark area MA and the peripheral area PA.
[0068] Please see Figure 3 and Figure 4G , among which, Figure 4G In the diagram, (a) is a schematic diagram of the array region AA, (b) is a schematic diagram of the alignment mark region MA, and (c) is a schematic diagram of the peripheral region PA. In step S34, the pattern layer 420 is removed from the array region AA, the sidewalls form a third pattern 423, and the mask layer 410 is exposed in the gap between the adjacent sidewalls 450 of the array region AA and the alignment mark region MA. In the peripheral region PA, the surface of the mask layer 410 is covered by the pattern layer 420.
[0069] In this embodiment, in this step, an etching material is selected such that its etching rate on the first sub-pattern layer 420A is greater than its etching rate on the second sub-pattern layer 420B. Then, after the step of removing the pattern layer 420, the pattern layer 420 of the alignment mark area MA and the peripheral area PA is retained, while the pattern layer 420 of the array area AA is removed.
[0070] Please see Figure 3 and Figure 4H , among which, Figure 4H In the diagram, (a) is a schematic diagram of the array region AA, (b) is a schematic diagram of the alignment mark region MA, and (c) is a schematic diagram of the peripheral region PA. In step S35, the third pattern 423 is used as a mask in the array region AA, and the second pattern 422 and the sidewall 450 are used as masks in the alignment mark region MA to remove part of the mask layer 410 to form mask patterns 460 and 461. In some embodiments, the mask layer 410 may be etched using an etching process.
[0071] In the array region AA, a mask pattern 460 with the same width as the third pattern 423 is formed in the mask layer 410; in the alignment mark region MA, a mask pattern 461 with the same width as the sum of the widths of the sidewall 450 and the second pattern 422 is formed in the mask layer 410; in the peripheral region PA, the pattern layer 420 on the surface of the mask layer 410 is removed, and the mask layer 410 is exposed.
[0072] In this embodiment, the mask layer 410 is a composite film layer composed of a hard mask layer, a polysilicon layer and a nitride layer. When forming the mask pattern, the nitride layer, the polysilicon layer and the hard mask layer are etched in sequence.
[0073] Please see Figure 3 and Figure 4I , among which, Figure 4I In the diagram, (a) is a schematic diagram of the array region AA, (b) is a schematic diagram of the alignment mark region MA, and (c) is a schematic diagram of the peripheral region PA. In step S36, the mask patterns 460 and 461 are transferred to the substrate 400 to form a target pattern 470 in the array region AA and an overlay alignment mark 471 in the alignment mark region MA.
[0074] In some embodiments, under the action of the masking layer 440, the critical dimension CD1 of the final formed target pattern 470 is smaller than the critical dimension CD2 of the overlay alignment mark 471.
[0075] In some embodiments, in this step, the substrate 400 is etched using the mask layer 410 as a shield, and the mask pattern 460 is transferred into the substrate 400 to form the target pattern 470 and the overlay alignment mark 471.
[0076] The formation method provided in this embodiment can form an integral standard overlay alignment mark 471 without sub-patterns in the alignment mark area MA while forming the array area AA using self-aligned dual imaging technology, which greatly improves the accuracy of overlay in semiconductor process.
[0077] The above are merely preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region and an alignment mark region, a mask layer, a pattern layer and a sidewall layer are disposed on the substrate, the pattern layer having a first pattern in the array region, the pattern layer having a second pattern in the alignment mark region, and the sidewall layer covering the sidewalls and top surface of the first pattern and the second pattern, and covering the exposed surface of the mask layer. A shielding layer is formed in the array area, where the shielding layer fills the gaps in the sidewall layer and exposes the top surface of the sidewall layer; in the alignment mark area, the shielding layer fills the gaps in the sidewall layer and covers the top surface of the sidewall layer. Using the shielding layer as a shield, a portion of the sidewall layer is removed to expose the top surface of the first pattern; Remove the shielding layer and part of the sidewall layer, and retain the sidewall layer of the first and second graphic sidewalls as sidewalls; The graphic layer is removed from the array region, and the sidewalls form a third graphic. In the array area, the third pattern is used as a mask, and in the alignment mark area, the second pattern and the sidewalls are used as masks to remove part of the mask layer to form a mask pattern. The mask pattern is transferred into the substrate to form the target pattern in the array region and to form overlay alignment marks in the alignment mark region; The step of forming the shielding layer includes: A shielding material layer is formed, which fills the gaps in the sidewall layer and covers the top surface of the sidewall layer. In the array area, the top surface of the shielding material layer has a first height to the top surface of the sidewall layer. In the alignment mark area, the top surface of the shielding material layer has a second height to the top surface of the sidewall layer, and the second height is greater than the first height. The shielding material layer is thinned to form the shielding layer; in the step of providing a substrate, the pattern density of the first pattern is greater than the pattern density of the second pattern; in the step of forming the shielding material layer, the initial amount of shielding material layer deposited in the array region and the alignment mark region is the same.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The substrate further includes a peripheral region, and the step of providing a substrate includes: A mask layer and a pattern material layer are formed on the substrate, and the pattern material layer is patterned to form the first pattern in the array region, the second pattern in the alignment mark region, and the pattern material layer located in the peripheral region is retained; Form the sidewall layer; In the step of forming the shielding material layer, in the peripheral area, the top surface of the shielding material layer to the top surface of the sidewall layer has a third height, which is greater than the second height; In the step of thinning the shielding material layer to form the shielding layer, the shielding layer also covers the top surface of the sidewall layer of the peripheral area.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The third height is 1.5 to 2.5 times the height of the first graphic.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, The height of the sidewall layer located on the top surface of the first graphic is less than the difference between the second height and the first height.
5. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of removing part of the sidewall layer while using the shielding layer as a shield, the shielding layer of the alignment mark area is thinned and the sidewall layer is not exposed.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The pattern layer includes a first sub-pattern layer and a second sub-pattern layer stacked together; in the step of removing the occlusion layer and part of the sidewall layer, the sidewall layer is etched using an etching process, and the etching rate of the etching material on the sidewall layer is greater than the etching rate on the second sub-pattern layer.
7. The method for forming a semiconductor structure according to claim 1, characterized in that, The width of the gap between adjacent second patterns is greater than the critical dimension of the overlay alignment mark.
8. The method for forming a semiconductor structure according to claim 1, characterized in that, In the steps of transferring the mask pattern into the substrate to form a target pattern in the array region and forming an overlay alignment mark in the alignment mark region, the critical dimension of the target pattern is smaller than the critical dimension of the overlay alignment mark.