Power conversion device
By introducing a phase-locked loop (PLL) circuit and a conduction time circuit into the power conversion device, and combining them with an SR flip-flop, the conduction time signal can be adjusted in real time. This solves the problem of inaccurate frequency tracking in the discontinuous conduction mode of the PLL circuit, and achieves stability and adaptability of frequency control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANPEC ELECTRONICS CORPORATION
- Filing Date
- 2022-03-25
- Publication Date
- 2026-06-30
AI Technical Summary
In the prior art, in the discontinuous conduction mode, the phase-locked loop circuit of a power conversion device with a fixed conduction time cannot effectively track the frequency change of the inductor voltage, resulting in inaccurate frequency control.
A power conversion device is employed, comprising a power conversion circuit, a feedback circuit, and a frequency control circuit. It receives a reference frequency signal and inductor voltage through a phase-locked loop circuit, and, in conjunction with a conduction time circuit and an SR flip-flop, adjusts the conduction time signal in real time to adapt to changes in input and output voltage, thereby ensuring the accuracy of frequency control.
It achieves accurate frequency tracking in discontinuous conduction mode and can adjust the conduction time in real time according to the input and output voltages to ensure the stability of frequency control and prevent it from being affected by load changes.
Smart Images
Figure CN116800086B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a power conversion device, and more particularly to a power conversion device having a fixed on-time. Background Technology
[0002] Power conversion devices with constant-on-time (COT) circuits typically add phase-locked loop (PLL) circuits to achieve accurate frequency synchronization. However, in discontinuous-conduction mode (DCM), the frequency variation of the inductor voltage in typical PLL circuit control methods prevents the PLL circuit from performing frequency tracking. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a power conversion device with a fixed on-time, addressing the shortcomings of the prior art. The device is characterized by comprising: a power conversion circuit; a feedback circuit connected to the power conversion circuit to output a comparison output signal; and a frequency control circuit connected to the power conversion circuit and the feedback circuit. The frequency control circuit includes: a phase-locked loop (PLL) circuit receiving a reference frequency signal and an inductor voltage in the power conversion circuit to provide a phase-locked signal; and an on-time circuit receiving the phase-locked signal, the inductor voltage, an input voltage, and an output voltage to provide an on-time comparison. A signal; an SR flip-flop, including a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the SR flip-flop of the frequency control circuit receives the conduction time comparison signal, and the second input terminal of the SR flip-flop of the frequency control circuit receives the comparison output signal, so as to output an conduction time signal via the output terminal of the SR flip-flop of the frequency control circuit; wherein, the frequency control circuit adjusts the conduction time of the conduction time comparison signal in real time according to the voltage change of the input voltage and the output voltage, so as to output the adjusted conduction time signal to the power conversion circuit.
[0004] Preferably, the feedback circuit includes a feedback signal circuit and a comparator. The comparator includes a first input terminal, a second input terminal, and an output terminal. One end of the feedback signal circuit is connected to the power conversion circuit, the other end of the feedback signal circuit is connected to the first terminal of the comparator, and the second terminal of the comparator is connected to a reference voltage.
[0005] Preferably, the power conversion circuit includes: a control circuit for receiving the conduction time signal provided by the frequency control circuit; a drive unit connected to the control circuit; an upper bridge switch unit including a first terminal, a second terminal, and a third terminal, wherein the first terminal of the upper bridge switch unit is connected to an input voltage, and the second terminal of the upper bridge switch unit is connected to the drive unit; a lower bridge switch unit including a first terminal, a second terminal, and a third terminal, wherein the first terminal of the lower bridge switch unit is connected to the third terminal of the upper bridge switch unit, the second terminal of the lower bridge switch unit is connected to the drive unit, and the third terminal of the lower bridge switch unit is connected to a ground voltage; and an inductor unit including a first terminal and a second terminal, wherein the first terminal of the inductor unit is connected to the third terminal of the upper bridge switch unit and the first terminal of the lower bridge switch unit. The second terminal of the inductor unit is an output terminal of the power conversion device, the voltage of the output terminal of the power conversion device is the voltage of the output terminal of the power conversion device, and the inductor voltage is the voltage of a node where the first terminal of the inductor unit, the third terminal of the upper bridge switch unit, and the first terminal of the lower bridge switch unit are interconnected; a load capacitor includes a first terminal and a second terminal, the first terminal of the load capacitor is connected to the second terminal of the inductor unit, and the second terminal of the load capacitor is connected to the ground voltage; and a zero current detection circuit includes a first terminal and a second terminal, the first terminal of the zero current detection circuit is connected to the control circuit, and the second terminal of the zero current detection circuit is connected to the third terminal of the upper bridge switch unit, the first terminal of the lower bridge switch unit, and the first terminal of the inductor unit.
[0006] Preferably, the frequency control circuit further includes a programmable frequency signal circuit connected to the phase-locked loop circuit. The programmable frequency signal circuit receives the inductor voltage, the input voltage, and the voltage at the output terminal to provide a programmable frequency signal.
[0007] Preferably, the phase-locked loop circuit receives the reference frequency signal, the inductor voltage, and the programmable frequency signal to provide the phase-locked signal to the on-time circuit, and the frequency control circuit provides the on-time signal to the power conversion circuit according to the reference frequency signal, the inductor voltage, and the programmable frequency signal.
[0008] Preferably, the programmable frequency signal circuit includes a phase detection circuit, a charge pump, an arithmetic unit circuit, a voltage-controlled oscillator (VCO), and a mode selection circuit; wherein the phase detection circuit is connected to the charge pump, the charge pump is connected to the arithmetic unit circuit, the arithmetic unit circuit is connected to the VCO, the VCO is connected to the mode selection circuit, and the mode selection circuit provides the programmable frequency signal to the phase detection circuit; wherein the phase detection circuit and the charge pump circuit generate a frequency detection voltage, and the frequency detection voltage is transmitted to the arithmetic unit circuit; and wherein the arithmetic unit circuit integrates the input voltage, the output voltage, and the frequency detection voltage into the VCO to generate a frequency signal.
[0009] Preferably, the programmable frequency signal circuit includes a first arithmetic unit, a first comparator, a second comparator, a third comparator, a first impedance, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first switching unit, a second switching unit, a first capacitor, a second capacitor, and an SR flip-flop; wherein, the first arithmetic unit includes a first input terminal, a second input terminal, and an output terminal; the first comparator includes a first input terminal, a second input terminal, and an output terminal; and the second comparator includes a first input terminal, a second input terminal, and an output terminal. The third comparator includes a first input terminal, a second input terminal, and an output terminal; the first impedance includes a first terminal and a second terminal; the first switching unit includes a first terminal, a second terminal, and a third terminal; the second switching unit includes a first terminal, a second terminal, and a third terminal; the third switching unit includes a first terminal, a second terminal, and a third terminal; the fourth switching unit includes a first terminal, a second terminal, and a third terminal; the first switching unit includes a first terminal and a second terminal; the second switching unit includes a first terminal and a second terminal; and the first capacitor includes a first terminal and a second terminal. The second capacitor includes a first terminal and a second terminal. The SR flip-flop of the programmable frequency signal circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first arithmetic unit receives a voltage difference signal. The second input terminal and the output terminal of the first arithmetic unit are connected to the first terminal of the first impedance. The second terminal of the first impedance is connected to the ground voltage. The first terminal of the first switching unit is connected to the first terminal of the second switching unit and the first terminal of the third switching unit. The second terminal of the first switching unit is connected to the second terminal of the second switching unit, the third terminal of the first switching unit, and the second terminal of the third switching unit. The third terminal of the first switching unit is connected to the output terminal, the second input terminal, and the first terminal of the first impedance of the first arithmetic unit. The third terminal of the second switching unit is connected to the first terminal of the second switching unit. The second terminal of the second switching unit is connected to the first terminal of the first capacitor. The first terminal of the first capacitor is connected to a current signal through the first switching unit. The second terminal of the first capacitor is connected to the ground voltage.
[0010] Preferably, the third terminal of the third switching unit is connected to the first terminal of the second capacitor, the first input terminal of the first comparator, and the first terminal of the fourth switching unit. The first terminal of the second capacitor is connected to the ground voltage. The second terminal of the fourth switching unit receives an upper bridge switching unit signal. The third terminal of the fourth switching unit is connected to the ground voltage. The second input terminal of the first comparator receives the frequency detection voltage. The first terminal of the first capacitor is connected to the first input terminal of the second comparator and the second input terminal of the third comparator. The second input terminal of the second comparator receives the frequency detection voltage. The first input terminal of the third comparator receives a fixed voltage.
[0011] Preferably, the output terminal of the second comparator is connected to the first input terminal of the SR flip-flop of the programmable frequency signal circuit, the output terminal of the third comparator is connected to the second input terminal of the SR flip-flop of the programmable frequency signal circuit, and the output terminal of the SR flip-flop of the programmable frequency signal circuit outputs the programmable frequency signal.
[0012] Preferably, the first switching unit, the second switching unit, and the third switching unit are P-type metal-oxide-semiconductor field-effect transistors, and the fourth switching unit is an N-type metal-oxide-semiconductor field-effect transistor.
[0013] One of the advantages of this invention is that the power conversion device provided by this invention can perform frequency tracking of discontinuous conduction mode through a simple circuit, and can also change the conduction time of discontinuous conduction mode in real time according to changes in input voltage and output voltage. Furthermore, the frequency control circuit of this invention will not change frequency due to load variations.
[0014] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of a power conversion device according to the first embodiment of the present invention.
[0016] Figure 2 This is a schematic diagram of a power conversion device according to a second embodiment of the present invention.
[0017] Figure 3 This is a block diagram of a programmable frequency signal circuit according to the second embodiment of the present invention.
[0018] Figure 4This is a circuit diagram of a programmable frequency signal circuit according to the second embodiment of the present invention.
[0019] Figure 5 This is a circuit concept diagram of a programmable frequency signal circuit according to the second embodiment of the present invention.
[0020] Figure 6 This is a schematic diagram of the generation of the conduction time signal TON in the power conversion device of the second embodiment of the present invention.
[0021] Figure 7 This is a schematic diagram of frequency detection voltage change and frequency change according to an embodiment of the present invention. Detailed Implementation
[0022] The following specific embodiments illustrate the implementation of the "power conversion device" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" as used herein may include, depending on the actual situation, any combination of any one or more of the associated listed items.
[0023] In this invention, if an electronic component in the diagram has three or more pins, the pin number is used to indicate the pin. If an electronic component has two pins, the left or upper end is designated as the input or first end, and the right or lower end is designated as the output or second end.
[0024] [First Embodiment]
[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of a power conversion device according to the first embodiment of the present invention.
[0026] In this embodiment, a power conversion device SYS with a fixed conduction time is provided.
[0027] The power conversion device SYS includes a power conversion circuit 1, a frequency control circuit 2, and a feedback circuit 3. The frequency control circuit 2 is connected to the power conversion circuit 1. The feedback circuit 3 is connected to both the power conversion circuit 1 and the frequency control circuit 2.
[0028] The frequency control circuit 2 receives at least a reference frequency signal REF_CLK and an inductor voltage LX from the power conversion circuit 1 to provide an on-time signal TON. The frequency control circuit 2 also receives a comparison output signal CPOUT provided by the feedback circuit, and provides the on-time signal TON based on the comparison signal, the reference frequency signal REF_CLK, and the inductor voltage LX from the power conversion circuit 1.
[0029] In this embodiment, the on-time signal TON is an on-time signal that provides a fixed on-time. That is, the power conversion device SYS in this embodiment can maintain a fixed on-time during the switching process between discontinuous-conduction mode (DCM) and continuous-conduction mode.
[0030] In this embodiment, the frequency control circuit 2 includes an SR flip-flop 21, an on-time circuit 22, and a phase-locked loop (PLL) circuit 23. The PLL circuit 23 is connected to the on-time circuit 22. The SR flip-flop 21 includes a first input terminal, a second input terminal, and an output terminal. The on-time circuit 22 is connected to the first input terminal R of the SR flip-flop 21. The output terminal Q of the SR flip-flop is connected to the power conversion circuit 1. The second input terminal S of the SR flip-flop 21 is connected to the feedback circuit 3. The feedback circuit 3 includes a feedback signal circuit 31 and a comparator 32. The comparator 32 includes a first input terminal -, a second input terminal +, and an output terminal. One end of the feedback signal circuit 31 is connected to the power conversion circuit 1. The other end of the feedback signal circuit 31 is connected to the first input terminal - of the comparator 32. The second input terminal + of the comparator is connected to a reference voltage REF. The feedback signal circuit 31 provides a feedback signal FB to the first input terminal - of the comparator 32.
[0031] The power conversion circuit 1 includes a control circuit 11, a drive unit 12, an upper bridge switch unit 13, a lower bridge switch unit 14, an inductor unit 15, a zero current detection circuit 16, and a load capacitor Cload.
[0032] Control circuit 11 is connected to the SR flip-flop 21 of frequency control circuit 2 to receive the conduction time signal TON provided by frequency control circuit 2. Drive unit 12 is connected to control circuit 11. Upper bridge switch unit 13 includes a first terminal, a second terminal, and a third terminal. The first terminal of upper bridge switch unit 13 is connected to an input voltage VIN. The second terminal of upper bridge switch unit 13 is connected to drive unit 12. Lower bridge switch unit 14 includes a first terminal, a second terminal, and a third terminal. The first terminal of lower bridge switch unit 14 is connected to the third terminal of upper bridge switch unit 13. The second terminal of lower bridge switch unit 14 is connected to drive unit 12. The third terminal of lower bridge switch unit 14 is connected to a ground voltage. Drive unit 12 provides an upper bridge voltage signal UG to the second terminal of upper bridge switch unit 13. Drive unit 12 provides a lower bridge voltage signal LG to the second terminal of lower bridge switch unit 14.
[0033] Inductor unit 15 includes a first terminal and a second terminal. The first terminal of inductor unit 15 is connected to the third terminal of upper bridge switch unit 13 and the first terminal of lower bridge switch unit 14. The inductor voltage LX is the voltage at a node where the first terminal of inductor unit 15, the third terminal of upper bridge switch unit 13, and the first terminal of lower bridge switch unit 14 are interconnected. The inductor current IL is the current flowing through inductor unit 15.
[0034] The load capacitor Cload includes a first terminal and a second terminal. The first terminal of the load capacitor Cload is connected to the second terminal of the inductor unit 15. The second terminal of the load capacitor Cload is connected to ground voltage.
[0035] The zero-current detection circuit 16 includes a first terminal and a second terminal. The first terminal of the zero-current detection circuit 16 is connected to the control circuit 11. The second terminal of the zero-current detection circuit 16 is connected to the third terminal of the upper bridge switching unit 13, the first terminal of the lower bridge switching unit 14, and the first terminal of the inductor unit 15. The zero-current detection circuit 16 provides a zero-current switching signal ZC to the control circuit 11.
[0036] The on-time circuit 22 receives a voltage signal UG, an inductor voltage LX, an input voltage VIN, and an output voltage VOUT of the power conversion device SYS from the second terminal of the upper bridge switching unit 13.
[0037] [Second Embodiment]
[0038] Please see Figure 2 , Figure 2 This is a schematic diagram of a power conversion device according to a second embodiment of the present invention.
[0039] In this embodiment, the power conversion device SYS' is similar to the power conversion device SYS in the first embodiment, the main difference being that the frequency control circuit 2 also includes a programmable frequency signal circuit 24.
[0040] The programmable frequency signal circuit 24 is connected to the phase-locked loop circuit 23. The programmable frequency signal circuit 24 receives the inductor voltage LX, the input voltage VIN, and the output voltage VOUT to provide a programmable frequency signal CLKP.
[0041] The programmable frequency signal circuit 24 operates by receiving the inductor voltage LX, the input voltage VIN, and the voltage at the output terminal VOUT, in order to output a programmable frequency signal CLKP.
[0042] Phase-locked loop circuit 23 receives reference frequency signal REF_CLK, inductor voltage LX, and programmable frequency signal CLKP to provide a phase-locked signal to conduction time circuit 22. Conduction time circuit 22 then provides a conduction time comparison signal COMP to SR flip-flop 21 based on the phase-locked signal, the upper bridge voltage signal UG at the second terminal of upper bridge switching unit 13, inductor voltage LX, input voltage VIN, and output voltage VOUT. SR flip-flop 21 then provides a conduction time signal TON to control circuit 11 based on the conduction time comparison signal COMP and the comparison output signal CPOUT of comparator 32 in feedback circuit 3.
[0043] In this embodiment, in continuous conduction mode, the conduction time of the conduction time signal TON can be determined by the inductor voltage LX and the programmable frequency signal CLKP.
[0044] In discontinuous conduction mode, the conduction time of the conduction time signal TON can be determined by the programmable frequency signal CLKP.
[0045] In another embodiment, the conduction time of the conduction time signal TON can be determined using the programmable frequency signal CLKP in both continuous conduction mode and discontinuous conduction mode.
[0046] In this embodiment, the on-time circuit 22 of the frequency control circuit 2 can detect the input voltage VIN and the output voltage VOUT so that it can still respond to the external frequency in real time in the discontinuous conduction mode, so as to provide an appropriate on-time signal TON.
[0047] Please see Figure 3 , Figure 3 This is a block diagram of a programmable frequency signal circuit according to the second embodiment of the present invention.
[0048] The programmable frequency signal circuit 24 includes a phase detection circuit 24A, a charge pump 24B, an arithmetic unit circuit 24C, a voltage-controlled oscillator 24D, and a mode selection circuit 24E.
[0049] Phase detection circuit 24A is connected to charge pump 24B. Charge pump 24B is connected to arithmetic unit circuit 24C. Arithmetic unit circuit 24C is connected to voltage-controlled oscillator 24D. Voltage-controlled oscillator 24D is connected to mode selection circuit 24E. Mode selection circuit 24E provides a programmable frequency signal CLKP to phase detection circuit 24A.
[0050] A frequency detection voltage VPHO can be generated using a phase detection circuit 24A and a charge pump 24B, based on a reference frequency signal REF_CLK and a programmable frequency signal CLKP. When there is a phase delay, the frequency detection voltage VPHO decreases; when there is a phase lead, the frequency detection voltage VPHO increases.
[0051] The frequency detection voltage VPHO is transmitted to the arithmetic unit circuit 24C. Additionally, the input voltage VIN and output voltage VOUT are also transmitted to the arithmetic unit circuit 24C for processing. Therefore, the frequency detection voltage VPHO, the input voltage VIN, and the output voltage VOUT are used by the voltage-controlled oscillator 24D to generate a virtual frequency signal. This virtual frequency signal can be provided to the mode selection circuit 24E according to whether the power conversion device SYS is in continuous or discontinuous conduction mode. The mode selection circuit 24E provides a corresponding programmable frequency signal CLKP based on whether the power conversion device SYS is in continuous or discontinuous conduction mode.
[0052] The duty cycle of the virtual frequency signal provided by the voltage-controlled oscillator 24D changes with the input voltage VIN, the output voltage VOUT, and the frequency of the virtual frequency signal.
[0053] Please see Figure 4 , Figure 4 This is a circuit diagram of a programmable frequency signal circuit according to the second embodiment of the present invention.
[0054] The programmable frequency signal circuit 24 includes a first operational unit OP1, a first comparator COM1, a second comparator COM2, a third comparator COM3, a first impedance R1, a first switching unit M1, a second switching unit M2, a third switching unit M3, a fourth switching unit M4, a first switching unit SW1, a second switching unit SW2, a first capacitor C1, a second capacitor C2, and an SR flip-flop FF.
[0055] The first operational unit OP1 includes a first input terminal, a second input terminal, and an output terminal. The first comparator COM1 includes a first input terminal, a second input terminal, and an output terminal. The second comparator COM2 includes a first input terminal, a second input terminal, and an output terminal. The third comparator COM3 includes a first input terminal, a second input terminal, and an output terminal. The first impedance R1 includes a first terminal and a second terminal. The first switching unit M1 includes a first terminal, a second terminal, and a third terminal. The second switching unit M2 includes a first terminal, a second terminal, and a third terminal. The third switching unit M3 includes a first terminal, a second terminal, and a third terminal. The fourth switching unit M4 includes a first terminal, a second terminal, and a third terminal. The first switching unit SW1 includes a first terminal and a second terminal. The second switching unit SW2 includes a first terminal and a second terminal. The first capacitor C1 includes a first terminal and a second terminal. The second capacitor C2 includes a first terminal and a second terminal. The SR flip-flop FF includes a first input terminal S, a second input terminal R, and an output terminal Q.
[0056] The first input terminal of the first arithmetic unit OP1 receives a voltage difference signal Vdiff. The second input terminal and the output terminal of the first arithmetic unit OP1 are connected to the first terminal of the first impedance R1. The second terminal of the first impedance R1 is connected to a ground voltage.
[0057] The first end of the first switching unit M1 is connected to the first end of the second switching unit M2 and the first end of the third switching unit M3.
[0058] The second terminal of the first switching unit M1 is connected to the second terminal of the second switching unit M2, the third terminal of the first switching unit M1, and the second terminal of the third switching unit M3. The third terminal of the first switching unit M1 is connected to the output terminal of the first arithmetic unit OP1, the second input terminal of the first arithmetic unit OP1, and the first terminal of the first impedance R1.
[0059] The third terminal of the second switching unit M2 is connected to the first terminal of the second switching unit SW2. The second terminal of the second switching unit SW2 is connected to the first terminal of the first capacitor C1. The first terminal of the first capacitor C1 is also connected to a current signal i1 through the first switching unit SW1, and the current value of the current signal i1 is (VOUT / R). The second terminal of the first capacitor C1 is connected to the ground voltage.
[0060] The third terminal of the third switching unit M3 is connected to the first terminal of the second capacitor C2, the first input terminal + of the first comparator COM1, and the first terminal of the fourth switching unit M4. The first terminal of the second capacitor is connected to ground. The second terminal of the fourth switching unit M4 receives an upper bridge switching unit signal UGON. The third terminal of the fourth switching unit M4 is connected to ground.
[0061] The second input of the first comparator COM1 is the received frequency detection voltage VPHO. The first comparator COM1 also includes an output terminal COMP.
[0062] The first terminal of the first capacitor C1 is connected to the first input terminal (+) of the second comparator COM2 and the second input terminal (-) of the third comparator COM3. The second input terminal of the second comparator COM2 receives the frequency detection voltage VPHO. The first input terminal (+) of the third comparator COM3 receives a fixed voltage VL.
[0063] The output of the second comparator COM2 is connected to the first input S of the SR flip-flop FF. The output of the third comparator COM3 is connected to the second input R of the SR flip-flop FF. The output Q of the SR flip-flop FF then outputs the programmable frequency signal CLKP.
[0064] In this embodiment, the first capacitor C1 and the second capacitor C2 both have the same capacitance value C. The first impedance R1 has an impedance value R.
[0065] The first operational unit OP1 receives the voltage difference signal Vdiff, which is the voltage difference between the input voltage and the output voltage VOUT. Combined with the first impedance R1, this signal, along with the first switching unit M1 and the second switching unit M2, provides a current at the third terminal of the second switching unit M2. The current value is (VIN - VOUT) / R. This current, through the charging and discharging process of the first capacitor C1, provides a ramp signal to the second comparator COM2 and the third comparator COM3.
[0066] The third switching unit M3 works in conjunction with the first switching unit M1 and the second switching unit M2. Through the design of a current mirror circuit, it can obtain the same current as that flowing through the third terminal of the second switching unit M2, and the current value is (VIN-VOUT) / R. In addition, the third switching unit M3 also provides a conduction time setting signal TONSET to the first input terminal + of the first comparator COM1.
[0067] The first switching unit M1, the second switching unit M2, and the third switching unit M3 are P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), and the fourth switching unit M4 is an N-type metal-oxide-semiconductor field-effect transistor (MOSFET).
[0068] according to Figure 4 From the circuit diagram, the following parameters can be calculated.
[0069] Power conversion device operating frequency FSW = (VOUT / VIN) / TON
[0070] Minimum conduction time Tonmin = VL*C / ((VIN-VOUT) / R)
[0071] Maximum on-time Tonmax = VPHO_max * C / ((VIN - VOUT) / R)
[0072] Please see Figure 6 , Figure 6 This is a schematic diagram of the generation of the conduction time signal TON in the power conversion device of the second embodiment of the present invention.
[0073] exist Figure 6 In this context, the conduction time signal TON can be calculated using the following formula based on the input voltage VIN, the voltage at the output terminal VOUT, the fixed voltage VL, and the frequency detection voltage VPHO.
[0074] TON=(((VIN-VOUT) / R) / C)*D=-(((-VOUT) / R) / C)*(1-D)
[0075] like Figure 5 As shown, the rising slope is ((VIN-VOUT) / R) / C, where C is a constant and the rising slope is proportional to (VIN-VOUT) / R. The falling slope is (VOUT / R) / C, where C is a constant and the falling slope is proportional to VOUT / R. This represents the slope of the ramp signal.
[0076] The working cycle D can be calculated using the following formula:
[0077] D = VOUT / VIN
[0078] Based on the calculations using the above parameters and formulas, this embodiment can adjust the frequency of the virtual frequency signal by using different frequency detection voltages VPHO (such as VPHO_1, VPHO_2, and VPHO_3 with different icons) in conjunction with the capacitance value of the first capacitor C1 or the impedance value of the first impedance R1. In this embodiment, the capacitance value of the first capacitor C1 and the impedance value of the first impedance R1 can be adjusted according to actual needs and are not limited in this invention. In other embodiments, the circuit design can be adjusted according to actual needs to adjust for different parameters, and this is not limited in this invention.
[0079] according to Figure 4 Circuit design can be based solely on the input voltage VIN and the output voltage VOUT, such as... Figure 5 As shown, Figure 5 This is a circuit concept diagram of a programmable frequency signal circuit according to the second embodiment of the present invention.
[0080] Figure 5In the circuit concept diagram, current sources IS1, IS2, and IS3 are set up using the input voltage VIN and the output voltage VOUT, along with corresponding circuits, to generate the frequency detection voltage VPHO. The impedance R, capacitor C, and related circuits of the current sources IS1, IS2, and IS3 can be adjusted according to actual needs.
[0081] exist Figure 6 In the above example, the frequency detection voltage VPHO_1, the fixed voltage VL, and the ramp signal together generate the waveform of the first frequency signal CLK1. The frequency detection voltage VPHO_2, the fixed voltage VL, and the ramp signal together generate the waveform of the second frequency signal CLK2. The frequency detection voltage VPHO_3, the fixed voltage VL, and the ramp signal together generate the waveform of the third frequency signal CLK3.
[0082] Please see Figure 7 , Figure 7 This is a schematic diagram of frequency detection voltage change and frequency change according to an embodiment of the present invention.
[0083] from Figure 7 It can be seen that under a fixed slope, the frequency detection voltage VPHO decreases, which can increase the frequency under a fixed working cycle.
[0084] The waveform CLK_REF is the reference frequency signal, which is a fixed frequency signal. By comparing it with the reference frequency signal CLK_REF, we can see that regions A and B are phase lagging regions, while region C is a phase leading region.
[0085] By adjusting the frequency detection voltage VPHO to decrease, and combining it with a ramp signal RAMP with the same rise and fall slope, a programmable frequency signal CLKP with a gradually increasing frequency can be generated.
[0086] [Beneficial Effects of the Examples]
[0087] One of the advantages of this invention is that the power conversion device provided by this invention can perform frequency tracking of discontinuous conduction mode through a simple circuit, and can also change the conduction time of discontinuous conduction mode in real time according to changes in input voltage and output voltage. Furthermore, the frequency control circuit of this invention will not change frequency due to load variations.
[0088] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.
Claims
1. A power conversion device with a fixed conduction time, characterized in that, include: A power conversion circuit; A feedback circuit is connected to the power conversion circuit to output a comparison output signal; as well as A frequency control circuit is connected to the power conversion circuit and the feedback circuit, the frequency control circuit comprising: A phase-locked loop circuit receives a reference frequency signal and an inductor voltage in the power conversion circuit to provide a phase-locked signal; An on-time circuit receives the phase-locked signal, the inductor voltage, an input voltage, and an output voltage to provide an on-time comparison signal; An SR flip-flop includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the SR flip-flop in the frequency control circuit receives the on-time comparison signal, and the second input terminal of the SR flip-flop in the frequency control circuit receives the comparison output signal, so as to output an on-time signal via the output terminal of the SR flip-flop in the frequency control circuit; and A programmable frequency signal circuit is connected to the phase-locked loop circuit. The programmable frequency signal circuit receives the inductor voltage, the input voltage, and the voltage at the output terminal to provide a programmable frequency signal. The frequency control circuit adjusts the conduction time of the conduction time comparison signal in real time according to the voltage changes of the input voltage and the output voltage, so as to output the adjusted conduction time signal to the power conversion circuit.
2. The power conversion device as described in claim 1, characterized in that, The feedback circuit includes a feedback signal circuit and a comparator. The comparator includes a first input terminal, a second input terminal, and an output terminal. One end of the feedback signal circuit is connected to the power conversion circuit, and the other end of the feedback signal circuit is connected to the first input terminal of the comparator. The second input terminal of the comparator is connected to a reference voltage.
3. The power conversion device as described in claim 2, characterized in that, The power conversion circuit includes: A control circuit receives the conduction time signal provided by the frequency control circuit; A drive unit is connected to the control circuit; An upper bridge switch unit includes a first terminal, a second terminal and a third terminal. The first terminal of the upper bridge switch unit is connected to an input voltage, and the second terminal of the upper bridge switch unit is connected to the drive unit. A lower bridge switch unit includes a first terminal, a second terminal and a third terminal. The first terminal of the lower bridge switch unit is connected to the third terminal of the upper bridge switch unit, the second terminal of the lower bridge switch unit is connected to the drive unit, and the third terminal of the lower bridge switch unit is connected to a ground voltage. An inductor unit includes a first terminal and a second terminal. The first terminal of the inductor unit is connected to the third terminal of the upper bridge switch unit and the first terminal of the lower bridge switch unit. The second terminal of the inductor unit is an output terminal of the power conversion device. The voltage at the output terminal of the power conversion device is the voltage at the output terminal of the power conversion device. The inductor voltage is the voltage at a node where the first terminal of the inductor unit, the third terminal of the upper bridge switch unit, and the first terminal of the lower bridge switch unit are interconnected. A load capacitor includes a first terminal and a second terminal, the first terminal of the load capacitor being connected to the second terminal of the inductor unit, and the second terminal of the load capacitor being connected to the ground voltage; and A zero-current detection circuit includes a first terminal and a second terminal. The first terminal of the zero-current detection circuit is connected to the control circuit, and the second terminal of the zero-current detection circuit is connected to the third terminal of the upper bridge switch unit, the first terminal of the lower bridge switch unit, and the first terminal of the inductor unit.
4. The power conversion device as described in claim 3, characterized in that, The phase-locked loop circuit receives the reference frequency signal, the inductor voltage, and the programmable frequency signal to provide the phase-locked signal to the on-time circuit, and the frequency control circuit provides the on-time signal to the power conversion circuit according to the reference frequency signal, the inductor voltage, and the programmable frequency signal.
5. The power conversion device as described in claim 4, characterized in that, The programmable frequency signal circuit includes a phase detection circuit, a charge pump, an arithmetic unit circuit, a voltage-controlled oscillator, and a mode selection circuit. The phase detection circuit is connected to the charging pump, the charging pump is connected to the arithmetic unit circuit, the arithmetic unit circuit is connected to the voltage-controlled oscillator, the voltage-controlled oscillator is connected to the mode selection circuit, and the mode selection circuit provides the programmable frequency signal to the phase detection circuit. The phase detection circuit and the charging pump generate a frequency detection voltage, which is transmitted to the arithmetic unit circuit; and The arithmetic unit circuit integrates the input voltage, the output voltage, and the frequency detection voltage into the voltage-controlled oscillator to generate a frequency signal.
6. The power conversion device as described in claim 4, characterized in that, The programmable frequency signal circuit includes a first arithmetic unit, a first comparator, a second comparator, a third comparator, a first impedance, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first switching unit, a second switching unit, a first capacitor, a second capacitor, and an SR flip-flop. Wherein, the first arithmetic unit includes a first input terminal, a second input terminal, and an output terminal; the first comparator includes a first input terminal, a second input terminal, and an output terminal; the second comparator includes a first input terminal, a second input terminal, and an output terminal; the third comparator includes a first input terminal, a second input terminal, and an output terminal; the first impedance includes a first terminal and a second terminal; the first switching unit includes a first terminal, a second terminal, and a third terminal; the second switching unit includes a first terminal, a second terminal, and a third terminal; the third switching unit includes a first terminal, a second terminal, and a third terminal; the fourth switching unit includes a first terminal, a second terminal, and a third terminal; the first switching unit includes a first terminal and a second terminal; the second switching unit includes a first terminal and a second terminal; the first capacitor includes a first terminal and a second terminal; the second capacitor includes a first terminal and a second terminal; and the SR flip-flop of the programmable frequency signal circuit includes a first input terminal, a second input terminal, and an output terminal. In this configuration, the first input terminal of the first arithmetic unit receives a voltage difference signal; the second input terminal and the output terminal of the first arithmetic unit are connected to the first terminal of the first impedance; the second terminal of the first impedance is connected to the ground voltage; the first terminal of the first switching unit is connected to the first terminal of the second switching unit and the first terminal of the third switching unit; the second terminal of the first switching unit is connected to the second terminal of the second switching unit, the third terminal of the first switching unit, and the second terminal of the third switching unit; the third terminal of the first switching unit is connected to the output terminal, the second input terminal, and the first terminal of the first impedance; the third terminal of the second switching unit is connected to the first terminal of the second switching unit; the second terminal of the second switching unit is connected to the first terminal of the first capacitor; the first terminal of the first capacitor is connected to a current signal through the first switching unit; and the second terminal of the first capacitor is connected to the ground voltage.
7. The power conversion device as described in claim 6, characterized in that, The third terminal of the third switching unit is connected to the first terminal of the second capacitor, the first input terminal of the first comparator, and the first terminal of the fourth switching unit. The first terminal of the second capacitor is connected to the ground voltage. The second terminal of the fourth switching unit receives an upper bridge switching unit signal. The third terminal of the fourth switching unit is connected to the ground voltage. The second input terminal of the first comparator receives a frequency detection voltage. The first terminal of the first capacitor is connected to the first input terminal of the second comparator and the second input terminal of the third comparator. The second input terminal of the second comparator receives the frequency detection voltage. The first input terminal of the third comparator receives a fixed voltage.
8. The power conversion device as described in claim 7, characterized in that, The output terminal of the second comparator is connected to the first input terminal of the SR flip-flop of the programmable frequency signal circuit, the output terminal of the third comparator is connected to the second input terminal of the SR flip-flop of the programmable frequency signal circuit, and the output terminal of the SR flip-flop of the programmable frequency signal circuit outputs the programmable frequency signal.
9. The power conversion device as described in claim 8, characterized in that, The first switching unit, the second switching unit, and the third switching unit are P-type metal-oxide-semiconductor field-effect transistors, and the fourth switching unit is an N-type metal-oxide-semiconductor field-effect transistor.