Memory and method of forming the same
By forming a groove under the capacitor and filling it with an isolation layer, the problem of leakage at the bottom of the capacitor in DRAM memory was solved, improving electrical performance and simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-03-10
- Publication Date
- 2026-07-24
AI Technical Summary
In existing DRAM memories, leakage is prone to occur at the bottom of the capacitor, which affects the electrical performance of the memory.
Before forming the capacitor, a groove is formed below the capacitor hole, and an isolation layer is filled in the groove. The isolation layer is formed directly below the capacitor to electrically isolate the bottom of the capacitor from the substrate and reduce leakage.
By setting up an isolation layer, leakage at the bottom of the capacitor is reduced or even avoided, improving the electrical performance of the memory, simplifying the manufacturing process, and reducing the difficulty of the process.
Smart Images
Figure CN116801607B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a memory and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] However, in existing DRAM and other memories, especially those with a TOC (Transistor On Capacitor) structure, leakage is prone to occur at the bottom of the capacitor, which reduces the performance of the memory.
[0004] Therefore, how to reduce leakage current at the bottom of the capacitor to improve the electrical performance of the memory is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] The present disclosure provides a memory and a method for forming the memory in some embodiments, which at least partially solve the problem of leakage at the bottom of the capacitor, thereby improving the electrical performance of the memory.
[0006] According to some embodiments, this disclosure provides a method for forming a memory, including the following steps:
[0007] Provide initial substrate;
[0008] The initial substrate is etched to form a plurality of capacitor holes and a plurality of grooves that are connected to each of the capacitor holes and located below the capacitor holes;
[0009] An isolation layer is formed to connect adjacent grooves and fill the grooves, with the initial substrate remaining below the isolation layer serving as the substrate;
[0010] A capacitor is formed within the capacitor hole.
[0011] In some embodiments, the specific steps of forming a plurality of capacitor holes and a plurality of grooves communicating with each of the plurality of capacitor holes and located below the capacitor holes include:
[0012] The initial substrate is etched to form a plurality of first etch trenches, each of the first etch trenches extending along a first direction, and the plurality of first etch trenches being parallel to each other and spaced apart in a second direction, both the first direction and the second direction being parallel to the top surface of the initial substrate, and the first direction and the second direction being orthogonal to each other.
[0013] The initial substrate is etched to form a plurality of second etch trenches, each of the second etch trenches extending along the second direction, and the plurality of second etch trenches are parallel to each other and spaced apart in the first direction. The portion of the initial substrate remaining at the bottom of the second etch trenches and the bottom of the first etch trenches serves as the substrate.
[0014] The initial substrate at the bottom of the second etching trench is etched to form a groove with a width greater than that of the second etching trench in a first direction;
[0015] The first etching groove and the second etching groove are connected to form the capacitor hole.
[0016] In some embodiments, before forming a plurality of second etching trenches, the following steps are further included:
[0017] A first filler layer is formed that completely fills the first etched groove.
[0018] In some embodiments, the specific steps for forming the groove with a width greater than that of the second etching groove include:
[0019] The initial substrate at the bottom of the second etching trench is etched using Bosch etching technology to form the groove.
[0020] In some embodiments, the specific steps for forming the capacitor hole by connecting the first etching trench and the second etching trench include:
[0021] A second filling layer is formed that fills the second etched groove and the recess;
[0022] A patterned mask layer is formed over the initial substrate, the mask layer including a plurality of openings exposing the overlapping area of the first etch trench and the second etch trench;
[0023] The first filler layer and the second filler layer are removed along the opening to form the capacitor hole.
[0024] In some embodiments, the specific steps of forming a patterned mask layer over the initial substrate, wherein the mask layer includes a plurality of openings exposing the overlapping region of the first etch trench and the second etch trench include:
[0025] A first sub-mask layer is formed over the initial substrate;
[0026] The first sub-mask layer is etched to form a plurality of first sub-openings that expose the first filling layer. Each first sub-opening extends along the first direction, and the plurality of first sub-openings are spaced apart along the second direction.
[0027] A third filling layer is formed to completely fill the first sub-opening;
[0028] The first sub-mask layer and the third fill layer are etched to form a plurality of second sub-openings that expose the initial substrate. Each second sub-opening extends in a direction parallel to the second direction, and the plurality of second sub-openings are spaced apart in the first direction.
[0029] The second sub-mask layer is filled into the second sub-opening to form the mask layer including the second sub-mask layer and the remaining first sub-mask layer, the mask layer including a plurality of openings exposing the third filling layer;
[0030] The third filler layer is removed along the opening, exposing the overlapping area of the first etched groove and the second etched groove.
[0031] In some embodiments, the initial substrate remaining between adjacent capacitor holes serves as a first isolation pillar, and the initial substrate remaining between adjacent grooves serves as a second isolation pillar.
[0032] In the first direction, the width of the second isolation post is 1 / 2 to 1 / 3 of the width of the first isolation post; in the second direction, the width of the second isolation post is equal to the width of the first isolation post.
[0033] In some embodiments, the specific steps of forming an isolation layer that connects adjacent grooves and fills the grooves include:
[0034] Along the first isolation pillar and all of the second isolation pillars of the opening oxidation portion, an isolation sidewall is formed on the sidewall of the capacitor hole, and a first sub-isolation layer is formed between adjacent grooves;
[0035] A second sub-isolation layer is deposited along the opening into the groove to form the isolation layer comprising the first sub-isolation layer and the second sub-isolation layer.
[0036] In some embodiments, the specific steps of depositing a second sub-isolation layer along the opening within the groove include:
[0037] A second sub-isolation layer is deposited along the opening into the groove and at the bottom of the capacitor hole, such that the top surface of the second sub-isolation layer is above the bottom surface of the first isolation pillar.
[0038] In some embodiments, the initial substrate is made of silicon, and both the first sub-isolation layer and the second sub-isolation layer are made of silicon dioxide.
[0039] In some embodiments, the specific steps of forming a capacitor within the capacitor hole include:
[0040] Remove the isolation sidewall;
[0041] A first electrode is formed covering the sidewall of the capacitor hole;
[0042] A dielectric layer is formed covering the surface of the first electrode, the top surface of the isolation layer, and the bottom surface of the mask layer;
[0043] A second electrode is formed to cover the dielectric layer, thereby forming the capacitor comprising the first electrode, the dielectric layer, and the second electrode.
[0044] In some embodiments, after forming the second electrode covering the dielectric layer, the following steps are further included:
[0045] Remove the mask layer and re-etch the first electrode, the dielectric layer, and the second electrode in the etched portion to expose the upper part of the first isolation pillar;
[0046] A covering layer is formed to enclose the exposed first isolation column.
[0047] In some embodiments, after forming a covering layer over the exposed first isolation pillar, the method further includes the following steps:
[0048] The first isolation pillar in the capping layer is doped to form the active region of the transistor.
[0049] According to other embodiments, this disclosure also provides a memory, including:
[0050] Substrate;
[0051] An isolation layer is located above the substrate;
[0052] A capacitor array, located above the isolation layer, includes multiple capacitors, each of which includes a first electrode extending in a direction perpendicular to the top surface of the substrate, a dielectric layer covering the surface of the first electrode, and a second electrode covering the surface of the dielectric layer.
[0053] In some embodiments, it also includes:
[0054] The first isolation post is located between two adjacent capacitors;
[0055] The isolation layer includes a first sub-isolation layer located between the first isolation pillar and the substrate, and a second sub-isolation layer located below the capacitor.
[0056] In some embodiments, the material of the first sub-isolation layer is the same as the material of the second sub-isolation layer.
[0057] In some embodiments, the substrate and the first isolation pillar are both made of silicon, and the first sub-isolation layer and the second sub-isolation layer are both made of silicon dioxide.
[0058] In some embodiments, the first electrode covers the sidewall of the first isolation pillar, and the dielectric layer covers the surface of the first electrode and the surface of the second sub-isolation layer.
[0059] In some embodiments, the bottom surface of the first isolation post is located below the bottom surface of the first electrode.
[0060] In some embodiments, it also includes:
[0061] The trench area is located above the first isolation pillar;
[0062] A gate is disposed around the channel region.
[0063] The memory and its formation method provided in some embodiments of this disclosure first form a groove below the capacitor hole for forming the capacitor before forming the capacitor. After forming an isolation layer that connects and fills the groove, the capacitor is then formed in the capacitor hole above the isolation layer. This electrically isolates the bottom of the capacitor from the substrate through the isolation layer, reducing or even avoiding the problem of leakage at the bottom of the capacitor, thereby improving the electrical performance of the memory. Furthermore, compared to forming the isolation layer directly on the substrate through deposition or oxidation processes, the memory formation method provided in this disclosure integrates the capacitor hole formation process with the isolation layer formation process. This allows the isolation layer to be formed simultaneously with the capacitor hole formation. The isolation layer is formed directly below the capacitor, ensuring that the isolation layer is fully aligned with the bottom of the capacitor. This simplifies the memory manufacturing process, reduces the manufacturing difficulty of the memory, and further improves the electrical isolation effect between the capacitor and the substrate. Attached Figure Description
[0064] Appendix Figure 1 This is a flowchart of a method for forming a memory according to a specific embodiment of this disclosure;
[0065] Appendix Figure 2A-2Q This is a schematic diagram of the main process structure in the formation of the memory according to a specific embodiment of the present disclosure;
[0066] Appendix Figure 3 This is a schematic diagram of the memory structure in a specific embodiment of this disclosure. Detailed Implementation
[0067] The specific embodiments of the memory and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0068] This specific embodiment provides a method for forming a memory, with appended... Figure 1 This is a flowchart illustrating the method for forming a memory according to a specific embodiment of this disclosure, with appended... Figure 2A - Appendix Figure 2Q This is a schematic diagram of the main process structure during the formation of the memory in a specific embodiment of this disclosure. The memory described in this embodiment may be, but is not limited to, DRAM memory. Figure 1 , Figures 2A-2Q As shown, the method for forming a memory provided in this specific embodiment includes the following steps:
[0069] Step S11, provide an initial substrate 20.
[0070] Specifically, the initial substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the initial substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
[0071] Step S12: Etch the initial substrate 20 to form a plurality of capacitor holes 35 and a plurality of grooves 24 that are connected to each of the capacitor holes 35 and located below the capacitor holes 35. The portion of the initial substrate remaining below the grooves 24 serves as the substrate 25.
[0072] In some embodiments, the specific steps of forming a plurality of capacitor holes 35 and a plurality of grooves 24 that communicate with each of the plurality of capacitor holes 35 and are located below the capacitor holes 35 include:
[0073] The initial substrate 20 is etched to form a plurality of first etch trenches 21. Each first etch trench 21 extends along a first direction D1. The plurality of first etch trenches 21 are parallel to each other and spaced apart along a second direction D2. Both the first direction D1 and the second direction D2 are parallel to the top surface of the initial substrate 20, and the first direction D1 and the second direction D2 are orthogonal. Figure 2A As shown;
[0074] The initial substrate 20 is etched to form a plurality of second etch trenches 23, each of the second etch trenches 23 extending along the second direction D2, and the plurality of second etch trenches 23 being parallel to each other and spaced apart in the first direction D1;
[0075] The initial substrate 20 at the bottom of the second etching trench 23 is etched to form the groove 24 with an inner diameter larger than that of the second etching trench 23, such as... Figure 2C As shown;
[0076] The capacitor hole 35 is formed by connecting the first etching groove 21 and the second etching groove 23. Figure 2J As shown.
[0077] Specifically, a dry etching process can be used along a direction perpendicular to the top surface of the initial substrate 20 (e.g., Figure 2A The initial substrate 20 is etched in a third direction (D3) to form a plurality of first etched trenches 21. Each first etched trench 21 extends along a first direction D1, and the plurality of first etched trenches 21 are arranged parallel to each other and spaced apart along a second direction D2. During the etching of the initial substrate 20 to form the first etched trenches 21, etching parameters, such as the dosage of etching gas and / or etching time, can be controlled so that the first etched trenches 21 do not penetrate the initial substrate 20 in a direction perpendicular to the top surface of the initial substrate 20.
[0078] In some embodiments, before forming the plurality of second etching grooves 23, the following steps are further included:
[0079] A first filler layer 22 is formed to fill the first etched groove 21, such as Figure 2B As shown.
[0080] In some embodiments, the specific steps for forming the groove 24 with an inner diameter larger than that of the second etching groove 23 include:
[0081] The initial substrate 20 at the bottom of the second etching trench 23 is etched using a Bosch etching process to form the groove 24, as follows: Figure 2C As shown.
[0082] Specifically, to prevent collapse or tipping during the etching of the initial substrate 20 to form the second etching trench 23, before forming the second etching trench 23, insulating materials such as silicon dioxide can be deposited in the first etching trench 21 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form the first filling layer 22 that fills the first etching trench 21. Figure 2B As shown. Then, a dry etching process can be used along a direction perpendicular to the top surface of the initial substrate 20 (e.g., Figure 2AThe initial substrate 20 is etched in the third direction (D3) to form a plurality of second etched trenches 23. Each second etched trench 23 extends along the second direction (D2), and the plurality of second etched trenches 23 are arranged parallel to each other and spaced apart along the first direction (D1). That is, the projection of the second etched trench 23 along the direction perpendicular to the top surface of the initial substrate 20 is orthogonal to the projection of the first etched trench 21 along the direction perpendicular to the top surface of the initial substrate 20. Then, the initial substrate 20 at the bottom of the second etched trench 23 is etched along the first etched trench 21 using Bosch etching technology, thereby forming a groove 24 that communicates with the bottom of the second etched trench 23 and has an inner diameter larger than the second etched trench 23. Since the inner diameter of the groove 24 is larger than the inner diameter of the second etched trench 23, the width of the initial substrate 20 remaining between adjacent second etched trenches 23 (i.e., the first isolation pillar 31) along the first direction (D1) is greater than the width of the initial substrate 20 remaining between adjacent grooves 24 (i.e., the second isolation pillar 32).
[0083] This specific embodiment uses a Bosch etching process to form the groove 24 after forming the second etching groove 23, thereby simplifying the formation process of the memory. In other embodiments, those skilled in the art can also select other etching processes as needed to form the second etching groove 23 and the groove 24 communicating with the second etching groove 23.
[0084] In some embodiments, the specific steps for forming the capacitor hole 35 by connecting the first etching trench 21 and the second etching trench 23 include:
[0085] A second filling layer 26 is formed to fill the second etched groove 23 and the recess 24, as shown in Figure 2D As shown;
[0086] A patterned mask layer is formed over the initial substrate 20, the mask layer including a plurality of openings 45 exposing the overlapping area of the first etch trench 21 and the second etch trench 23, such as... Figure 2I As shown;
[0087] The first filler layer 22 and the second filler layer 26 are removed along the opening 45 to form the capacitor hole 35, as shown below. Figure 2J As shown.
[0088] Specifically, by selecting appropriate materials for the first filler layer 22 and the second filler layer 26, the first filler layer 22 and the second filler layer 26 can be selectively etched away, thereby connecting the first etch trench 21 and the second etch trench 23 inside the initial substrate 20.
[0089] In some embodiments, the specific steps of forming a patterned mask layer over the initial substrate 20, wherein the mask layer includes a plurality of openings 45 exposing the overlapping region of the first etch trench 21 and the second etch trench 23, include:
[0090] A first sub-mask layer 27 is formed over the initial substrate 20, as follows: Figure 2E As shown;
[0091] The first sub-mask layer 27 is etched to form a plurality of first sub-openings 28 exposing the first filling layer 22. Each first sub-opening 28 extends along the first direction D1, and the plurality of first sub-openings 28 are arranged in parallel along the second direction D2. Figure 2F As shown;
[0092] A third filling layer 39 is formed to completely fill the first sub-opening 28, such as... Figure 2G As shown;
[0093] The first sub-mask layer 27 and the third fill layer 39 are etched to form a plurality of second sub-openings 30 exposing the initial substrate 20. Each second sub-opening 30 extends along a direction parallel to the second direction D2, and the plurality of second sub-openings 30 are arranged in parallel along the first direction D1. Figure 2H As shown;
[0094] The second sub-mask layer 33 is filled into the second sub-opening 30 to form the mask layer comprising the second sub-mask layer 33 and the remaining first sub-mask layer 27, the mask layer including a plurality of openings 45 exposing the third filling layer 39, such as... Figure 2I As shown;
[0095] The third filler layer 39 is removed along the opening 45, exposing the overlapping area of the first etched groove 21 and the second etched groove 23.
[0096] Specifically, after forming the second filling layer 26 that fills the second etched trench 23 and the recess 24, a hard mask material such as silicon nitride or an organic mask material such as carbon is deposited on the top surface of the initial substrate 20 to form the first sub-mask layer 27, such as... Figure 2EAs shown. The first sub-mask layer 27 serves as a mask for subsequent removal of the first filler layer 22 and the second filler layer 26; it also supports the first isolation pillars 31 between adjacent second etched grooves 23, preventing tilting or collapse during the removal of the first filler layer 22 and the second filler layer 26. Next, the first sub-mask layer 27 can be etched using the same mask used to form the first etched groove 21, forming multiple first sub-openings 28 exposing the first filler layer 22. Each first sub-opening 28 extends along the first direction D1, and the multiple first sub-openings 28 are arranged parallel to each other along the second direction D2, as shown. Figure 2F As shown. Then, the first sub-opening 28 is filled to form the third filling layer 39, as... Figure 2G As shown. Then, the first sub-mask layer 27 and the third fill layer 39 are etched to form a plurality of second sub-openings 30 exposing the initial substrate 20. Each second sub-opening 30 extends along a direction parallel to the second direction D2, and the plurality of second sub-openings 30 are arranged parallel to each other and spaced apart along the first direction D1, as shown. Figure 2H As shown. A second sub-mask layer 33 filled with a nitride material (e.g., silicon nitride) forms the mask layer including the second sub-mask layer 33 and the remaining first sub-mask layer 27 at the second sub-opening 30. The remaining first sub-mask layer 27 intersects the second sub-mask layer 33 in a direction parallel to the top surface of the initial substrate 20, thereby forming a plurality of openings 45 exposing the third filling layer 39, as shown. Figure 2I As shown. An etching process is used to remove the third filler layer 39, the first filler layer 22, and the second filler layer 26 along the opening 45, thereby connecting the first etched trench 21 and the second etched trench 23 inside the initial substrate 20, forming the capacitor hole 35, as shown. Figure 2J As shown.
[0097] In one embodiment, the materials of the first filling layer 22, the second filling layer 26, and the third filling layer 39 are all the same. For example, the materials of the first filling layer 22, the second filling layer 26, and the third filling layer 39 are all silicon dioxide, so that the first filling layer 22, the second filling layer 26, and the third filling layer 39 can be removed simultaneously by a one-step etching process, thereby further simplifying the manufacturing process of the memory.
[0098] Step S13: An isolation layer is formed that connects adjacent grooves 24 and fills the grooves 24. The initial substrate 20 remaining below the isolation layer serves as substrate 25. Figure 2M As shown.
[0099] In some embodiments, the initial substrate 20 remaining between adjacent capacitor holes 35 serves as a first isolation pillar 31, and the initial substrate 20 remaining between adjacent grooves 24 serves as a second isolation pillar 32, such as... Figure 2J As shown;
[0100] In the first direction D1, the width of the second isolation post 32 is 1 / 2 to 1 / 3 of the width of the first isolation post 31, and in the second direction D2, the width of the second isolation post 32 is equal to the width of the first isolation post 31.
[0101] Specifically, by setting the inner diameter of the groove 24 to be larger than the inner diameter of the capacitor hole 35 above it, the width of the second isolation post 32 between adjacent grooves 24 in the first direction D1 is smaller than the width of the first isolation post 31 between adjacent capacitor holes 35 in the first direction. This allows for sufficient modification of the second isolation post 32 to effectively isolate the substrate 25 from the capacitor. Simultaneously, the width of the second isolation post 32 should not be too small, as an insufficient width would prevent stable support of the first isolation post 31 above it.
[0102] In some embodiments, the specific steps of forming an isolation layer that connects adjacent grooves 24 and fills the grooves 24 include:
[0103] Along the oxidized portion of the opening 45, the first isolation pillar 31 and all of the second isolation pillars 32 form an isolation sidewall 37 on the sidewall of the capacitor hole 35, and a first sub-isolation layer 36 is formed between adjacent grooves 24, as shown. Figure 2K As shown;
[0104] A second sub-isolation layer 38 is deposited along the opening 45 within the groove 24, forming the isolation layer comprising the first sub-isolation layer 36 and the second sub-isolation layer 38, as shown below. Figure 2M As shown.
[0105] In some embodiments, the initial substrate 20 is made of silicon, and the first sub-isolation layer 36 and the second sub-isolation layer 38 are both made of silicon dioxide.
[0106] The following explanation uses silicon as an example, with silicon dioxide as the material of the initial substrate 20 and silicon dioxide as the material of the first sub-isolation layer 36 and the second sub-isolation layer 38. For example, in-situ oxidation (e.g., in-situ water vapor generation) of the first isolation pillar 31, the second isolation pillar 32, and a portion of the initial substrate 20 at the bottom of the groove 24 is performed. Since the width of the first isolation pillar 31 in the first direction D1 is greater than the width of the second isolation pillar 32 in the first direction D1, by controlling oxidation parameters (e.g., oxidation time, oxidant dosage, etc.), the second isolation pillar 32 can be completely oxidized, while only the surface of the first isolation pillar 31 is oxidized. This forms the isolation sidewall 37 covering the sidewall of the capacitor hole 35, and the first sub-isolation layer 36 located between adjacent grooves 24 and covering the bottom surface of the grooves 24. Figure 2K As shown. Then, silicon dioxide material is deposited along the opening 45 into the capacitor hole 35 and the groove 24 to form a second sub-isolation layer 38 that fills the opening 45, capacitor hole 35, and groove 24, as shown. Figure 2L As shown. Next, the second sub-isolation layer 38 is etched back, and a portion of the isolation sidewall 37 is removed, exposing the first isolation pillar 31, and the remaining second sub-isolation layer 38 fills the groove 24, as shown. Figure 2M As shown.
[0107] In some embodiments, the specific steps of depositing a second sub-isolation layer 38 along the opening 45 within the groove 24 include:
[0108] A second sub-isolation layer 38 is deposited along the opening 45 in the groove 24 and at the bottom of the capacitor hole 35, such that the top surface of the second sub-isolation layer 38 is above the bottom surface of the first isolation post 31.
[0109] Specifically, during the etch-back of the second sub-isolation layer 38, the etch-back parameters are controlled so that the top surface of the remaining second sub-isolation layer 38 is located above the bottom surface of the first isolation pillar 31, thereby fully isolating adjacent capacitors and preventing leakage between adjacent capacitors.
[0110] This specific embodiment uses the oxidation of the second isolation pillar 32 to form the first sub-isolation layer 36 as an example for illustration. In other specific embodiments, other modification methods can also be used to treat the second isolation pillar 32 to form the first sub-isolation layer 36. Among these other modification methods, doping is one of them.
[0111] Step S14, forming a capacitor within the capacitor hole 35, as follows: Figure 2O As shown.
[0112] In some embodiments, the specific steps of forming a capacitor within the capacitor hole 35 include:
[0113] Remove the isolation sidewall 37;
[0114] Forming a first electrode 40 covering the sidewall of the capacitor hole 35, such as Figure 2N As shown;
[0115] A dielectric layer 41 is formed covering the surface of the first electrode 40, the top surface of the isolation layer, and the bottom surface of the mask layer;
[0116] A second electrode 42 is formed covering the dielectric layer 41 to form the capacitor including the first electrode 40, the dielectric layer 41, and the second electrode 42, as shown. Figure 2O As shown.
[0117] Specifically, atomic layer deposition (ALD) can be used to selectively deposit the first conductive material on the sidewalls of the capacitor aperture 35 without depositing it on the bottom surface of the capacitor aperture 35, thus eliminating the need for a step to remove the first conductive material from the bottom of the capacitor aperture and further simplifying the formation process of the memory. Next, an ALD is used to deposit the dielectric layer 41 on the surface of the first electrode 40, the surface of the isolation layer, and the bottom surface of the mask layer. Then, a second electrode 42 is formed covering the dielectric layer 41. The materials of the first electrode 40 and the second electrode 42 can both be Ru, RuO2, or TiN to enhance the conductivity of the capacitor. The material of the dielectric layer 41 can be one or a combination of two or more of STO (lithium titanate SrTiO3), Al2O3, ZrO, and HfO2.
[0118] In some embodiments, after forming the second electrode 42 covering the dielectric layer 41, the following steps are further included:
[0119] Remove the mask layer and re-etch the first electrode 40, the dielectric layer 41, and the second electrode 42 in the etched portion to expose the upper part of the first isolation pillar 31, as shown below. Figure 2P As shown, Figure 2P yes Figure 2O A cross-sectional schematic diagram of the plane containing the first direction D1 and the second direction D3;
[0120] A covering layer 44 is formed to cover the exposed first isolation pillar 31, such as Figure 2Q As shown.
[0121] In some embodiments, after forming a covering layer 44 that covers the exposed first isolation pillar 31, the following steps are further included:
[0122] The first isolation pillar 31 in the capping layer 44 is doped to form the active region of the transistor.
[0123] Specifically, after forming the capacitor, the mask layer is removed, and a portion of the capacitor is etched back to expose the upper part of the first isolation pillar 31 at a predetermined height. Spacing grooves 43 are then formed between adjacent first isolation pillars 31. Figure 2P As shown. Then, an insulating material such as silicon dioxide is deposited within the spacer groove 43 to form the covering layer 44 that fills the spacer groove 43, as shown. Figure 2Q As shown. Then, by doping the first isolation pillar 31 covered by the capping layer 44, an active region is formed to create a TOC (Transistor on Capacitor) structure. The active region includes a channel region and a direction perpendicular to the top surface of the substrate 25 (e.g., Figure 2Q The third-party D3) is distributed on the source and drain regions on opposite sides of the channel region. The drain region is electrically connected to the capacitor, and the source region is used to connect to the bit line. This allows the bit line to be positioned above the capacitor, reducing the bit line resistance, simplifying the memory manufacturing process, reducing the footprint of a single memory, and improving the memory integration.
[0124] This specific embodiment also provides a memory, attached... Figure 3 This is a schematic diagram of the structure of the memory in a specific embodiment of this disclosure. The memory provided in this specific embodiment can adopt, for example... Figure 1 , Figures 2A-2Q The memory is formed using the method shown. For example... Figure 3 As shown, the memory includes:
[0125] Substrate 25;
[0126] An isolation layer is located above the substrate 25;
[0127] A capacitor array, located above the isolation layer, includes multiple capacitors, each of which includes a first electrode 40 extending in a direction perpendicular to the top surface of the substrate 25, a dielectric layer 41 covering the surface of the first electrode 40, and a second electrode 42 covering the surface of the dielectric layer 41.
[0128] In some embodiments, the memory further includes:
[0129] The first isolation post 31 is located between two adjacent capacitors;
[0130] The isolation layer includes a first sub-isolation layer 36 located between the first isolation pillar 31 and the substrate 25, and a second sub-isolation layer 38 located below the capacitor.
[0131] In some embodiments, the material of the first sub-isolation layer 36 is the same as the material of the second sub-isolation layer 38.
[0132] In some embodiments, the substrate 25 and the first isolation pillar 31 are both made of silicon, and the first sub-isolation layer 36 and the second sub-isolation layer 38 are both made of silicon dioxide.
[0133] In some embodiments, the first electrode 40 covers the sidewall of the first isolation pillar 31, and the dielectric layer 41 covers the surface of the first electrode 40 and the surface of the second sub-isolation layer 38.
[0134] In some embodiments, the bottom surface of the first isolation post 31 is located below the bottom surface of the first electrode 40.
[0135] In some embodiments, the memory further includes:
[0136] The trench area is located above the first isolation pillar 31;
[0137] A gate is disposed around the channel region.
[0138] The memory and its formation method provided in some embodiments of this specific implementation first form a groove below the capacitor hole for forming the capacitor before forming the capacitor. After forming an isolation layer that connects and fills the groove, the capacitor is then formed in the capacitor hole above the isolation layer. This electrically isolates the bottom of the capacitor from the substrate through the isolation layer, reducing or even avoiding the problem of leakage at the bottom of the capacitor, thereby improving the electrical performance of the memory. In addition, compared with the method of forming the isolation layer directly on the substrate through deposition or oxidation processes, the memory formation method provided in this disclosure integrates the capacitor hole formation process and the isolation layer formation process, so that the isolation layer formation process can be performed at the same time as forming the capacitor hole. The isolation layer is formed directly below the capacitor, ensuring that the isolation layer can be fully aligned with the bottom of the capacitor. This simplifies the manufacturing process of the memory, reduces the process difficulty of the memory, and further improves the electrical isolation effect between the capacitor and the substrate.
[0139] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a memory, characterized in that, Includes the following steps: Provide initial substrate; The initial substrate is etched to form a plurality of capacitor holes and a plurality of grooves that are connected to each of the capacitor holes and located below the capacitor holes; An isolation layer is formed to connect adjacent grooves and fill the grooves, with the initial substrate remaining below the isolation layer serving as the substrate; A capacitor is formed within the capacitor hole; The specific steps for forming multiple capacitor holes and multiple grooves that communicate with each of the capacitor holes and are located below the capacitor holes include: The initial substrate is etched to form a plurality of first etch trenches, each of the first etch trenches extending along a first direction, and the plurality of first etch trenches being parallel to each other and spaced apart in a second direction, both the first direction and the second direction being parallel to the top surface of the initial substrate, and the first direction and the second direction being orthogonal to each other. The initial substrate is etched to form a plurality of second etch trenches, each of the second etch trenches extending along the second direction, and the plurality of second etch trenches are parallel to each other and spaced apart in the first direction; The initial substrate at the bottom of the second etching trench is etched to form a groove with a width greater than that of the second etching trench in a first direction; The first etching groove and the second etching groove are connected to form the capacitor hole.
2. The method for forming a memory according to claim 1, characterized in that, Before forming multiple second etching trenches, the following steps are also included: A first filler layer is formed that completely fills the first etched groove.
3. The method for forming a memory according to claim 2, characterized in that, The specific steps for forming the groove with a width greater than that of the second etching groove include: The initial substrate at the bottom of the second etching trench is etched using Bosch etching technology to form the groove.
4. The method for forming a memory according to claim 2, characterized in that, The specific steps for forming the capacitor hole by connecting the first etching trench and the second etching trench include: A second filling layer is formed that fills the second etched groove and the recess; A patterned mask layer is formed over the initial substrate, the mask layer including a plurality of openings exposing the overlapping area of the first etch trench and the second etch trench; The first filler layer and the second filler layer are removed along the opening to form the capacitor hole.
5. The method for forming a memory according to claim 4, characterized in that, The specific steps of forming a patterned mask layer over the initial substrate, wherein the mask layer includes a plurality of openings exposing the overlapping region of the first etch trench and the second etch trench include: A first sub-mask layer is formed over the initial substrate; The first sub-mask layer is etched to form a plurality of first sub-openings that expose the first filling layer. Each first sub-opening extends along the first direction, and the plurality of first sub-openings are spaced apart along the second direction. A third filling layer is formed to completely fill the first sub-opening; The first sub-mask layer and the third fill layer are etched to form a plurality of second sub-openings that expose the initial substrate. Each second sub-opening extends in a direction parallel to the second direction, and the plurality of second sub-openings are spaced apart in the first direction. The second sub-mask layer is filled into the second sub-opening to form the mask layer including the second sub-mask layer and the remaining first sub-mask layer, the mask layer including a plurality of openings exposing the third filling layer; The third filler layer is removed along the opening, exposing the overlapping area of the first etched groove and the second etched groove.
6. The method for forming a memory according to claim 5, characterized in that, The initial substrate remaining between adjacent capacitor holes serves as a first isolation pillar, and the initial substrate remaining between adjacent grooves serves as a second isolation pillar. In the first direction, the width of the second isolation post is 1 / 2 to 1 / 3 of the width of the first isolation post; in the second direction, the width of the second isolation post is equal to the width of the first isolation post.
7. The method for forming a memory according to claim 6, characterized in that, The specific steps for forming an isolation layer that connects adjacent grooves and fills the grooves include: Along the first isolation pillar and all of the second isolation pillars along the oxidized portion of the opening, an isolation sidewall is formed on the sidewall of the capacitor hole, and a first sub-isolation layer is formed between adjacent grooves; a second sub-isolation layer is deposited along the opening in the groove, forming the isolation layer including the first sub-isolation layer and the second sub-isolation layer.
8. The method for forming a memory according to claim 7, characterized in that, The specific steps of depositing a second sub-isolation layer within the groove along the opening include: A second sub-isolation layer is deposited along the opening into the groove and at the bottom of the capacitor hole, such that the top surface of the second sub-isolation layer is above the bottom surface of the first isolation pillar.
9. The method for forming a memory according to claim 7, characterized in that, The initial substrate is made of silicon, and both the first sub-isolation layer and the second sub-isolation layer are made of silicon dioxide.
10. The method for forming a memory according to claim 7, characterized in that, The specific steps for forming a capacitor within the capacitor hole include: Remove the isolation sidewall; A first electrode is formed covering the sidewall of the capacitor hole; A dielectric layer is formed covering the surface of the first electrode, the top surface of the isolation layer, and the bottom surface of the mask layer; A second electrode is formed to cover the dielectric layer, thereby forming the capacitor comprising the first electrode, the dielectric layer, and the second electrode.
11. The method for forming a memory according to claim 10, characterized in that, After forming the second electrode covering the dielectric layer, the following steps are also included: Remove the mask layer and re-etch the first electrode, the dielectric layer, and the second electrode in the etched portion to expose the upper part of the first isolation pillar; A covering layer is formed to enclose the exposed first isolation column.
12. The method for forming a memory according to claim 11, characterized in that, After forming the covering layer that encloses the exposed first isolation pillar, the following steps are also included: The first isolation pillar in the capping layer is doped to form the active region of the transistor.
13. A memory, formed using the memory forming method according to any one of claims 1-12, characterized in that, include: Substrate; An isolation layer is located above the substrate; A capacitor array, located above the isolation layer, includes multiple capacitors, each of which includes a first electrode extending in a direction perpendicular to the top surface of the substrate, a dielectric layer covering the surface of the first electrode, and a second electrode covering the surface of the dielectric layer.
14. The memory according to claim 13, characterized in that, Also includes: The first isolation post is located between two adjacent capacitors; The isolation layer includes a first sub-isolation layer located between the first isolation pillar and the substrate, and a second sub-isolation layer located below the capacitor.
15. The memory according to claim 14, characterized in that, The material of the first sub-isolation layer is the same as the material of the second sub-isolation layer.
16. The memory according to claim 15, characterized in that, The substrate and the first isolation pillar are both made of silicon, and the first sub-isolation layer and the second sub-isolation layer are both made of silicon dioxide.
17. The memory according to claim 16, characterized in that, The first electrode covers the sidewall of the first isolation pillar, and the dielectric layer covers the surface of the first electrode and the surface of the second sub-isolation layer.
18. The memory according to claim 15, characterized in that, The bottom surface of the first isolation pillar is located below the bottom surface of the first electrode.
19. The memory according to claim 14, characterized in that, Also includes: The trench area is located above the first isolation pillar; A gate is disposed around the channel region.