Defect detection method, device and computer readable storage medium of memory

Abstract

The application relates to a memory defect detection method, a memory defect detection device and a computer readable storage medium. The memory defect detection method comprises the following steps: writing first data to a target memory cell array; opening a word line of the target memory cell when a bit line voltage of the target memory cell is at a target voltage after being pulled up or pulled down, so as to store data opposite to the first data in the target memory cell, and the storage time of the target memory cell is a preset time; closing the word line of the target memory cell; reading second data stored in the target memory cell; judging whether the first data and the second data are consistent; and when the first data and the second data are consistent, determining that the target memory cell has a defect causing storage failure within the preset time. The embodiment of the application can effectively improve the defect detection capability.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a method, apparatus and computer-readable storage medium for detecting defects in memory. Background Technology

[0002] The manufacturing process of memory (such as DRAM) is intricate and complex, inevitably leading to process defects. In particular, word line (WL) driver circuitry can suffer from defects such as excessively high WL resistance due to factors like mask and etching anomalies. Since memory typically contains a large number of repetitive word line driver circuits, establishing relevant defect detection methods is crucial. However, the defect detection capabilities of current word line driver circuits still need improvement. Summary of the Invention

[0003] Based on this, embodiments of this application provide a defect detection method, apparatus, and computer-readable storage medium for a memory that can improve defect detection capabilities.

[0004] A method for detecting defects in a memory, the memory including a target storage cell, the method comprising:

[0005] Write the first data to the target storage cell array;

[0006] When the bit line voltage of the target memory cell is at the target voltage after being pulled up or pulled down, the word line of the target memory cell is opened to store data opposite to the first data back into the target memory cell. The opening time of the word line of the target memory cell is a preset time.

[0007] Turn off the word line of the target memory cell;

[0008] Read the second data stored in the target storage unit;

[0009] Determine whether the first data and the second data are consistent;

[0010] When the first data and the second data are consistent, it is determined that the target storage unit has a defect that causes write-back failure within a preset time.

[0011] In one embodiment, after determining whether the first data and the second data are consistent, the method further includes:

[0012] When the first data and the second data are inconsistent, the first data is rewritten to the target storage unit array, and the write-back time is shortened until the first data and the second data are consistent. The write-back time when the first data and the second data are consistent is obtained.

[0013] In one embodiment, the first data is "1", and the data opposite to the first data is "0".

[0014] In one embodiment, the first data is "0", and the data opposite to the first data is "1".

[0015] In one embodiment, the word lines of the target memory cell are precharged while the word lines are turned off.

[0016] In one embodiment, the memory includes multiple memory arrays, in which the target memory cells are arranged according to a preset method.

[0017] In one embodiment, all storage cells in the storage array are target storage cells.

[0018] In one embodiment, a Y-Page Write mode is used to write data to the storage array to achieve the writing of first data to the target storage cell array.

[0019] In one embodiment, a Y-Page Read mode is used to read data within the storage array, thereby enabling the independent reading of second data stored in the target storage unit.

[0020] In one embodiment, the preset time is 5ns to 20ns.

[0021] In one embodiment, prior to opening the word line, the method further includes:

[0022] Adjust the turn-on voltage of the word line.

[0023] In one embodiment, prior to opening the word line, the method further includes:

[0024] Adjust the shut-off voltage of the word line.

[0025] A defect detection device for a memory includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described above.

[0026] In one embodiment, the device is externally attached to the memory.

[0027] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0028] The aforementioned defect detection method, apparatus, and computer-readable storage medium for memory, by opening the word line of the target memory cell within a preset time and pulling up or down the bit line voltage of the target memory cell to the target voltage, can store back data to the target memory cell that is opposite to the first data originally stored within the preset time. By comparing the second data stored back in the target memory cell with the first data originally stored, defects such as excessively high word line resistance in the word line driving circuit can be detected, thereby improving the defect detection capability of the word line driving circuit and helping to improve product reliability and yield. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a partial circuit diagram of the word line driving circuit;

[0031] Figure 2 This is a flowchart illustrating a defect detection method for a memory in one embodiment;

[0032] Figure 3 This is a waveform diagram of the word line / bit line and memory cell when the word line resistance is normal and the word line resistance is too high during the detection process in one embodiment;

[0033] Figure 4 This is a schematic diagram illustrating the write-back process of memory cells on each word line of the same primary word line in one embodiment.

[0034] Figure 5 This is a flowchart illustrating a defect detection method for a memory in another embodiment. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0038] As mentioned in the background section, memory typically has a large number of repeating word line drive circuits.

[0039] Specifically, please refer to Figure 1 The word line driver circuit typically includes the main word line (MWL). The drain of transistor P1 is configured to receive the signal FXT, the source of transistor P1 is coupled to the word line WL, and the gate of transistor P1 is connected to the main word line driver. Furthermore, the source of transistor N1 is coupled to the word line WL, the drain of transistor N1 is configured to receive the negative word line voltage Vkk, and the gate of transistor N1 is connected to the main word line driver. Additionally, the source of transistor N2 is coupled to the word line WL, the drain of transistor N2 is configured to receive the negative word line voltage Vkk, and the gate of transistor N2 is configured to receive the signal FXB.

[0040] When the main word line MWL receives a low-level signal, transistor P1 turns on and transistor N1 turns off. At the same time, if a high-level signal FXT is provided, the word line is turned on, thereby enabling the memory cells on the word line; simultaneously, a signal FXB can be provided to turn on transistor N2, thereby grounding the word line and preventing word line voltage fluctuations.

[0041] In word line driver circuits, defects such as excessively high WL resistance can severely affect device performance.

[0042] Based on this, embodiments of this application provide a defect detection method, apparatus, and computer-readable storage medium for a memory that can improve defect detection capabilities.

[0043] In one embodiment, see Figure 2 A method for detecting defects in a memory is provided, comprising:

[0044] Step S100: Write the first data to the target storage cell array;

[0045] Step S200: When the bit line voltage of the target memory cell is at the target voltage after being pulled up or pulled down, open the word line of the target memory cell to store back data that is opposite to the first data into the target memory cell. The storage time of the target memory cell is a preset time.

[0046] Step S300: Turn off the word line of the target memory cell;

[0047] Step S400: Read the second data stored in the target storage unit;

[0048] Step S500: Determine whether the first data and the second data are consistent;

[0049] Step S600: When the first data and the second data are consistent, it is determined that the target storage unit has a defect that will cause a write-back failure within a preset time.

[0050] In step S100, the first data can be either "0" or "1", there is no restriction on this. Meanwhile, the target storage unit is a storage unit in the memory used for defect detection.

[0051] In step S200, the write-back time (TRAS) of the target memory cell is the word line open time of the target memory cell. The preset time can be set according to actual requirements. As an example, the preset time can be the JEDEC standard write-back time, or it can be lower than the JEDEC standard write-back time. Specifically, the preset time can be limited to 5ns to 20ns.

[0052] Before the word line of the target memory cell is turned on, its bit line voltage can be pulled up or pulled down to the target voltage by the precharge voltage. The precharge voltage can be the intermediate voltage between the target voltage Vary pulled up and the target voltage Vss pulled down.

[0053] As an example, the specific process of pulling up the bit line voltage of the target memory cell to the target voltage Vary (or pulling down to the target voltage Vss) can be as follows: First, select the bit line of the target memory cell and connect it to the input terminal to receive the external input voltage; then, amplify the voltage signal on the bit line through the sense amplifier (SA) so that the bit line voltage is pulled up (or pulled down) to the target voltage.

[0054] When the first data is "0", the data opposite to the first data is "1". Please refer to [link / reference needed]. Figure 3 When the bit line voltage of the target memory cell is at the target voltage Vary, the word line (WL on) of the target memory cell can be turned on to store a "1" back into the target memory cell within a preset time. The target voltage Vary is used to store a "1" back into the target memory cell.

[0055] When the first data is "1", the opposite data is "0". At this time, when the bit line voltage of the target memory cell is at the target voltage Vss, the word line of the target memory cell can be opened to store "0" back into the target memory cell within a preset time. The target voltage Vss is used to store "0" back into the target memory cell.

[0056] In step S300, after the word line is turned off, the transistor in the target memory cell is turned off, so that the capacitor in it no longer stores data.

[0057] At this point, if the target memory cell is functioning normally and has not failed, it will store data that is the opposite of the first data. However, if the word line resistance of the target memory cell is too high, within the preset time in the previous step, the word line voltage of the target memory cell slowly rises from Vkk to VPP, making it difficult to store the data that is the opposite of the first data back to the target memory cell. In this case, the target memory cell fails to store the data, and it still stores the first data, not the data that is the opposite of the first data.

[0058] Specifically, please refer to Figure 3 as well as Figure 4 When the first data is "0", after the word line is turned off (WL off), if the target memory cell is normal and not invalid, it will store back "1". However, when the word line resistance of the target memory cell is too high, the word line of the target memory cell will slowly rise from Vkk to VPP within the preset time in the previous step. At this time, within a short preset time, the high potential of BL is difficult to store back to the target memory cell, which will cause the target memory cell to fail to store back "1".

[0059] In step S400, the second data is the data stored in the target storage unit. If the target storage unit successfully writes back the data within a preset time, the second data read is the reverse of the first data after writing back the data. If the target storage unit fails to write back the data within the preset time, the second data read is still the first data.

[0060] Specifically, when the first data is "0", if the target storage unit successfully writes back within a preset time, the second data read is "1". If the target storage unit fails to write back within the preset time, the second data read is "0".

[0061] In step S500, the comparison between the first data and the second data can determine whether the target storage unit has failed to be stored.

[0062] In step S600, the comparison and judgment results of the first data and the second data can effectively discover that the target storage unit has a defect that causes a write-back failure within a preset time.

[0063] In this embodiment, when the bit line voltage of the target memory cell is at the target voltage after being pulled up or pulled down, the word line of the target memory cell is opened, and data opposite to the original first data is stored back to the target memory cell within a preset time. By comparing the second data in the target memory cell after storage back with the original first data, defects such as excessively high word line resistance in the word line driving circuit can be detected, thereby improving the defect detection capability of the word line driving circuit and helping to improve product reliability and yield.

[0064] It should be noted that, by applying the method of this embodiment, not only can write-back failure be effectively detected when the target memory cell has defects such as excessively high word line resistance, but also when it has defects such as excessively high FXT to WL resistance, excessively high WL contact resistance, and excessively high Cell contact resistance.

[0065] Specifically, "FXT to WL resistance too high" means that the data line between FXT and WL has an excessively high resistance; "WLcontact" means that the Licon (metal wire) connected to WL has an excessively high resistance or poor contact; "Cell contact G resistance too high" means that the NC resistance connected to the Cell (storage capacitor) pillar has an excessively high resistance or poor contact between the two. Here, NC stands for storage node contact, which is the contact structure between the capacitor and the source.

[0066] When the target storage cell has defects such as excessively high FXT to WL resistance, excessively high WL contact resistance, or excessively high Cell contact resistance, data that is opposite to the first data will also be difficult to be stored back into the target storage cell within a preset time, thus the storage failure can be detected.

[0067] In one embodiment, see Figure 5 After step S500, the following steps are also included:

[0068] Step S700: When the first data and the second data are inconsistent, rewrite the first data to the target storage cell array and shorten the write-back time until the first data and the second data are consistent, and obtain the write-back time when the first data and the second data are consistent.

[0069] TRAS (Read Back Time) refers to shortening the open time of the word line of the target memory cell.

[0070] When the first and second data are inconsistent, it indicates that the target memory cell has not failed to be written back within the preset time. That is, at this time, when the write-back time is the preset time, the resistance values ​​at the word lines and other points of the target memory cell meet the requirements.

[0071] However, if the data recall time is shortened, and the target storage unit cannot recall the data in time within the shortened time, it may lead to data recall failure.

[0072] In this embodiment, by shortening the write-back time, the limit value of the write-back time for the target storage unit to maintain normal operation can be obtained.

[0073] In one embodiment, step S300 precharges the bit lines while shutting down the word lines of the target memory cell.

[0074] The bit line is pre-charged, meaning the bit line returns from the target voltage to the pre-charge voltage. This allows for timely reading of the second data stored in the target memory cell.

[0075] Specifically, when reading the second data stored in the target memory cell in step S400, the bit lines must first be pre-charged. Here, step S300 pre-charges the bit lines while turning off the word lines of the target memory cell, meaning the reading phase can begin at this point. This allows for timely reading of the second data stored in the target memory cell, thereby improving detection efficiency.

[0076] Of course, in other embodiments, the bit lines can be pre-charged after the word lines of the target memory cell have been turned off for a period of time, and there is no limitation on this.

[0077] In one embodiment, the memory includes multiple memory arrays, in which target memory cells are arranged according to a preset method.

[0078] Specifically, the memory may include multiple memory banks, each bank may contain multiple memory arrays, and each memory array may contain multiple memory cells. First, a bank is selected, and then a memory array is chosen within that bank to detect the target memory cell within that array. Then, the memory array can be changed until all memory arrays within the bank have been detected. Afterward, the bank can be changed again until all banks have been detected, thus completing the detection of the memory.

[0079] At this point, the target storage units can be arranged in each storage array according to a preset method.

[0080] In the default mode, all memory cells in the memory array can be used as target memory cells, thereby performing a comprehensive inspection of the memory array and further determining the type of defect. For example, if all memory cells corresponding to the word line of the target memory cell that failed during write-back are also failed, but only that memory cell is failed among all memory cells corresponding to its bit line, then it can be determined that the defect of the target memory cell is located in the word line driving circuit.

[0081] Specifically, in the default mode, when all storage cells in the storage array are used as target storage cells, if the first data is "0", the default mode is Solid "0". Please refer to Table 1 below; Solid "0" mode means writing logical data "0" to all storage cells in the entire storage array. If the first data is "1", the default mode is Solid "1". Please refer to Table 2 below; Solid "1" mode means writing logical data "1" to all storage cells in the entire storage array.

[0082] Table 1

[0083]

[0084] Table 2

[0085]

[0086] Of course, in the default mode, some storage units in the storage array can also be used as target storage units.

[0087] As an example, the preset methods could include Checkboard, Diagonal, Row Stripe, Column Stripe, etc.

[0088] Specifically, please refer to Tables 3 and 4 below. The Checkboard method refers to writing logical data "0" and "1" to adjacent storage cells in the storage array respectively. The logical data "0" and "1" are arranged like a chessboard.

[0089] Table 3

[0090]

[0091] Table 4

[0092]

[0093] Please refer to Tables 5 and 6 below. The Diagonal arrangement refers to the diagonal layout.

[0094] Table 5

[0095]

[0096]

[0097] Table 6

[0098]

[0099] Please refer to Tables 7 and 8 below. The Row Stripe method refers to arranging logical data according to the word line direction, with different logical data arranged in different word line directions.

[0100] Table 7

[0101]

[0102] Table 8

[0103]

[0104] Please refer to Tables 9 and 10 below. The Column Stripe method refers to arranging data according to the direction of the bit lines, with different logical data arranged in different bit line directions.

[0105] Table 9

[0106]

[0107] Table 10

[0108]

[0109] In one embodiment, a Y-Page Write mode is used to write data to the storage array in order to write the first data to the target storage cell array.

[0110] Page read and write operations are the most time-efficient. Therefore, using the Y-Page Write mode to write data to the storage array can reduce mass production testing time and thus save testing costs.

[0111] Of course, in other embodiments, when writing data to the storage array, modes such as Y-March Write, Y-Fast Write, X-March Write, and X-Fast Write can also be used.

[0112] In one embodiment, a Y-Page Read mode is used to read data within the storage array, thereby enabling the independent reading of second data stored in the target storage unit.

[0113] Page read and write operations are the most time-efficient. Therefore, using the Y-Page Read mode to read data within the storage array can reduce mass production testing time and thus save testing costs.

[0114] Of course, in other embodiments, Y-March Read, Y-Fast Read, X-March Read, X-Fast Read and other modes can also be used when reading data in the storage array.

[0115] In one embodiment, before step S200, the method further includes: adjusting the turn-on voltage of the word line.

[0116] Specifically, the turn-on voltage VPP of the word line can be reduced from the standard turn-on voltage. The standard turn-on voltage can be the turn-on voltage during the normal operation of the storage device.

[0117] A decrease in the word line turn-on voltage (VPP) affects the transistor turn-on of the target memory cell, making it more difficult for the target memory cell to write data back. If the target memory device does not fail at the reduced word line turn-on voltage, it is even less likely to fail at the standard turn-on voltage. Therefore, this improves product reliability.

[0118] In one embodiment, before step S200, the method further includes: adjusting the shut-off voltage of the word line.

[0119] Specifically, the word line shutdown voltage VKK can be reduced from the standard shutdown voltage. The standard shutdown voltage can be the shutdown voltage for the normal operation of the storage device.

[0120] Lowering the word line shutdown voltage VKK makes it take longer for the word line voltage of the target memory cell to rise from VKK to VPP. If the target memory device does not fail at the reduced word line shutdown voltage, it is even less likely to fail at the standard shutdown voltage. Therefore, this improves product reliability.

[0121] It should be understood that, although Figure 2 as well as Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 as well as Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0122] In one embodiment, a defect detection device is also provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0123] Step S100: Write the first data to the target storage cell array;

[0124] Step S200: When the bit line voltage of the target memory cell is at the target voltage after being pulled up or pulled down, open the word line of the target memory cell to store back data that is opposite to the first data into the target memory cell. The storage time of the target memory cell is a preset time.

[0125] Step S300: Turn off the word line of the target memory cell;

[0126] Step S400: Read the second data stored in the target storage unit;

[0127] Step S500: Determine whether the first data and the second data are consistent;

[0128] Step S600: When the first data and the second data are consistent, it is determined that the target storage unit has a defect that will cause the write-back failure within a preset time.

[0129] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0130] When the first data and the second data are inconsistent, the first data is rewritten to the target storage cell array, and the write-back time is shortened until the first data and the second data are consistent; the write-back time when the first data and the second data are consistent is obtained.

[0131] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0132] While disabling the word lines of the target memory cell, the bit lines are pre-charged.

[0133] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0134] The Y-Page Write mode is used to write data to the storage array in order to write the first data to the target storage cell array.

[0135] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0136] Using the Y-Page Read mode, data within the storage array is read, enabling the independent reading of the second data stored in the target storage unit.

[0137] In one embodiment, the defect detection device is externally mounted to the memory, thereby enabling the detection capability of the defect detection device to be effectively improved without being limited by the memory.

[0138] Of course, in some embodiments, the defect detection device may also be integrated with the memory, and there is no limitation on this.

[0139] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, the computer program performing the following steps when executed by a processor:

[0140] Step S100: Write the first data to the target storage cell array;

[0141] Step S200: When the bit line voltage of the target memory cell is at the target voltage after being pulled up or pulled down, open the word line of the target memory cell to store back data that is opposite to the first data into the target memory cell. The storage time of the target memory cell is a preset time.

[0142] Step S300: Turn off the word line of the target memory cell;

[0143] Step S400: Read the second data stored in the target storage unit;

[0144] Step S500: Determine whether the first data and the second data are consistent;

[0145] Step S600: When the first data and the second data are consistent, it is determined that the target storage unit has a defect that will cause the write-back failure within a preset time.

[0146] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0147] When the first data and the second data are inconsistent, the first data is rewritten to the target storage cell array, and the write-back time is shortened until the first data and the second data are consistent; the write-back time when the first data and the second data are consistent is obtained.

[0148] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0149] While disabling the word lines of the target memory cell, the bit lines are pre-charged.

[0150] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0151] The Y-Page Write mode is used to write data to the storage array in order to write the first data to the target storage cell array.

[0152] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0153] Using the Y-Page Read mode, data within the storage array is read, enabling the independent reading of the second data stored in the target storage unit.

[0154] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0155] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0156] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0157] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for detecting defects in a memory, characterized in that, The memory includes a target storage unit, and the method includes: Write the first data to the target storage cell array; When the bit line voltage of the target memory cell is at the target voltage after being pulled up or pulled down, the word line of the target memory cell is opened to store data opposite to the first data back into the target memory cell. The storage time of the target memory cell is a preset time. Turn off the word line of the target memory cell; Read the second data stored in the target storage unit; Determine whether the first data and the second data are consistent; When the first data and the second data are consistent, it is determined that the target storage unit has a defect that causes write-back failure within a preset time.

2. The method according to claim 1, characterized in that, After determining whether the first data and the second data are consistent, the method further includes: When the first data and the second data are inconsistent, the first data is rewritten to the target storage unit array, and the write-back time is shortened until the first data and the second data are consistent. The write-back time when the first data and the second data are consistent is obtained.

3. The method according to claim 1, characterized in that, The first data is "1", and the data opposite to the first data is "0".

4. The method according to claim 1, characterized in that, The first data is "0", and the data opposite to the first data is "1".

5. The method as described in claim 1, characterized in that, While shutting down the word lines of the target memory cell, the bit lines are precharged.

6. The method as described in claim 1, characterized in that, The memory includes multiple memory arrays, in which the target memory cells are arranged according to a preset method.

7. The method as described in claim 6, characterized in that, All storage units in the storage array are target storage units.

8. The method as described in claim 6, characterized in that, Using the Y-Page Write mode, data is written to the storage array to achieve the writing of first data to the target storage cell array.

9. The method as described in claim 6, characterized in that, Using the Y-Page Read mode, data within the storage array is read to enable the independent reading of the second data stored in the target storage unit.

10. The method according to claim 1, characterized in that, The preset time is from 5ns to 20ns.

11. The method according to claim 1, characterized in that, Before opening the word line, the method further includes: Adjust the turn-on voltage of the word line.

12. The method according to claim 1, characterized in that, Before opening the word line, the method further includes: Adjust the shut-off voltage of the word line.

13. A defect detection device for a memory, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method according to any one of claims 1 to 12.

14. The defect detection device for a memory according to claim 13, characterized in that, The device is attached externally to the memory.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

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