A high-precision timekeeping method suitable for low-precision clock systems

Abstract

The application provides a high-precision time keeping method suitable for a low-precision clock system, which realizes accurate compensation relative to a GPS / BD clock by using proportional errors of an internal low-precision clock and an external low-precision clock of the low-precision clock system. The method is designed ingeniously, is suitable for time keeping requirements of low-cost power distribution network automation equipment by using a simple proportional operation rule, meets high-precision time keeping requirements of fault analysis and the like, has a smaller demand for calculation amount, does not increase CPU operation load, and has no influence on original performance functions.

Description

Technical Field

[0001] This invention relates to the field of power system distribution network technology, and specifically provides a high-precision timekeeping method suitable for low-precision clock systems. Background Technology

[0002] Electronic devices are increasingly integrated, with reduced physical and environmental footprints. This means the demand for real-time clocks that consume less power and maintain accurate time over a wider temperature range will continue to grow. Distribution network users are demanding higher reliability, requiring more accurate time stamps for fault analysis. When modules in equipment lack high-precision clocks, the sequencing requirements for sequential event recall in multi-device distribution network systems cannot be met. From a clock chip manufacturing perspective, higher precision often means increased power consumption and cost, but distribution network equipment budgets are relatively low, creating a significant conflict between this demand and the need for high performance. Summary of the Invention

[0003] The technical objective of this invention is to address the aforementioned problems by providing a high-precision timekeeping method suitable for low-precision clock systems.

[0004] In one aspect, the present invention provides a high-precision timekeeping method suitable for low-precision clock systems. The method achieves accurate compensation relative to GPS / BD clocks by utilizing the proportional errors of the low-precision clocks inside and outside the low-precision clock system.

[0005] Furthermore, the low-precision clock system refers to the clock system of the 10kV distribution automation terminal installed on the distribution network line. The system has an internal clock and an external clock, and the external clock has a power failure retention function.

[0006] Furthermore, the crystal oscillator accuracy of the internal clock of the low-precision clock system is less than 25ppm, and the crystal oscillator accuracy of the external clock is less than 10ppm, but the timekeeping accuracy is required to be less than 5ms.

[0007] Furthermore, the implementation of the method includes clock calibration and clock keeping:

[0008] The clock calibration includes two types: initial calibration and secondary calibration.

[0009] The clock timekeeping includes two types: non-power-loss timekeeping and power-loss timekeeping.

[0010] Furthermore, the initial clock calibration employs a long-term calibration method, and the calibration process includes:

[0011] After connecting the system to the GPS / BD second pulse, initiate the calibration process.

[0012] Gradually approach and adjust the time of the external clock so that the error between the rising edge of its second pulse and the rising edge of the GPS / BD second pulse is less than or equal to 1ms, and synchronously adjust the rising edge of the internal clock's second pulse to be consistent with the rising edge of the GPS / BD second pulse.

[0013] The current value of the free counter, which relies on the system's millisecond interrupt, is latched, and the reception and processing of GPS / BD second pulses are stopped; the free counter is a 32-bit counter.

[0014] After running for 2 hours, latch the free counter values ​​at the rising edges of the GPS / BD second pulse, the rising edges of the external clock second pulse, and the rising edges of the internal clock second pulse;

[0015] Calculate the difference between the latched values ​​of the GPS / BD second pulse rising edge, the external clock second pulse rising edge, and the internal clock second pulse rising edge, and record them in the power-off storage area.

[0016] Furthermore, the secondary calibration of the clock calibration adopts a short-time calibration method, and the calibration process includes:

[0017] After connecting the system to the GPS / BD second pulse, initiate the calibration process.

[0018] The external clock time is gradually adjusted to be closer to the actual time, so that the error between the rising edge of its second pulse and the rising edge of the GPS / BD second pulse is less than or equal to 1ms.

[0019] Synchronize the rising edge of the internal clock's second pulse to match the rising edge of the GPS / BD second pulse.

[0020] Furthermore, the secondary calibration process does not rewrite the recorded value of the difference between the latched values ​​of the GPS / BD second pulse rising edge, the external clock second pulse rising edge, and the internal second pulse rising edge.

[0021] Furthermore, the timekeeping process of the clock without power loss includes:

[0022] After the initial clock calibration is completed, while the system remains powered on, monitor the difference between the rising edge of the external clock's second pulse and the rising edge of the internal clock's second pulse.

[0023] The theoretical difference between the rising edge of the GPS / BD second pulse and the rising edge of the internal clock second pulse is calculated based on the proportional relationship between the differences in the latched values ​​of the rising edge of the GPS / BD second pulse, the rising edge of the external clock second pulse, and the rising edge of the internal clock second pulse.

[0024] When the calculated difference is greater than 3ms, the rising edge of the internal clock second pulse is adjusted, and the external clock chip is calibrated at the same time. The rising edge of the external clock second pulse is made to coincide with the rising edge of the internal clock second pulse by using a successive approximation method to obtain a relatively accurate clock timekeeping.

[0025] Furthermore, the clock-down timekeeping process includes:

[0026] After the system restarts, read the current clock from an external clock.

[0027] Calculate the time elapsed from the last power outage to the current power-on.

[0028] Adjust the internal clock value based on the difference between the rising edge of the GPS / BD second pulse and the rising edge of the external clock second pulse recorded over 2 hours.

[0029] The external clock is calibrated by using a successive approximation method to ensure that the rising edge of the second pulse of the external clock coincides with the rising edge of the second pulse of the internal clock.

[0030] Furthermore, before the system loses power again, after the initial clock calibration is completed, when the system is not powered down, the difference between the rising edge of the external clock second pulse and the rising edge of the internal clock second pulse is monitored.

[0031] The theoretical difference between the rising edge of the GPS / BD second pulse and the rising edge of the internal clock second pulse is calculated based on the proportional relationship between the differences in the latched values ​​of the rising edge of the GPS / BD second pulse, the rising edge of the external clock second pulse, and the rising edge of the internal clock second pulse.

[0032] When the calculated difference is greater than 3ms, the rising edge of the internal clock second pulse is adjusted, and the external clock chip is calibrated at the same time. The rising edge of the external clock second pulse is made consistent with the rising edge of the internal clock second pulse by using a successive approximation method to obtain a relatively accurate long-term clock timekeeping.

[0033] Compared with existing technologies, the high-precision timekeeping method for low-precision clock systems of the present invention has the following outstanding advantages:

[0034] The method of this invention is ingeniously designed and uses a simple proportional arithmetic rule to meet the timekeeping requirements of low-cost distribution network automation equipment. It meets the high-precision timekeeping requirements for fault analysis and other tasks, requires less computation, does not increase the CPU's computational load, and has no impact on the original performance and functions. Attached Figure Description

[0035] Figure 1 This is a program logic diagram of the implementation of the method of the present invention;

[0036] Figure 2 This is a schematic diagram of the GPS / BD and internal / external clock latch of the present invention;

[0037] Figure 3 This is a schematic diagram of the method for obtaining the system clock t0 under the condition of no power loss according to the present invention;

[0038] Figure 4 This is a schematic diagram of the method for obtaining the system clock t0 under power failure conditions according to the present invention. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. Example

[0040] The calibration and timekeeping functions implemented by the method of this invention include:

[0041] Initial calibration: The procedure is as follows Figure 1 As shown, the path is: Start -> Calibration (Y) -> Pulse Alignment (Y) -> First Time (Y) -> Delay 2 hours -> Pulse Difference Latch, and the specific process is as follows:

[0042] After connecting the system to the GPS / BD second pulse, initiate the calibration operation, gradually approximating and adjusting the external clock's time until the error between its second pulse rising edge and the GPS / BD second pulse rising edge is less than or equal to 1ms. Simultaneously adjust the internal clock's second pulse rising edge to match the GPS / BD second pulse rising edge. Latch the current value of the free counter, which relies on the system's millisecond interrupt, and stop receiving and processing GPS / BD second pulses. After running for 2 hours, latch the free counter values ​​at the rising edges of the GPS / BD second pulse, the external clock's second pulse, and the internal clock's second pulse. Figure 2 As shown: the difference ab=3ms, the difference ac=5ms, the difference bc=8ms, and recorded in the power failure storage area.

[0043] Secondary calibration: The procedure is as follows Figure 1 As shown, the path is: Start -> Calibration (Y) -> Pulse Alignment (Y) -> First Time (N), and the specific implementation process is as follows:

[0044] After connecting the system to the GPS / BD second pulse, start the calibration operation to gradually approach and adjust the time of the external clock so that the error between the rising edge of its second pulse and the rising edge of the GPS / BD second pulse is less than or equal to 1ms. Synchronously adjust the rising edge of the internal clock's second pulse to be consistent with the rising edge of the GPS / BD second pulse.

[0045] No power failure and timekeeping: The program flow follows Figure 1 If the deviation is greater than 3ms (Y), the internal and external clocks are corrected. The specific process is as follows:

[0046] The difference between the rising edges of the external clock's second pulse and the internal clock's second pulse is monitored. Based on the proportional relationship between the differences in the latched values ​​of the GPS / BD second pulse rising edges, the external clock's second pulse rising edges, and the internal clock's second pulse rising edges, the theoretical difference between the GPS / BD second pulse rising edges and the internal clock's second pulse rising edges is calculated. When the calculated difference is greater than 3ms, the internal clock's second pulse rising edge is adjusted, and simultaneously, the external clock chip is calibrated. A successive approximation method is used to ensure that the occurrence time of the external clock's second pulse rising edge is consistent with that of the internal clock's second pulse rising edge, thereby obtaining relatively accurate clock timing. Figure 3 As shown, the deviation Δt = ((t2-t1) / bc)*ab. If Δt>=3ms, then the correction t0 = t1+Δt.

[0047] Power-off timekeeping: The program flow is as follows Figure 1 The path is: Start -> Calibration (N) -> Correct internal and external clocks -> Deviation greater than 3ms (Y) -> Correct internal and external clocks. The specific process is as follows:

[0048] After the system restarts, it reads the current clock from the external clock, calculates the time elapsed from the last power outage to the current power-on, and adjusts the internal clock value based on the recorded difference between the rising edge of the GPS / BD second pulse and the rising edge of the external clock's second pulse over a 2-hour period. The external clock is then calibrated, using a successive approximation method to ensure that the rising edge of the external clock's second pulse coincides with the rising edge of the internal clock's second pulse. Before the system experiences another power outage, it maintains a constant clock position to achieve relatively accurate long-term timekeeping. Figure 4 As shown, the deviation Δt = ca * T / 2 (Note: T is the duration of power failure), then the correction t0 = t2 - Δt.

[0049] The embodiments described above are merely preferred embodiments of the present invention. Ordinary variations and substitutions made by those skilled in the art within the scope of the technical solutions of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-precision timekeeping method suitable for low-precision clock systems, characterized in that, The method achieves accurate compensation relative to the GPS / BD clock by utilizing the proportional errors of the low-precision clock inside the low-precision clock system and the external low-precision clock. The implementation of the method includes clock calibration and clock keeping: The clock calibration includes two types: initial calibration and secondary calibration. The clock timekeeping includes two types: clock timekeeping without power loss and clock timekeeping without power loss. The initial clock calibration uses a long-time calibration method, and the calibration process includes: After connecting the system to the GPS / BD second pulse, initiate the calibration process. Gradually approach and adjust the time of the external clock so that the error between the rising edge of its second pulse and the rising edge of the GPS / BD second pulse is less than or equal to 1ms, and synchronously adjust the rising edge of the internal clock's second pulse to be consistent with the rising edge of the GPS / BD second pulse. The current value of the free counter, which relies on the system's millisecond interrupt, is latched, and the reception and processing of GPS / BD second pulses are stopped; the free counter is a 32-bit counter; After running for 2 hours, latch the free counter values ​​at the rising edges of the GPS / BD second pulse, the rising edges of the external clock second pulse, and the rising edges of the internal clock second pulse; Calculate the difference between the latched values ​​of the GPS / BD second pulse rising edge, the external clock second pulse rising edge, and the internal clock second pulse rising edge, and record them in the power-down storage area; The timekeeping process of the clock without power loss includes: After the initial clock calibration is completed, when the system is not powered off, monitor the difference between the rising edge of the external clock second pulse and the rising edge of the internal clock second pulse. The theoretical difference between the rising edge of the GPS / BD second pulse and the rising edge of the internal clock second pulse is calculated based on the proportional relationship between the differences in the latched values ​​of the rising edge of the GPS / BD second pulse, the rising edge of the external clock second pulse, and the rising edge of the internal clock second pulse. When the calculated difference is greater than 3ms, the rising edge of the internal clock second pulse is adjusted, and the external clock chip is calibrated at the same time. The rising edge of the external clock second pulse is made to coincide with the rising edge of the internal clock second pulse by using a successive approximation method to obtain a relatively accurate clock timekeeping.

2. The high-precision timekeeping method for low-precision clock systems according to claim 1, characterized in that: The low-precision clock system refers to the clock system of the 10kV distribution automation terminal installed on the distribution network line. The clock system has an internal clock and an external clock, wherein the external clock has a power failure retention function.

3. The high-precision timekeeping method for low-precision clock systems according to claim 1, characterized in that: The low-precision clock system has an internal clock crystal oscillator accuracy of less than 25ppm, an external clock crystal oscillator accuracy of less than 10ppm, and a timekeeping accuracy of less than 5ms.

4. A high-precision timekeeping method suitable for low-precision clock systems according to claim 3, characterized in that, The secondary calibration of the clock calibration adopts a short-time calibration method, and the calibration process includes: After connecting the system to the GPS / BD second pulse, start the calibration operation; Gradually adjust the time of the external clock so that the error between the rising edge of its second pulse and the rising edge of the GPS / BD second pulse is less than or equal to 1ms. Synchronize the rising edge of the internal clock's second pulse to match the rising edge of the GPS / BD second pulse.

5. A high-precision timekeeping method for low-precision clock systems according to claim 4, characterized in that, The secondary calibration process does not rewrite the recorded value of the difference between the latched values ​​of the GPS / BD second pulse rising edge, the external clock second pulse rising edge, and the internal second pulse rising edge.

6. A high-precision timekeeping method for low-precision clock systems according to claim 4, characterized in that, The clock-down timekeeping process includes: After the system restarts, read the current clock from an external clock. Calculate the time elapsed from the last power outage to the current power-on. Adjust the internal clock value based on the difference between the rising edge of the GPS / BD second pulse and the rising edge of the external clock second pulse recorded over 2 hours. The external clock is calibrated by using a successive approximation method to ensure that the rising edge of the second pulse of the external clock coincides with the rising edge of the second pulse of the internal clock.

7. A high-precision timekeeping method for low-precision clock systems according to claim 6, characterized in that, Before the system loses power again, after the first clock calibration is completed, when the system is not powered off, monitor the difference between the rising edge of the external clock second pulse and the rising edge of the internal clock second pulse. The theoretical difference between the rising edge of the GPS / BD second pulse and the rising edge of the internal clock second pulse is calculated based on the proportional relationship between the differences in the latched values ​​of the rising edge of the GPS / BD second pulse, the rising edge of the external clock second pulse, and the rising edge of the internal clock second pulse. When the calculated difference is greater than 3ms, the rising edge of the internal clock second pulse is adjusted, and the external clock chip is calibrated at the same time. The rising edge of the external clock second pulse is made consistent with the rising edge of the internal clock second pulse by using a successive approximation method to obtain a relatively accurate long-term clock timekeeping.

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