Module for asynchronous differential serial communication

Abstract

A module for asynchronous differential serial communication on a bus is disclosed. The module can be connected to the bus in a first connection mode and a second connection mode. In the first connection mode, the module's non-inverting terminal is connected to a non-inverting bus signal line, and its inverting terminal is connected to an inverting bus signal line. The second connection mode is given by the inversion of the first connection mode. The module includes a detector that determines the connection mode based on the binary state of the start bit of a received signal provided by the module's transceiver based on a received communication signal, and the binary state of the first bit of a reference signal, the reference signal corresponding to the voltage difference between the voltages of the signals received via the non-inverting and inverting terminals during the reception of the communication signal.

Description

Technical Field

[0001] This invention relates to a module for asynchronous differential serial communication on a bus, the module comprising: a processor, a transceiver connected to the processor, and a terminal group connected to the transceiver; the terminal group comprising: a reference terminal and two signal terminals, the reference terminal being connected to or capable of being connected to a reference potential, and the two signal terminals comprising a non-inverting terminal and an inverting terminal; wherein the transceiver is configured to transmit a communication signal corresponding to a transmit signal provided by the processor via either a non-inverting port connected thereto to one of the signal terminals providing a non-inverting signal corresponding to a transmit signal, or an inverting port connected thereto to another of the signal terminals providing an inverted signal corresponding to an inverted transmit signal, each communication signal including a start bit having a predetermined binary number specified for communication on the bus. The transceiver is configured to receive communication signals and, during the reception of a corresponding communication signal, determine a corresponding received signal based on the voltage difference between the voltage of a signal received via its non-inverting port and the voltage of a signal received via its inverting port, such that each received signal includes a start bit having a predetermined binary state; and wherein the module is capable of connecting to the bus in two different connection modes, including a first connection mode and a second connection mode, in which the non-inverting terminal is connected to the non-inverting bus signal line of the bus and the inverting terminal is connected to the inverting bus signal line of the bus, and in the second connection mode, the non-inverting terminal is connected to the inverting bus signal line and the inverting terminal is connected to the non-inverting bus line. Background Technology

[0002] In process automation technology, field devices are used to monitor, regulate, and / or control the operation of an industrial site, as well as to monitor, regulate, and / or control at least one process, such as a production process performed at, on, or by an industrial site. Field devices used for this purpose include measuring devices that measure at least one variable (e.g., pressure, temperature, or flow rate) and field devices that include actuators, such as valves, applied to influence operation and / or the process.

[0003] In many applications, communication buses are used to enable field devices to communicate with at least one other field device and / or upper-level unit connected to the same bus. Upper-level units (e.g., control units, automation systems, and programmable logic controllers) are frequently used in process automation to monitor, regulate, and / or control the operation of a site and / or at least one process performed at, on, or by the site. As an example, a valve can be opened or closed based on the liquid level of a product in a container, based on communication signals transmitted via the bus, such as measurement signals and / or control signals.

[0004] In industrial applications, asynchronous differential serial communication is frequently used because this form of communication is highly sensitive to noise and electromagnetic interference. When using bidirectional asynchronous differential serial communication, communication via the bus is performed by transmitting a start bit, consisting of two complementary signals. Each of these complementary signals is transmitted along a separate signal line on the bus. One of the complementary signals is a non-inverted signal corresponding to the transmitted signal, and the other is an inverted signal corresponding to the inverted transmitted signal. Reception of the communication signal is performed by determining the corresponding receive signal based on the voltage difference between the two complementary signals received from the bus.

[0005] To allow for interoperability between devices from different manufacturers, field devices and upper-level units operating on the same bus preferably each include communication modules designed according to the same standard. In this regard, the RS-485 standard, also known as TIA-485(-A) or EIA-485, jointly published by the Telecommunications Industry Association and the Electronic Industries Alliance (TIA / EIA), is widely recognized in the industry.

[0006] The communication module designed according to this standard includes two signal terminals for connecting the module to two signal lines of the bus. Optionally, and particularly advantageously, when communication signals are transmitted over long distances, the communication module's reference terminal can be connected, for example, to a reference line on the bus that provides a reference potential. This option provides better communication stability and reduces sensitivity to electromagnetic interference.

[0007] The RS-485 standard defines the electrical characteristics of drivers and receivers that can be applied to these communication modules and describes the voltage relationship between two complementary signals for two binary states.

[0008] The RS-485 standard does not define the logical functions of the driver and receiver, nor does it define the specific connector type for connecting the communication module to the bus. Therefore, some manufacturers label the two signal terminals as inverted and non-inverted based on their correspondence with the logical states of the signals to be transmitted, while others label the two signal terminals according to the logical functions of the driver and receiver.

[0009] This makes it difficult for technicians to determine which of the module's two signal terminals should be connected to which of the bus's two signal lines when connecting a communication module designed according to the RS485 standard to the bus. Because different manufacturers use different labeling schemes, in many cases, the correct wiring pattern can only be determined based on the manufacturer's instruction manual. This is tedious and time-consuming, especially when a large number of field devices must be connected to the bus, each including a communication module designed according to the RS485 standard. Furthermore, communication modules will not function properly unless they are wired correctly. If communication failures caused by incorrect wiring are not noticed, this can have serious consequences for the site where the module is used. Communication failures can be caused by a variety of reasons. Therefore, when a communication failure is noticed, especially when the technician performing the search assumes the module is wired correctly, finding the underlying root cause can be tedious.

[0010] Therefore, further contributions are still needed in this technological field.

[0011] As an example, a module is needed for asynchronous differential serial communication that can be connected to the bus more easily and efficiently. Summary of the Invention

[0012] This invention discloses a module for asynchronous differential serial communication on a bus, the module comprising:

[0013] A processor, a transceiver connected to the processor, and a terminal group connected to the transceiver; the terminal group includes: a reference terminal connected to or capable of being connected to a reference potential and two signal terminals comprising a non-inverting terminal and an inverting terminal;

[0014] The transceiver is implemented to transmit a communication signal corresponding to the transmission signal provided by the processor via a non-inverting port connected to one of the signal terminals that provides a non-inverting signal corresponding to the transmission signal, or via an inverting port connected to another of the signal terminals that provides an inverting signal corresponding to the inverting signal of the transmission signal. Each communication signal includes a start bit having a predetermined binary state for communication on the bus.

[0015] The transceiver is configured to receive communication signals and, during the reception of a corresponding communication signal, to determine a corresponding received signal based on the voltage difference between the voltage of the signal received via its non-inverting port and the voltage of the signal received via its inverting port, such that each received signal includes a start bit having a predetermined binary state.

[0016] The module can be connected to the bus in two different connection modes, namely a first connection mode and a second connection mode. In the first connection mode, the non-inverting terminal is connected to the non-inverting bus signal line of the bus, and the inverting terminal is connected to the inverting bus signal line of the bus. In the second connection mode, the non-inverting terminal is connected to the inverting bus signal line, and the inverting terminal is connected to the non-inverting bus line.

[0017] The module further includes a detector configured to determine a connection mode based on the binary state of the start bit of a received signal provided by the transceiver based on a communication signal received when the module is connected to the bus and the binary state of the first bit of a reference signal, and to provide an output indicating the detected connection mode, the reference signal corresponding to the voltage difference between the voltage of a signal received via a non-inverting terminal and the voltage of a signal received via an inverting terminal during the reception of the same communication signal.

[0018] This module offers the following advantages: the detector determines and provides the connection pattern. Therefore, this connection pattern can be obtained based on the first communication signal received by the module. This provides the advantage that undesired connection patterns are not ignored, and appropriate countermeasures can be applied. Thus, it is easier and more effective to ensure the proper operation of the module.

[0019] In one embodiment, the detector is configured to: provide an output indicating that the module is connected to the bus in a first connection mode when the binary state of the first bit of the reference signal is the same as the binary state of the start bit of the received signal; and is configured to: provide an output indicating that the module is connected to the bus in a second connection mode when the binary state of the first bit of the reference signal is different from the binary state of the start bit of the received signal.

[0020] In another embodiment, the detector includes: a signal generator having a first input connected to a non-inverting terminal, a second input connected to an inverting terminal, and an output providing a voltage difference between the voltage of a signal received via the non-inverting terminal and the voltage of a signal received via the inverting terminal; and a signal processor: connected to the output of the signal generator; connected to the output of a transceiver providing the received signal; and configured to: determine a binary state of a first bit based on the voltage difference provided by the signal generator to the signal processor; compare the binary state of the first bit with the binary state of the corresponding start bit of the received signal; and provide an output indicating a connection mode determined by the signal processor based on the two binary states.

[0021] In another embodiment, the signal generator is a differential amplifier or includes a differential amplifier that provides a voltage corresponding to the voltage difference, the differential amplifier having a non-inverting input connected to a non-inverting terminal, an inverting input connected to an inverting terminal, and an output connected to a signal processor.

[0022] In another embodiment, the module includes at least one of the following: an indicator connected to the output of the detector; the indicator including at least one of: a single LED or a single red LED that illuminates when a second connection mode is detected; or two LEDs including a first LED or a green LED that illuminates when a first connection mode is detected and a second LED or a red LED that illuminates when a second connection mode is detected; a display showing the connection mode detected by the detector; and a signal output connected to the output of the detector and providing a connection mode signal indicating the connection mode detected by the detector.

[0023] In another embodiment, the module additionally includes a signal inverter, wherein the signal inverter is: inserted into a set of connection lines including connection lines connecting a non-inverting port to a non-inverting terminal and connection lines connecting an inverting port to an inverting terminal; configured such that when the signal inverter is disabled, a signal traveling along the connection lines in either direction of communication passes through the signal inverter without alteration; and configured such that when the signal inverter is enabled, a signal traveling along the connection lines in either direction of communication is inverted by the signal inverter.

[0024] In a first embodiment, the module includes a signal inverter inserted into a set of connection lines, the set of connection lines including connection lines connecting a non-inverting port to a non-inverting terminal and connection lines connecting an inverting port to an inverting terminal. The signal inverter is configured such that when the signal inverter is disabled, a signal traveling along the connection lines in either direction of communication passes through the signal inverter without alteration. The signal inverter is further configured such that, during the transmission of each communication signal transmitted when the signal inverter is enabled, the enabled signal inverter provides a signal to the non-inverting terminal corresponding to the inverted signal received from the non-inverting port of the transceiver, and provides a signal to the inverting terminal corresponding to the inverted signal received from the inverting port of the transceiver. The signal inverter is further configured such that, during the reception of each communication signal received when the signal inverter is enabled, the enabled signal inverter provides a signal to the non-inverting port of the transceiver corresponding to the inverted signal received from the non-inverting terminal, and provides a signal to the inverting port corresponding to the inverted signal received from the inverting terminal.

[0025] In another embodiment, the signal inverter is inserted into a set of connection lines including connection lines connecting a non-inverting port to a non-inverting terminal and connection lines connecting an inverting port to an inverting terminal; and the signal inverter is a switching system or includes a switching system configured to: operate with a first switch setting when the signal inverter is disabled, wherein the switching system connects the non-inverting terminal to the non-inverting port and the inverting terminal to the inverting port; and operate with a second switch setting when the signal inverter is enabled, wherein the switching system connects the non-inverting terminal to the inverting port and the inverting terminal to the non-inverting port.

[0026] In another embodiment, the signal inverter is inserted into a set of connection lines, including lines connecting a non-inverting port to a non-inverting terminal and lines connecting an inverting port to an inverting terminal. In this embodiment, the signal inverter includes two signal converters, each inserted into one of the two connection lines; when the signal inverter is enabled, both signal converters are enabled, and when the signal inverter is disabled, both signal converters are disabled. Each signal converter is configured such that a signal traveling through a disabled signal converter in either direction passes through that signal converter without alteration, and a signal traveling through an enabled signal converter in either direction is inverted as it passes through the signal converter, such that each non-inverted signal traveling through the signal converter is converted to a corresponding inverted signal, and vice versa.

[0027] In an embodiment of the first embodiment, the output of the detector is connected to the enable port of the signal inverter.

[0028] In another embodiment of the first embodiment, the module is configured to execute a startup routine, wherein the detector determines a connection mode when the signal inverter is disabled, and subsequently operates in one of two predetermined operating modes selected based on the detected connection mode; these operating modes include: a first operating mode selected when the connection mode detected during the startup routine is a first connection mode; and a second operating mode selected when the connection mode detected during the startup routine is a second connection mode, wherein the signal inverter is disabled in the first operating mode and the signal inverter is enabled in the second operating mode.

[0029] In another embodiment, the module includes an integrated circuit comprising a transceiver and a detector; or the integrated circuit comprises a transceiver, a detector, and a signal inverter; wherein the signal inverter is inserted into a set of connection lines including connection lines connecting a non-inverting port to a non-inverting terminal and connection lines connecting an inverting port to an inverting terminal, and is configured such that when the signal inverter is disabled, a signal traveling along the connection lines in either direction of communication passes through the signal inverter without alteration, and that when the signal inverter is enabled, a signal traveling along the connection lines in either direction of communication is inverted by the signal inverter.

[0030] In another embodiment, the transceiver is an RS-485 transceiver and / or a transceiver provided by a Universal Asynchronous Receiver / Transmitter (UART), or a transceiver including the UART.

[0031] The present invention further includes a field device comprising the disclosed module, the field device comprising: a device component provided by a sensor, measurement probe, measurement transducer or other type of measurement device for measuring at least one variable, or a device component provided by a valve, pump, stepper motor or other type of actuator, and device electronics connected to the device component; wherein the module is connected to the device electronics.

[0032] In one embodiment of the field device, the module’s processor is included in the device electronics, connected to the device electronics, or is a component shared by the module and the device electronics. Attached Figure Description

[0033] The described embodiments and other features, advantages, and disclosures contained herein, as well as the ways of obtaining these features, advantages, and disclosures, will become apparent, and the invention will be better understood by referring to the following description of various embodiments of the invention in conjunction with the accompanying drawings, in which:

[0034] Figure 1 A module for asynchronous differential serial communication is shown;

[0035] Figure 2 A module including a signal inverter is shown, which includes a switching system;

[0036] Figure 3 A module including a signal inverter is shown, which includes a signal converter;

[0037] Figure 4 The steps for transmitting communication signals are shown;

[0038] Figure 5 The steps for receiving communication signals are shown;

[0039] Figure 6 This illustrates the use of a connection in a second connection mode. Figure 1 The steps for the module shown to receive communication signals;

[0040] Figure 7 The steps for detecting the first connection mode are shown;

[0041] Figure 8 The steps for detecting the second connection mode are shown;

[0042] Figure 9 The field equipment is shown; and

[0043] Figure 10 The field devices and upper-level units connected to the bus are shown. Detailed Implementation

[0044] The present invention includes a module for asynchronous differential serial communication on bus 1 and a field device including the module. Figure 1 , Figure 2 and Figure 3 An example of the module and bus 1 connected to each module is shown.

[0045] As shown in the figure, bus 1 includes two signal lines BS. One of the two signal lines BS is a non-inverting bus signal line B+ used to transmit the non-inverting signal S+. The other is an inverting bus signal line B- used to transmit the inverting signal S-. Optionally, bus 1 may additionally include a reference line BR, also known as a signal sharing line, which provides a reference potential and is shared by all devices connected to the same bus 1.

[0046] Each of the disclosed modules includes a processor 3, a transceiver 5 connected to the processor 3, and a terminal block for connecting the module to bus 1.

[0047] The terminal block includes a reference terminal TR that is connected to or can be connected to a reference potential, and two signal terminals comprising a non-inverting terminal T+ and an inverting terminal T-. Optionally, and particularly advantageously, when communication signals are transmitted over long distances, the reference terminal TR can be connected to or can be connected to a reference line BR providing the reference potential on bus 1. This option provides better communication stability and reduces sensitivity to electromagnetic interference.

[0048] Each of the two signal terminals can be connected to either of the two signal lines BS of bus 1. Therefore, two different connection modes for connecting the module to bus 1 are possible. In the first connection mode, the module's non-inverting terminal T+ is connected to the non-inverting bus signal line B+, and the inverting terminal T- is connected to the inverting bus signal line B-. In the second connection mode, the non-inverting terminal T+ is connected to the inverting bus signal line B-, and the inverting terminal T- is connected to the non-inverting bus signal line B+.

[0049] The processor 3 is configured to provide a transmit signal Tx to be transmitted by the transceiver 5 to the bus 1, and to receive a receive signal Rx determined by the transceiver 5 based on the communication signals received from the bus 1 by the module.

[0050] Transceiver 5 is implemented to transmit a communication signal corresponding to the transmit signal Tx provided by processor 3 onto bus 1. Due to the application of asynchronous communication, each transmit signal Tx includes a start bit with a predetermined binary state for communication on bus 1. The corresponding communication signal provided by transceiver 5 each includes two complementary signals S. One complementary signal is a non-inverted signal S+ corresponding to the transmit signal Tx. The other is an inverted signal S- corresponding to the inverted transmit signal Tx.

[0051] Transceiver 5 is implemented to: receive communication signals from bus 1; determine a corresponding received signal Rx based on the voltage difference ΔV between the voltages V(S+) and V(S-) of two received complementary signals S; and provide the thus determined received signal Rx to processor 3. Transceiver 5 is further configured to determine and provide each received signal Rx such that the received signal includes a start bit having a predetermined binary state specified for communication on bus 1.

[0052] Alternatively, the transmit signal Tx and the receive signal Rx may be additionally included in at least one stop bit after the data frame.

[0053] As an example, transceiver 5 may be a transceiver comprising a driver D and a separate receiver R, the driver driving a voltage on a bus signal line BS connected to transceiver 5 during transmission, and the separate receiver reading the voltage on the bus signal line BS connected to transceiver 5 during reception. Alternatively, transceiver 5 may be implemented as a single component (e.g., a modem) to perform the functions of both driver D and receiver R.

[0054] As an option, transceiver 5 may be, for example, an RS-485 transceiver. RS-485 transceivers are designed according to the RS-485 standard, also known as TIA-485(-A) or EIA-485, jointly published by the Telecommunications Industry Association and the Electronic Industries Alliance (TIA / EIA). This standard is widely recognized in industry, and corresponding transceivers are available on the market. As an additional or alternative option, the transceiver may be, for example, a transceiver provided by a Universal Asynchronous Receiver / Transmitter (UART), or may include a UART.

[0055] Transceiver 5 includes a non-inverting port P+ and an inverting port P-, each port being connected to one of the two signal terminals of the module. Additionally, the reference port Pref of transceiver 5 is connected to the reference terminal TR, for example, via the reference line Lref.

[0056] The transmission of each communication signal is performed by transceiver 5 providing a non-inverted signal S+ corresponding to the transmit signal Tx via its non-inverting port P+, and by transceiver 5 providing an inverted signal S- corresponding to the inverted phase of the transmit signal Tx via its inverting port P-. When the module is connected to bus 1, the transmission of communication signals is performed by transceiver 5's driver D providing the non-inverted signal S+ and the inverted signal S- to the signal terminals connected to transceiver 5, thereby driving the voltage on the signal line BS of bus 1 connected to the signal terminals accordingly.

[0057] exist Figure 1 In the example shown, the module is connected to bus 1 in a first connection mode. Additionally, the non-inverting port P+ of transceiver 5 is connected to the non-inverting terminal T+, and the inverting port P- is connected to the inverting terminal T-. Therefore, in this example, transmission is performed by driver D driving the voltage on the non-inverting bus signal line B+ connected to the non-inverting terminal T+ according to the non-inverting signal S+, and driving the voltage on the inverting bus signal line B- connected to the inverting terminal T- according to the inverting signal S-. This is... Figure 4 The example illustration is based on the transmit signal Tx shown on the left-hand side. The transmit signal Tx is illustrated in the form of a sequence of logic levels representing the digital data to be transmitted. In the example shown, positive logic is applied. Therefore, binary 1 is represented by a high logic level H, and binary 0 is represented by a low logic level L. The transmit signal Tx begins with a start bit having a predetermined binary state (e.g., ...). Figure 4 The data frame shown begins with a binary 0 and is followed by a data frame consisting of at least one bit or sequence of data bits. In the example shown, the data frame includes... Figure 4 The data bit sequence shown is [1, 1, 0, 1].

[0058] like Figure 4As indicated, driver D provides a non-inverted signal S+ to bus 1 via the non-inverted port P+ of transceiver 5 connected to the non-inverted bus line B+, and driver D provides an inverted signal S- to bus 1 via the inverted port P- of transceiver 5 connected to the inverted bus line B-.

[0059] The voltage V(S+) of the non-inverting signal S+ and the voltage V(S-) of the inverting signal S- provided by driver D are in Figure 4 It is shown on the right-hand side. In this example, transceiver 5 is implemented such that during the transmission of the non-inverting signal S+, the voltage V(S+) is at a low voltage level V. LA Furthermore, the voltage V(S-) of the inverted signal S- is at a high voltage level V. HB During the transmission of the high logic level H, the voltage V(S+) of the non-inverting signal S+ is at a high voltage level V. HA Furthermore, the voltage V(S-) of the inverted signal S- is at a low voltage level V. LB In this case, the voltage V(S+) of the non-inverting signal S+ corresponds to the logic level of the transmitted signal Tx.

[0060] The disclosed invention is not limited to this type of transceiver 5. As an alternative, an inverting transceiver can be used instead of transceiver 5, which is configured such that during transmission at a low logic level L, the voltage of the non-inverted signal is at a high voltage level and the voltage of the inverted signal is at a low voltage level; and configured such that during transmission at a high logic level H, the voltage of the non-inverted signal is at a low voltage level and the voltage of the inverted signal is at a high voltage level. In this case, the voltage of the non-inverted signal corresponds to the inversion of the logic level of the transmitted signal Tx.

[0061] In the opposite communication direction, transceiver 5 is configured, for example, to begin receiving communication signals from bus 1 each time at a start time t0 determined by transceiver 5. As an example, the start time t0 corresponds, for example, to the time when the absolute value of the voltage difference ΔV between the voltage of the signal received via the non-inverting port P+ and the voltage of the signal received via the inverting port P- exceeds a predetermined threshold.

[0062] After the start time t0, transceiver 5 determines the received signal Rx based on the voltage difference ΔV between the voltage of the signal received via its non-inverting port P+ and the voltage of the signal received via its inverting port P-. As described above, transceiver 5 is configured to determine and provide each received signal Rx such that the received signal begins with a start bit having a predetermined binary state specified for communication on bus 1. Figure 5 The diagram illustrates the reception of communication signals, based on... Figure 1In the example shown, the module is connected to bus 1 in a first connection mode, and the non-inverting port P+ of transceiver 5 is connected to the non-inverting terminal T+, and the inverting port P- is connected to the inverting terminal T-. Therefore, in receiving... Figure 5 During the communication signal period shown on the left-hand side, transceiver 5 receives the non-inverted signal S+ via its non-inverting port P+ and the inverted signal S- via its inverting port P-.

[0063] The voltage difference ΔV obtained by subtracting the voltage V(S-) of the inverted signal S- received via the inverting port P- from the voltage V(S+) of the non-inverted signal S+ received via the non-inverting port P+ is... Figure 5 The voltage difference ΔV is shown on the right-hand side of the receiver R. It increases at the same time point as the voltage V(S+) of the received non-inverting signal S+, and decreases at the same time point as the voltage V(S+) of the received non-inverting signal S+. Therefore, in the first connection mode, the binary state of the first received bit determined based on the voltage difference ΔV is equal to the binary state predetermined for the start bit. Thus, this start bit is recognized as a valid bit by the transceiver 5, and the received signal Rx provided by the transceiver 5 begins with this valid start bit.

[0064] exist Figure 5 In the middle, the complementary signal received from bus 1 and Figure 4 The non-inverting signal S+ and the inverting signal S- shown on the right-hand side are the same. Therefore, the received signal Rx determined by transceiver 5 based on the voltage difference ΔV is the same as... Figure 4 The transmitted signal Tx shown on the left side is the same.

[0065] Figure 6 It shows receiving from bus 1 Figure 5 The communication signals shown are Figure 1 Another example of the module shown. This example is related to... Figure 5 The only difference in the example shown is that Figure 1 The module shown is connected to bus 1 in the second connection mode. Therefore, in Figure 6 In this module, the non-inverting terminal T+ is connected to the inverting bus signal line B-, and the inverting terminal T- is connected to the non-inverting bus signal line B-. Therefore, transceiver 5 receives the non-inverting signal S+ via its inverting port P- connected to the inverting terminal T-, and transceiver 5 receives the inverting signal S- via its non-inverting port P+ connected to the non-inverting terminal T+.

[0066] therefore, Figure 6The voltage difference ΔV' shown on the right-hand side of transceiver R is determined by subtracting the voltage V(S+) of the non-inverted signal S+ received via the inverting port P- from the voltage V(S-) of the inverted signal S- received via the non-inverting port P+. Therefore, the voltage difference ΔV' obtained in the second connection mode corresponds to the inverse of the voltage difference ΔV obtained in the first connection mode. Thus, during the reception of the same communication signal from bus 1, each bit that can be determined based on the voltage difference ΔV' determined in the second connection mode has a binary state that is the inverse of the binary state of the corresponding bit that can be determined based on the voltage difference ΔV determined in the first connection mode.

[0067] Similar to the previous example, the reception of the communication signal also begins at a start time t0 corresponding to the time when the absolute value of the voltage difference ΔV' exceeds the threshold. Therefore, the same start time t0 is determined regardless of when the module... Figure 5 The first connection mode shown is still based on Figure 6 The second connection mode is shown.

[0068] When the module is Figure 6 When connected in the second connection mode shown, the first receive bit, which can be determined based on the voltage difference ΔV' within a first time interval starting from the start time t0, has a binary state opposite to the predetermined binary state specified for communication on bus 1. Therefore, the first receive bit is not recognized as a valid start bit by the transceiver 5. Nevertheless, the transceiver 5 is configured to provide a receive signal Rx such that the receive signal begins with a start bit having the predetermined binary state.

[0069] Figure 6 The diagram illustrates two examples of how transceiver 5 can determine the received signal Rx such that the received signal begins with a start bit having a predetermined binary state. In the first example, transceiver 5 adds a start bit with a predetermined binary state, which is followed by a sequence of bits determined based on the voltage difference ΔV'. The resulting received signal Rx1 is... Figure 6 The diagram shows the voltage difference ΔV' above the voltage level. In this case, the received signal Rx1 begins with the added start bit, followed by the first received bit. In the second example, transceiver 5 is configured to interpret the first received bit as a start bit, regardless of its binary state. The resulting received signal Rx2 is... Figure 6 This is shown below the voltage difference ΔV'. In this case, the received signal Rx2 begins with a start bit having a predetermined binary state, followed by the second received bit. In this received signal Rx2, the binary state of the start bit is the inverse of the binary state of the first received bit. Figure 6 The two received signals Rx1 and Rx2 shown do not correspond to the received signal Rx, but the transceiver 5 provides this signal if the module is connected in the first connection mode.

[0070] When using an inverting transducer in a modern replacement transducer, the interpretation of the received signal Rx is applied in the same way. The only difference is that the conversion of voltage differences ΔV, ΔV' to logic levels is inverted. While the original transducer interprets high voltage differences ΔV, ΔV' as binary 1 and low voltage differences ΔV, ΔV' as binary 0, this inverting transducer interprets high voltage differences ΔV, ΔV' as binary 0 and low voltage differences ΔV, ΔV' as binary 1.

[0071] The module further includes a detector 7, which is configured to determine a connection mode when the module is connected to bus 1 during the reception of a communication signal, and to provide an output Out indicating the detected connection mode. In this case, detector 7 is configured to determine the connection mode based on the binary state of the start bit of the received signal Rx provided by transceiver 5 based on the received communication signal and the binary state of the first bit A of the reference signal Sref. The reference signal Sref is a signal corresponding to the voltage difference VR between the voltage of the signal received via the non-inverting terminal T+ of the module and the voltage of the signal received via the inverting terminal T- of the module during the reception of the same communication signal.

[0072] When the module is connected in the first connection mode, the signal received via the non-inverting terminal T+ is the non-inverting signal S+ received from the non-inverting bus line B+, and the signal received via the inverting terminal T- is the inverted signal S- received from the inverting bus line B-. In this case, the voltage difference VR between the voltage of the signal received via the non-inverting terminal T+ and the voltage of the signal received via the inverting terminal T- is given by the following formula: VR:=V(S+)-V(S-), and therefore corresponds to the non-inverting signal S+. Therefore, the binary state of the first bit A of the reference signal Sref corresponding to the voltage difference VR is equal to the predetermined binary state of the start bit of the transmitted signal, which is transmitted to bus 1 in the form of a communication signal received during detection. Therefore, the binary state of the first bit A is equal to the binary state of the start bit of the corresponding received signal Rx. This situation occurs in... Figure 7 The accompanying diagram illustrates, as shown in... Figure 5 The voltage difference VR obtained in the first connection mode during the reception of the communication signal is shown, along with the corresponding reference signal Sref starting with the first bit A.

[0073] When the module is connected in the second connection mode, the signal received via the non-inverting terminal T+ is the inverted signal S- received from the inverting bus signal line B-. In this case, the voltage difference VR between the voltage of the signal received via the non-inverting terminal T+ and the voltage of the signal received via the inverting terminal T- is given by the following formula: VR:=V(S-)-V(S+), and therefore corresponds to the inverted signal S-. As a result, the binary state of the first bit A of the reference signal Sref corresponding to the voltage difference VR is equal to the inversion of the predetermined binary state of the start bit of the transmitted signal, which is transmitted to bus 1 in the form of a communication signal received during detection. Therefore, the binary state of the first bit A and the binary state of the corresponding start bit of the received signal Rx are different. This situation occurs in... Figure 8 The accompanying diagram illustrates, as shown in... Figure 6 The voltage difference VR obtained in the second connection mode during the reception of the communication signal is shown, along with the corresponding reference signal Sref starting with the first bit A.

[0074] As an option, detector 7 may be configured, for example, to provide an output Out indicating a first connection mode when the two binary states are the same, and / or to provide an output Out indicating a second connection mode when the two binary states are different.

[0075] Detector 7 can be implemented in various ways, such that it determines the connection mode based on the binary state of the first bit of the reference signal Sref and the binary state of the start bit of the corresponding received signal Rx, both of which are determined during the reception of the same communication signal from bus 1.

[0076] Figure 1 , Figure 2 and Figure 3 Each is illustrated with the following example: Detector 7 includes a signal generator 9 having a first input connected to a non-inverting terminal T+, a second input connected to an inverting terminal T-, and an output providing the voltage difference VR between the voltage of the signal received via the non-inverting terminal T+ and the voltage of the signal received via the inverting terminal T-. As an example, signal generator 9 is, for instance, composed of... Figure 1 , Figure 2 and Figure 3 The differential amplifier shown in the triangle diagram provides or includes this differential amplifier. In this case, the first input of the signal generator 9 is given by the non-inverting input of the differential amplifier, the second input of the signal generator 9 is given by the inverting input of the differential amplifier, and the voltage corresponding to the voltage difference VR is given by the output of the differential amplifier.

[0077] Figure 1 , Figure 2 and Figure 3The detector 7 shown further includes a signal processor 11 connected to the output of the signal generator 9 and the output of the transceiver 5, the output of which provides the received signal Rx determined by the transceiver 5. The signal processor 11 is configured to: determine the binary state of the first bit A of the reference signal Sref based on the voltage difference VR provided by the signal generator 9; compare the binary state of the first bit A with the binary state of the start bit of the corresponding received signal Rx; and provide an output Out indicating the connection mode determined based on these two binary states.

[0078] As such Figure 1 and Figure 3 As shown in the options, the signal processor 11 is implemented as a separate component, such as a microprocessor, which is connected to the signal generator 9 and the transceiver 5. As such Figure 2 As shown in the alternative, signal processor 11 is included or embedded in processor 3.

[0079] The present invention provides the advantages described above. The various components of this module can be implemented in different ways without departing from the scope of the invention.

[0080] As an example, the indicator module of detector 7 can be connected to the bus output Out in one or more different ways, whether in the first connection mode or the second connection mode.

[0081] exist Figure 1 In the example shown, the output Out of detector 7 is connected, for example, to indicator 13, which is located outside the module and indicates the detected connection mode determined by detector 7. As an example, indicator 13 includes, for example, a single LED 15, such as a red LED, which illuminates when a second connection mode is detected. As another example, indicator 13 includes, for example, two LEDs 15, such as a first LED and a second LED, where the first LED is, for example, a green LED and illuminates when a first connection mode is detected, and the second LED is, for example, a red LED and illuminates when a second connection mode is detected. As an additional or alternative option, indicator 13 includes, for example, a display 17 that displays the connection mode detected by detector 7.

[0082] Indicator 13 provides the advantage that, upon receiving a communication signal, it immediately notifies the technician connecting the module to bus 1 of the connection mode. This provides the advantage that undesirable connection modes are not overlooked, and that appropriate remedies can be applied and performed by the technician while the technician is still on-site.

[0083] As also Figure 1As shown in the additional or alternative options, the output Out of detector 7, indicating the detected connection mode, is provided, for example, via signal output 19 connected to the output Out of detector 7, in the form of a connection mode signal CM. This provides the advantage that information about the connection mode can be easily provided to devices, such as service tools used by technicians and / or devices located in remote locations. In this case, the connection mode signal CM is transmitted to the corresponding device, for example, via a wireless or hardwired connection, to connect the corresponding device to signal output 19.

[0084] As an option, combine Figure 1 The described indicator 13 and / or signal output 19 are also, for example, in Figure 2 and Figure 3 The module shown is foreseen.

[0085] Regardless of whether the module includes indicator 13 and / or signal output 19, its functionality can be further enhanced by additionally including signal inverters 21 and 23, which are inserted into a set of connection lines including connection line 25 connecting the non-inverting port P+ to the non-inverting terminal T+ and connection line 27 connecting the inverting port P- to the non-inverting terminal T-. Examples are provided in... Figure 2 and Figure 3 As shown in the image.

[0086] These signal inverters 21 and 23 are each configured such that when the signal inverters 21 and 23 are disabled, the signal traveling along the connection lines 25 and 27 in either direction of communication through the signal inverters 21 and 23 passes through the signal inverters 21 and 23 without alteration.

[0087] Furthermore, signal inverters 21 and 23 are each configured such that when signal inverters 21 and 23 are enabled, signals traveling along connection lines 25 and 27 in either direction of communication through signal inverters 21 and 23 are inverted by signal inverters 21 and 23.

[0088] For example, signal inversion is performed such that during the transmission of each communication signal when signal inverters 21 and 23 are enabled, the enabled signal inverters 21 and 23 provide a signal to the non-inverting terminal T+ corresponding to the inverted signal received from the non-inverting port P+ of the transceiver 5, and provide a signal to the inverting terminal T- of the module corresponding to the inverted signal received from the inverting port P- of the transceiver 5. During the reception of each communication signal when signal inverters 21 and 23 are enabled, the enabled signal inverters 21 and 23 provide a signal to the non-inverting port P+ of the transceiver 5 corresponding to the inverted signal received from the non-inverting terminal T+, and provide a signal to the inverting port P- of the transceiver 5 corresponding to the inverted signal received from the inverting terminal T-.

[0089] Regarding signal inverters 21 and 23, any type of inverter can be applied, which is suitable for performing the required inversion in both communication directions.

[0090] Figure 2 An example is shown where the signal inverter 21 is or includes a switching system 29 inserted into connection lines 25, 27 that connect the transceiver 5 to signal terminals. The switching system 29 is configured to operate in a first switching setting when the signal inverter 21 is disabled. In the first switching setting, the switching system 29 connects the non-inverting terminal T+ to the non-inverting port P+ of the transceiver 5 and connects the inverting terminal T- to the inverting port P- of the transceiver 5. Furthermore, the switching system 29 is configured to operate in a second switching setting when the signal inverter 21 is enabled. In the second switching setting, the switching system 29 connects the module's non-inverting terminal T+ to the inverting port P- of the transceiver 5 and connects the module's inverting terminal T- to the non-inverting port P+ of the transceiver 5.

[0091] Figure 3 An alternative embodiment is shown, wherein the signal inverter 23 includes two signal converters 31. Each signal converter 31 is inserted into one of the two connection lines 25, 27. When the signal inverter 23 is enabled, both signal converters 31 are enabled, and when the signal inverter 23 is disabled, both signal converters are disabled. Furthermore, each signal converter 31 is configured such that when a signal converter 31 is disabled, a signal traveling through the corresponding signal converter 31 in either direction passes through the signal converter 31 without alteration. Additionally, each signal converter 31 is configured such that a signal traveling through the corresponding signal converter 31 in either direction is inverted as it passes through the corresponding signal converter 31, such that each non-inverted signal S+ traveling through the signal converter 31 is converted to a corresponding inverted signal S-, and vice versa.

[0092] As an option for use with a module including signal inverters 21 and 23, the module may, for example, be configured to execute a startup routine in which detector 7 determines a connection mode when signal inverters 21 and 23 are disabled, and is configured to subsequently operate in one of two predetermined operating modes selected based on the detected connection mode. These two operating modes include a first operating mode and a second operating mode, selected when the detected connection mode during the startup routine is the first connection mode, and selected when the detected connection mode during the startup routine is the second connection mode. In the first operating mode, signal inverters 21 and 23 remain disabled. In the second operating mode, signal inverters 21 and 23 are enabled.

[0093] In the first operating mode, the disabled signal inverters 21 and 23 have no effect on the bidirectional communication performed by the module. Therefore, when the module is connected in the first connection mode, during the operation of the module in the first operating mode, the bidirectional communication performed by the module is... Figure 2 and Figure 3 The modules shown are in conjunction with the above. Figure 4 and Figure 5 The same way of describing Figure 1 The module shown performs bidirectional communication.

[0094] In the second operating mode, signal inverters 21 and 23 are enabled. Due to the signal inversion performed by the enabled signal inverters 21 and 23, when the module is connected in the second connection mode and signal inverters 21 and 23 are enabled, the signals received by the transceiver 5 via the non-inverting port P+ and via the inverting port P- are respectively the same as the signals received by the transceiver 5 via the corresponding ports if the module is connected in the first connection mode and signal inverters 21 and 23 are disabled. In the opposite communication direction, during the transmission of communication signals, when the module is connected in the second connection mode and signal inverters 21 and 23 are enabled, the signals provided to the non-inverting terminal T+ and the inverting terminal T- are respectively the same as the signals provided to the corresponding signal terminals if the module is connected in the first connection mode and signal inverters 21 and 23 are disabled.

[0095] Modules configured to automatically select an operating mode based on the connection mode determined by detector 7 during the startup routine and subsequently operate in the selected operating mode offer the additional advantage of always operating correctly regardless of whether the module is connected in the first or second connection mode. This provides the advantage that it is no longer necessary to determine the specific wiring pattern required to implement a particular connection mode, and it is impossible to connect the module in a connection mode that would lead to communication failure.

[0096] Optionally, the output Out of detector 7, which determines the connection mode during the startup routine, can be connected, for example, to the enable port of signal inverters 21 and 23. In this case, signal inverters 21 and 23 are configured such that the output Out provided by detector 7 during the startup routine is enabled when the detected connection mode is the second connection mode, and remains disabled when the detected connection mode is the first connection mode.

[0097] As an alternative, the output Out of detector 7 may be provided, for example, to a controller—not shown—which selects an operating mode based on the detected connection mode and accordingly enables or disables signal inverters 21, 23.

[0098] As an additional or alternative option, transceiver 5 and detector 7 are implemented, for example, as components comprising a single integrated circuit (IC) of each of these components. When the module additionally includes signal inverters 21 and 23, transceiver 5, detector 7, and signal inverters 21 and 23 are implemented, for example, as components comprising a single integrated circuit (IC) of each of these components. The corresponding integrated circuit (IC) is... Figure 1 and Figure 3 The dotted lines indicate this. Each of these integrated circuits (ICs) offers the advantage of reducing module manufacturing costs when producing large quantities of modules.

[0099] Another advantage is that, due to the smaller size of the integrated circuit (IC), less space is required inside the module to accommodate the transceiver 5, detector 7, and optional signal inverters 21 and 23. This allows for a corresponding reduction in the overall module size. The smaller module size is particularly advantageous when the module is to be implemented in a field device.

[0100] Examples of field devices in Figure 9 As shown in the diagram. The field device includes device component 33, device electronics 35 connected to device component 33, and module 37, such as... Figure 1 , Figure 2 and Figure 3 One of the modules shown. In the field device, the processor 3, which provides the transmit signal Tx and receives the receive signal Rx, is included in or connected to the device electronics 35, for example. Figure 9 The following example is shown: where processor 3 is a component shared by module 37 and device electronics 35.

[0101] Device component 33 may be, for example, a measuring device, such as a sensor, measuring probe, measuring transducer, or other type of measuring device that measures at least one variable. Device component 33 may be an actuator, such as a valve, pump, stepper motor, or other type of actuator, for example, an actuator applied to affect the operation of a site or facility and / or affect a process performed at, on, or by a site or facility.

[0102] Module 37 enables field devices to communicate via bus 1, which is connected to or can be connected to the terminals of module 37. Figure 10 An example of the application is shown, in which multiple field devices FD and a super-level unit 39 are connected to the same bus 1. The multiple field devices FD are located at dispersed locations in the site, for example, at various different locations distributed throughout the site, and each super-level unit 39 includes a module 37 for asynchronous differential serial communication.

[0103] In this application, module 37 of the field device FD enables each field device FD to communicate with at least one other field device FD and / or a higher-level unit 39 connected to the same bus 1. As an example, the higher-level unit 39 is, for example, a control unit, an automation system, or a programmable logic controller that implements monitoring, regulating, and / or controlling field operations and / or at least one process performed at, on, or by the field. As an example, a valve included in one of the field device FDs can be opened or closed by the higher-level unit 39 based on a physical variable such as pressure, temperature, or level, which is measured by another field device FD based on corresponding communication signals (e.g., measurement signals and / or control signals) transmitted via bus 1.

Claims

1. A module for asynchronous differential serial communication on a bus, the module comprising: A processor, a transceiver connected to the processor, and a terminal block connected to the transceiver; The terminal group includes a reference terminal that is connected to or can be connected to a reference potential, and further includes two signal terminals comprising a non-inverting terminal and an inverting terminal; The transceiver is configured to transmit communication signals corresponding to the transmit signals provided by the processor. Each communication signal includes a start bit having a predetermined binary state for communication on the bus. The transceiver includes a non-inverting port and further includes an inverting port. The non-inverting port is connected to one of the signal terminals that provides a non-inverted signal corresponding to the transmitted signal, and the inverting port is connected to the other of the signal terminals that provides an inverted signal corresponding to the inversion of the transmitted signal. The transceiver is configured to receive communication signals, and during the reception of a corresponding communication signal, determines a corresponding received signal based on the voltage difference between the voltage of the signal received via the non-inverting port of the transceiver and the voltage of the signal received via the inverting port of the transceiver, such that each received signal includes a start bit having a predetermined binary state. The module can be connected to the bus in two different connection modes, including a first connection mode and a second connection mode. In the first connection mode, the non-inverting terminal is connected to the non-inverting bus signal line of the bus, and the inverting terminal is connected to the inverting bus signal line of the bus. In the second connection mode, the non-inverting terminal is connected to the inverting bus signal line, and the inverting terminal is connected to the non-inverting bus signal line. The module further includes a detector configured to: determine the connection mode based on the binary state of the start bit of the received signal provided by the transceiver based on the communication signal received when the module is connected to the bus and the binary state of the first bit of a reference signal, and provide an output indicating the detected connection mode, wherein the reference signal corresponds to the voltage difference between the voltage of the signal received via the non-inverting terminal and the voltage of the signal received via the inverting terminal during the reception of the same communication signal.

2. The module according to claim 1, wherein, The detector is configured to: provide an output instructing the module to connect to the bus in the first connection mode when the binary state of the first bit of the reference signal is the same as the binary state of the start bit of the received signal; and is configured to: provide an output instructing the module to connect to the bus in the second connection mode when the binary state of the first bit of the reference signal is different from the binary state of the start bit of the received signal.

3. The module according to claim 1, wherein, The detector includes: A signal generator having a first input connected to the non-inverting terminal, a second input connected to the inverting terminal, and an output providing the voltage difference between the voltage of a signal received via the non-inverting terminal and the voltage of the signal received via the non-inverting terminal; and A signal processor connected to the output of the signal generator and to the output of the transceiver providing the received signal, wherein the signal processor is configured to: determine the binary state of the first bit based on a voltage difference provided by the signal generator to the signal processor; compare the binary state of the first bit with the binary state of the corresponding start bit of the received signal; and provide an output indicating a connection mode determined by the signal processor based on the two binary states.

4. The module according to any one of claims 1-3, wherein, The signal generator is a differential amplifier or includes a differential amplifier that provides a voltage corresponding to the voltage difference. The differential amplifier has a non-inverting input connected to the non-inverting terminal, an inverting input connected to the inverting terminal, and an output connected to the signal processor.

5. The module according to any one of claims 1-3, further comprising at least one of the following: An indicator connected to the output of the detector; the indicator includes at least one of the following: a single LED or two LEDs, the single LED illuminating when the second connection mode is detected, the two LEDs including a first LED illuminating when the first connection mode is detected, and a second LED illuminating when the second connection mode is detected; A display showing the connection pattern detected by the detector; as well as A signal output is provided, which is connected to the output of the detector and provides a connection mode signal indicating the connection mode detected by the detector.

6. The module according to claim 5, wherein, The single LED is a single red LED.

7. The module according to claim 5, wherein, The first LED is a green LED and the second LED is a red LED.

8. The module according to any one of claims 1-3, further comprising: Signal inverter, wherein the signal inverter: Inserted into a set of connection lines, the set of connection lines including connection lines connecting the non-inverting port to the non-inverting terminal and connection lines connecting the inverting port to the inverting terminal; Configured such that when the signal inverter is disabled, a signal traveling along the connection line through the signal inverter in either direction of communication passes through the signal inverter without alteration; and It is configured such that when the signal inverter is enabled, signals traveling along the connection line in either direction of communication through the signal inverter are each inverted by the signal inverter.

9. The module according to any one of claims 1-3, further comprising: A signal inverter, which is inserted into a connection line that connects the non-inverting port to the non-inverting terminal and the connection line that connects the inverting port to the inverting terminal; The signal inverter is configured such that when the signal inverter is disabled, a signal traveling along the connection line in either direction of communication through the signal inverter passes through the signal inverter without alteration. The signal inverter is further configured such that, during the transmission of each communication signal transmitted when the signal inverter is enabled, the enabled signal inverter provides the non-inverting terminal with a signal corresponding to the inversion of the signal received from the non-inverting port of the transceiver, and provides the inverting terminal with a signal corresponding to the inversion of the signal received from the inverting port of the transceiver; and The signal inverter is further configured such that during the reception of each communication signal received when the signal inverter is enabled, the enabled signal inverter provides a signal to the non-inverting terminal of the transceiver that corresponds to the inversion of the signal received from the non-inverting port, and provides a signal to the inverting terminal that corresponds to the inversion of the signal received from the inverting port.

10. The module according to any one of claims 1-3, further comprising: A signal inverter, which is inserted into a connection line that connects the non-inverting port to the non-inverting terminal and the connection line that connects the inverting port to the inverting terminal; The signal inverter is a switching system or includes a switching system configured to: operate with a first switch setting when the signal inverter is disabled, wherein the switching system connects the non-inverting terminal to the non-inverting port and the inverting terminal to the inverting port; and operate with a second switch setting when the signal inverter is enabled, wherein the switching system connects the non-inverting terminal to the inverting port and the inverting terminal to the non-inverting port.

11. The module according to any one of claims 1-3, further comprising: A signal inverter, which is inserted into a connection line that connects the non-inverting port to the non-inverting terminal and the connection line that connects the inverting port to the inverting terminal. The signal inverter includes two signal converters, each of which is inserted into one of the two connection lines. Specifically, when the signal inverter is enabled, both signal converters are enabled, and when the signal inverter is disabled, both signal converters are disabled. Each signal converter is configured such that a signal traveling through a disabled signal converter in either direction passes through the signal converter without alteration, and a signal traveling through an enabled signal converter in either direction is inverted as it passes through the signal converter, such that each non-inverted signal traveling through the signal converter is converted to a corresponding inverted signal, and vice versa.

12. The module according to claim 8, wherein, The detector's output is connected to the enable port of the signal inverter.

13. The module according to claim 8, in, The module is configured to execute a startup routine, wherein the detector determines the connection mode when the signal inverter is disabled, and is further configured to subsequently operate in one of two predetermined operating modes selected based on the detected connection mode; and The two predetermined operating modes include a first operating mode selected when the connection mode detected during the startup routine is the first connection mode, and a second operating mode selected when the connection mode detected during the startup routine is the second connection mode. In the first operating mode, the signal inverter is disabled, and in the second operating mode, the signal inverter is enabled.

14. The module according to any one of claims 1-3, further comprising: An integrated circuit, the integrated circuit including the transceiver and the detector, or including the transceiver, the detector and a signal inverter; The signal inverter is inserted into a connection line that connects the non-inverting port to the non-inverting terminal and a connection line that connects the inverting port to the inverting terminal. The signal inverter is configured such that when the signal inverter is disabled, a signal traveling along the connection line in either direction of communication passes through the signal inverter without alteration, and that when the signal inverter is enabled, signals traveling along the connection line in either direction of communication are inverted by the signal inverter.

15. The module according to any one of claims 1-3, wherein, The transceiver is an RS-485 transceiver and / or a transceiver provided by a Universal Asynchronous Receiver / Transmitter (UART), or a transceiver that includes the Universal Asynchronous Receiver / Transmitter (UART).

16. A field device, comprising: A module for asynchronous differential serial communication on a bus, the module comprising: A processor, a transceiver connected to the processor, and a terminal group connected to the transceiver; the terminal group includes a reference terminal connected to or capable of being connected to a reference potential, and further includes two signal terminals comprising a non-inverting terminal and an inverting terminal; The transceiver is configured to transmit communication signals corresponding to the transmit signals provided by the processor. Each communication signal includes a start bit having a predetermined binary state for communication on the bus. The transceiver includes a non-inverting port and further includes an inverting port. The non-inverting port is connected to one of the signal terminals that provides a non-inverted signal corresponding to the transmitted signal, and the inverting port is connected to the other of the signal terminals that provides an inverted signal corresponding to the inversion of the transmitted signal. The transceiver is configured to receive communication signals, and during the reception of a corresponding communication signal, determines a corresponding received signal based on the voltage difference between the voltage of the signal received via the non-inverting port of the transceiver and the voltage of the signal received via the inverting port of the transceiver, such that each received signal includes a start bit having a predetermined binary state. The module can be connected to the bus in two different connection modes, including a first connection mode and a second connection mode. In the first connection mode, the non-inverting terminal is connected to the non-inverting bus signal line of the bus, and the inverting terminal is connected to the inverting bus signal line of the bus. In the second connection mode, the non-inverting terminal is connected to the inverting bus signal line, and the inverting terminal is connected to the non-inverting bus signal line. The module further includes a detector configured to: determine the connection mode based on the binary state of the start bit of the received signal provided by the transceiver based on the communication signal received when the module is connected to the bus and the binary state of the first bit of a reference signal, and provide an output indicating the detected connection mode, wherein the reference signal corresponds to the voltage difference between the voltage of the signal received via the non-inverting terminal and the voltage of the signal received via the inverting terminal during the reception of the same communication signal; Equipment components, provided by sensors, measuring probes, measuring transducers or other types of measuring devices that measure at least one variable, or provided by valves, pumps, stepper motors or other types of actuators; and Equipment electronics, which are connected to the equipment components; The module is connected to the electronic components of the device.

17. The field device according to claim 16, wherein, The processor of the module is included in the device electronics, connected to the device electronics, or is a component shared by the module and the device electronics.

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