Can bus transmitter

Abstract

A CAN bus transmitter has inputs for receiving transmitted data signals, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter includes multiple CAN driver circuits with inputs coupled to their common CANH and CANL outputs and connected to the CAN bus via delay circuits. Matching of the Cgs capacitors between devices in the CANH and CANL branches provides substantially synchronized changes in the CANH and CANL output logic levels as the input logic levels change. The variable delay of this input logic level change for each of the multiple CAN driver circuits reduces the transmission of unwanted signals from the CAN bus.

Description

[0001] Related patent applications

[0002] This application claims priority to co-owned U.S. Provisional Patent Application Serial No. 63 / 219,577, entitled “Can Bus Transmitter,” filed July 8, 2021, which is incorporated herein by reference for all purposes. Technical Field

[0003] This application relates to Controller Area Network (CAN) physical layer communication, and more specifically to a CAN bus transmitter having CANH and CANL signal lines having substantially matched rise and fall times. Background Technology

[0004] CAN, defined in International Organization for Standardization (ISO) 11898, is an international standard specification for high-speed communication in road vehicles. ISO 11898 is a family of specifications, with ISO 11898-1 covering the data link layer, and ISO 118980-2 and ISO 118980-3 covering the physical layer of CAN. CAN is a robust communication protocol. The CAN physical layer is further detailed in Microchip Application Note AN 228 (www.microchip.com), which is incorporated herein by reference for all purposes.

[0005] Electronic systems may have microprocessor-based modules that communicate via a CAN bus using a message-based protocol; these microprocessor-based modules are called CAN modules. A significant application for CAN modules is in the automotive market. CAN modules must fully comply with the latest International Electrotechnical Commission (IEC) 6228-3 standard, which specifies the testing and measurement methods for electromagnetic compatibility (EMC). All CAN modules used in vehicle (automotive) applications must meet the IEC 6228-3 standard for transmitting unwanted signals and robustness against external interference, such as the Direct Power Injection (DPI) test, which can be used to predict the interference immunity of integrated circuits (ICs) to withstand electromagnetic interference without exhibiting any failures.

[0006] The physical layer for CAN network transmissions can be implemented using differential pair transmission lines—CANH and CANL. CAN can specify two logic states: recessive and dominant. During the recessive logic state, CANH and CANL can be approximately the same voltage, or within a voltage tolerance specified for each other. During the dominant logic state, CANH and CANL can be separated by the voltage difference VDiff.

[0007] In the recessive state (e.g., a logic '1' on the input of a CAN transceiver (transmitter / receiver)), the differential voltage on CANH and CANL is less than a minimum threshold (<0.5V receiver input or <1.5V transmitter output). In the dominant state (e.g., a logic '0' on the input of a CAN transceiver), VDiff is greater than the minimum threshold. Dominant bits overdrive recessive bits on the CAN bus to achieve non-destructive bit- wise arbitration. SUMMARY

[0008] Emission requirements in automotive CAN bus systems are becoming more stringent, especially at higher data rates (e.g., CAN Flexible Data Rate (FD) - 5 megabits per second). Therefore, signal matching from two bus drivers (transmitters) for CANH and CANL bus lines can be significantly improved to meet new emission standards for undesired signals as well as robustness against external disturbances such as, for example, but not limited to, direct power injection (DPI). The terms "bus driver" and "transmitter" will be used interchangeably hereinafter.

[0009] According to one embodiment, a controller area network (CAN) domino driver circuit can comprise: a CAN high (CANH) leg having an input coupled to a transmit data (TXD) signal and a first output for a CANH circuit coupled to a CAN bus; and a CAN low (CANL) leg having an input coupled to the TXD signal and a second output for a CANL circuit coupled to the CAN bus; wherein a logic level change of the TXD signal will generate a logic level change at the first and second outputs of the CANH and CANL legs.

[0010] According to another embodiment, the CANH leg can comprise: a P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET); a first resistor; a cascode PMOSFET; a first diode; and an inverting buffer; wherein the PMOSFET source can be coupled to a first voltage level, the gate can be coupled to an output of the first buffer, and the drain can be coupled to a first node of the first resistor; the cascode PMOSFET source can be coupled to a second node of the first resistor, the gate can be coupled to a bias voltage, and the drain can be coupled to an anode of the first diode; a cathode of the first diode can be coupled to the first output of the CANH leg; and an input of the first buffer amplifier can be coupled to the input of the CANH leg.

[0011] According to another embodiment, the CANL branch may include: an N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET); a second resistor; a cascode NMOSFET; a second diode; and a non-inverting buffer; wherein the source of the NMOSFET is coupled to a second voltage level, the gate is coupled to the output of a second buffer amplifier, and the drain is coupled to a first node of the second resistor; the source of the cascode NMOSFET is coupled to a second node of the second resistor, the gate is coupled to the bias voltage, and the drain is coupled to the cathode of the second diode; the anode of the second diode is coupled to the second output of the CANL branch; the input of the second buffer is coupled to the input of the CANL branch; a first capacitor is coupled between the gate and the source of the first NMOSFET; and a second capacitor is coupled between the gate and the source of the cascode NMOSFET.

[0012] According to another embodiment, the first capacitor and the second capacitor are respectively configured to make the gate-source capacitance of the NMOSFET and the cascode NMOSFET substantially the same as the gate-source capacitance of the PMOSFET and the cascode PMOSFET. According to another embodiment, the first capacitor is adjustable. According to another embodiment, the resistance value Rds-on of the second NMOSFET is adjustable. According to another embodiment, the second PMOSFET is a cascode laterally diffused (LD) MOSFET. According to another embodiment, the second NMOSFET may have an 0x3 configuration. According to another embodiment, the first PMOSFET is a laterally diffused (LD) MOSFET. According to another embodiment, the buffer is an inverting buffer, and the second buffer is a non-inverting buffer. According to another embodiment, the buffer can adjustably control the rise and fall times of the signal on the CANH branch. According to another embodiment, the first resistor and the second resistor provide substantially the same signal voltage amplitude on the first output and the second output of the CANH branch and the CANL branch.

[0013] According to another embodiment, the Controller Area Network (CAN) bus driver circuit may include: a plurality of CAN domino driver circuits, each CAN domino driver circuit having an input and a first output and a second output for coupling to a CANH terminal and a CANL terminal of the CAN bus, respectively; a plurality of time delay circuits, each time delay circuit having an input and an output; the input of a first CAN domino driver circuit in the plurality of CAN domino driver circuits and the input of a first delay circuit in the plurality of time delay circuits are coupled to a node for coupling to a Transmit Data (TXD) signal; and the input of each subsequent delay circuit in the plurality of time delay circuits may be coupled to the output of a previous time delay circuit in the plurality of time delay circuits, and the input of each subsequent CAN domino driver circuit in the plurality of CAN domino driver circuits may be coupled to the output of the previous time delay circuit in the plurality of time delay circuits, such that the respective time delay circuit may be located between each CAN domino driver circuit after the first CAN domino driver circuit in the plurality of CAN domino driver circuits.

[0014] According to another embodiment, the plurality of time delay circuits may have an adjustable time delay. According to another embodiment, the time delay of the plurality of adjustable time delay circuits may be statically adjustable. According to another embodiment, the time delay of the plurality of adjustable time delay circuits may be dynamically adjustable. According to another embodiment, the plurality of time delay circuits may have different time delays. According to another embodiment, the plurality of time delay circuits may have a jitter time delay. According to another embodiment, each time delay circuit in the plurality of time delay circuits may have a time delay from approximately 3 nanoseconds to approximately 5 nanoseconds.

[0015] According to another embodiment, a method for driving a Controller Area Network (CAN) bus may include: providing a plurality of CAN domino driver circuits, each CAN domino driver circuit having an input and a first output and a second output for coupling to a CANH terminal and a CANL terminal of the CAN bus, respectively; providing a plurality of time delay circuits, each time delay circuit having an input and an output; coupling the input of a first CAN domino driver circuit of the plurality of CAN domino driver circuits and the input of a first delay circuit of the plurality of time delay circuits to a node for coupling to a Transmit Data (TXD) signal; and coupling the input of each subsequent delay circuit of the plurality of time delay circuits to the output of a preceding time delay circuit of the plurality of time delay circuits, and coupling the input of each subsequent CAN domino driver circuit of the plurality of CAN domino driver circuits to the output of the preceding time delay circuit of the plurality of time delay circuits, such that the respective time delay circuit may be located between each CAN domino driver circuit after the first CAN domino driver circuit of the plurality of CAN domino driver circuits.

[0016] According to another embodiment, the sequential time-delayed TXD signal may include a step of statically adjusting the time delay of at least some of the time delay circuits in the time delay circuit. According to another embodiment, the sequential time-delayed TXD signal may further include a step of dynamically adjusting the time delay of at least some of the time delay circuits in the time delay circuit. According to another embodiment, the sequential time-delayed TXD signal may further include a step of jittering the time delay of at least some of the time delay circuits in the time delay circuit. Attached Figure Description

[0017] A more complete understanding of this disclosure can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is a diagram of an electronic system that uses a CAN bus for communication between electronic control units (ECUs);

[0019] Figure 2 This is an illustration of an exemplary CAN bus driver circuit comprising multiple domino driver circuits separated by associated delay circuitry, according to an example of this disclosure.

[0020] Figure 3 It is an example of the use of this disclosure Figure 2 An illustration of an exemplary domino driver circuit for a CAN bus driver circuit; and

[0021] Figure 4 It is an example of the use of this disclosure Figure 2A diagram of another exemplary domino driver circuit for a CAN bus driver circuit.

[0022] While this disclosure is susceptible to various modifications and alternatives, specific examples thereof have been shown in the accompanying drawings and described in detail herein. However, it should be understood that the description of specific examples herein is not intended to limit this disclosure to the forms disclosed herein. Detailed Implementation

[0023] When differential signals on a transmission line have equal amplitudes and are 180 degrees out of phase, their common-mode voltage will be significantly reduced. When the amplitudes are not the same and / or the phase difference is not 180 degrees, the vector subtraction of the two signals will not completely cancel each other out, and this can result in spurious emissions (signals).

[0024] Output driver circuits for the physical layer of a CAN bus system fully compliant with the latest IEC 6228-3 specification can be used in classic CAN and CAN FD networks in automotive, aerospace, medical, industrial, and consumer applications. The output driver circuits can use switched resistors to generate the output amplitude of the CAN bus signal. Pulse shaping can be performed by using adjustable delay steps between multiple driver circuits (“dominoes”) configured as a cascaded domino effect CAN bus driver circuit. This paper discloses trimming laterally diffused N-channel metal-oxide-semiconductor (LDNMOS) and laterally diffused P-channel metal-oxide-semiconductor (LDPMOS) transistors to reduce mismatch between them. Matching between the CANH driver output and the CANL driver output provides improved transmit performance. The use of switched resistors in the output stage significantly improves this matching and provides the desired low transmit results.

[0025] Referring now to the accompanying drawings, details of the example are schematically shown. Similar elements in the drawings will be represented by similar numerals, and similar elements will be represented by similar numerals with different lowercase letter suffixes.

[0026] refer to Figure 1This describes an electronic system using a CAN bus for communication between electronic control units (ECUs). The electronic system, typically represented by the numeral 100, may include multiple CAN nodes 110, denoted as 110a, 110b, ..., 110y, 110z, communicating via a CAN bus consisting of CANH signal line 102 and CANL signal line 104. A terminating resistor 106 may be coupled at one end of the CAN bus, and a terminating resistor 108 may be coupled at the other end of the CAN bus (CANH 102, CANL 104). CAN nodes 110 may include a CAN bus transmitter / receiver (transceiver) 112, a CAN controller 114, and an electronic control unit (ECU) 116. Each ECU 116 may control different subsystems of the electronic system 100. Examples of different subsystems for a vehicle may include any of the following: engine control unit, driver assistance, automatic transmission control, airbags, anti-lock braking / ABS, cruise control, electric power steering, audio system, power windows, doors, and mirror adjustment, battery and recharging system, to name just a few.

[0027] refer to Figure 2 This document describes an exemplary CAN bus driver circuit according to an example of the present disclosure, comprising multiple domino driver circuits separated by associated delay circuitry. The CAN driver circuit, typically indicated by the numeral 212, may include multiple domino driver circuits 214 that can generate substantially symmetrical CANH and CANL signals at CANH 102 and CANL 104 terminals. CAN driver circuit 212 is the transmitter portion of the CAN bus transmitter / receiver 112. "Domino driver circuit" is defined herein as a series of driver circuits arranged for cascading, each driver circuit being sequentially driven by the preceding domino driver circuit through a time delay in a chain reaction similar to cascading domino chips.

[0028] Each domino driver circuit 214 can drive the CAN bus independently and can be configured to drive the CAN bus based on the logic value received at the Transmit Data (TXD) input 216. Figure 1 and Figure 2The CANH 102 terminal and CANL 104 terminal shown generate CANH and CANL output signals, respectively. The first domino driver circuit 214a is coupled to the TXD input 216 via an inverter 220 that inverts the TXD signal thereto. Subsequent domino driver circuits 214 are coupled to the output of the inverter 220 via corresponding time delay circuits 218. The time delay circuits 218 provide an accumulated time delay of the inverted TXD input to each subsequent domino driver circuit 214 of the CAN driver circuit 212, such that the delay between the inverted TXD signal and each subsequent domino driver circuit 214 is increased by the corresponding time delay circuit 218. Any suitable number and type of domino driver circuits 214 and time delay circuits 218 can exist. For example, but not limited to, twenty (20) domino driver circuits 214 separated by nineteen (19) time delay circuits 218 can exist. The domino driver circuit 214 and the time delay circuit 218 can be implemented in any suitable manner, such as by analog circuitry, digital circuitry, instructions for execution by a digital processor (not shown), or any suitable combination thereof.

[0029] The time delay provided by each delay circuit in delay circuit 218 can vary from delay circuit 218a to delay circuit 218y. The delay time is longer than the switching time of transistor driver circuit 214. The time delay can range, for example, from about three (3) nanoseconds to about five (5) nanoseconds. The time delay can vary according to, for example, a sine function, a ramp function, or any other suitable function. The time delay provided by each delay circuit in delay circuit 218 can start high, decrease, and then rise again in a given period. The time delay can vary with the iterations performed, or can be delayed from one another within a given iteration. If all time delays are equal, such as two (2) nanoseconds, frequency spikes that can be observed on the CAN bus may occur. The time delays can be changed (adjusted) so that these spikes are not at the same frequency. Time delay control and jitter circuit 220 can be used to statically or dynamically set different time delays for each of the multiple time delay circuits in time delay circuit 218.

[0030] refer to Figure 3 This describes an example of a device for use according to this disclosure. Figure 2 An exemplary domino driver circuit 314 for a CAN bus driver circuit. The domino driver circuit 314 can be used in... Figure 2The domino driver circuit 314 may include any one of the domino driver circuits in the domino driver circuit 214. The domino driver circuit 314 may include an inverting buffer 316, a non-inverting buffer 318, a P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) 320, a first impedance 322, a cascode PMOSFET 324, a first diode 326, a second diode 328, a cascode N-channel MOSFET (NMOSFET) 330, a first capacitor 332, a second impedance 334, an NMOSFET 336, and a second capacitor 338. Power (Vcc) may be coupled to the domino driver circuit 314 via a first current limiter 340. Half-voltage bias (Vcc / 2) may be coupled to the domino driver circuit 314 via a voltage divider 342. A second voltage level (ground) or power return may be coupled to the domino driver circuit 314 via a second current limiter 344. Current limiters 340 and 344, and voltage divider 342, can be shared by all domino driver circuits 314, including CAN driver circuit 212. PMOSFET 320 and NMOSFET 336 can be of Ox3 construction, where Ox3 construction refers to: a gate thin layer of SiO2 oxide + tetraethyl orthosilicate (TEOS), chemical formula Si(OC2H5)4, thermally grown in an N2O environment, deposited using an oxidation process. The common-source cascode PMOSFET 324 and NMOSFET 330 can be either MOSFETs or laterally diffused (LD) MOSFETs.

[0031] The inputs of the inverting buffer 316 and the non-inverting buffer 318 are coupled to the inverted transmitted data ( / TXD) signal. The non-delayed / TXD signal is coupled to the input of the first domino driver circuit 214a, and subsequent / TXD signals are delayed by each corresponding time delay circuit 218 and then coupled to the corresponding domino driver circuit in the domino driver circuit 214, such that the delay of the / TXD signal of each subsequent domino driver circuit 214 is increased relative to the previous domino driver circuit by the corresponding time delay circuit 218. The inverting buffer 316 and the non-inverting buffer 318 can be coupled between Vcc and Vcc / 2 and between Vcc / 2 and common (Gnd), respectively, to obtain operating voltages therefrom. The CANH 102 bus operates at approximately 2.5 volts to 5 volts, and the CANL 104 bus operates at approximately 0 volts to 2.5 volts.

[0032] The TXD signal can be inverted, for example, to form a / TXD signal, because it is received for... Figure 3Proper operation of the circuit shown. The / TXD signal can be coupled to the gate of PMOSFET 320 via inverting buffer 316, and PMOSFET 320 can be selected as a high-speed switch for the CANH signal. The / TXD signal can be coupled to the gate of NMOSFET 336 via non-inverting buffer 318, and NMOSFET 336 can be selected as a high-speed switch for the CANL signal.

[0033] The CANH branch may include a PMOSFET 320, a first impedance 322, a cascode PMOSFET 324, and a first diode 326 coupled to the CANH terminal 102. The CANH branch may be coupled between Vcc and the CANH terminal 102. A first current limiter 340 may be coupled between Vcc, an inverting buffer 316, and the source of the PMOSFET 320 in the CANH branch.

[0034] The CANH branch may include an 0x3 or 3-volt PMOS transistor or other suitable solid-state switch for the PMOSFET 320. This solid-state switch of the PMOSFET 320 may be switched with a delay smaller than that of the corresponding delay circuit 218, i.e., it may be faster than the delay of the corresponding delay circuit 218, and may be driven by the output of the buffer 316. The first impedance 322 of the CANH branch may include a resistor, a resistor package, or other suitable impedance. Depending on the operation of the PMOSFET 320, the first impedance 322 may be switched in and out of the circuit. The first impedance 322 may be connected between the drain of the 0x3 PMOSFET 320 and the source of the cascode PMOSFET 324. A first diode 326 may be coupled between the drain of the cascode PMOSFET 324 and the CANH terminal 102. The gate of the cascode PMOSFET 324 may be biased by the VCC / 2 output from the voltage divider 342.

[0035] The CANL branch may include an NMOSFET 336, a second impedance 334, a cascode NMOSFET 330, and a second diode 328 coupled to the CANL terminal 104. The CANL branch may be coupled between the CANL terminal 104 and a second voltage level (ground). A second current limiter 344 may be coupled between a grounded, non-inverting buffer 318 and the source of the NMOSFET 336 in the CANL branch.

[0036] The CANL branch may include a 0x3 or 3-volt NMOS transistor or other suitable solid-state switch for the NMOSFET 336. This solid-state switch of the NMOSFET 336 may be switched with a delay smaller than that of the corresponding delay circuit 218, i.e., it may be faster than the delay of the corresponding delay circuit 218, and may be driven by the output of the buffer 318. The second impedance 334 of the CANL branch may include a resistor, a resistor package, or other suitable impedance. The second impedance 334 may be switched depending on the operation of the NMOSFET 336. The second impedance 334 may be connected between the drain of the NMOSFET 336 and the source of the cascode NMOSFET 330. A second diode 328 may be coupled between the drain of the cascode NMOSFET 330 and the CANL terminal 104. The gate of the cascode NMOSFET 320 may be biased by the VCC / 2 output from the voltage divider 342.

[0037] PMOSFETs have a larger physical structure than NMOSFETs, therefore PMOSFETs have a larger Cgs value than NMOSFETs. Capacitors 332 and 338 can be added between the source and gate of the cascode NMOSFET 330 and NMOSFET 336, respectively, to provide Cgs that are closely matched to the total input capacitance (Cgs) of PMOSFET 324 and PMOSFET 320, respectively. These added capacitors allow the switching times of NMOSFET 330 and NMOSFET 336 to be better matched to the switching times of PMOSFET 324 and PMOSFET 320, respectively, thus resulting in better slope and edge delay matching of the CANH driver output and CANL driver output for better emitter performance. Furthermore, the use of resistors (e.g., first impedance 322 and second impedance 334) in the driver outputs (CANH branch and CANL branch) significantly improves the signal amplitude matching between the CANH signal waveform and the CANL signal waveform. Essentially matching the slope, edge delay, and amplitude of the CANH and CANL signals provides better emitter performance (reduced emissions) for CAN node 110. The values ​​for capacitors 332 and 338 can be selected during integrated circuit design to provide total Cgs that are closely matched to the total Cgs of NMOSFETs 330 and 336 with those of PMOSFETs 324 and 320, respectively. The values ​​for resistors 322 and 334 can be determined during integrated circuit design and can be different for each domino driver circuit in domino driver circuit 214 of CAN driver circuit 212.

[0038] In one example, the large capacitance value Cgs of the cascode PMOSFET 324 can be compensated in the CANL branch. The structure of the cascode NMOSFET 330 can be significantly smaller than that of the PMOSFET 324, and therefore its Cgs will be smaller than that of the PMOSFET 324. Therefore, the time required to activate the PMOSFET 324 may be greater than the time required to activate the NMOSFET 330. This can cause the PMOSFET 324 to operate more slowly than the NMOSFET 330, resulting in poor synchronization between the CANH output signal and the CANL output signal on the CANH terminal 102 and the CANL terminal 104. Therefore, a capacitor 332 can be added between the gate and source of the NMOSFET 330 so that its total capacitance substantially matches the Cgs capacitance of the PMOSFET 324. The capacitance of the first capacitor 332 and therefore the total Cgs of the NMOSFET 330 can be determined during integrated circuit design. Similarly, a capacitor 338 can be added between the gate and source of the NMOSFET 336 so that its total Cgs is substantially the same as that of the PMOSFET 320.

[0039] refer to Figure 4 This describes an example of a device for use according to this disclosure. Figure 2 Another exemplary domino driver circuit 414 is shown in the CAN bus driver circuit. The domino driver circuit 414 can be used in... Figure 2 Any one of the domino driver circuits in domino driver circuit 214. Domino driver circuit 414 has a CANH branch and a CANL branch, which are connected to... Figure 3 The branches in the domino driver circuit 314 operate in essentially the same way as described above.

[0040] In one example, the large capacitance value Cgs of the cascode PMOSFET 324 can be compensated in the CANL branch. The structure of the cascode NMOSFET 430 can be significantly smaller than that of the PMOSFET 324, and therefore its Cgs will be smaller than that of the PMOSFET 324. Therefore, the time required to activate the PMOSFET 324 may be greater than the time required to activate the NMOSFET 430. This can cause the PMOSFET 324 to operate more slowly than the NMOSFET 430, resulting in poor synchronization of the CANH and CANL output signals on CANH bus line 102 and CANL bus line 104. Therefore, a fixed or variable capacitor 432 can be added between the gate and source of the NMOSFET 430 so that its total capacitance substantially matches the Cgs capacitance of the PMOSFET 324. The capacitance of capacitor 432, and therefore the total Cgs of the NMOSFET 430, can be determined during integrated circuit design. Similarly, a capacitor 338 can be added between the gate and source of the NMOSFET 336 to make its total Cgs substantially the same as that of the PMOSFET 320. Furthermore, the cascode NMOSFET 430 allows its resistance value Rds-on to be adjusted during design to match the Rds-on of the cascode PMOSFET 324. This can be achieved by enabling / disabling small transistors coupled to the cascode NMOSFET 430.

[0041] Inverting buffer 462 can be configured to provide rise and fall time regulation of the CAN bus signal by adjusting Del_h_d2r and Del_h_r2d. Capacitor 464, resistors 460 and 470, and NMOSFET 468 provide voltage level shifting between the respective outputs of inverting buffer 462 and buffer 466 and the inputs of inverting buffer 316 and non-inverting buffer 466. The CANH bus line 102 has a voltage range of approximately 2.5 volts to 5 volts, and the CANL bus line 104 has a voltage range of approximately 0 volts to 2.5 volts, where Vcc starts at approximately 5 volts. If voltage level functionality is not required and for circuit operation purposes, the inverting buffer amplifier 316 or the non-inverting buffer amplifier 318 can be regarded as a buffer amplifier that provides adjustable rise and fall times for signals on CANH bus line 102 or CANL bus line 104, respectively. In this case, the rise and fall times can be adjusted and incorporated into the inverting buffer amplifier 462 in response to signals Del_h_d2r and Del_h_r2d.

[0042] This disclosure has been described with reference to one or more examples, and it should be understood that many equivalents, substitutions, variations, and modifications are possible and within the scope of this disclosure, in addition to those expressly stated. While this disclosure is susceptible to various modifications and alternatives, specific examples thereof have been shown in the accompanying drawings and described in detail herein. However, it should be understood that the description of specific examples herein is not intended to limit this disclosure to the specific forms disclosed herein.

Claims

1. A Controller Area Network (CAN) domino driver circuit, comprising: A CAN high (CANH) branch, the CANH branch having an input coupled to a transmit data (TXD) signal and a first output of a CANH circuit for coupling to a CAN bus; and A CAN low (CANL) branch, the CANL branch having an input coupled to the TXD signal and a second output for coupling to the CAN bus; The logic level change of the TXD signal will generate a logic level change at the first and second outputs of the CANH branch and the CANL branch, wherein... The CANH branch includes: First P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET); First resistor; Common-source cascode PMOSFET; First diode; and First buffer; in The first PMOSFET The source is coupled to the first voltage level. The gate is coupled to the output of the first buffer, and The drain is coupled to the first node of the first resistor; The common-source cascode PMOSFET The source is coupled to the second node of the first resistor. The gate is coupled to the bias voltage, and The drain is coupled to the anode of the first diode; The cathode of the first diode is coupled to the first output of the CANH branch; and The input of the first buffer is coupled to the input of the CANH branch.

2. The CAN domino driver circuit according to claim 1, wherein the CANL branch comprises: First N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET); Second resistor; Common-source NMOSFET; Second diode; and Second buffer; in The first NMOSFET The source is coupled to the second voltage level. The gate is coupled to the output of the second buffer, and The drain is coupled to the first node of the second resistor; The common-source NMOSFET The source is coupled to the second node of the second resistor. The gate is coupled to the bias voltage, and The drain is coupled to the cathode of the second diode; The anode of the second diode is coupled to the second output of the CANL branch; and The input of the second buffer is coupled to the input of the CANL branch; A first capacitor coupled between the gate and the source of the first NMOSFET; and A second capacitor coupled between the gate and the source of the common-source NMOSFET.

3. The CAN domino driver circuit according to claim 2, wherein the first capacitor and the second capacitor respectively make the capacitance between the gate and the source of the first NMOSFET and the cascode NMOSFET substantially the same as the capacitance between the gate and the source of the first PMOSFET and the cascode PMOSFET.

4. The CAN domino driver circuit according to any one of claims 2 to 3, wherein the first capacitor is adjustable.

5. The CAN domino driver circuit according to any one of claims 2 to 3, wherein the common-source cascode NMOSFET resistance value Rds-on is adjustable.

6. The CAN domino driver circuit according to any one of claims 1 to 3, wherein the common-source cascode PMOSFET is a common-source cascode laterally diffused (LD) MOSFET.

7. The CAN domino driver circuit according to any one of claims 2 to 3, wherein the common-source cascode NMOSFET has a 0x3 configuration.

8. The CAN domino driver circuit according to any one of claims 1 to 3, wherein the first PMOSFET is a laterally diffused (LD) MOSFET.

9. The CAN domino driver circuit according to any one of claims 2 to 3, wherein the first buffer is an inverting buffer and the second buffer is a non-inverting buffer.

10. The CAN domino driver circuit according to any one of claims 1 to 3, wherein the first buffer adjustably controls the rise time and fall time of the signal on the CANH branch.

11. The CAN domino driver circuit according to any one of claims 2 to 3, wherein the first resistor and the second resistor provide substantially the same signal voltage amplitude at the first output and the second output of the CANH branch and the CANL branch.

12. A Controller Area Network (CAN) bus driver circuit, comprising: Multiple CAN domino driver circuits, each CAN domino driver circuit having an input and a first output and a second output for coupling to the CANH terminal and CANL terminal of the CAN bus, respectively; Multiple time delay circuits, each with inputs and outputs; The input of the first CAN domino driver circuit in the plurality of CAN domino driver circuits and the input of the first delay circuit in the plurality of delay circuits are coupled to a node, the node being used to couple to a transmit data (TXD) signal. and The input of a corresponding subsequent delay circuit in the plurality of delay circuits is coupled to the output of a preceding time delay circuit in the plurality of time delay circuits, and the input of each subsequent CAN domino driver circuit in the plurality of CAN domino driver circuits is coupled to the output of the preceding time delay circuit in the plurality of time delay circuits, such that the corresponding time delay circuit is located between the corresponding CAN domino driver circuits after the first CAN domino driver circuit in the plurality of CAN domino driver circuits, wherein the plurality of time delay circuits have an adjustable time delay.

13. The CAN bus driver circuit according to claim 12, wherein the time delay of the plurality of adjustable time delay circuits is statically adjustable.

14. The CAN bus driver circuit according to any one of claims 12 to 13, wherein the time delay of the plurality of adjustable time delay circuits is dynamically adjustable.

15. The CAN bus driver circuit according to any one of claims 12 to 13, wherein the plurality of time delay circuits have different time delays.

16. The CAN bus driver circuit according to any one of claims 12 to 13, wherein the plurality of time delay circuits have jitter time delay.

17. The CAN bus driver circuit according to any one of claims 12 to 13, wherein each time delay circuit in the time delay circuit has a time delay from about 3 nanoseconds to about 5 nanoseconds.

18. A method for driving a Controller Area Network (CAN) bus, the method comprising: Multiple CAN domino driver circuits are provided, each having an input and a first and a second output for coupling to the CANH and CANL terminals of the CAN bus, respectively. Multiple time delay circuits are provided, each with inputs and outputs; The input of the first CAN domino driver circuit in the plurality of CAN domino driver circuits and the input of the first delay circuit in the plurality of delay circuits are coupled to a node, the node being used to couple to a transmit data (TXD) signal. The time delay of at least some of the plurality of time delay circuits is dynamically adjusted; as well as The input of a corresponding subsequent delay circuit in the plurality of delay circuits is coupled to the output of a preceding time delay circuit in the plurality of time delay circuits, and the input of a corresponding subsequent CAN domino driver circuit in the plurality of CAN domino driver circuits is coupled to the output of a preceding time delay circuit in the plurality of time delay circuits, such that the corresponding time delay circuit is located between the corresponding CAN domino driver circuits after the first CAN domino driver circuit in the plurality of CAN domino driver circuits.

19. The method of claim 18, wherein the step of dynamically adjusting the time delay includes the step of jittering the time delay of at least some of the time delay circuits in the time delay circuit.

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