Cache management method applied to memory and memory
By dividing the cache unit into hotspot write cache and random write cache, and counting hotspot index addresses based on the number of write operations, the secondary mapping table is stored first, which solves the problem of frequent load and unload operations in DRAM-less solid-state drives, improves access performance, extends service life, and reduces power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MAXIO TECHNOLOGY (HANGZHOU) CO LTD
- Filing Date
- 2022-03-25
- Publication Date
- 2026-05-12
AI Technical Summary
Existing DRAM-less solid-state drives suffer from degraded access performance due to frequent loading and unloading of secondary mapping tables during mapping table management, which increases bandwidth usage and power consumption between the controller and storage media.
By dividing the cache unit into hot write cache and random write cache, and counting the hot index address based on the number of write operations, the secondary mapping table is stored in the hot cache first, and data is merged and compressed during read and write operations to reduce unnecessary load and unload operations.
It improves the read and write performance and lifespan of solid-state drives while reducing power consumption.
Smart Images
Figure CN116841454B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data storage technology, and in particular to a cache management method for memory and a memory. Background Technology
[0002] Solid-state drives (SSDs) are storage hard drives made using solid-state electronic storage chips. A storage hard drive includes a controller and storage media. Currently, the most common SSDs use flash memory as the storage medium to store data, such as non-volatile memory like NAND flash.
[0003] Solid-state drives (SSDs) are widely used in various applications. When using an SSD to store and write data, a mapping table from the FTL (flash translation layer) is required to record the mapping relationship between the host logical space address and the physical address of the flash memory. Therefore, an SSD not only stores the data written by the user, but also stores the mapping table that maintains the mapping relationship of the write data.
[0004] Currently, DRAM-less solid-state drives (SSDs) manage their mapping tables by creating two-level mapping tables. This involves grouping the logical addresses corresponding to write data into a primary mapping table, which includes the logical addresses corresponding to multiple data blocks. Then, multiple secondary mapping tables are created, each storing the mapping between the logical address and physical address of a single data block. For DRAM-less SSDs, the primary mapping table is stored in the controller's cache unit (typically SRAM), while the secondary mapping tables are stored in the storage medium. However, when the controller receives a host access command, it needs to load the secondary mapping table to be accessed from the storage medium into the cache unit. Since the cache unit has a limited capacity, when the cache unit is full, some secondary mapping tables need to be unloaded from the cache unit. Therefore, it's understandable that the loading and unloading of secondary mapping tables is closely related to the SSD's access performance; reducing the loading and unloading operations of secondary mapping tables will help improve the SSD's access performance. Summary of the Invention
[0005] In view of the above problems, the purpose of the present invention is to provide a cache management method and apparatus for memory, which reduces the loading and unloading operations of secondary mapping tables by planning and managing the cache units of memory.
[0006] According to a first aspect of the present invention, a cache management method for a memory is provided, the memory including a controller and a storage medium, the controller including a cache unit, the cache unit storing a first-level mapping table, the first-level mapping table storing a plurality of index addresses pointing to a plurality of second-level mapping tables stored on the storage medium, the cache management method being executed by the controller, including:
[0007] The cache unit is divided into a hotspot write cache and a random write cache;
[0008] The number of write operations corresponding to each index address in the first-level mapping table is continuously accumulated within a set time period. The index addresses in the first-level mapping table are sorted from largest to smallest according to the number of write operations corresponding to each index address, and the index addresses with the highest number of write operations are recorded as system hotspots.
[0009] For a received write command, if its corresponding index address belongs to a system hotspot, a hotspot cell is allocated in the hotspot write cache, and all data of the secondary mapping table pointed to by the corresponding index address is loaded into the hotspot cell; otherwise, a random write cell is allocated in the random write cache, and data is written into the random write cell based on the write command.
[0010] Optionally, it further includes: dividing the cache unit into a read cache, and when a read command is received, allocating a read cell from the read cache to load the secondary mapping table pointed to by the corresponding index address.
[0011] Optionally, for a received write command, if its corresponding index address is a system hotspot, but the secondary mapping table pointed to by its corresponding index address is already cached in the random write cache and / or the read cache, then the secondary mapping table pointed to by its corresponding index address is merged from the random write cache and / or the read cache into the hotspot cell.
[0012] Optionally, during the step of allocating a read cell from the read cache to load the secondary mapping table pointed to by the corresponding index address, the secondary mapping table is also compressed.
[0013] Optionally, a fixed-size read cell is allocated on the cache unit to store the compressed secondary mapping table.
[0014] Optionally, in the read cache, read cells of non-fixed size are allocated according to the size of the compressed secondary mapping table to store the compressed secondary mapping table.
[0015] Optionally, it also includes: continuously accumulating the access volume of each secondary mapping table within a set time period in the read cache, and when the read cache space is insufficient, prioritizing the release of read cells with low access volume in ascending order of access volume.
[0016] Optionally, it also includes: data smoothing of the cumulative number of write operations based on write commands.
[0017] Optionally, the memory is a DRAM-less solid-state drive.
[0018] According to a second aspect of the present invention, a memory is provided, comprising:
[0019] A controller, connected to a host, is used to receive write data from the host;
[0020] A storage medium, connected to the controller, is used to store the write data.
[0021] The controller further includes a cache unit for storing a first-level mapping table corresponding to the write data, and the storage medium is further used to store mapping table data corresponding to the first-level mapping table. The controller is used for any of the cache management methods described above.
[0022] According to this embodiment, by counting the number of accesses of write commands, the top few secondary mapping tables with the highest access counts are identified as hotspots, and the rest are non-hotspots. Hotspot cells are assigned to the hotspots to store all the data of the corresponding secondary mapping tables. The random write cache is updated according to the write commands. The data in the secondary mapping tables stored in the hotspot cells is always the latest and most complete, but the secondary mapping tables in the random write cache may only contain a portion of the data. This ensures that the secondary mapping tables of the hotspots can remain in the cache, thereby reducing the loading and unloading operations of the secondary mapping tables between the controller and the storage medium, which helps to improve the read and write performance and lifespan of the memory.
[0023] Furthermore, compressing the secondary mapping table and writing it into the read cache can reduce write amplification, and since the reading and writing mapping table is smaller, power consumption can also be reduced. Attached Figure Description
[0024] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0025] Figure 1 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown;
[0026] Figure 2 This illustrates how a secondary mapping table is stored in a solid-state drive (SSD).
[0027] Figure 3This is a flowchart of a cache management method applied to a memory, provided in an embodiment of this disclosure;
[0028] Figure 4 This is a schematic diagram illustrating the storage method of embodiments of this disclosure;
[0029] Figures 5a to 5c It is a bar chart showing random write mode, short-term frequent write mode, and long-term frequent write mode;
[0030] Figure 6 This is a flowchart of a compression method used in an embodiment of this disclosure;
[0031] Figure 7 This is a flowchart of a compression method used in another embodiment of this disclosure. Detailed Implementation
[0032] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.
[0033] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0034] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0035] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0036] Figure 1 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown.
[0037] like Figure 1As shown, the computer system 100 includes a host 110 and a solid-state drive (SSD). The SSD includes a controller 120 and a storage medium 130. The controller 120 is connected to the host 110 and is used to exchange write data with the host 110. The controller 120 connects the host 110 and the storage medium 130 and stores the write data from the host 110 into the storage medium 130.
[0038] The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a memory controller 128. The host interface 121 of the control system 120 is connected to the host 110 to transmit data and read / write commands. The processor 123 is connected to the host interface 121, the cache unit 124, and the memory controller 128. The processor 123 parses read / write commands and executes read / write operations. The cache unit 124, for example, is SRAM, used to store a mapping table. The memory controller 128 controls the transmission and storage of write data. The processor 123 also implements the core software layer for memory control, namely the FTL (flash translation layer). The FTL consists of several programs. The processor 123 executes these programs, enabling it to translate read / write commands upon receipt, thereby completing access to the storage medium 130. Therefore, the host 110's file system and operating system can access the storage medium as if it were their own memory. The FTL also features, for example, support for bad block management, wear leveling, garbage collection, power-off recovery, and write balancing technologies.
[0039] Storage medium 130 is, for example, a flash memory chip array. To improve data read and write performance, the memory controller 128 of controller 120 can read and write to the flash memory chips of storage medium 130 via multiple channels (e.g., CH0 and CH2), with each channel connected to a group of flash memory chips.
[0040] Cache unit 124 can use SRAM and / or DRAM. Comparatively, SRAM offers speed advantages as a cache, but it is more expensive and has a smaller storage capacity per unit space. Accordingly, to improve cache space utilization, DRAM-less solid-state drives (SDS) employ a two-level mapping table for address management.
[0041] like Figure 2 As shown, the logical addresses (LAAs) corresponding to the written data are first grouped, and then sorted according to data blocks (e.g., ...). Figure 1 Physical blocks 131 and 132 in the document are used for storage. See also Figure 2On the left side, all logical addresses in the solid-state drive are divided into m+1 blocks (0 to m) and stored in the first-level mapping table. The first-level mapping table (first-level table) can be regarded as an array L1[m] with m+1 elements (index starts from 0). The array L1[m] stores (m+1) index addresses, which point to (m+1) cells. These cells are located on the storage medium of the DRAM-less solid-state drive and are used to store a second-level mapping table. Each second-level mapping table contains the mapping relationship between the logical address and physical address of the corresponding data block. Taking L1[1] as an example, it points to cell b1 in the storage medium. b1 stores the mapping relationship between LAA 0~LAA(x-1) and FAA0~FAA(x-1). FAA is an abbreviation for Flash Access Agent (physical address). However, since the logical addresses LAA0 to LAA(x-1) are numerically consecutive, in some implementations, each cell can store the secondary mapping table as follows: first, store the logical starting address LAA0 (the first logical address), and then store the corresponding FAA0 to FAA(x-1) sequentially. Each cell has a fixed size, for example, 4kB, so the secondary mapping table will occupy (m+1)*4kB of flash memory space.
[0042] In the prior art, when a write command is received from the host, the controller 120 reads the corresponding index address from the first-level mapping table according to the write command, and determines whether the second-level mapping table pointed to by the index address already exists in the cache unit 124. If so, the controller updates the corresponding second-level mapping table in the cache unit 124 according to the write command. If not, the controller allocates another cache cell c1 in the cache unit 124 for the write command. The size of the cache cell is consistent with the size of the second-level mapping table. Then, the controller writes the corresponding data into the cache cell c1 according to the write command, and refreshes the data in c1 to b1 when appropriate (e.g., when c1 is full or the cache unit is insufficient and cache space needs to be freed up).
[0043] However, this on-demand cache space allocation scheme can lead to frequent loading and unloading operations of the secondary mapping table when real-time access to the primary table is very random. This increases the bandwidth usage between the controller and the storage medium. Furthermore, the secondary mapping table on the cache unit may need to be stored in the storage medium even when the data changes very little, which increases write amplification.
[0044] Figure 3 This is a flowchart illustrating a cache management method for memory provided in an embodiment of this disclosure. It includes the following steps.
[0045] In step S301, the cache unit is divided into a hotspot write cache and a random write cache.
[0046] In step S302, the number of write operations corresponding to each index address in the first-level mapping table within a set time period is accumulated. The index addresses in the first-level mapping table are sorted from largest to smallest according to the number of write operations corresponding to each index address, and the index addresses with the highest number of write operations are recorded as system hotspots.
[0047] In step S303, for a received write command, if its corresponding index address belongs to the system hotspot, a hotspot cell is allocated in the hotspot write cache, and all data of the secondary mapping table pointed to by the corresponding index address is loaded into the hotspot cell; otherwise, a random write cell is allocated in the random write cache, and data is written to the random write cell based on the write command.
[0048] According to this embodiment, by counting the number of accesses of write commands, the top few secondary mapping tables with the highest access counts are identified as hotspots, and the rest are non-hotspots. Hotspot cells are assigned to the hotspots to store all the data of the corresponding secondary mapping tables. The random write cache is updated according to the write commands. The data in the secondary mapping tables stored in the hotspot cells is always the latest and most complete, but the secondary mapping tables in the random write cache may only contain a portion of the data. This ensures that the secondary mapping tables of the hotspots can remain in the cache, thereby reducing the loading and unloading operations of the secondary mapping tables between the controller and the storage medium, which helps to improve the read and write performance and lifespan of the memory.
[0049] However, it should be noted that steps S302 and S303 are not executed sequentially. Step S302 needs to be executed repeatedly. For example, step S302 calculates the number of write operations corresponding to each index address at each preset time interval (e.g., 1 second) based on the continuously received write commands, while step S303 can be executed once every time a write command is received.
[0050] refer to Figure 4As shown, an array space for storing statistical values can be allocated in cache unit 124. The size of this array space corresponds to the number of entries in the first-level mapping table. Each time the controller 120 receives a write command, it updates the statistical values in the array space corresponding to the write command. The statistical values represent the number of write operations corresponding to each index address in the first-level mapping table. The statistical values are sorted from largest to smallest. Simultaneously, cache unit 124 is divided into a hotspot write cache, a random write cache, and a read cache. The hotspot write cache can consist of a set of hotspot cells d1 to dm, used to cache the second-level mapping tables pointed to by the first m index addresses of the statistical values. For any received write command, if its corresponding index address belongs to a system hotspot (i.e., it belongs to one of the first m index addresses of the statistical values), then a hotspot cell is allocated to load all the data in the second-level mapping table pointed to by that index address. Otherwise, random write cells such as c1 to cn are allocated in the random cache to write the mapping relationship of the write command.
[0051] Optionally, the controller 120 can pre-set the ratio of hotspot write cache, read cache, and random write cache, and divide the space according to the ratio. It should also be noted that, for convenience, hotspot cells d1 to dm, random write cells c1 to cn, and read cells k1 to kk can be set to cells of the same size. For example, if the secondary mapping table is 4K, then the size of the hotspot cells, random write cells, and read cells is 4K, but this is not mandatory.
[0052] The following is based on Figure 4 Describe the state change process of read and write operations and how to update the cache accordingly.
[0053] At a certain moment, the controller 120 needs to start writing the secondary mapping table corresponding to L1[1](F000). At this time, L1[1] does not belong to the system hotspot (i.e., it does not belong to the top n table entries). Then, according to the write command, a random write cell c1 is obtained, and the mapping relationship data is written into c1 according to the write command.
[0054] If, over time, the host makes continuous high-frequency accesses to the secondary mapping table corresponding to L1[1], then at a certain point, it is calculated that L1[1] is the current system hotspot. The controller 120 then allocates a hotspot cell to L1[1]. At this time, the secondary mapping table corresponding to L1[1] may be in random cell c1, or on storage medium 130. If a read operation has occurred, it may also be in read cell k1 of the read cache. In other words, the secondary mapping table corresponding to L1[1] is stored in at least these three storage locations. The controller 120 then reads data from these storage locations and merges it into the hotspot cell d1. Finally, the hotspot cell d1 will store the most complete and up-to-date secondary mapping table. At the same time, the controller 120 will delete the secondary mapping table of L1[3] in the random write cache and / or read cache corresponding to L1[1]. At this time, L1[1] points to the hotspot cell d1 and cell b1 on storage medium 130. Thus, the hotspot cell stores the unique, latest, and most complete secondary mapping table corresponding to L1[1]. Subsequent read and write operations on the secondary mapping table of L1[1] are all based on hot cells, which reduces the loading and unloading operations of the secondary mapping table corresponding to L1[1]. In this case, the system can achieve read and write performance of L1[1] that is close to that of the DRAM scheme.
[0055] As the system runs, the access volume of L1[1] decreases. At a certain moment, L1[1] loses the right to use the hot cell. At this time, it is necessary to refresh the data of the hot cell occupied by L1[1] into the storage medium.
[0056] However, if, over time, the host does not continuously access L1[1] frequently, meaning L1[1] has not become a system hotspot, then the update of the secondary mapping table corresponding to L1[1] will be performed in the random write cache. When the storage space in the random cache is insufficient, it may be necessary to refresh the secondary mapping table corresponding to L1[1] to the storage medium and release the random write cell it occupies in the random cache, so that if the secondary mapping table corresponding to L1[1] needs to be accessed again, it will need to be imported from the storage medium into the cache unit.
[0057] Figures 5a to 5c It is a bar chart showing random write mode, short-term frequent write mode, and long-term frequent write mode. Figure 5a This indicates a sudden surge of writes to a specific secondary table. (Reference) Figures 5a to 5c As shown, according to this embodiment, only Figure 5c The secondary mapping table accessed frequently and evenly will be stored in the hot write cache for a long time, while the secondary mapping table corresponding to 5a will not reach the hot write cache. Figure 5bAlthough the corresponding secondary mapping table may reach the hot spot cache, it will not be persistent. However, once the corresponding period has passed, the hot spot cache will be lost. This method can improve read and write performance.
[0058] Optionally, for the number of write operations obtained based on write command statistics, a method similar to data filtering is used to smooth the statistical value, reducing the impact of a large amount of data written to a certain first-level table at any given time on the system hotspot value (because the host's writing to the SSD is sometimes only for a short period of time, such as when the system copies a large file and the data is concentrated in a certain first-level table, there may not be any more writes to that first-level table for a long time after the copy is completed, so it is desirable to exclude this situation from the system hotspot).
[0059] For each read command received by controller 120, controller 120 can first determine whether the corresponding secondary mapping table belongs to a system hotspot. If so, it can read the mapping relationship data from the corresponding hotspot cell; otherwise, it reads the secondary mapping table from the storage medium and loads it into a read unit, such as k1, of the read cache. If, over time, the corresponding secondary mapping table becomes a system hotspot, it reads from the hotspot cell. Furthermore, refer to... Figure 4 As shown, the read cache space is limited. As time goes by, the read cache may no longer be able to provide new cells. At this time, it is necessary to release read cells. To achieve this, the access volume of each secondary mapping table within a set time period can be accumulated according to the read command. When the read cache space is insufficient, read cells with low access volume can be released first in order of ascending access volume.
[0060] In some embodiments, the controller 120 stores the secondary mapping table before reading it from the storage medium and storing it in the read unit. A compression ratio that can be set to compress all secondary mapping tables can be defined. This compression ratio is then multiplied by the size of a fixed-size read cell on the storage medium to obtain the size of the fixed-size read cell. Alternatively, non-fixed-size read cells can be dynamically allocated or allocated in the read cache based on the size of the compressed secondary mapping table to store it.
[0061] like Figure 6 As shown, an exemplary compression method includes the following steps.
[0062] In step S601, multiple physical addresses are divided into at least one segment based on whether they are numerically consecutive.
[0063] In step S602, the number of physical addresses contained in each segment of at least one segment is counted.
[0064] In step S603, storing multiple physical addresses is replaced by storing the starting physical address of each segment and the number of physical addresses contained in it, which is the same as storing at least one segment.
[0065] As mentioned above, a two-level mapping table can store a logical starting address and its corresponding multiple physical addresses. After reading the two-level mapping table from the storage medium, the data can be compressed by dividing the multiple physical addresses into multiple segments. Each segment can contain one or more physical addresses, but if it contains multiple physical addresses, these addresses must be numerically consecutive. For example, a segment might contain numerically consecutive physical addresses FAA and FAA+1. After obtaining several such segments, the number of physical addresses contained in each segment is counted. Then, in the cache unit, the storage method changes from storing all physical addresses to storing the starting physical address of each of the segments and the number of physical addresses it contains.
[0066] For illustration, this example uses decimal numbers to represent physical addresses. Assume there are 2048 physical addresses; the first 444 are:
[0067] 100,101,102,103,104,105,106,107,108,109,110,125,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280, 281,282,283,284,285,600,601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,...................,811,300,301,302,303,...................,499.
[0068] Scanning the addresses sequentially, addresses 1 through 11 are numerically consecutive and are grouped into the first segment, starting at physical address 100, with 11 addresses in the first segment. Address 12 is not consecutive and is grouped into the second segment, starting at physical address 125, with 1 address in the second segment. Addresses 12 through 42 are consecutive and are grouped into the third segment, starting at physical address 255, with 31 addresses in the third segment. Address 43 is not consecutive and is grouped into the fourth segment, starting at physical address 600, with 212 addresses in the fourth segment. Address 254 is not consecutive and is grouped into the fifth segment, starting at physical address 300, with 200 addresses in the fifth segment, and so on. The starting physical addresses and the number of addresses for each of the first to fifth segments are then stored in the flash memory.
[0069] However, it should be noted that this method does not always save storage space. For example, if the multiple physical address values stored in the secondary mapping table are not contiguous, this storage method may actually increase storage space. Therefore, another compression method is provided, such as... Figure 7 As shown, the steps include the following.
[0070] In step S701, multiple physical addresses are divided into at least one segment based on whether they are numerically consecutive. This step will result in at least one segment. If a segment contains two or more physical addresses, then the physical addresses contained in that segment are numerically consecutive.
[0071] In step S702, the number of physical addresses contained in each segment of at least one segment is counted.
[0072] In step S703, the required storage space for each of the two storage methods is calculated. The new storage method stores the starting physical address of each segment of at least one segment and the number of physical addresses it contains, while the original storage method stores all physical addresses.
[0073] In step S704, it is determined whether the space required by the new storage method is less than the space required by the original storage method. If so, step S705 is executed.
[0074] In step S705, storing multiple physical addresses is replaced by storing the starting physical address of each segment and the number of physical addresses contained in at least one segment.
[0075] Compared with the embodiment in Figure 5, this embodiment adds a judgment step, and the new storage method is used to replace the old storage method only when the space required by the new storage method is greater than that required by the original storage method.
[0076] In the above embodiments, by compressing the secondary mapping table of the read command cache, the space occupied by the cache unit 124 can be reduced. For example, in some cases, the above compression algorithm can reduce the space occupied by a secondary mapping table in the cache unit 124 by 60%.
[0077] In a further embodiment, although the multiple secondary mapping tables stored in the read cache can be stored in cells of the same size, the sizes of the compressed secondary mapping tables may not be the same. Therefore, it is not necessary to use cells of the same size for storage. Instead, cells of different sizes can be used for storage. At the same time, a linked list can be used for organization, with each node in the linked list corresponding to a secondary mapping table, and each node connected to the next node.
[0078] In a further embodiment, the access volume of each secondary mapping table in the read cache within a set time period is counted, and the storage space of the read cache is managed according to the access volume. For example, when the capacity of the read cache is exhausted, the cell used by the secondary mapping table with the least access volume is used to cache the new secondary mapping table.
[0079] Furthermore, as mentioned above, when the controller 120 receives a write command, if it finds that the corresponding index address has become a system hotspot and the secondary mapping table it points to has been cached in the read cache, the controller 120 needs to copy the secondary mapping table from the read cache to the hotspot cell. If the secondary mapping table in the read cache has been compressed using the compression method described above, it needs to be decompressed. The decompression involves restoring the starting physical address of each segment of at least one segment and the number of physical addresses contained therein to multiple physical addresses. The decompression method can be given in conjunction with the compression method, which will not be described in detail here.
[0080] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A cache management method applied to a memory, the memory including a controller and a storage medium, the controller including a cache unit, the cache unit storing a first-level mapping table, the first-level mapping table storing multiple index addresses to point to multiple second-level mapping tables stored on the storage medium, the cache management method being executed by the controller, including: The cache unit is divided into a hotspot write cache and a random write cache; The number of write operations corresponding to each index address in the first-level mapping table is accumulated within a set time period. The index addresses in the first-level mapping table are sorted from largest to smallest according to the number of write operations corresponding to each index address, and the index addresses with the highest number of write operations are recorded as system hotspots. For a received write command, if its corresponding index address belongs to a system hotspot, a hotspot cell is allocated in the hotspot write cache, and all data of the secondary mapping table pointed to by the corresponding index address is loaded into the hotspot cell; otherwise, a random write cell is allocated in the random write cache, and data is written into the random write cell based on the write command.
2. The cache management method according to claim 1 further includes: A read cache is further partitioned on the cache unit, and when a read command is received, a read cell is allocated from the read cache to load the secondary mapping table pointed to by the corresponding index address.
3. The cache management method according to claim 2, wherein, For a received write command, if its corresponding index address is a system hotspot, but the secondary mapping table pointed to by its corresponding index address is scattered and stored in at least one of the random write cache, the read cache, and the storage medium, then data is read from at least one of the random write cache, the read cache, and the storage medium and merged into the hotspot cell.
4. The cache management method according to claim 2, wherein, In the step of allocating a read cell from the read cache to load the secondary mapping table pointed to by the corresponding index address, the secondary mapping table pointed to by the corresponding index address is also compressed.
5. The cache management method according to claim 4, wherein, A fixed-size read cell is allocated on the cache unit to store the compressed secondary mapping table.
6. The cache management method according to claim 4, wherein, In the read cache, read cells of non-fixed size are allocated according to the size of the compressed secondary mapping table to store the compressed secondary mapping table.
7. The cache management method according to claim 2 further includes: In the read cache, the access volume of each secondary mapping table within a set time period is accumulated, and when the read cache space is insufficient, the read cells with low access volume are released first in order of ascending access volume.
8. The cache management method according to claim 1 further includes: Perform data smoothing on the cumulative number of write operations based on write commands.
9. The cache management method according to any one of claims 1 to 8, wherein, The storage device is a DRAM-less solid-state drive.
10. A memory comprising: A controller, connected to a host, is used to receive write data from the host; A storage medium, connected to the controller, is used to store the write data. The controller further includes a cache unit for storing a first-level mapping table corresponding to the written data, and the storage medium is further used to store mapping table data corresponding to the first-level mapping table. The controller is used to execute the cache management method according to any one of claims 1-9.