Drive circuit and display panel

Abstract

This invention discloses a driving circuit and a display panel. By setting the driving circuit to include at least one compensation capacitor connected in parallel with the storage capacitor, the capacitance value of the storage capacitor is increased, which is equivalent to increasing the charge storage capacity of the storage capacitor. This makes the gate voltage of the transistor connected to the electrode plate of the storage capacitor more stable, thereby improving the display quality of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving circuit and a display panel. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for the quality of screen display.

[0003] The display panel includes a driving circuit, which includes a storage capacitor for storing electrical charge.

[0004] However, in the existing technology, there is a problem that the storage capacitor has a relatively small charge storage capacity. Summary of the Invention

[0005] This invention provides a driving circuit and a display panel to increase the storage capacitor in the driving circuit, thereby improving the charge storage capacity and enhancing the display quality.

[0006] In a first aspect, embodiments of the present invention provide a driving circuit, including at least two transistors, a storage capacitor and at least one compensation capacitor, wherein the storage capacitor is electrically connected to the gate of at least one transistor and is used to store the gate potential of the connected transistor; at least one compensation capacitor is connected in parallel with the storage capacitor.

[0007] Optionally, the vertical distance between the two plates of the compensation capacitor is smaller than the vertical distance between the two plates of the storage capacitor.

[0008] Optionally, at least two transistors are vertically stacked; in a first direction, the orthographic projections of the vertically stacked at least two transistors at least partially overlap; wherein the first direction is the direction in which the at least two transistors are vertically stacked.

[0009] The optional driving circuit also includes a shielding structure, which is connected to a fixed voltage signal; in the first direction, the shielding structure is located between adjacent transistors.

[0010] The shielding structure is projected orthogonally in a first direction, and the gates of the transistors on both sides of the shielding structure are projected orthogonally in a first direction at least partially; wherein the transistors on both sides of the shielding structure are transistors located on both sides of the shielding structure in the first direction.

[0011] Optionally, the orthographic projections of the active layers of at least two transistors in the first direction at least partially overlap.

[0012] Optionally, the driving circuit includes a first compensation capacitor; the first compensation capacitor includes a first plate and a second plate, and the storage capacitor includes a third plate and a fourth plate;

[0013] The third electrode plate is reused as the first electrode plate or electrically connected to the first electrode plate; in the first direction, the second electrode plate and the fourth electrode plate are located on the same side or opposite side of the first electrode plate, and the second electrode plate and the fourth electrode plate are electrically connected.

[0014] And / or,

[0015] The driving circuit includes a second compensation capacitor, which includes a fifth plate and a sixth plate; the fifth plate is electrically connected to the third plate and is located between the third plate and the fourth plate, and the fourth plate is reused as the sixth plate.

[0016] Optionally, the driving circuit includes a pixel circuit, which includes a driving transistor and at least one switching transistor; the driving transistor and at least one switching transistor are arranged in a vertically stacked configuration.

[0017] Optionally, the pixel circuit includes a switching transistor and a data writing transistor, the gate of the data writing transistor being connected to the scan line, the first terminal of the data writing transistor being connected to the data line, and the second terminal of the data writing transistor being connected to the gate of the driving transistor.

[0018] The first electrode of the driving transistor is connected to the first power supply line, the second electrode of the driving transistor is connected to the first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to the second power supply line.

[0019] Optionally, the shielding structure is electrically connected to the first power line or the second power line;

[0020] Optionally, when the shielding structure is connected to the first power line, the shielding structures of different pixel circuits are interconnected in a set direction, wherein the set direction intersects with the extension direction of the first power line.

[0021] Optionally, both the first power line and the data line extend along the second direction; the active layer of the driving transistor includes a first active portion, a second active portion, and a third active portion, the second active portion connecting the first active portion and the third active portion, the first active portion and the third active portion extending along the second direction, the second active portion extending along the third active direction, the second direction intersecting the third active direction and both being perpendicular to the first direction; in the first direction, the orthographic projection of the third active portion is located between the orthographic projections of the first power line and the data line;

[0022] In the first direction, the orthographic projections of the first active portion and the first power line at least partially overlap; the first active portion is electrically connected to the first power line, and the third active portion is electrically connected to the first electrode of the light-emitting device.

[0023] The active layer of the data writing transistor includes a fourth active portion and a fifth active portion. The fourth active portion extends along a second direction, and the fifth active portion extends along a third direction. In the first direction, the orthographic projections of the fourth active portion and the third active portion at least partially overlap. The fourth active portion is electrically connected to the gate of the driving transistor, and the fifth active portion is electrically connected to the data line.

[0024] Optionally, the scan line extends along a third direction, and in the first direction, the orthographic projection of the scan line overlaps with the orthographic projections of the first active part and the fourth active part.

[0025] Optionally, the first active part is electrically connected to the first power line through a first via, the third active part is electrically connected to the first electrode of the light-emitting device through a second via, the fourth active part is electrically connected to the gate of the driving transistor through a third via, and the fifth active part is electrically connected to the data line through a fourth via.

[0026] Optionally, the pixel circuit also includes a substrate, with the driving transistor located between the substrate and the switching transistor;

[0027] Optionally, the driving transistor can be a bottom-gate structure or a top-gate structure, and the switching transistor can be a top-gate structure;

[0028] Optionally, the gate of the driving transistor is multiplexed as a first plate and a third plate;

[0029] The driving transistor includes an N-type transistor, the first electrode of the light-emitting device is multiplexed as the fourth electrode, and the first electrode of the light-emitting device is located on the side of the switching transistor away from the driving transistor; the second electrode is electrically connected to the fourth electrode and is located between the gate and the substrate of the driving transistor.

[0030] The first electrode of the light-emitting device is reused as the sixth electrode of the second compensation capacitor, and the fifth electrode is electrically connected to the first and second electrodes of the switching transistor; optionally, the fifth electrode is electrically connected to the second electrode of the data writing transistor.

[0031] Alternatively, the driving transistor includes a P-type transistor, with a shielding structure electrically connected to the first power line, the shielding structure serving as a second electrode; and a fourth electrode electrically connected to the first power line.

[0032] Optionally, the pixel circuit also includes a substrate, with the switching transistor located between the substrate and the driving transistor;

[0033] Optionally, the driving transistor can be a bottom-gate structure or a top-gate structure, and the switching transistor can be a top-gate structure;

[0034] Optionally, the gate of the driving transistor is multiplexed as a first plate and a third plate, the second plate is electrically connected to the fourth plate, and the second plate is located between the fourth plate and the first plate;

[0035] The driving transistor includes an N-type transistor, and the first electrode of the light-emitting device is multiplexed as a fourth electrode plate. The first electrode of the light-emitting device is located on the side of the driving transistor away from the switching transistor.

[0036] The first electrode of the light-emitting device is reused as the sixth electrode of the second compensation capacitor, and the fifth electrode is electrically connected to the first and second electrodes of the switching transistor; optionally, the fifth electrode is electrically connected to the second electrode of the data writing transistor.

[0037] Optionally, the orthographic projections of the fifth electrode plate and the second electrode plate on the substrate overlap;

[0038] Alternatively, the driving transistor may include a P-type transistor, with a shielding structure electrically connected to the first power line, and the shielding structure serving as a second electrode; or a fourth electrode may be electrically connected to the first power line.

[0039] Optionally, conductive structures located in different layers are electrically connected through vias filled with conductive material;

[0040] Optionally, the driving circuit also includes a via protection structure, which is located in a metal layer between the active layer of the transistor and the substrate, and the conductive material in the via is electrically connected to the via protection structure.

[0041] Optionally, the driving circuit includes a gate driving circuit, which includes a plurality of switching transistors, with at least two switching transistors stacked vertically.

[0042] The gate drive circuit includes at least one fixed potential input terminal, and the shielding structure is electrically connected to the fixed potential input terminal.

[0043] Secondly, embodiments of the present invention also provide a display panel, including the driving circuit of the first aspect.

[0044] The driving circuit and display panel of the present invention, by setting the driving circuit to include at least one compensation capacitor connected in parallel with the storage capacitor, effectively increase the capacitance value of the storage capacitor, that is, increase the charge storage capacity of the storage capacitor, so that the gate voltage of the transistor connected to the electrode plate of the storage capacitor can be more stable, thereby improving the display quality of the display panel. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention.

[0046] Figure 2 This is a top view of a driving circuit provided in an embodiment of the present invention;

[0047] Figure 3 yes Figure 2 Schematic diagram of each conductive structural layer in the middle;

[0048] Figure 4 yes Figure 2 A sectional view obtained by cutting along AA';

[0049] Figure 5 yes Figure 2 Sectional view obtained by cutting along BB'

[0050] Figure 6 yes Figure 2 A sectional view obtained by cutting along CC';

[0051] Figure 7 This is a top view of another driving circuit provided in an embodiment of the present invention;

[0052] Figure 8 yes Figure 7 Schematic diagram of each conductive structural layer in the middle;

[0053] Figure 9 yes Figure 7 A sectional view obtained by cutting along DD';

[0054] Figure 10 yes Figure 7 A sectional view obtained by cutting along EE';

[0055] Figure 11 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0056] Figure 12 This is a top view of another driving circuit provided in an embodiment of the present invention;

[0057] Figure 13 yes Figure 12 Schematic diagram of each conductive structural layer in the middle;

[0058] Figure 14 yes Figure 12 A sectional view obtained by cutting along FF';

[0059] Figure 15 yes Figure 12 A cross-sectional view obtained by cutting along HH';

[0060] Figure 16 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0061] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0062] As described in the background section, existing technologies suffer from a problem with the limited charge storage capacity of storage capacitors. This is because the size of the storage capacitor directly affects its charge storage capacity. The charge storage capacity of a storage capacitor is positively correlated with its size; that is, the larger the storage capacitor, the stronger its charge storage capacity, and vice versa. In existing technologies, a single transistor in a driving circuit is typically connected to only one storage capacitor, and the capacitance value cannot be made very large, thus limiting the charge storage capacity. When the driving circuit is a pixel circuit, a small storage capacity of the storage capacitor can easily cause flickering on the display panel. When the driving circuit provides a driving signal to the pixel circuit, a small storage capacity of the storage capacitor can lead to instability in the driving signal provided to the pixel circuit, affecting its normal operation and consequently impacting the image display quality.

[0063] For the reasons stated above, embodiments of the present invention provide a driving circuit. Figure 1 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention, for reference. Figure 1 The driving circuit includes at least two transistors 100, a storage capacitor 200 and at least one compensation capacitor 300. The storage capacitor 200 is electrically connected to the gate of at least one transistor 100 and is used to store the gate potential of the connected transistor 100. The at least one compensation capacitor 300 is connected in parallel with the storage capacitor 200.

[0064] The driving circuit can be the pixel circuit in the display panel. Figure 1 The schematic diagram illustrates the structure of a pixel circuit as the driving circuit, and Figure 1 The illustration shows a driving circuit comprising two transistors 100. In other alternative embodiments of the invention, the driving circuit may include more transistors 100. The display panel may also be a circuit in the display panel that outputs driving signals to the pixel circuit. Exemplarily, the driving circuit may be a gate driving circuit for providing a gate driving signal, wherein when the gate driving signal is a scan signal, the gate driving circuit is a scan circuit; and when the gate driving signal is a light emission control signal, the driving circuit is a light emission control driving circuit.

[0065] Continue to refer to Figure 1The driving circuit also includes a storage capacitor 200 and at least one compensation capacitor 300, wherein the at least one compensation capacitor 300 is connected in parallel with the storage capacitor 200. This effectively increases the capacitance value of the storage capacitor 200, thereby increasing its charge storage capacity and making the gate voltage of the transistor 100 connected to the storage capacitor 200 more stable. When the driving circuit is a pixel circuit, it can improve screen flicker; when the driving circuit is a circuit that provides a driving signal to the pixel circuit, it can provide a more stable driving signal to the pixel circuit, thus enabling the pixel circuit to function normally.

[0066] In this embodiment, the driving circuit includes at least one compensation capacitor connected in parallel with the storage capacitor, which effectively increases the capacitance value of the storage capacitor, i.e., increases the charge storage capacity of the storage capacitor. This makes the gate voltage of the transistor connected to the electrode plate of the storage capacitor more stable, thereby improving the display quality of the display panel.

[0067] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0068] Optionally, the vertical distance between the two plates of the compensation capacitor is smaller than the vertical distance between the two plates of the storage capacitor.

[0069] The capacitance value is negatively correlated with the vertical distance between the two plates of the capacitor. All other factors affecting capacitance are equal, a larger vertical distance between the two plates results in a smaller capacitance value, and vice versa. In this embodiment, the vertical distance between the two plates of the compensation capacitor is smaller than that between the two plates of the storage capacitor. This allows the compensation capacitor to easily achieve a larger capacitance value. Therefore, when the storage capacitor is connected in parallel with the compensation capacitor, the capacitance value of the storage capacitor is significantly increased, which is more conducive to improving charge storage capacity and thus improving image display quality.

[0070] As demands for image display quality increase, so does the need for high-resolution display products. This necessitates pixel size compression, and consequently, the size of the driving circuit must also be reduced. Based on this, the present invention proposes a structure in which at least some circuit components are vertically stacked in the driving circuit. Figure 2 This is a top view of a driving circuit provided in an embodiment of the present invention. Figure 3 yes Figure 2A schematic diagram of the structure of each conductive layer in the diagram, wherein... Figure 3 Will Figure 2 The conductive structural layers are shown in order from bottom to top. Figure 4 yes Figure 2 The sectional view obtained by cutting along AA' Figure 5 yes Figure 2 The sectional view obtained by cutting along BB', see reference. Figures 2-5 Optionally, at least two transistors 100 are arranged to be vertically stacked; in a first direction x1, the orthographic projections of the vertically stacked at least two transistors 100 have at least partial overlap; wherein the first direction x1 is the direction in which the at least two transistors 100 are vertically stacked.

[0071] Specifically, at least two transistors 100 in the driving circuit are vertically stacked, and along the first direction x1 of the vertical stacking of the at least two transistors 100, the orthographic projections of the vertically stacked at least two transistors 100 overlap at least partially. This reduces the orthographic projection area of ​​the entire driving circuit in the first direction x1 relative to the flat arrangement of each circuit device in the driving circuit, which in turn reduces the plane area occupied by the entire driving circuit. This, in turn, reduces the size of the driving circuit and is beneficial for achieving a high-resolution display panel structure.

[0072] Figure 6 yes Figure 2 The sectional view obtained by cutting along CC', continue to refer to Figures 2-6 Optionally, the driving circuit also includes a shielding structure 400, which is connected to a fixed voltage signal; in the first direction x1, the shielding structure is between adjacent transistors 100; the orthographic projection of the shielding structure 400 in the first direction x1 covers at least a portion of the orthographic projection of the gates of the transistors 100 on both sides of the shielding structure 400 in the first direction x1; wherein, the transistors 100 on both sides of the shielding structure 400 are transistors 100 located on both sides of the shielding structure 400 in the first direction x1.

[0073] Specifically, in the driving circuit, the signals connected to the gates of different transistors 100 are usually different. When at least two transistors 100 are vertically stacked, the signals connected to different transistors 100 may interfere with each other, affecting the normal operation of the driving circuit. Furthermore, when at least two transistors 100 in the driving circuit are vertically stacked, the distance between the gate of one transistor 100 and the active layer of another transistor 100 in the first direction x1 may be small, causing the original single-gate transistor 100 to become a dual-gate transistor 100 structure, similarly affecting the normal operation of the driving circuit. To avoid the aforementioned problems, in this embodiment, the driving circuit includes a shielding structure 400, which is positioned between adjacent transistors 100 in the first direction x1. The orthographic projection of the shielding structure 400 in the first direction x1 covers the orthographic projection of the gates of the transistors 100 on both sides of the shielding structure 400 in the first direction x1. Furthermore, the shielding structure 400 is connected to a fixed voltage signal. This ensures that changes in the gate potential of the transistors 100 on one side of the shielding structure 400 do not affect the gate potential of the transistors 100 on the other side of the shielding structure 400. It also prevents the original single-gate transistors 100 from becoming dual-gate transistors 100. Thus, while reducing the size of the driving circuit, it ensures that the vertically stacked transistors 100 in the driving circuit do not interfere with each other, guaranteeing the normal operation of the driving circuit.

[0074] in, Figures 2-6 The driving circuit shown is Figure 1 The driving circuit shown corresponds to... Figures 2-6 This schematically illustrates a drive circuit that includes two compensation capacitors. (Refer to...) Figures 1-6 The driving circuit includes a driving transistor 110. The source of the driving transistor 110 is connected to a first power supply line VDD, and the drain of the driving transistor 110 is connected to the first electrode of the light-emitting device 500. The second electrode of the light-emitting device 500 is connected to a second power supply line VSS. The signal connected to the first power supply line VDD is a fixed first power supply voltage, and the signal connected to the second power supply line VSS is a fixed second power supply voltage. The shielding structure 400 can be electrically connected to either the first power supply line VDD or the second power supply line VSS. This configuration eliminates the need for an additional power supply to provide a fixed voltage signal to the shielding structure 400 and a signal line to transmit that signal in the display panel, simplifying the wiring of the display panel and allowing for further reduction in the size of the driving circuit. Figure 6 The schematic diagram of the driving circuit structure shows the driving circuit structure in which the shielding structure 400 is connected to the first power line VDD.

[0075] Continue to refer to Figures 2-6Transistor 100 includes an active layer. Optionally, the orthographic projections of the active layers of at least two transistors 100 in the first direction x1 at least partially overlap. This configuration can further reduce the orthographic projection area of ​​the entire driving circuit in the first direction x1, that is, reduce the planar area occupied by the entire driving circuit, thereby reducing the size of the driving circuit and making it more conducive to realizing a high-resolution display panel structure. The active layer of the driving transistor 110 is designated as the first active layer 112, and the active layer of the switching transistor 120 is designated as the second active layer 122.

[0076] Continue to refer to Figures 2-6 Optionally, the driving circuit includes a first compensation capacitor 310; the first compensation capacitor 310 includes a first electrode 311 and a second electrode 312, and the storage capacitor 200 includes a third electrode 210 and a fourth electrode 220.

[0077] The third electrode plate 210 is reused as the first electrode plate 311 or electrically connected to the first electrode plate 311; in the first direction x1, the second electrode plate 312 and the fourth electrode plate 220 are located on the same side or opposite side of the first electrode plate 311, and the second electrode plate 312 and the fourth electrode plate 220 are electrically connected.

[0078] Specifically, when the third plate 210 of the storage capacitor 200 is reused as the first plate 311, there is no need to separately set the third plate 210 of the first compensation capacitor 310. This can reduce the film layer of the driving circuit required by additionally setting the third plate 210 of the first compensation capacitor 310 and / or the increased orthographic projection area of ​​the driving circuit in the first direction x1 required by additionally setting the third plate 210 of the first compensation capacitor 310, thereby further reducing the size of the circuit. When the third plate 210 is an additional structure electrically connected to the first plate 311, the film layer where the third plate 210 is located can be flexibly set, which is conducive to realizing a first compensation capacitor 310 with a larger capacitance value.

[0079] Depending on the stacking arrangement of transistors 100 in the driving circuit, and the connection relationship between storage capacitor 200 and compensation capacitor 300 and transistors 100, along the first direction x1, the second electrode plate 312 and the fourth electrode plate 220 can be disposed on the same side of the first electrode plate 311, or on opposite sides of the first electrode plate 311. The second electrode plate 312 and the fourth electrode plate 220 are electrically connected. This electrical connection can be achieved through a via structure, or by both the second electrode plate 312 and the fourth electrode plate 220 being connected to the same conductive structure indirectly to achieve their electrical connection.

[0080] Optionally, the driving circuit includes a second compensation capacitor 320, which includes a fifth plate 321 and a sixth plate 322. The fifth plate 321 is electrically connected to the third plate 210 and is located between the third plate 210 and the fourth plate 220. The fourth plate 220 is reused as the sixth plate 322.

[0081] Specifically, the fourth plate 220 of the storage capacitor 200 is reused as the sixth plate 322 of the second compensation capacitor 320. The fifth plate 321 is electrically connected to the third plate 210. In the first direction x1, the fifth plate 321 is located between the third plate 210 and the fourth plate 220. This ensures that the vertical distance between the fifth plate 321 and the sixth plate 322 is less than the vertical distance between the third plate 210 and the fourth plate 222. This allows the second compensation capacitor 320 to more easily have a larger capacitance value. After the second compensation capacitor 320 is connected in parallel with the storage capacitor 200, the capacitance value of the storage capacitor 200 can be significantly increased, thereby improving the charge storage capacity.

[0082] Continue to refer to Figures 1-6 Optionally, the driving circuit includes a pixel circuit, which includes a driving transistor 110 and at least one switching transistor 120; the driving transistor 110 and at least one switching transistor 120 are arranged in a vertically stacked configuration.

[0083] In the pixel circuit, the driving transistor 110 and the switching transistor 120 have different electrical characteristics. The driving transistor 110 has a larger channel length, resulting in a larger area of ​​its orthographic projection in the first direction x1, meaning it occupies a larger planar area. In this embodiment, the driving transistor 110 and at least one switching transistor 120 are arranged in a perpendicular stacked configuration. This ensures that the overlapping portion of the orthographic projections of the driving transistor 110 and the switching transistor 120 in the first direction x1 does not occupy additional planar area, which helps reduce the size of the pixel circuit and thus the pixel size, facilitating the realization of a high-resolution display panel structure.

[0084] Optionally, the pixel circuit includes a switching transistor 120 and a data writing transistor T0. The gate of the data writing transistor T0 is connected to the scan line SCAN. The first electrode of the data writing transistor T0 is connected to the data line VDATA. The second electrode of the data writing transistor T0 is connected to the gate of the driving transistor 110. The first electrode of the driving transistor 110 is connected to the first power line VDD. The second electrode of the driving transistor 110 is connected to the first electrode 510 of the light-emitting device 500. The second electrode of the light-emitting device 500 is connected to the second power line VSS.

[0085] In this embodiment, the data writing transistor T0 is turned on or off according to the scan signal transmitted on the scan line SCAN. When the data writing transistor T0 is on, the data voltage on the data line VDATA is transmitted to the gate of the driving transistor 110 through the data writing transistor T0. The driving transistor 110 can generate a driving current to output the light-emitting device 500 according to the voltage between its gate and the first electrode. The pixel circuit of this embodiment includes only two transistors 100, namely one data writing transistor T0 and one driving transistor 110. The smaller number of devices included in the pixel circuit is more conducive to realizing a small-sized pixel circuit, thereby realizing a high-resolution display panel structure, which can be applied to display products of virtual reality (VR), augmented reality (AR), and mixed reality (MR).

[0086] The signal transmitted on the first power line VDD is a fixed first power supply voltage, and the signal transmitted on the second power line VSS is a fixed second power supply voltage. As described above, optionally, the shielding structure 400 is electrically connected to the first power line VDD or the second power line VSS, which simplifies the wiring of the display panel and is beneficial to further reduce the size of the driving circuit.

[0087] Based on the above technical solution, optionally, when the shielding structure 400 is connected to the first power line VDD, the shielding structures 400 of different pixel circuits are connected to each other in a set direction, wherein the set direction intersects with the extension direction of the first power line VDD.

[0088] Specifically, the pixel circuits are arranged in an array in the display panel, with the first power line VDD extending along the column direction of the pixel circuit array. The shielding structures 400 of the pixel circuits in the same row are interconnected, that is, the shielding structures 400 are interconnected in the row direction of the pixel circuit array (i.e., the set direction is the row direction of the entire column of pixel circuits), so that the shielding structures 400 and the first power line VDD are interconnected to form a mesh structure, which is equivalent to reducing the resistance of the first power line VDD, thereby helping to reduce the voltage drop when the first power line VDD transmits the first power supply voltage, thus improving the uniformity of the image display and further improving the image display quality.

[0089] Continue to refer to Figures 2-6 Optionally, the pixel circuit also includes a substrate 600, with a driving transistor 110 located between the substrate 600 and the switching transistor 120.

[0090] Specifically, the driving transistor 110 in the pixel circuit generates a driving current, thereby driving the light-emitting device 500 to emit light, enabling the display panel to display. Higher requirements are placed on the electrical properties and uniformity of the driving transistor 110 in the display panel. In this embodiment, based on the vertical stacking of at least two transistors 100 in the pixel circuit, the driving transistor 110 is positioned between the substrate 600 and the switching transistor 120. That is, the film layer containing the driving transistor 110 is located between the substrate 600 and the film layer containing the switching transistor 120. A patterned film layer may not be provided between the driving transistor 110 and the substrate 600; that is, the film layer on the side of the driving transistor 110 closest to the substrate 600 can be a flat film layer, or the driving transistor 110 can be directly fabricated on the flat substrate 600. This allows for better electrical properties and uniformity of the driving transistor 110, thereby improving the display image quality.

[0091] Based on the above technical solution, optionally, the driving transistor 110 is a bottom-gate structure or a top-gate structure, and the switching transistor 120 is a top-gate structure. In other optional embodiments of the present invention, the switching transistor 120 may also be a bottom-gate structure, and the present invention does not specifically limit this. The top-gate or bottom-gate structure of the driving transistor 110 and the switching transistor 120 can be specifically set according to actual needs.

[0092] Continue to refer to Figures 2-6 Optionally, the driving transistor 110 includes an N-type transistor 100, and the driving circuit includes a first compensation capacitor 310. The gate of the driving transistor 110 is multiplexed as a first electrode 311 and a third electrode 210. The first electrode 510 of the light-emitting device 500 is multiplexed as a fourth electrode 220, and the first electrode 510 of the light-emitting device 500 is located on the side of the switching transistor 120 away from the driving transistor 110. The second electrode 312 is electrically connected to the fourth electrode 220, and the second electrode 312 is located between the gate of the driving transistor 110 and the substrate 600. The first electrode 510 of the light-emitting device 500 is the anode of the light-emitting device 500, and the second electrode of the light-emitting device 500 is the cathode of the light-emitting device 500.

[0093] In the pixel circuit, the gate area of ​​the driving transistor 110 is relatively large, which can be used as the electrode of a capacitor. In this embodiment, the gate of the driving transistor 110 is directly reused as the first electrode 311 and the third electrode 210, reducing the need for additional film structures for the first electrode 311 and the third electrode 210. This prevents the thickness of the vertically stacked driving circuit from becoming too thick, thereby reducing the size of the pixel circuit and improving the resolution while ensuring a relatively thin display panel. In the first direction x1, the distance between the third electrode 210 and the fourth electrode 220 of the storage capacitor 200 is relatively large, that is, the vertical distance between the third electrode 210 and the fourth electrode 220 of the storage capacitor 200 is relatively large, resulting in a smaller capacitance value of the storage capacitor 200. The second electrode 312 is electrically connected to the fourth electrode 220, forming a parallel structure between the first compensation capacitor 310 and the storage capacitor 200. The driving transistor 110 is a bottom-gate transistor 100. The driving transistor 110 is located between the switching transistor 120 and the substrate 600. The film layer between the driving transistor 110 and the substrate 600 is relatively small. The second electrode 312 is located between the gate of the driving transistor 110 and the substrate 600, which makes the distance between the second electrode 312 and the gate of the driving transistor 110 smaller, making it easier to realize a first compensation capacitor 310 with a larger capacitance value.

[0094] Continue to refer to Figures 2-6 Optionally, the driving circuit includes a second compensation capacitor 320, the first electrode 510 of the light-emitting device 500 is reused as the sixth electrode 322 of the second compensation capacitor 320, and the fifth electrode 321 is electrically connected to the first or second electrode of the switching transistor 120.

[0095] like Figure 5 As shown, the first electrode 510 of the light-emitting device 500 is reused as the fourth electrode 220 of the storage capacitor 200 and the sixth electrode 322 of the second compensation capacitor 320. The fifth electrode 321 is electrically connected to the first or second electrode of the switching transistor 120. The first electrode of the switching transistor 120 can be either the source or the drain, and the second electrode can be either the drain or the source. In this embodiment, the driving transistor 110 is located between the substrate 600 and the switching transistor 120, and the light-emitting device 500 is located on the side of the switching transistor 120 away from the substrate 600. Therefore, the switching transistor 120 is closer to the first electrode 510 of the light-emitting device 500 than the driving transistor 110. The first and second electrodes of the switching transistor 120 are closer to the first electrode 510 of the light-emitting device 500 than the gate of the driving transistor 110. Therefore, the second compensation capacitor 320 can easily have a larger capacitance value than the storage capacitor 200, so that when the second compensation capacitor 320 is connected in parallel with the storage capacitor 200, the capacitance value of the storage capacitor 200 is effectively increased. Furthermore, corresponding to... Figures 2-6The driving circuit shown is such that the driving transistor 110 is located between the substrate 600 and the switching transistor 120, and the driving transistor 110 is the bottom gate and the switching transistor 120 is the top gate. The first electrode and the second electrode of the switching transistor 120 are respectively the metal layers that form the metal layers of the transistor 100 and the capacitor that are closest to the first electrode 510 of the light-emitting device 500, making it easier for the second compensation capacitor 320 to achieve a larger capacitance value.

[0096] Optionally, the fifth electrode 321 is electrically connected to the second electrode of the data writing transistor T0. In some embodiments of the present invention, the lead-out structure of the fifth electrode 321 and the second electrode of the data writing transistor T0 is an integral structure. In this case, during the fabrication of the driving circuit, the fifth electrode 321 and the lead-out structure of the second electrode of the data writing transistor T0 can be fabricated as a single pattern, which simplifies the mask structure and fabrication process.

[0097] Figure 7 This is a top view of another driving circuit provided in an embodiment of the present invention. Figure 8 yes Figure 7 A schematic diagram of the structure of each conductive layer in the diagram, wherein... Figure 8 Will Figure 7 The conductive structural layers are shown in order from bottom to top. Figure 9 yes Figure 7 The sectional view obtained by cutting along DD' Figure 10 yes Figure 7 A sectional view obtained by cutting along EE'. Wherein, Figures 7-10 The driving circuit shown can be used with Figure 1 To correspond, Figures 7-10 An example is shown where the drive circuit includes two compensation capacitors. (Reference) Figures 7-10 Optionally, in this driving circuit, the pixel circuit also includes a substrate 600, with the switching transistor 120 located between the substrate 600 and the driving transistor 110. That is, the switching transistor 120 is closer to the substrate 600 than the driving transistor 110.

[0098] Based on the above technical solution, optionally, the driving transistor 110 is a bottom-gate structure or a top-gate structure, and the switching transistor 120 is a top-gate structure. In other optional embodiments of the present invention, the switching transistor 120 may also be a bottom-gate structure, and the present invention does not specifically limit this.

[0099] refer to Figures 7-9Optionally, the driving circuit includes a first compensation capacitor 310, the gate of the driving transistor 110 is multiplexed as a first plate 311 and a third plate 210, the second plate 312 is electrically connected to the fourth plate 220, and the second plate 312 is located between the fourth plate 220 and the first plate 311; the driving transistor 110 includes an N-type transistor 100, the first electrode 510 of the light-emitting device 500 is multiplexed as the fourth plate 220, and the first electrode 510 of the light-emitting device 500 is located on the side of the driving transistor 110 away from the switching transistor 120.

[0100] As described in the above embodiments, the gate of the driving transistor 110 is directly reused as the first electrode 311 and the third electrode 210, reducing the need for additional film structures for the first electrode 311 and the third electrode 210, thus preventing the vertical stacking thickness of the driving circuit from becoming excessive. In this embodiment, the second electrode 312 is electrically connected to the fourth electrode 220, and the second electrode 312 is located before the fourth electrode 220 and the first electrode 311. This ensures that the vertical distance between the first electrode 311 and the second electrode 312 of the first compensation capacitor 310 is less than the vertical distance between the third electrode 210 and the fourth electrode 220 of the storage capacitor 200, making it easier for the first compensation capacitor 310 to achieve a larger capacitance value compared to the storage capacitor 200. When the driving transistor 110 is an N-type transistor 100, the first electrode 510 of the light-emitting device 500 is reused as the fourth electrode 220, reducing the need for additional film structures for the fourth electrode 220, further facilitating the thinning of the display panel.

[0101] Continue to refer to Figures 7-10 Optionally, the first electrode 510 of the light-emitting device 500 is reused as the sixth electrode 322 of the second compensation capacitor 320, and the fifth electrode 321 is electrically connected to the first or second electrode of the switching transistor 120. The beneficial effects of this arrangement are... Figure 5 In the driving circuit structure shown, the first electrode 510 of the light-emitting device 500 is reused as the sixth electrode 322 of the second compensation capacitor 320. The fifth electrode 321 is electrically connected to the first or second electrode of the switching transistor 120, which has the same beneficial effect and will not be described in detail here.

[0102] Optionally, the fifth electrode 321 is electrically connected to the second electrode of the data writing transistor T0. In some optional embodiments of the present invention, the fifth electrode 321 and the second electrode of the data writing transistor T0 are integrally formed.

[0103] refer to Figures 6-8The fifth electrode 321 and the second electrode 312 overlap in their orthogonal projections onto the substrate 600. This arrangement allows the second electrode 312 and the fifth electrode 321 to form another compensation capacitor, in addition to the structures of the first compensation capacitor 310 and the second compensation capacitor 320. This effectively increases the storage capacitor 200, further enhancing its charge storage capacity. Furthermore, the compensation capacitor formed by the overlap of the fifth electrode 321 and the second electrode 312 is added to the existing first compensation capacitor 310 and the second compensation capacitor 320 in the driving circuit. No new film layer structure is required, thus further enhancing the charge storage capacity without increasing the thickness of the driving circuit, ensuring a relatively thin and light display panel.

[0104] Figure 11 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention. Figure 12 This is a top view of another driving circuit provided in an embodiment of the present invention. Figure 13 yes Figure 12 A schematic diagram of the structure of each conductive layer in the diagram, wherein... Figure 13 Will Figure 12 The conductive structural layers are shown in order from bottom to top. Figure 14 yes Figure 12 A sectional view obtained by cutting along FF'. Figure 15 yes Figure 12 The sectional view obtained by cutting along HH', see reference. Figures 11-15 Optionally, in this driving circuit, the driving transistor 110 is located between the substrate 600 and the switching transistor 120, and both the driving transistor 110 and the switching transistor 120 are top-gate structures. The driving transistor 110 includes a P-type transistor 100, and the gate of the driving transistor 110 is multiplexed as a first plate 311 and a third plate 210. The shielding structure 400 is electrically connected to the first power line VDD and serves as a second plate 312; the fourth plate 220 is electrically connected to the first power line VDD.

[0105] To achieve shielding between the vertically stacked transistors 100, the shielding structure 400 has a relatively large area. Specifically, the orthographic projection of the shielding structure 400 onto the substrate 600 covers the orthographic projection of the gates of the transistors 100 on both sides of the shielding structure 400. Reusing the shielding structure 400 as the second electrode 312 reduces the need for additional film layers due to the additional second electrode 312. Furthermore, the sufficiently large area of ​​the shielding structure 400 allows for a larger capacitance value in the resulting compensation capacitor 300, thus effectively compensating for the capacitance value of the storage capacitor 200 and improving its charge storage capacity. The fourth electrode 220 can be on the same layer as the second electrode of the data writing transistor T0; in some optional embodiments, the fourth electrode 220 can be integrally formed with the second electrode of the data writing transistor T0.

[0106] Based on the above embodiments, optionally, both the first power line VDD and the data line VDATA extend along the second direction y1; the active layer (i.e., the first active layer 112) of the driving transistor 110 includes a first active portion 1121, a second active portion 1122, and a third active portion 1123. The second active portion 1122 connects the first active portion 1121 and the third active portion 1123. The first active portion 1121 and the third active portion 1123 extend along the second direction y1, and the second active portion 1122 extends along the third direction z1. The second direction y1 intersects the third direction z1 and is perpendicular to the first direction x1; in the first direction x1, the orthographic projection of the third active portion 1123 is located between the orthographic projections of the first power line VDD and the data line VDATA; in the first... In direction x1, the orthographic projections of the first active portion 1121 and the first power line VDD at least partially overlap; the first active portion 1121 is electrically connected to the first power line VDD, and the third active portion 1123 is electrically connected to the first electrode 510 of the light-emitting device 500; the active layer (i.e., the second active layer 122) of the data writing transistor T0 includes a fourth active portion 1221 and a fifth active portion 1222, the fourth active portion 1221 extends along the second direction y1, and the fifth active portion 1222 extends along the third direction z1; in the first direction x1, the orthographic projections of the fourth active portion 1221 and the third active portion 1123 at least partially overlap, the fourth active portion 1221 is electrically connected to the gate of the driving transistor 110, and the fifth active portion 1222 is electrically connected to the data line VDATA.

[0107] The orthographic projections of the first active portion 1121 and the first power line VDD at least partially overlap. The orthographic projection of the third active portion 1123 in the first direction x1 lies between the orthographic projections of the first power line VDD and the data line VDATA. This allows the driving circuit to occupy a smaller planar area, which is beneficial for reducing the size of the driving circuit and thus improving the resolution of the display panel. Furthermore, in this embodiment, the orthographic projections of the fourth active portion 1221 of the active layer in the data writing transistor T0 and the third active portion 1123 of the active layer in the driving transistor 110 in the first direction x1 overlap. This overlap of the orthographic projections of the active layers of the driving transistor 110 and the data writing transistor T0 in the first direction x1 further helps to reduce the size of the driving circuit.

[0108] Based on the above technical solution, optionally, the scan line SCAN extends along the third direction z1, and in the first direction x1, the orthographic projection of the scan line SCAN overlaps with the orthographic projections of the first active part 1121 and the fourth active part 1221.

[0109] Specifically, in the first direction x1, the orthographic projection of the scan line SCAN overlaps with the orthographic projection of the fourth active part 1221, forming a data writing transistor T0. The orthographic projection of the scan line SCAN overlaps with the orthographic projections of both the first active part 1121 and the fourth active part 1221. That is, the orthographic projection of the scan line SCAN in the first direction x1 overlaps with the orthographic projection of the driving circuit in the first direction x1. Compared to a structure where the scan line SCAN is located outside the driving circuit, this reduces the additional area occupied by the scan line SCAN, which is beneficial for further improving the resolution of the display panel. Specifically, when the data writing transistor T0 is a top-gate transistor 100, the layer containing the scan line SCAN is located on the side of the active layer of the data writing transistor T0 away from the substrate 600; when the data writing transistor T0 is a bottom-gate transistor 100, the layer containing the scan line SCAN is located on the side of the active layer of the data writing transistor T0 closer to the substrate 600.

[0110] Continue to refer to Figures 2-6 ,as well as Figures 11-15 Optionally, the first active part 1121 is electrically connected to the first power line VDD through the first via M1, the third active part 1123 is electrically connected to the first electrode of the light-emitting device through the second via M2, the fourth active part is electrically connected to the gate of the driving transistor through the third via M3, and the fifth active part is electrically connected to the data line VDATA through the fourth via M4.

[0111] Specifically, in the topology of the driving circuit, vias also occupy a certain area. In this embodiment, the first active part 1121 is electrically connected to the first power line VDD, the third active part 1123 is connected to the light-emitting device, the fourth active part is connected to the gate of the driving transistor, and the fifth active part is connected to the data line VDATA through a via, which reduces the number of vias in the driving circuit, thereby helping to further reduce the size of the driving circuit, thereby reducing the pixel size and improving the resolution.

[0112] Based on the above technical solution, optionally, the shielding structure 400 is electrically connected to the first power supply VDD through the fifth via M5, thereby further reducing the size of the drive circuit.

[0113] Based on the above technical solution, optionally, conductive structures located in different layers are electrically connected through vias filled with conductive material. The conductive structures include the active layer of transistor 100 and the metal layer in the driving circuit. The metal layer of the driving circuit includes the gate, first electrode, and second electrode of transistor 100, the plates of storage capacitor 200 and compensation capacitor 300, and various signal lines (including the first power line VDD, the second power line VSS, the data line VDATA, the scan line SCAN, etc.). The conductive structures in different layers are electrically connected through vias filled with conductive material.

[0114] Optionally, the driving circuit also includes a via protection structure 700, which is located in a metal layer between the active layer of the transistor 100 and the substrate 600, and the conductive material in the via is electrically connected to the via protection structure 700.

[0115] Specifically, an insulating layer is provided between any two adjacent conductive layers of the driving circuit. The material of the insulating layer can be inorganic or organic. When forming vias, the insulating layer needs to be etched. The via protection structure 700 prevents over-etching of the insulating layer during etching, thus avoiding over-etching.

[0116] The above embodiments describe the driving circuit including a pixel circuit. In other optional embodiments of the present invention, the driving circuit includes a gate driving circuit, which includes a plurality of switching transistors, with at least two switching transistors vertically stacked; the gate driving circuit includes at least one fixed potential input terminal, and a shielding structure is electrically connected to the fixed potential input terminal.

[0117] The gate driving circuit may include a high-level input terminal and a low-level input terminal, both of which are input voltages with fixed levels. In this embodiment, the shielding structure is electrically connected to the fixed-potential input terminal of the gate driving circuit. This eliminates the need for additional signal lines in the gate driving circuit due to the shielding structure, ensuring a smaller area occupied by the gate driving circuit. Since the gate driving circuit is located in the non-display area of ​​the display panel, its small area facilitates the achievement of a narrow bezel in the display panel.

[0118] This invention also provides a display panel. Figure 16 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel 10 includes the driving circuit of any of the above embodiments of the present invention and has the beneficial effects of the driving circuit of any of the above embodiments of the present invention, which will not be described again here. This display panel can be applied to... Figure 16 The same technology can be used in mobile phones, computers, or wearable display devices.

[0119] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A drive circuit characterized by comprising: The driving circuit comprises at least two transistors, a storage capacitor and at least one compensation capacitor, the storage capacitor is electrically connected with the gate of at least one of the transistors, and is used for storing the gate potential of the connected transistor; At least one of the compensation capacitors is connected in parallel with the storage capacitor; The at least two transistors are vertically stacked; in a first direction, the orthographic projections of the vertically stacked at least two transistors at least partially overlap; The first direction is the direction in which the at least two transistors are vertically stacked; the driving circuit further comprises a shielding structure, the shielding structure is connected to a fixed voltage signal; in the first direction, the shielding structure is between adjacent transistors; The driving circuit comprises a pixel circuit, the pixel circuit comprises a driving transistor and at least one switching transistor; the driving transistor and at least one of the switching transistors are vertically stacked; The first electrode of the driving transistor is connected to a first power line, the second electrode of the driving transistor is connected to the first electrode of a light emitting device, and the second electrode of the light emitting device is connected to a second power line; The shielding structure is electrically connected with the first power line or the second power line; When the shielding structure is connected with the first power line, the shielding structures of different pixel circuits are connected with each other in a set direction, and the set direction intersects with the extension direction of the first power line.

2. The drive circuit according to claim 1, characterized in that, The vertical distance between the two plates of the compensation capacitor is less than the vertical distance between the two plates of the storage capacitor.

3. The driving circuit of claim 2, wherein, The orthographic projection of the shielding structure in the first direction covers at least part of the orthographic projection of the gate of the transistor on both sides of the shielding structure in the first direction; wherein the transistors on both sides of the shielding structure are the transistors located on both sides of the shielding structure in the first direction.

4. The drive circuit according to claim 3, characterized in that, The orthographic projections of the active layers of the at least two transistors in the first direction at least partially overlap.

5. The drive circuit according to claim 3, characterized by The driving circuit comprises a first compensation capacitor; the first compensation capacitor comprises a first plate and a second plate, and the storage capacitor comprises a third plate and a fourth plate; The third plate is multiplexed as the first plate or is electrically connected with the first plate; in the first direction, the second plate and the fourth plate are located on the same side or on the opposite side of the first plate, and the second plate is electrically connected with the fourth plate; And / or, The driving circuit comprises a second compensation capacitor, the second compensation capacitor comprises a fifth plate and a sixth plate; the fifth plate is electrically connected with the third plate and located between the third plate and the fourth plate, and the fourth plate is multiplexed as the sixth plate.

6. The driving circuit of claim 5, wherein, The switching transistor of the pixel circuit comprises a data writing transistor, the gate of the data writing transistor is connected with a scan line, the first electrode of the data writing transistor is connected with a data line, and the second electrode of the data writing transistor is connected with the gate of the driving transistor.

7. The drive circuit according to claim 6, characterized in that, The first power line and the data line extend along a second direction; an active layer of the drive transistor comprises a first active part, a second active part and a third active part, the second active part connects the first active part and the third active part, the first active part and the third active part extend along the second direction, the second active part extends along a third direction, the second direction intersects the third direction and both are perpendicular to the first direction; in the first direction, a projection of the third active part is located between projections of the first power line and the data line; In the first direction, a projection of the first active part at least partially overlaps a projection of the first power line; the first active part is electrically connected with the first power line, and the third active part is electrically connected with the first electrode of the light emitting device; An active layer of the data write transistor comprises a fourth active part and a fifth active part, the fourth active part extends along the second direction, and the fifth active part extends along the third direction; in the first direction, a projection of the fourth active part at least partially overlaps a projection of the third active part, the fourth active part is electrically connected with the gate of the drive transistor, and the fifth active part is electrically connected with the data line.

8. The drive circuit according to claim 7, characterized in that, The scan line extends along the third direction, and in the first direction, a projection of the scan line overlaps projections of the first active part and the fourth active part.

9. The drive circuit according to claim 8, characterized in that, The first active part is electrically connected with the first power line through a first via, and the third active part is electrically connected with the first electrode of the light emitting device through a second via; the fourth active part is electrically connected with the gate of the drive transistor through a third via, and the fifth active part is electrically connected with the data line through a fourth via.

10. The drive circuit of claim 6, wherein, The pixel circuit further comprises a substrate, and the drive transistor is located between the substrate and the switch transistor.

11. The drive circuit according to claim 10, characterized in that, The drive transistor is a bottom-gate structure or a top-gate structure, and the switch transistor is a top-gate structure.

12. The drive circuit of claim 11, wherein, The gate of the drive transistor is multiplexed as the first plate and the third plate. The drive transistor comprises an N-type transistor, the first electrode of the light emitting device is multiplexed as the fourth plate, and the first electrode of the light emitting device is located on a side of the switch transistor away from the drive transistor. The second plate is electrically connected with the fourth plate, and the second plate is located between the gate of the drive transistor and the substrate. The first electrode of the light emitting device is multiplexed as a sixth plate of the second compensation capacitor, and the fifth plate is electrically connected with the first plate or the second plate of the switch transistor. Alternatively, the drive transistor comprises a P-type transistor, the shielding structure is electrically connected with the first power line, and the shielding structure serves as the second plate; and the fourth plate is electrically connected with the first power line.

13. The drive circuit of claim 12, wherein, The fifth plate is electrically connected with the second plate of the data write transistor.

14. The drive circuit of claim 6, wherein, The pixel circuit further comprises a substrate, and the switch transistor is located between the substrate and the drive transistor.

15. The drive circuit of claim 14, wherein, The drive transistor is a bottom-gate structure or a top-gate structure, and the switch transistor is a top-gate structure.

16. The drive circuit of claim 15, wherein, The gate of the driving transistor is multiplexed as the first plate and the third plate, the second plate is electrically connected with the fourth plate, and the second plate is located between the fourth plate and the first plate; The driving transistor comprises an N-type transistor, the first electrode of the light emitting device is multiplexed as the fourth plate, and the first electrode of the light emitting device is located on a side of the driving transistor away from the switching transistor; The first electrode of the light emitting device is multiplexed as the sixth plate of the second compensation capacitor, and the fifth plate is electrically connected with the first electrode or the second electrode of the switching transistor. Alternatively, the driving transistor comprises a P-type transistor, the shielding structure is electrically connected with the first power supply line, and the shielding structure serves as the second plate; or the fourth plate is electrically connected with the first power supply line.

17. The drive circuit of claim 16, wherein, The fifth plate is electrically connected with the second electrode of the data writing transistor.

18. The drive circuit of claim 17, wherein, The fifth plate and the second plate have an overlap in the orthogonal projection on the substrate.

19. The drive circuit of claim 3, wherein, The conductive structures located in different layers are electrically connected through the via filled with conductive material.

20. The drive circuit of claim 19, wherein, The driving circuit further comprises a via protection structure, the via protection structure is located in the metal layer between the active layer of the transistor and the substrate, and the conductive material in the via is electrically connected with the via protection structure.

21. The drive circuit of claim 3, wherein, The driving circuit comprises a gate driving circuit, the gate driving circuit comprises a plurality of switching transistors, and at least two switching transistors are vertically stacked. The gate driving circuit comprises at least one fixed potential input end, and the shielding structure is electrically connected with the fixed potential input end.

22. A display panel, comprising: The driving circuit comprises any one of claims 1-21.

Images