Method for memory cell and circuit structure thereof

Abstract

Disclosed herein are methods for memory cells and their circuit structures. In accordance with the principles discussed herein, EEPROM cells are provided and then converted to read-only memory ("ROM") cells after testing the code using the exact same architecture, transistors, memory cells, and layout. This conversion is done on the exact same integrated circuit die using the same layout, design, and timing, with only a single change to the upper level mask in the memory array. In one embodiment, the mask change is a via mask that connects metal 1 to polysilicon. This allows for flexibility to store programming code as non-volatile memory code and then after testing, some or all of the code from the code that can be written to read-only code is stored in ROM cells that are composed of the same transistors and have the same layout when selected by the customer.

Description

[0001] Divisional Description

[0002] This application is a divisional application of Chinese Patent Application No. 201811622142.6, filed on December 28, 2018, entitled “Method for Memory Cell and Circuit Structure Thereof”. TECHNICAL FIELD

[0003] The present disclosure relates to the field of converting non-volatile memory into read-only memory (“ROM”), and in particular to converting code programmed into a non-volatile memory array into ROM code using a single mask. BACKGROUND

[0004] There are many circuit applications where the product requires non-volatile memory, such as EEPROM, to be used during the initial stages of product development, and during the first part of testing, and even during field use. For example, automobiles, elevators, microcontrollers, and various other task-specific ASIC chips have a portion of the memory that controls the operation of the program. During the initial stages of operation development, this memory must be written, algorithms tested, and then modified many times. Once the code is confirmed to be accurate and final, the non-volatile memory is replaced with read-only memory (“ROM”). This ensures that there are no errors in the programming and that the code cannot be further modified. This is particularly beneficial in microcontrollers used in high production machines such as automobiles, building controls, airplanes, etc. Therefore, it is widely used that the circuit where the microcontroller has a portion that is initially writable memory, usually stored as non-volatile memory such as EEPROM, and then, once the code has been tested in the field and proven to be accurate, it must be stored in ROM, and therefore cannot be changed or programming errors do not occur.

[0005] In the prior art, when the non-volatile memory is replaced with ROM, this requires a complete change of the full mask set for the microprocessor. Since most ROMs have a significantly different layout and cell design than EEPROM or other non-volatile memory, there is a significant impact on the entire layout and floor plan of the entire semiconductor die. This causes changes in the design structure, timing of signal transmission throughout the die (e.g., due to changes in line length and interfaces), and further integration between different parts of the die. Therefore, changing the non-volatile memory circuit to a standard ROM sometimes requires a complete integrated circuit chip redesign and layout, which has very high costs, can take several months, and unfortunately can propagate errors in the redesign as new layouts are required with new timing of clock signals to each part of the circuit and other changes. SUMMARY

[0006] In accordance with the principles discussed herein, the same exact architecture, transistors, memory cells, and layout are used to convert the non-volatile memory into read-only memory ("ROM"). This conversion is done on the exact same integrated circuit die using the same layout, design, and timing, with only a single change to the upper level mask in the memory array. This allows for flexibility in storing programming code as non-volatile memory code, and then at a timing selected by the customer, some or all of the code from the code that can be written can be converted to read-only code stored in ROM.

[0007] In accordance with the principles of the present disclosure taught herein, a layout is provided for providing an EEPROM structure of non-volatile memory. Programming code can be written to the memory cells of the EEPROM structure to generate a logical "1" or a logical "0", and stored in the individual memory cells according to a desired software code that controls the operation of the microcontroller. The desired code is written for the microcontroller and tested for a variety of potential operating modes during the development and early stages of product generation. The manufacturer of the die, as well as the customer, is able to program the desired code into the EEPROM structure and operate it according to different scenarios in order to ensure that the code runs correctly under all possible conditions that the product can encounter during use under the control of the microcontroller. After the code has been confirmed to be correct and accurate under all conditions, the data of the code is stored in the exact same structure as read-only memory code. In particular, a structure that was formerly an EEPROM, floating gate structure, is converted to become a ROM structure, and the code is permanently written into the structure as firmware. This portion of memory changes from EEPROM to ROM, with the final code stored in the ROM as hardwired code "1" and "0" that can only be read but never changed, as the data is stored in the form of actual physical connections inside the individual memory cells.

[0008] According to one proposed solution, the memory array can be divided into two or more sections, the first section can be modifiable such that that portion of the array is not converted to a ROM version, but remains as an EEPROM. This portion of the memory array has the advantage and flexibility that the application can still be modified, and the code can be changed. Thus, the code that controls the operation of the system can be further changed in this portion of the memory, and allows the microcontroller operation to be further adjusted while the product is in the field. The second portion of the memory can have the code completely frozen in it. That is, a portion of the EEPROM memory is converted to a ROM version of the memory, which has the code stored in the hardware within the memory and can never be changed. The EEPROM can have two or more portions that are kept as writable memory and two or more portions where the structure of the memory is converted to a ROM in which the code is frozen and can only be read and not further modified.

[0009] According to the principles taught herein, a non-volatile memory is converted to a ROM by changing the metal mask that is located on the upper metal layer. In particular, a standard EEPROM array is built on a silicon die. The code that is desired to be tested is programmed into the EEPROM, where the cells are programmed to either a "1" or a "0". After the code has been confirmed to be accurate, a single metal mask is changed to hardwire the floating gate of the EEPROM to a different voltage level to create a ROM, depending on whether the cell was programmed to a "1" or a "0". If a particular memory cell was programmed to a "1", the metal mask is modified for that particular cell to hardwire the gate of the floating transistor to the gate of the select transistor. This metal coupling ensures that the particular bit always stores a logic level of "1". On the other hand, if it is desired to store a logic level of "0" in a cell that is an erase cell, the same metal mask has a contact to connect the floating gate to the P-well, the body of which is connected to the P-well. This connects the floating gate to the P-well that is the body of the storage transistor, and thus permanently stores a "0" in that particular memory cell. This allows the code that is stored in the EEPROM to be permanently stored in the exact same memory cells that are converted from EEPROM cells to ROM cells. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a circuit diagram of an EEPROM constructed according to the principles disclosed herein.

[0011] Figure 2 is a circuit diagram of an EEPROM array that is converted to a ROM in one portion while one portion remains an EEPROM according to the principles taught herein.

[0012] Figure 3A and Figure 3BThis paper illustrates how a standard EEPROM cell can be converted into a ROM cell that is permanently erased and thus stores 0, based on the principles disclosed herein.

[0013] Figure 3C and Figure 3D This paper illustrates how a standard EEPROM cell can be converted into a ROM cell that is permanently programmed and thus stores 1, based on the principles disclosed herein.

[0014] Figure 4A and Figure 4B An alternative embodiment of an EEPROM cell, which is converted into a ROM cell that is permanently erased and thus stores 0 according to the principles disclosed herein, is shown.

[0015] Figure 4C and Figure 4D An alternative embodiment of an EEPROM cell that is converted into a ROM cell that is permanently programmed and thus stores 1 according to the principles disclosed herein is shown.

[0016] Figure 5A and Figure 5B Another alternative embodiment of an EEPROM cell, which is converted into a ROM cell that permanently stores 0 and serves as an eraser cell according to the principles disclosed herein, is shown.

[0017] Figure 5C and Figure 5D Another alternative embodiment of an EEPROM cell, which is converted into a ROM cell for permanent storage as a programming cell according to the principles disclosed herein, is shown.

[0018] Figure 6A , Figure 6B and Figure 6C Various alternative embodiments are shown, such as Figure 1 The diagram shows a cross-sectional view of the EEPROM cell at position 6-6. Detailed Implementation

[0019] Figure 1A circuit diagram of a non-volatile memory array is shown. This particular non-volatile memory array is an EEPROM, however the teachings disclosed herein can be applied to other non-volatile arrays besides EEPROMs. NOR flash and NAND flash are included in the general class of EEPROMs, as well as other types of EEPROMs. A particular EEPROM is shown and described in detail in U.S. Patent No. 8,693,256 (the '256 patent), which provides an acceptable circuit structure for using the inventive technology taught herein. The '256 patent discloses a non-volatile memory array that can be integrated into a semiconductor die. Preferably, the non-volatile memory array 10 is an embedded memory array within a microcontroller. The term "microcontroller" as used herein has the broad meaning of an integrated circuit that includes a CPU and at least two types of memory on the same integrated circuit die. One type of memory is a writable memory, which can be DRAM, SRAM, or EEPROM, and the second type of memory is a non-writable memory, which is ROM. A microcontroller is also a microprocessor. The ROM on the memory typically stores the operating code that controls the functions of the microcontroller itself as well as some basic functions of the product that uses the microcontroller. The microcontroller can be an ASIC dedicated to heavy machinery such as automobiles, elevators, telephones, cell phones and tablets, as well as other machinery and transportation devices such as airplanes, ships, and entertainment devices such as TVs, stereos, etc.

[0020] Turning to Figure 1 The significant features of the memory array 10 will now be described to highlight those features that operate as an EEPROM in the initial stage, and then one or more memory cells can be converted to ROM memory cells. More specific details of the full features of the operation are described in the '256 patent, the entirety of which is incorporated herein by reference.

[0021] As Figure 1 shown, the memory array 10 shows 10 different memory cells, but a standard array embedded in a microcontroller will typically have thousands of memory cells. Each memory cell 12 includes a select transistor 14, a floating gate transistor 16, and a control gate transistor 18. In this particular design, the control gate 20 of the control gate transistor 18 is in a P-well of the substrate, although in some embodiments the control gate can also be a second polysilicon level or a metal level that overlies the floating gate transistor 16. In the particular design shown for the memory array 10, only a single polysilicon level is used. Thus, the design is described for a single polysilicon floating gate array. A single polysilicon level floating gate has a particular feature in its structure. In this feature, the floating gate is a single polysilicon layer. The control gate can be a metal layer, or preferably, as in the current design, can be a P-well in the substrate, as described later herein in the description of the EEPROM.Figures 6A to 6C The '256 patent also shows a control gate in the P-well, which provides a complete description of the operation of such a memory cell.

[0022] Turning now to Figure 6A , Figure 6B and Figure 6C , which are silicon representations of the memory cell 12 taken along line 6-6 in Figure 1 , each showing a single polysilicon layer as the floating gate 22. Figures 6A to 6C Each of the foregoing shows a different example of a design for implementing the memory cell of the previous figures. As noted above, these are many different EEPROM cell designs that can be used, and Figures 6A to 6C three such cells are shown that are acceptable. Similar structures have the same reference numerals even though certain parts can be somewhat different. The following description will be provided generally for Figures 6A to 6C , with common reference numerals used in each figure for generally corresponding features even though there are differences between the embodiments. The floating gate 22 extends from a position above the P-well 20 that is the control gate 20 to overlie the P-well 24 of the floating gate transistor 16 and the select transistor 14. An electrically insulating layer 28 is between the polysilicon floating gate 22 and the P-well 20 of the control gate transistor 18. An electrically insulating layer 30 is between the floating gate 22 and the P-well 24 of the floating gate transistor 16 and the select transistor 14. There is also an electrically insulating layer 32 between the P-well 24 and the gate 34 of the select transistor 14. In some embodiments, a heavily doped isolation N-well is between the P-well 20 containing the control gate and the P-well 24 that is the body of the floating gate transistor, however, this is not required and is not shown. The P-well 24 is labeled P_Well_HV in Figures 6A to 6C , and this is also the same as the PW_Well that is the memory well, as shown by the P+ contact connected to line 56, which is labeled PW_MEM.

[0023] It can also be seen from Figures 6A to 6C that there is a substrate 36, which is lightly doped P-type and has a P contact 38 connected thereto. Overlying the P substrate 36 is the N-well 26. There can be an N-type buried layer at the lower portion of the N-well 26, but this is not required. Within the N-well 26 are the lightly doped P-wells 20 and 24. In a preferred embodiment, the various P-wells, as well as portions of the N-well 26, are epitaxially grown to overlie the silicon substrate 36 as part of an epitaxial layer.

[0024] The common line 42 electrically connects the source and drain, as well as the body, of the control gate 42 to doped regions in the P-well 20, as shown in Figures 6A to 6C . It can be seen that Figure 1And Fig. 6, the connection 42 electrically connects the source and drain of each control gate to a common voltage and also serves as the electrical connection to the P-well of the control gate 20. The bit line BL2 is electrically connected at a heavily doped N-type region 44 used as the source / drain region of the floating gate transistor 16, while the bit line BL1 is electrically connected to a heavily doped N-type region 46 used as the source / drain region of the select transistor 14. Another source / drain region 48 extends between the select transistor and the floating gate transistor, used as a common source / drain region for both the select transistor 14 and the floating gate transistor 16.

[0025] Those skilled in the art will fully appreciate Figure 1 The basic operational principles of the memory cell shown in Fig. 6 and generally described in the previously introduced '256 patent will be fully appreciated by those skilled in the art and thus the basic operation will not be repeated here. A brief explanation of the voltages on the various nodes will help to understand the operation of the memory cell and how the cell is ultimately converted into a ROM cell and thus will be described as follows. In a conventional single polysilicon floating gate array, a program cell is defined as a memory cell that provides a "0" current during a read operation. It is defined as a "0" because it is expected that there is charge stored on the floating gate of the programmed memory cell. Thus, if there is charge stored on the programmed memory cell, that data stored in that cell is read out as a logical data value of "1". An erase cell is defined as a memory cell that can output a small amount of current during a read operation that is sufficiently different from the zero current to be detected. In one example, the amount of current for an erase cell is on the order of 5-10 μΑ of current during a read operation which is stored as a logical "0", although it can be slightly different, such as 10-100 nA or some other low value above 0. It is expected that the floating gate of the erase memory cell is depleted of charge. Thus, the threshold voltage is very low and current can flow out of the erase memory cell. This memory cell is defined as storing a "0". Table 1 below shows the voltages on each of the nodes during the read, program and erase steps.

[0026] For the purposes of this disclosure, an erase cell is defined as storing a "0" and a program cell is defined as storing a "1", but in some designs, an erase cell can be defined as storing a "1" and a program cell can be defined as storing a "0". Thus, while the convention used herein is that the erase cell is a "0" and the program cell is a "1", the convention can be reversed by having a simple inverter at a selected location in the system output to change the "1" to a "0" and the "0" to a "1", or, simply deciding that a particular output, whether program or erase, should be defined as a "1" and the other as a "0", depending on the convention used for that particular design.

[0027] The doped N-type layer can be below the N-type well 26 and at some or all locations, but this is optional.

[0028] Table 1

[0029]

[0030]

[0031] It can be seen that for EEPROM cells, such as Figure 1 As shown, during a read operation, the P-well, which serves as the control gate 20, remains at a low voltage, as do the select line and N-well 26. Bit line BL1 and the P-well memory band remain at 0 volts. Bit line BL2 is less than 1 volt. Data can be read from the EEPROM cell during this stage. Table 1 also shows the voltages at each node for program execution, and the same applies to the voltages at each node for erase execution. The program sequence stores "0"s in the memory cell, and the erase sequence stores "1"s. During programming operations, BL2 remains at 0 volts or low enough to be within the range of 0 volts and the suppression voltage (IH). It can be seen that multiple terminals have the same voltage during a specific operation. During a read operation, the P-well, select transistor, and N-well 26 all remain at the same voltage, which is low. During programming operations, the control gate 20 and N-well 26 remain at high voltages, and the select line, BL1, and the P-well memory nodes remain at "0" voltages. During programming, the value provided on BL2 should be approximately 0 volts. Although the voltage may be slightly higher than 0 volts, it should always be lower than the high voltage divided by 3 to ensure that "0" is stored on the floating gate of the memory cell. During the erase cycle, BL1 and BL2 remain floating, while the select line, N-well 26, and P-well memory band are brought to a high voltage and the control gate is brought to 0 volts.

[0032] A review of Table 1 shows that during programming and erasing operations, the SEL and PW_MEM nodes have the same voltage as each other. Therefore, a ROM cell can be created because SEL and PW_MEM are identical for both data states. For programming operations, both nodes are held low, at 0 volts. Therefore, if the two nodes are permanently connected to a low voltage via a hardwire connection, this will have the effect of creating a programmed ROM cell. Thus, when these two lines are connected to each other via a hardwire connection at metal 1, they will be connected to 0 volts or a low voltage to create a programmed ROM cell. For erasing operations, both SEL and PW_MEM nodes are held high, at a high voltage HV. Therefore, if the two nodes are permanently connected to a high voltage via a hardwire connection, this will have the effect of creating an erased ROM cell.

[0033] Preferably, the microcontroller provides, for exampleFigure 1 The EEPROM array shown, and the operating code for controlling the microcontroller itself and critical aspects of the machine that the machine operates on can be stored in the EEPROM. In the early stages of microcontroller and product development, it is desirable to be able to write different code and data values into the memory cells in order to test the operation of the microcontroller and product under various conditions. After the code has been proven correct to provide correct operation of the microcontroller and product under all conditions, it is desirable to freeze the verified code into a ROM version. Freezing the code into a ROM version has the benefit of avoiding future potential errors of the data stored in the EEPROM cells. In addition, there is no longer a need to further write data to the EEPROM cells, and reading data from ROM is generally faster than reading data from EEPROM. Accordingly, the present disclosure provides a method to convert previously verified code that has been stored in EEPROM into being stored in the exact same precise memory cells, however, the data is stored as read only. The memory cell address buffers and clock lines also remain the same. This is accomplished by converting the EEPROM memory array cells into ROM.

[0034] According to the principles of the present disclosure, the exact same data cells that previously stored bits as either a “1” or a “0” are converted to permanently store the exact same data bits as either a “1” or a “0”. This particular embodiment has the benefit that all the circuit locations remain the same, so the sequence of timing to read out the data will be exactly the same as provided by storing the code as EEPROM. Specifically, when the memory cells are converted from EEPROM to ROM memory cells, the resistance of each line will remain the same, as will the length of the travel path into and out of the memory cells for various signals, so there is no change to any of the line or circuit locations. Accordingly, no additional testing time is required because it can be assured that reading out the data from ROM will occur on the exact same timing sequence that the data was previously stored in EEPROM. In addition, since EEPROM uses the exact same silicon and transistor connections, the timing to read out data from the various data cells will not change, either relative to other data or relative to other clocks and sequences that can occur on the microcontroller at the same time as the data is being read out.

[0035] In general, the freezing of code previously stored in the non-volatile memory is generally solved by completely replacing the non-volatile memory with a brand new memory array organized as a ROM instead of an EEPROM. In particular, according to the state of the art techniques, the EEPROM memory array on the microcontroller is removed and replaced with a standard ROM array that permanently stores the code that is now frozen. The drawback is that replacing the previous EEPROM with a new ROM version requires multiple mask changes for the entire array. This change also changes the bottom layout due to the different profile between EEPROM and ROM cells. Moreover, the replacement requires a brand new system-on-chip design verification because there are different interfaces, timing sequences and protocols in the ROM cells compared to those present in the EEPROM. Therefore, this increases the risk of additional errors that can occur in the microcontroller operation even if the code has been frozen. Therefore, in some cases, instead of converting the data code from an EEPROM version to a ROM version, the EEPROM is left in place with the same data stored on it and it is treated as if it were a ROM, but in fact it is still an EEPROM.

[0036] According to the proposed solution provided herein, only a single contact mask is changed, the EEPROM physical structure is converted into a ROM. The memory cells storing the logical "1" and the logical "0" according to the latest approved data code in the EEPROM array are stored in exactly the same cells and these cells are converted into ROM cells that permanently store the logical "1" and the logical "0". According to an alternative embodiment, the EEPROM memory array can operate as two different parts. The first part can remain modifiable and continue to operate as an EEPROM. In the modifiable part, this part of the array is not converted into a ROM version and these cells remain as EEPROM cells. This part of the memory provides advantages and flexibility for the system because further tests can be performed with different code stored in the part of the array that remains as EEPROM cells. In addition, further adjustments can be made in the field or after a period of operation of the product to allow additional code to be stored in this part of the EEPROM array. At a later time, additional EEPROM cells can be converted into ROM cells. According to this embodiment, the second part of the array, part 24a, has code fixed in it by converting part 2 of the array into ROM memory cells (see Figure 2 ).

[0037] The technique for converting EEPROM cells into ROM cells according to the first embodiment will now be described as shown in Figures 3A to 3D . Figure 3A is shown in Figure 1one example of the memory cell 12 shown. In a standard microcontroller, a first metal layer will be provided that overlies the transistors in silicon. For clarity, this first metal layer is not shown in Figure 1 but is shown in Figure 2 for the array portion 24a. It is generally well known in the art to provide a series of metal interconnect layers over various insulating layers on top of a semiconductor substrate. The first metal layer is commonly referred to as metal 1, with subsequent metal layers referred to as metal 2, metal 3, or commonly listed as Ml, M2, M3, etc. The first metal layer Ml will be a wiring layer that provides electrical interconnects between various transistors in a microcontroller, including a CPU. It will also provide electrical interconnects to read and write data to the memory cell array 10, as shown in Figure 1 As part of its standard connections, this first metal layer Ml will have a wiring layer 50 with contacts 52 that electrically connect the metal layer Ml to the select lines of the select transistors 14. It will also have wiring 6. When the memory cells are organized as EEPROMs, there will be an insulating layer that overlies the polysilicon floating gate 22 to separate it from the Ml lines 50 and 54.

[0038] In particular, when a single polysilicon floating gate memory cell as an EEPROM is converted to an erase ROM cell, the floating connection to the control gate is maintained, but a local contact 54 is added to the floating gate 22 and connected to the select transistor 14. In some embodiments, the P-well control gate driver connection will be permanently deselected for this particular transistor. That is, the control gate will remain floating in the entire row that has been converted to convert the cell from an EEPROM cell to an erase ROM cell. The select line will then be one of the select bit line paths that will remain active, with the select transistor remaining on and the storage transistor 16 also remaining on and active.

[0039] After the code has been confirmed to be correct and is desired to be stored permanently, if the particular cell is planned to store a "0", a change is made to the metal 1 contact mask to electrically connect the line 50 to the floating gate 22 to provide a new contact 54, as shown in Figure 3B This is shown by the text + CNT, indicating that a contact is added at that location. Electrically connecting the select transistor to the floating gate converts the memory cell to an erase ROM cell that permanently stores a "0" in the ROM cell. That is, the ROM cell will be programmed to always be on, and thus outputs a small current whenever the ROM cell is accessed.

[0040] Figure 3D Changes to be made when a memory cell is converted to a programmed ROM are shown when it is desired to store a logical "1" into the memory cell. In particular, as shown in Figure 3CAs shown, a metal wiring layer 56 of Ml extending parallel to the metal wiring layer 50 also overlies the floating gate 22. This additional metal line 56 is present in the structure of Figure 3A Figure 1, but is not shown for greater clarity. That is, in one embodiment, Figure 3A the metal mask layer between the Figure 3C metal lines 40, 50 and 56 is the same, and the metal line 40, 50 and 56 are present as in a standard EEPROM cell. When it is desired to convert the EEPROM cell of Figure 3C Figure 1 to a ROM that is programmed and stores a logical "1", the contact mask is changed to provide a contact 58 between the metal line 56 and the floating gate 22, as shown by text + CNT. This metal line 56 is electrically connected to the P-well 20, which is labeled PW_MEM in Table 1 and shown in Figures 6A to 6C Figure 2. Since the metal line 56 is electrically connected to the P-well memory, when a contact is made to the floating gate 22, the EEPROM cell is converted to a ROM cell that is permanently programmed and thus stores a logical "1".

[0041] That is, when a single polysilicon gate cell is converted to a programmed ROM cell, the connection of the floating gate 22 to the control gate 20 is maintained, but a local contact 58 is added that connects the gate of the control transistor 18 to the metal line 56, which is permanently connected to the P-well of the control transistor 18. That is, the metal strip 56 is wired to connect to the P-well. In this variation, the P-well of the control gate is also deselected, so that the control gate 20 remains floating throughout the row. Since the P-well is always held at ground during the read cycle, the select bit line path is never active, and the storage transistor 16 can never turn on and thus remains in a permanently off position storing the data value of "0".

[0042] Thus, by changing a single mask, the contact mask between Ml and the polysilicon layer 1, an EEPROM cell can be converted to a ROM cell, and can also be selected to store a "1" or a "0", depending on where the contact is made. Changing the contact mask between metal 1 and the polysilicon level 1 is a low cost change, requiring only a single mask in the process. Furthermore, no changes are required in any layout of the memory cell, and no additional wiring layers are required.

[0043] Figure 2 A proposed memory array is shown having one portion 24a converted from an EEPROM array to a ROM array. In particular, Figure 2 the memory cell array 10 of Figure 1 has a portion 60 of the array 10 converted from an EEPROM cell to a ROM cell and a portion 62 of the array 10 that remains as an EEPROM cell. This has been accomplished by making the contact mask between the Figures 3A to 3DThe first memory cell 12a has been converted from an EEPROM cell to a program cell storing a "1" by making a contact between the metal layer 56 and the floating gate 22. Similarly, the memory cell 12e has been converted from an EEPROM cell to a program ROM cell by making a contact between its floating gate 22e and the metal line 56. The memory cells 12b and 12c have been converted from EEPROM cells to ROM cells storing a logical "0", i.e., as erase cells, by providing a contact from the metal line 54 to the floating gates of each respective cell 12b and 12c, as shown. Figure 2 Thereafter, the portion 60 of the memory array 10 can be addressed and data read out as a ROM array, and there is no longer a need to program data into this portion of the memory cell array 10, as the code has been permanently written into the memory cells of this portion of the memory by the change in the contact mask. On the other hand, the portion 62 of the memory cell 10 remains as EEPROM memory cells, and data can continue to be written to and read from the portion 62 of the memory cell 10. The wiring layer Ml forms the lines 40, 50 and 56 that are connected to the various nodes in the memory cells 12. For the Sel_L transistor, the wiring 50 is connected to the gate of the select transistor 14, and for the Sel_R transistor, the wiring 40 is connected to the gate of the select transistor 14.

[0044] In the embodiment shown in Figure 1 and Figure 2 The P-well of the control gate 20 can be the same P-well, and thus, when the memory cell is converted to a ROM cell, this P-well is selected to be floating, as shown in Figure 2 and as can also be seen from Figures 6A to 6C The P-well 24a of the floating gate transistor of the first memory portion is electrically isolated from the P-well 24b of another portion of the memory cell array. Thus, when a portion of the memory becomes a ROM and another portion of the memory remains as EEPROM, different voltages can be provided in these respective P-wells. Although Figure 1The memory cell array shown in the middle has a common P-well control gate 20 for two portions of the memory array, but in one design the P-well 20 will be physically separate P-wells that are electrically isolated for one portion of the EEPROM array compared to the other portion of the EEPROM array. For example, the next pair of rows of memory cells can be organized in a lateral step pattern where the P-well 24 of adjacent rows is shared and the P-well of the control gate is electrically isolated for that particular row from the other rows. The array can be a mirror image with respect to the control gate P-well or the floating gate P-well. Thus, rows of the array with electrically isolated P-wells can be selected for different portions of the memory array that can remain EEPROM or alternatively can become a ROM array and other portions of the memory array can remain EEPROM.

[0045] Figure 6A Additional features with a buried N-well 41 and further heavy N-doped isolation regions 27. These provide additional noise protection and can reduce parasitic currents in some designs. Figure 6B is an example of a more basic cell layout and is acceptable in many cases. Figure 6C has some different features and generally corresponds to Figure 5 of U.S. Patent 8,693,256 that has been previously introduced and incorporated by reference herein.

[0046] According to the principles taught herein, the non-volatile memory is replaced by a ROM by changing only a single mask in the array. Thus, by using the same architecture and exactly the same layout, it is easy to convert a circuit starting with non-volatile memory into a ROM. This allows the customer to flexibly store the code of the microcontroller in either non-volatile memory or ROM. The proposed integration can be used for many different types of EEPROM. Three examples of different EEPROMs have been provided and it is understood that different EEPROM memory cells can use the principles taught herein and be converted from EEPROM to ROM memory cells by using a single mask. In various embodiments as discussed herein, the contact mask providing the contacts from the metal to the polysilicon lines is the mask that is changed in order to convert the cells from EEPROM to ROM cells. Alternatively, and as discussed in one embodiment herein, the single mask that is changed can also be the polysilicon etch mask. Alternatively, it can also be the metal 1 etch mask. Thus, the proposed integration discussed herein provides only very few changes in the actual contact locations and does not change the actual layout and thus does not affect the timing of transferring data to other circuits on the same die and does not require a complete redesign of the CPU system of the die based on the memory cells being located in different locations or having different distances for signal propagation travel. In some embodiments where EEPROM is expected to be converted to ROM, the wiring of the metal wiring that is the P-well strap is selected to have local wiring that will extend over the floating gate so that new contacts can be provided for those memory cells that it is desired to convert to ROM cells. In addition, many different types of EEPROM cells can be used in addition to those specifically shown herein and using the principles taught herein, EEPROM cells can be converted from EEPROM cells to ROM cells.

[0047] Figures 4A to 4D Another alternative embodiment is shown for converting EEPROM memory cells to ROM cells with data permanently stored therein. Figure 4A A different design of EEPROM memory cell 70 is shown having two select transistors, left select transistor 72 and right select transistor 74. It has a polysilicon floating gate as previously discussed with respect to Figure 1 and Figure 6. Thus, the operation of the memory cell shown in the second embodiment is slightly different; however, it can be readily understood by those skilled in the art based on the description provided herein to be a standard EEPROM cell of the type known to be used in microcontrollers. In the case of the EEPROM cell shown in Figure 7, the operation is as follows: Figure 4AIn the EEPROM cell shown, the first metal layer Ml contains two select lines to select the EEPROM cell during read and write. A first metal line 76 is connected to the left select transistor 72 and a second metal line 78 is connected to the right select transistor 74. These connections allow data to be read from and written to the memory cell 70. By selectively activating different transistors and applying voltages, any desired data bit value can be written to the memory cell to store a "1" or a "0". After the code is confirmed to be accurate, and if it is desired to freeze the code, the EEPROM cell can be converted to a ROM cell that can selectively store a "1" or a "0". If it is desired to store the data bit as a permanent "0" so that the ROM cell becomes an erase ROM cell, as shown in Figure 4A The EEPROM cell shown is converted to a ROM cell that can selectively store a "1" or a "0". If it is desired to store the data bit as a permanent "0" so that the ROM cell becomes an erase ROM cell, as shown in Figure 4B The contact mask is changed to electrically connect the left select transistor to the floating gate 22 at the contact location 83, as shown. This electrically connects the left select transistor to the floating gate and permanently changes the memory cell to an erase ROM cell. On the other hand, if it is desired to change the EEPROM cell to a permanently programmed ROM cell to permanently store a logical "1" therein, the contact mask is changed to provide a contact 82 that electrically connects the right select transistor gate to the floating gate 22 by forming an additional contact on the metal line 78, as shown in Figure 4D Thus, with different EEPROM cells of the type shown in Figure 4A and Figure 4C The EEPROM cell shown is converted to a ROM cell that can selectively store a "1" or a "0". If it is desired to store the data bit as a permanent "0" so that the ROM cell becomes an erase ROM cell, as shown in

[0048] Figures 5A to 5D A different type of EEPROM cell and a different technique by which a single mask can be changed to permanently store a "1" or a "0" into a ROM cell is shown. In this different memory cell 90, the floating gate 22 extends from the control gate to the storage transistor 16 in a similar manner as previously described. In this particular memory cell layout, a metal line Ml can or can not be present at this location in the memory cell, depending on the desired design parameters. If it is desired to convert the memory cell of Figure 5A to a permanently erased ROM cell, the polysilicon mask is changed to have a new configuration. In the new polysilicon mask configuration, the gate of the storage transistor 16 is electrically connected to the gate of the select transistor 14 via a polysilicon layer using a polysilicon strap 92. As part of this mask change, the electrical connection between the controlled transistor 18 is removed so that there is no electrical connection between the control gate 20 and the floating gate that was previously present as the floating gate 22. Thus, with this single change of the polysilicon level mask,Figure 5A EEPROM cells permanently change to ROM cells that are in an erased state and thus permanently store a "0".

[0049] If it is desired to convert the EEPROM to a programmed ROM cell, the conversion from Figure 5D the memory cell shown in Figure 5C is made as shown in Figure 5D . In particular, in this conversion, the same mask change is made to the polysilicon level so as to electrically connect the storage transistor 16 to the gate of the select transistor 14. In addition, at a different location on the chip, the polysilicon line 94 is electrically connected to the P-well. The particular transistor that connects the polysilicon level 94 is not shown in Figure 5A ; however, it would exist at a location within the memory array 10 or outside of the memory array 10 and would be readily understood and implemented by one of ordinary skill in the art. This can be accomplished again by changing the polysilicon mask that provides the connection of the polysilicon layer between the storage transistor 16 and the select transistor 14 and also converts that polysilicon layer to be electrically connected to the P-well. In some embodiments, this can also have a change of two mask layers by adding a contact between the polysilicon layer and the P-well, but in other embodiments, only a single mask change would be required, i.e., a change to the polysilicon to extend over the previously existing contact. That is, the contact to the P-well can be provided at a selected location on the semiconductor die and extend to the top of the insulating layer. When the cell is operating as an EEPROM, Figure 5C the shape of the polysilicon layer in and

[0050] is selected to go a different path and not overlap on that contact that exists. This can be done by having the polysilicon level terminate just before reaching the contact or having its shape such that it avoids the contact extending from the P-well up to the polysilicon layer at those locations. Then, when it is desired to freeze the code in the memory cell, the polysilicon mask is changed so that the now polysilicon layer is wired to overlap the contact to the P-well that existed in the previous contact mask. This will provide an electrical connection from the polysilicon layer to the P-well and thus store the data as a "1" or "0" according to the desired code value. Figures 5A to 5D In another alternative embodiment, the conversion shown in

[0051] The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications referred to in this specification are incorporated by reference herein in their entirety, for the disclosure specifically referred to, and more generally for the general principles taught herein and the disclosures in conjunction with which the embodiments described in this specification are sought to be patentable. Aspects of the embodiments can be modified, if necessary, to employ various patents, applications and publications to provide yet further embodiments.

[0052] These and other changes can be made to the embodiments in light of the above Detailed Description. The elements of the embodiments described above are to be used in providing further embodiments and are not meant to limit the scope of the application. The scope of the application is to be defined by the claims and encompass modifications within their scope.

Claims

1. A memory cell comprising: a substrate; a first well in the substrate, the first well having a first surface; a first doped region, a second doped region, and a third doped region in the first well and adjacent to the first surface; a first gate insulator on the first surface of the first well and on the first doped region and the second doped region in the first well; a floating gate coupled to the first gate insulator; a second gate insulator on the first surface of the first well and on the second doped region and the third doped region in the first well; a select gate on the second gate insulator; a second well in the substrate spaced apart from the first well, the second well having a second surface coplanar with the first surface, the second well including a fourth doped region, a fifth doped region, a sixth doped region adjacent to the second surface and separated from each other, the sixth doped region being a different conductivity type than the fourth doped region and the fifth doped region; and a third gate insulator on the second surface and on the fourth doped region and the fifth doped region; wherein the floating gate extends from the first gate insulator to the third gate insulator, and wherein the first gate insulator, the second gate insulator, and the third gate insulator are spaced apart from each other.

2. The memory cell of claim 1, wherein the second well is a control gate for a floating gate transistor, and a control gate electrode is coupled to the second well.

3. The memory cell of claim 2, wherein the floating gate is polysilicon.

4. The memory cell of claim 1, further comprising an isolation region in the substrate between the first well and the second well, the isolation region being spaced apart from the first well and the second well.

5. The memory cell of claim 4, wherein the isolation region is an N-doped well.

6. The memory cell of claim 1, wherein the first well and the second well are P-doped wells.

7. The memory cell of claim 1, further comprising a first bit line coupled to the first well.

8. The memory cell of claim 1, further comprising a third well in the substrate, wherein each of the first well and the second well extends into the third well and has a conductivity type opposite to a conductivity type of the third well.

9. The memory cell of claim 8, wherein the first well and the second well are spaced apart from each other by a portion of the third well.

10. The memory cell of claim 8, further comprising a buried layer under the third well, and an isolation region extending through the third well between the first well and the second well to the buried layer.

11. The memory cell of claim 1, further comprising a select transistor having a first source or drain region on the first doped region in the first well; a floating gate transistor, on the third doped region in the first well, the third doped region being a second source or drain region in the first well, and the second doped region in the first well being a third source or drain region in the first well between the first source or drain region and the second source or drain region, the third source or drain region being a common source or drain region for the select transistor and the floating gate transistor.

12. A semiconductor device, substrate; and an array of memory cells, each of the memory cells comprising: a first well in the substrate, the first well having a first surface; a first doped region and a second doped region in the first well adjacent the first surface and spaced apart from each other; a first gate insulator on the first surface of the first well and on the first doped region and the second doped region in the first well; a select gate on the first well; a second well in the substrate spaced apart from the first well, the second well having a second surface coplanar with the first surface, the second well comprising a third doped region and a fourth doped region adjacent the second surface and separated from each other; a second gate insulator on the second surface and on the third doped region and the fourth doped region; an isolation region in the substrate between the first well and the second well, the isolation region extending from the first surface toward the substrate and further into the substrate than the first well and the second well; and a floating gate extending from the first gate insulator to the second gate insulator.

13. The device of claim 12, wherein each of the memory cells comprises: a third gate insulator between the first well and the select gate, the first gate insulator being between the first well and the floating gate, and the second gate insulator being between the second well and the floating gate.

14. The device of claim 12, wherein the second well is a control gate for a floating gate transistor, and a control gate electrode is coupled to the second well.

15. The device of claim 12, wherein each of the memory cells further comprises a buried layer, and the isolation region extends into the buried layer between the first well and the second well.

16. The device of claim 12, wherein the first well and the second well are P-doped wells.

17. A semiconductor device, comprising: a substrate; a memory array in the substrate, the memory array comprising a plurality of EEPROM cells, the memory array having a first portion and a second portion, the plurality of EEPROM cells of the first portion each being coupled as a ROM cell via connections at a first metal level on the memory array, each EEPROM cell comprising: a first well of a first type, the first well including three doped regions of a second type and a doped region of the first type; a second well of a second type, the second well including two doped regions of the second type and a doped region of the first type; an isolation region of the second type between and isolated from the first well and the second well; a buried well of the second type, the first well and the second well between the buried well and a first surface of the substrate, the isolation region extending between the first surface and the buried well; and a floating gate coupled to two of the doped regions of the second type in the first well and to the two doped regions of the second type in the first well.

18. The device of claim 17, wherein each of the memory arrays includes: a first gate insulator over the first well in the substrate; a second gate insulator over the first well in the substrate; a third gate insulator over the second well in the substrate, the floating gate coupled to the first gate insulator and the third gate insulator.

19. The device of claim 18, wherein the second well is for a control gate of a floating gate transistor, wherein a control gate electrode is coupled to the second well.

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