Method and apparatus for determining sensing amplifier sensing boundary, medium and device

Abstract

This disclosure relates to a method, apparatus, computer-readable storage medium, and electronic device for determining the sensing boundary of an inductive amplifier, and pertains to the field of integrated circuit technology. The method for determining the sensing boundary of an inductive amplifier includes: writing first data into a storage array; reading the first data from a first storage cell in the storage array and writing second data inversely to the first storage cell; after a preset row precharge time, reading the first data from a second storage cell on the bit line where the first storage cell is located; if the first data is read from the second storage cell, writing the second data inversely to the second storage cell and changing the preset row precharge time until the inductive amplifier can no longer correctly read the first data on the bit line, and determining the corresponding critical row precharge time as the row precharge time boundary value. This disclosure can measure the sensing capability of an inductive amplifier.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a method for determining the sensing boundary of a sensing amplifier, a device for determining the sensing boundary of a sensing amplifier, a computer-readable storage medium, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. Due to its advantages such as simple structure, high density, low power consumption, and low price, it has been widely used in the computer field and the electronics industry.

[0003] For DRAM, during the read and write phases, it is often necessary to amplify the minute voltage changes on the bit lines through an inductive amplifier and convert them into digital signals in order to complete the data reading.

[0004] However, some inductive amplifiers are prone to sensing errors at their sensing boundaries, leading to incorrect data readings. Therefore, determining the sensing boundaries of an inductive amplifier is crucial for evaluating its amplification performance.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a method, apparatus, computer-readable storage medium, and electronic device for determining the sensing boundary of an inductive amplifier, in order to measure the sensing capability of an inductive amplifier.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0008] According to a first aspect of this disclosure, a method for determining the sensing boundary of an inductive amplifier is provided, characterized in that the method includes: writing first data into a storage array; reading the first data from a first storage cell in the storage array and writing second data inversely to the first storage cell; after a preset row precharge time, reading the first data from a second storage cell on the bit line where the first storage cell is located; when the first data is read from the second storage cell, writing the second data inversely to the second storage cell and changing the preset row precharge time until the inductive amplifier can no longer correctly read the first data on the bit line, and determining the corresponding critical row precharge time as the row precharge time boundary value.

[0009] In one exemplary embodiment of this disclosure, the method further includes: if the first data is not read in the second storage unit, writing the second data back in the second storage unit and changing the preset row precharge time tRP until the sensing amplifier correctly reads the first data on the bit line, and determining the corresponding previous preset row precharge time as the row precharge time boundary value.

[0010] In one exemplary embodiment of this disclosure, the second storage cell is the next storage cell on the bit line where the first storage cell is located.

[0011] In one exemplary embodiment of this disclosure, the first storage unit is a plurality of storage units on a first word line, the second storage unit is a plurality of storage units on a second word line, and the first word line and the second word line share the same bit line.

[0012] In one exemplary embodiment of this disclosure, the second word line is the next word line after the first word line.

[0013] In one exemplary embodiment of this disclosure, the time for writing the first data into the storage array is a preset write recovery delay.

[0014] In one exemplary embodiment of this disclosure, when the first data is 0, after the preset write recovery delay, the corresponding first data to be written is any value between 0 and 0.5.

[0015] In one exemplary embodiment of this disclosure, when the first data is 1, after the preset write recovery delay, the corresponding first data written is any value between 0.5 and 1.

[0016] In one exemplary embodiment of this disclosure, the determined row precharge time boundary value is any value between 5 and 20 ns.

[0017] In one exemplary embodiment of this disclosure, the time to write the second data back in the first storage unit is the same as the time to write the second data back in the second storage unit.

[0018] In one exemplary embodiment of this disclosure, writing first data into a storage array includes writing the first data into each storage cell of the storage array.

[0019] In one exemplary embodiment of this disclosure, writing the first data into the memory array includes writing the first data into memory cells on the bit line where the sensing amplifier is located in the memory array.

[0020] In one exemplary embodiment of this disclosure, writing the first data into the memory cells on the bit line where the sensing amplifier of the memory array is located includes: turning on a word line on the bit line, sequentially writing the first data into each memory cell on the word line; turning off the word line, turning on the next word line, and sequentially writing the first data into each memory cell on the next word line, until the first data is sequentially turned on and written into all word lines on the same bit line.

[0021] In one exemplary embodiment of this disclosure, the method further includes: during the process of writing the second data back into the first storage cell, reducing the voltage applied to the word line of the first storage cell so that the voltage of the written second data is insufficient.

[0022] In one exemplary embodiment of this disclosure, the voltage applied to the first memory cell word line is equal to the voltage applied to the second memory cell word line.

[0023] According to a second aspect of this disclosure, an inductive amplifier sensing boundary determination device is provided. The device includes: a data writing module for writing first data into a storage array; a data rewriting module for reading the first data from a first storage cell in the storage array and rewriting second data from the first storage cell; a data reading module for reading the first data from a second storage cell on a bit line where the first storage cell is located after a preset row precharge time; and a boundary value determination module for rewriting the second data from the second storage cell when the first data is read from the second storage cell, and changing the preset row precharge time until the inductive amplifier cannot correctly read the first data on the bit line, and determining the corresponding critical row precharge time as a row precharge time boundary value.

[0024] According to a third aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described method for determining the sensing boundary of an inductive amplifier.

[0025] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described inductive amplifier sensing boundary determination method by executing the executable instructions.

[0026] The technical solution provided in this disclosure may include the following beneficial effects:

[0027] In an exemplary embodiment of this disclosure, by writing first data into the storage array, and after reading the first data in the first storage cell of the storage array, the potential on the bit line and the complementary bit line can be changed by writing the second data back into the first storage cell. Then, after a preset row precharge time, the first data in the second storage cell on the bit line where the first storage cell is located is read. If the first data is read in the second storage cell, the second data is written back into the second storage cell, and the preset row precharge time is changed until the sensing amplifier can no longer correctly read the first data on the bit line. This indicates that the potential difference between the bit line and the complementary bit line has reached a certain critical value, resulting in a failure to sense or read the first data in the next storage cell. Thus, the corresponding critical row precharge time can be determined as the row precharge time boundary value, which is used to determine and measure the sensing boundary of the sensing amplifier, thereby measuring the sensing capability of the sensing amplifier.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0030] Figure 1 The illustration schematically shows a structural diagram of a storage cell according to an exemplary embodiment of the present disclosure;

[0031] Figure 2 The diagram illustrates a connection structure between an inductive amplifier and a memory cell according to an exemplary embodiment of the present disclosure.

[0032] Figure 3 The illustration schematically shows a potential change during normal data reading 0 of an inductive amplifier according to an exemplary embodiment of the present disclosure;

[0033] Figure 4 The illustration schematically depicts a potential change during abnormal data 0 readout of an inductive amplifier according to an exemplary embodiment of the present disclosure;

[0034] Figure 5 The illustration schematically shows a comparison of potential changes in data 1 read from an inductive amplifier according to an exemplary embodiment of the present disclosure;

[0035] Figure 6 A flowchart illustrating an inductive amplifier sensing boundary determination method according to an exemplary embodiment of the present disclosure is shown schematically.

[0036] Figure 7 The illustration schematically shows a storage array after first data has been written according to an exemplary embodiment of the present disclosure;

[0037] Figure 8 Schematic illustration Figure 7 A schematic diagram of the storage array after writing the second data backwards;

[0038] Figure 9 The illustration schematically shows the potential change of the inductive amplifier according to an exemplary embodiment of the present disclosure during the reading of data 0;

[0039] Figure 10 The illustration schematically shows the potential change of the inductive amplifier according to an exemplary embodiment of the present disclosure during the reading of data 1;

[0040] Figure 11 Schematic illustration Figure 8 A schematic diagram showing the storage array performing read and write operations.

[0041] Figure 12 Schematic illustration of the Figure 11 A schematic diagram showing the reading and writing operations performed by the sensing amplifier on the next bit line of the memory array;

[0042] Figure 13 The illustration schematically shows another schematic diagram of a memory array after performing a read and write operation according to an exemplary embodiment of the present disclosure;

[0043] Figure 14 A block diagram schematically illustrates an inductive amplifier sensing boundary determination apparatus according to an exemplary embodiment of the present disclosure;

[0044] Figure 15 The illustration schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0045] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0046] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0047] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0048] Semiconductor memories are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications. A semiconductor memory comprises multiple memory cells in a memory array, each memory cell storing at least one bit of information. DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Therefore, the following description of embodiments is made with reference to DRAM as a non-limiting example.

[0049] In DRAM integrated circuit devices, memory cell arrays are typically arranged in rows and columns, allowing specific memory cells to be addressed by specifying their row and column in the array. Word lines connect rows to bit-line sense amplifiers (SAs) that detect data in a set of probe cells. Then, during a read operation, a subset of data in the sense amplifiers is selected, either by choice or column selection, for output.

[0050] Reference Figure 1 Each memory cell 100 in a DRAM typically includes a capacitor 110, a transistor 120, a word line (WL) 130, and a bit line (BL) 140. The gate of transistor 120 is connected to word line 130, the drain of transistor 120 is connected to bit line 140, and the source of transistor 120 is connected to capacitor 110. The voltage signal on word line 130 can control the opening or closing of transistor 120, thereby reading data information stored in capacitor 110 through bit line 140, or writing data information into capacitor 110 for storage through bit line 140. The memory array is composed of multiple memory cells as described above. The memory array generally occupies 50-65% of the total area of ​​the DRAM device, while the remaining area of ​​the DRAM device is mainly composed of peripheral circuitry.

[0051] During the reading of data stored in memory cell 100, a sensor amplifier is needed to amplify the minute voltage changes on the bit lines and convert them into digital signals. See [link to documentation]. Figure 2 This diagram illustrates a connection structure between a sense amplifier and a memory cell. It includes a bit line BL, a complementary bit line / BL, a word line WL, a sense amplifier 200, and a memory cell 100. The gate of the memory cell 100 is connected to the word line WL, and its drain is connected to the bit line BL. The sense amplifier 200 operates using the bit line BL and the complementary bit line / BL, which serves as a reference line, to detect and amplify the voltage difference across a pair of bit lines BL and / BL.

[0052] In an exemplary embodiment of this disclosure, a bit line balancing module 210 is further provided between the bit line BL and the complementary bit line / BL. The bit line balancing module 210 is used to pinch the bit line BL and the complementary bit line / BL together under the action of the bit line balancing control signal BLEQ, so as to close the read and write operations on the memory cell 100.

[0053] The following details the process by which the inductive amplifier 200 amplifies the data stored in the storage unit 100, such as data 0. (Reference) Figure 3 Upon receiving the activation signal ACT, V is provided. BLP The voltage causes the bit line balance control signal BLEQ to turn off (i.e., BLEQ Off), separating the pinched bit line BL and the complementary bit line / BL; then, the word line WL turns on (i.e., WL ON), the transistor connected to the word line turns on, and the voltage on the capacitor connected to the transistor is released to the bit line BL through charge sharing. The capacitor stores data 1, or it can store data 0.

[0054] Taking the data 0 stored in the capacitor as an example, storing 0 is shared from the bit line BL to the capacitor terminal, generating a negative voltage difference ΔV, which causes the voltage on the bit line BL to become V. BLP -ΔV, at this point, the voltage on the complementary bit line / BL is still V. BLP .

[0055] Figure 2 The inductive amplifier 200 includes a first transistor ①, a second transistor ②, a third transistor ③, and a fourth transistor ④. The first transistor ① and the second transistor ② are both NMOS (Negative channel Metal Oxide Semiconductor) transistors, and the third transistor ③ and the fourth transistor ④ are both PMOS (Positive channel Metal Oxide Semiconductor) transistors.

[0056] Reference Figure 3 This diagram illustrates the process of an inductive amplifier reading data 0, with the voltage on bit line BL being VBLP-ΔV and the voltage on the complementary bit line / BL being V. BLP In this case, the first transistor ① and the second transistor ② will be turned on. Since the first transistor ① is turned on to a greater extent than the second transistor ②, the potential on the bit line BL is rapidly pulled down to the voltage V at node NCS. SS Simultaneously, as the potential on bit line BL is pulled low, the second transistor ② will be turned off, and the fourth transistor ④ will be turned on, increasing the voltage V at node PCS. ARY It will be applied to the complementary bit line / BL, causing the potential on the complementary bit line / BL to be pulled up to V. ARY At this point, normal data reading (RD) can be performed. After the data reading is completed, the word line can be turned off (i.e., WL OFF), the inductive amplifier is also turned off (i.e., SA OFF), and the bit line balance control signal is turned on (i.e., BLEQ ON), etc., to complete the reading process of memory cell 100.

[0057] It should be noted that before the next activation signal ACT arrives, there is a precharge (PRE) process, also known as the row precharge time (tRP). The magnitude of this row precharge time tRP determines the potential of the bit line BL and the complementary bit line / BL. Figure 3 As shown, if the row precharge time tRP is small, it is possible that the bit line BL and the complementary bit line / BL may not recover to the same potential.

[0058] Figure 3 The sensing process (SA sensing) shown is the normal sensing process of a sensing amplifier to detect a zero signal. (Refer to...) Figure 4 The diagram illustrates the potential change of an abnormal induced 0 signal in an inductive amplifier. Figure 4 In the process of sensing a 0 signal, the potential of the bit line BL will be pulled up to voltage V by the inductive amplifier. ARY This situation causes the read signal to be 1, instead of the actual stored signal 0, resulting in a read error. In other words, the correctness of the read data can be used to determine whether the inductive amplifier has failed to sense 0.

[0059] contrast Figure 3 and Figure 4It can be seen that during normal sensing of a 0 signal by the inductive amplifier, the potential on the bit line BL is always lower than the potential on the complementary bit line / BL. However, when the inductive amplifier is abnormally sensing a 0 signal, the potential on the bit line BL may be higher than the potential on the complementary bit line / BL. Based on this, an exemplary embodiment of this disclosure provides a method to control and change the magnitude of the row precharge time tRP (i.e., card tRP) to generate a situation where the potential on the bit line BL is higher than the potential on the complementary bit line / BL. This allows for the determination of the sensing boundary of the inductive amplifier, thereby enabling comparative analysis of the sensing capability of the inductive amplifier.

[0060] During the process of controlling and changing the size of the row precharge time tRP, as the row precharge time tRP becomes smaller and smaller, the potential on the bit line BL will gradually be higher than the potential on the complementary bit line / BL. When the potential on the bit line BL is higher than the potential on the complementary bit line / BL to a certain critical value, the above-mentioned sensing 0 failure will occur. At this time, the corresponding row precharge time tRP can be used as the sensing boundary of the sensing amplifier to measure the sensing capability of the sensing amplifier.

[0061] Corresponding to the failure of sensing 0, there is also a case of failure of sensing 1. (See reference...) Figure 5 As shown, during normal sensing of a 1 signal by the inductive amplifier, the potential on bit line BL is consistently higher than the potential on the complementary bit line / BL. However, when the inductive amplifier malfunctions in sensing a 1 signal, the potential on bit line BL may fall below the potential on the complementary bit line / BL. Similarly, by controlling and changing the row precharge time tRP, a situation can be created where the potential on bit line BL is lower than the potential on the complementary bit line / BL. This allows for the determination of the inductive amplifier's sensing boundary, enabling comparative analysis of the inductive amplifier's sensing capability.

[0062] The inductive amplifier sensing boundary determination method provided in the exemplary embodiments of this disclosure is referred to... Figure 6 This may include the following steps:

[0063] Step S610: Write the first data into the storage array;

[0064] Step S620: Read the first data from the first storage cell in the storage array, and write the second data back into the first storage cell;

[0065] Step S630: After a preset row precharge time, read the first data from the second memory cell on the bit line where the first memory cell is located;

[0066] Step S640: If the first data is read in the second storage cell, the second data is written back in the second storage cell, and the preset row precharge time is changed until the sensing amplifier can no longer read the first data correctly on the bit line. The corresponding critical row precharge time is then determined as the row precharge time boundary value.

[0067] In the inductive amplifier sensing boundary determination method provided by the exemplary embodiments of this disclosure, first data is written into the storage array. After reading the first data in the first storage cell of the storage array, second data is written back into the first storage cell, which can change the potential on the bit line BL and the complementary bit line / BL. Then, after a preset row precharge time tRP, the first data in the second storage cell on the bit line where the first storage cell is located is read. If the first data is read in the second storage cell, the second data is written back into the second storage cell, and the preset row precharge time tRP is changed. When the inductive amplifier can no longer correctly read the first data on the bit line, it indicates that the potential difference between the bit line BL and the complementary bit line / BL has reached a certain critical value, and a failure to sense or read the first data in the next storage cell will occur. Thus, the corresponding critical row precharge time can be determined as the row precharge time boundary value, which is used to determine and measure the sensing boundary of the inductive amplifier, thereby measuring the sensing capability of the inductive amplifier.

[0068] In step S610, first data is written into the storage array.

[0069] In an exemplary embodiment of this disclosure, writing the first data into the storage array can be done by writing the first data into each storage cell of the storage array, or by writing the first data into the storage cells on the bit line where the sensing amplifier is located, so that it is only used to determine the sensing boundary of the sensing amplifier.

[0070] It should be noted that the first data written to each storage unit can be either 0 or 1.

[0071] In practical applications, there are several ways to write the first data into a storage array. For example, writing the first data to each storage cell of the storage array can be done sequentially or in an X-Fast-Write manner.

[0072] In an exemplary embodiment of this disclosure, if the first data is only written to the memory cells on the bit line where the induction amplifier is located, the method may include: enabling one word line on the bit line, sequentially writing the first data to each memory cell on that word line; then, disabling the word line, enabling the next word line, and sequentially writing the first data to each memory cell on the next word line, until the first data is sequentially enabled and written to all word lines on the same bit line BL. In other words, the first data can be written to all word lines on the same bit line BL in a word-line-by-word manner.

[0073] Alternatively, the first data can be written to all word lines on the next bit line (e.g., YC+1) in the memory array in the manner described above, until the first data has been written to all word lines in the memory array, to obtain the following result: Figure 7 The case shown, where the first data to be written is 0, can also achieve the goal of writing the first data to each storage cell of the storage array.

[0074] It should be noted that if the first data is written to all word lines on the bit line BL where the sensing amplifier is located, then the first data can be written only to a specific bit line BL in the memory array, and thus only used to determine the sensing boundary of the sensing amplifier on that bit line BL. Alternatively, the first data can be written to any number of word lines on the bit lines BL in the memory array. The exemplary embodiments of this disclosure do not impose a special limitation on the number of bit lines BL on which the first data is written.

[0075] In step S620, the first data in the first storage cell of the storage array is read, and the second data is written back in the first storage cell.

[0076] In the exemplary embodiments of this disclosure, the process of reading the first data can start from the first storage unit. The first storage unit may be, for example, the first storage unit on a bit line BL, or a storage unit preset by the system or a storage unit specified by the user. In addition, the first storage unit may also be multiple storage units on the first word line or the second word line. The exemplary embodiments of this disclosure do not make any special limitation on the specific location of the first storage unit.

[0077] When the first storage unit is a single storage unit, the process of reading the first data in the first storage unit can be a direct read; when the first storage unit is multiple storage units on a word line, reading the first data in the first storage unit is equivalent to reading the first data in multiple storage units on the word line simultaneously.

[0078] After reading the first data from the first storage unit, it is necessary to write the second data back into the first storage unit, such as... Figure 8 As shown, 1 is written in reverse.

[0079] In the process of reading the first data according to the arrangement order of the storage units, when the storage unit is the last storage unit on a word line, the next storage unit is the first storage unit on the next word line.

[0080] In step S630, after a preset row precharge time tRP, the first data in the second memory cell on the bit line where the first memory cell is located is read.

[0081] Reference Figure 9 The diagram illustrates the potential changes of the sensing amplifier during the reading of data 0 and the writing of data 1. In an exemplary embodiment of this disclosure, the time for writing the first data 0 into the memory array can be a preset write recovery delay tWR; after the preset write recovery delay tWR, the second data 1 can be written after a normal row precharge time Normal tRP, wherein the duration of writing the second data 1 is one normal write recovery delay Normal tWR. Figure 9 In the diagram, ①-④ represent a continuous process. ① and ② involve writing and reading the first data, while ③ and ④ involve writing the second data backward and reading the first data from the second memory cell on the bit line where the first memory cell is located. After writing the second data backward, the row precharge time tRP needs to be strictly controlled. After the preset row precharge time tRP, the first data from the adjacent second memory cell on the bit line where the first memory cell is located is read, i.e., the data is read from the second memory cell. Figure 8 The data in the first row and second column is 0.

[0082] After the normal row precharge time (Normal tRP), since the read data is 0, the potential on bit line BL is close to Vss, i.e., close to 0. Then, during the data write-back process, the potential on bit line BL rises. Because the duration of writing the second data 1 is one normal write recovery delay (Normal tWR), the potential on bit line BL approaches Vss. ARY That is, close to 1. Next, when reading the first data in the second memory cell on the bit line where the first memory cell is located, the first data in the second memory cell can be read after a preset row precharge time tRP. The preset row precharge time tRP can be adjusted according to actual conditions; that is, the accuracy of the sensing amplifier in sensing the first data can be changed by adjusting tRP, thereby determining the sensing boundary of the sensing amplifier.

[0083] Accordingly, refer to Figure 10The diagram illustrates the potential changes of the sensing amplifier during the reading of data 1 and the writing of data 0. In an exemplary embodiment of this disclosure, the time for writing the first data 1 into the memory array can be a preset write recovery delay tWR; after the preset write recovery delay tWR, the second data 0 can be written after a normal row precharge time Normal tRP, wherein the duration of writing the second data 0 is one normal write recovery delay Normal tWR. Figure 10 ①-④ in the diagram represent a continuous process. ① and ② involve writing and reading the first data, while ③ and ④ involve writing the second data backward and reading the first data from the second memory cell on the bit line where the first memory cell is located. After writing the second data backward, the row precharge time tRP needs to be strictly controlled. After the preset row precharge time tRP, the first data from the adjacent second memory cell on the bit line where the first memory cell is located is read, i.e., data 0 is read.

[0084] After the normal row precharge time (Normal tRP), since the data read is 1, the potential on the bit line BL is close to V. ARY That is, close to 1. Then, during the data write-back process, the potential on the bit line BL will decrease. Since the duration of writing the second data 0 is one normal write recovery delay (Normal tWR), the potential on the bit line BL will be close to V. SS That is, close to 0. Next, when reading the first data in the second memory cell on the bit line where the first memory cell is located, the first data in the second memory cell can be read after a preset row precharge time tRP. The preset row precharge time tRP can be adjusted according to actual conditions; that is, the accuracy of the sensing amplifier in sensing the first data can be changed by adjusting tRP, thereby determining the sensing boundary of the sensing amplifier, i.e., the critical row precharge time.

[0085] In the actual determination of the critical row precharge time, its magnitude is affected by the write recovery delay. Therefore, in the exemplary embodiment of this disclosure, during the sequential reading of the first data in each memory cell and the reverse writing of the second data, the write recovery delay Normal tWR for rewriting the second data in each memory cell is the same. That is, the write recovery delay Normal tWR for rewriting the second data in the first memory cell is the same as the write recovery delay Normal tWR for rewriting the second data in the second memory cell. Under the same write recovery delay tWR, the determined critical row precharge time is more accurate. The sequential reading of the first data in each memory cell can be based on the arrangement order of the memory cells or the arrangement order of the word lines; no special limitation is made here. It should be noted that the write recovery delay here can be either the normal row precharge time Normal tRP or the preset write recovery delay tWR.

[0086] After the preset row precharge time tRP, during the process of reading the first data in the second storage unit, two situations may occur: the data read is the first data and the data read is the second data.

[0087] In step S640, if the first data is read in the second storage unit, the second data is written back in the second storage unit, and the preset row precharge time is changed until the sensing amplifier cannot read the first data correctly on the bit line, that is, a sensing error occurs. At this time, the corresponding critical row precharge time is determined as the row precharge time boundary value.

[0088] In other words, when the read data is the first data, it means that the reading is correct. Then, the second data is written back in the second storage cell, and the preset row precharge time tRP is changed. The first data in the next storage cell of the second storage cell is read until the sensing amplifier can no longer read the first data correctly on its bit line BL. Then, the corresponding critical row precharge time is determined as the row precharge time boundary value.

[0089] However, if the read data is the second data, meaning the first data is not read from the second storage unit, it indicates a read error and is considered an abnormal data read. The corresponding critical row precharge time can be defined as the row precharge time boundary value. Alternatively, the second data can be written back, and the preset row precharge time tRP (i.e., the card tRP) can be changed until the first data is correctly read. Then, the previous preset row precharge time tRP is defined as the row precharge time boundary value. Specifically, the size of the card tRP can be determined according to the actual situation, and this exemplary embodiment does not impose any special limitations on it.

[0090] then Figure 7 and Figure 8 After performing the first data read and the second data write-back on the first and second storage units, refer to Figure 11 Furthermore, the first data read and the second data write can be performed on the next memory cell and the next memory cell after that, until the row precharge time boundary value of the induction amplifier on the output line is determined.

[0091] After the boundary value of the row precharge time of the inductive amplifier on the first line is determined, refer to Figure 12 The row precharge time boundary value of the inductive amplifier on the next bit line can be determined. The specific determination method is the same and will not be repeated here.

[0092] Following the above method, refer to Figure 13 When the first data is 1 and the second data is 0, for the first bit line, starting from the first memory cell, a first data read and a second data write-back process can be performed. The first data in the second memory cell is read via the card tRP, and then the second data is written back to the second memory cell. This process is repeated until the row precharge time boundary value of the inductive amplifier corresponding to the first bit line is determined. Next, the same first data read and second data write-back process can be performed on the memory cells on the second bit line, and the data in the next memory cell is read via the card tRP to determine the row precharge time boundary value of the inductive amplifier corresponding to the second bit line.

[0093] In practical applications, the sensing capability of an inductive amplifier can be measured by the magnitude of the row precharge time boundary value. Under the same write recovery delay tWR, a smaller row precharge time boundary value indicates a stronger sensing capability. Taking sensing 0 data as an example, a smaller row precharge time boundary value indicates... Figure 9 The greater the potential difference between the bit line BL in the sensing region 910 and the complementary bit line / BL, the stronger the fault tolerance and the higher the reliability of the sensing amplifier.

[0094] In practical applications, different inductive amplifiers determine different line precharge time boundary values. In the exemplary embodiment of this disclosure, for a conventional inductive amplifier, the determined line precharge time boundary value is any value between 5 and 20 ns.

[0095] It should be noted that since one sensing amplifier corresponds to one bit line, the memory cells used in determining the sensing boundary of the sensing amplifier, such as the first memory cell and the second memory cell mentioned above, need to be memory cells on the same bit line. Alternatively, if the first memory cell is multiple memory cells on the first word line and the second memory cell is multiple memory cells on the second word line, the first word line and the second word line need to be on the same bit line, that is, they need to share the same bit line.

[0096] To facilitate data retrieval, and to allow data to be written backwards from the first storage unit to affect the second storage unit (which is the next storage unit on the bit line following the first), data is typically written to the first storage unit before being written to the second, or vice versa. Alternatively, the second word line may be the next word line after the first, meaning that reading from or writing to the first word line will precede reading from or writing to the second.

[0097] In an exemplary embodiment of this disclosure, to induce a sensing error, the preset write recovery delay tWR for writing the first data can be changed based on the aforementioned card tRP. This preset tWR, for example, reduces the preset tWR, which can result in insufficient data being written, thus facilitating the occurrence of a sensing error when the card tRP is reached.

[0098] In practical applications, when the first data is 0, after the preset write recovery delay, the corresponding first data to be written is any value between 0 and 0.5, i.e., region 920; when the first data is 1, after the preset write recovery delay, the corresponding first data to be written is any value between 0.5 and 1, i.e., region 920.

[0099] In practical applications, to make the voltage of the second data being written insufficient, that is, to further create an unfavorable condition (i.e., a Worse condition), making the potential difference between the bit line BL and the complementary bit line / BL larger, the voltage applied to the word line of the first memory cell can be reduced during the process of writing the second data back in the first memory cell. The smaller the voltage on the word line, the smaller the degree to which the word line is open, thereby reducing the write-back voltage.

[0100] It should be noted that, in order to improve the comparability of the determined row precharge time boundary values, the voltage applied to the word line in each memory cell is consistent, that is, the voltage applied to the word line of the first memory cell is equal to the voltage applied to the word line of the second memory cell.

[0101] In summary, the exemplary embodiments of this disclosure, by writing first data into the storage array, reading the first data in the storage cell, and writing the second data backwards, combined with the card's preset row precharge time tRP, can change the potential difference between the bit line BL and the complementary bit line / BL. When the potential difference reaches a certain critical value, an error will occur in reading the first data. The critical row precharge time determined in this case is the row precharge time boundary value, which can be used to measure the sensing capability of the sensing amplifier.

[0102] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0103] Furthermore, in this exemplary embodiment, an inductive amplifier sensing boundary determination device is also provided. (Refer to...) Figure 14 The sensing amplifier sensing boundary determination device 1400 may include: a data writing module 1410, a data rewriting module 1420, a data reading module 1430, and a boundary value determination module 1440, wherein:

[0104] The data writing module 1410 can be used to write first data into the storage array;

[0105] The data write-back module 1420 can be used to read the first data in the first storage cell of the storage array and write the second data back in the first storage cell;

[0106] The data reading module 1430 can be used to read the first data in the second memory cell on the bit line where the first memory cell is located after a preset row precharge time;

[0107] The boundary value determination module 1440 can be used to reverse write the second data in the second storage cell when the first data is read in the second storage cell, and change the preset row precharge time until the sensing amplifier can no longer read the first data correctly on the bit line, and determine the corresponding critical row precharge time as the row precharge time boundary value.

[0108] In one exemplary embodiment of this disclosure, the boundary value determination module 1440 can also be used to reverse write the second data in the second storage unit when the first data is not read in the second storage unit, and change the preset row precharge time until the sensing amplifier correctly reads the first data on the bit line, and determine the corresponding previous preset row precharge time as the row precharge time boundary value.

[0109] In one exemplary embodiment of this disclosure, the second storage cell is the next storage cell on the bit line where the first storage cell is located.

[0110] In one exemplary embodiment of this disclosure, the first storage unit is a plurality of storage units on a first word line, the second storage unit is a plurality of storage units on a second word line, and the first word line and the second word line share the same bit line.

[0111] In one exemplary embodiment of this disclosure, the second word line is the next word line after the first word line.

[0112] In one exemplary embodiment of this disclosure, the time for writing the first data into the storage array is a preset write recovery delay.

[0113] In one exemplary embodiment of this disclosure, when the first data is 0, after the preset write recovery delay, the corresponding first data to be written is any value between 0 and 0.5.

[0114] In one exemplary embodiment of this disclosure, when the first data is 1, after the preset write recovery delay, the corresponding first data written is any value between 0.5 and 1.

[0115] In one exemplary embodiment of this disclosure, the determined row precharge time boundary value is any value between 5 and 20 ns.

[0116] In one exemplary embodiment of this disclosure, the time to write the second data back in the first storage unit is the same as the time to write the second data back in the second storage unit.

[0117] In one exemplary embodiment of this disclosure, the data writing module 1410 can be used to write the first data into each storage cell of the storage array.

[0118] In one exemplary embodiment of this disclosure, the data writing module 1410 can be used to write the first data into the memory cells on the bit line where the sensing amplifier of the memory array is located.

[0119] In one exemplary embodiment of this disclosure, the data writing module 1410 can be used to enable a word line on the bit line, sequentially write the first data into each of the storage cells on the word line; disable the word line, enable the next word line, and sequentially write the first data into each of the storage cells on the next word line, until the first data is sequentially enabled and written into all word lines on the same bit line.

[0120] In one exemplary embodiment of this disclosure, the data write-back module 1420 can be used to reduce the voltage applied to the word line of the first storage cell during the process of writing the second data back into the first storage cell, so that the voltage of the written second data is insufficient.

[0121] In one exemplary embodiment of this disclosure, the voltage applied to the first memory cell word line is equal to the voltage applied to the second memory cell word line.

[0122] The specific details of the virtual modules of each induction amplifier induction boundary determination device mentioned above have been described in detail in the corresponding induction amplifier induction boundary determination method, so they will not be repeated here.

[0123] It should be noted that although several modules or units of the inductive amplifier sensing boundary determination device have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0124] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0125] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0126] The following reference Figure 15 To describe an electronic device 1500 according to this embodiment of the present invention. Figure 15 The electronic device 1500 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0127] like Figure 15 As shown, the electronic device 1500 is manifested in the form of a general-purpose computing device. The components of the electronic device 1500 may include, but are not limited to: at least one processing unit 1510, at least one storage unit 1520, a bus 1530 connecting different system components (including storage unit 1520 and processing unit 1510), and a display unit 1540.

[0128] The storage unit 1520 stores program code that can be executed by the processing unit 1510, causing the processing unit 1510 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 1510 can perform actions such as... Figure 6 The steps shown are as follows: S610: Write first data into the storage array; S620: Read the first data in the first storage cell of the storage array and write the second data in the first storage cell; S630: After a preset row precharge time, read the first data in the second storage cell on the bit line where the first storage cell is located; S640: If the first data is read in the second storage cell, write the second data in the second storage cell and change the preset row precharge time until the sensing amplifier can no longer read the first data correctly on the bit line, and then determine the corresponding critical row precharge time as the row precharge time boundary value.

[0129] Storage unit 1520 may include readable media in the form of volatile storage units, such as random access memory (RAM) 15201 and / or cache memory 15202, and may further include read-only memory (ROM) 15203.

[0130] Storage unit 1520 may also include a program / utility 15204 having a set (at least one) program module 15205, such program module 15205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0131] Bus 1530 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0132] Electronic device 1500 can also communicate with one or more external devices 1570 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 1500, and / or with any device that enables electronic device 1500 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1550. Furthermore, electronic device 1500 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1560. As shown, network adapter 1560 communicates with other modules of electronic device 1500 via bus 1530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0133] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0134] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section of this specification.

[0135] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0136] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0137] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0138] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0139] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0140] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0141] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0142] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A method for determining the sensing boundary of an inductive amplifier, characterized in that, The method includes: Write the first data into the storage array; Read the first data from the first storage unit in the storage array, and write the second data back into the first storage unit; After a preset row precharge time, the first data is read from the second storage cell on the bit line where the first storage cell is located; When the first data is read in the second storage unit, the second data is written back in the second storage unit, and the preset row precharge time is changed until the sensing amplifier can no longer read the first data correctly on the bit line. The corresponding critical row precharge time is then determined as the row precharge time boundary value. During the reverse writing of the second data, the voltage applied to the word line of the first memory cell is reduced so that the voltage of the written second data is insufficient.

2. The method of claim 1, wherein, The method further includes: If the first data is not read in the second storage unit, the second data is written backwards in the second storage unit, and the preset row precharge time tRP is changed until the sensing amplifier correctly reads the first data on the bit line. Then, the corresponding previous preset row precharge time is determined as the row precharge time boundary value.

3. The method of claim 1, wherein, The second storage cell is the next storage cell on the bit line where the first storage cell is located.

4. The method according to claim 1, characterized in that, The first storage unit is a plurality of storage units on a first word line, and the second storage unit is a plurality of storage units on a second word line. The first word line and the second word line share the same bit line.

5. The method of claim 4, wherein, The second character line is the character line following the first character line.

6. The method according to any one of claims 1-5, characterized in that, The time for writing the first data into the storage array is a preset write recovery delay.

7. The method according to claim 6, characterized in that, When the first data is 0, after the preset write recovery delay, the corresponding first data to be written is any value between 0 and 0.

5.

8. The method of claim 6, wherein, When the first data is 1, after the preset write recovery delay, the corresponding first data to be written is any value between 0.5 and 1.

9. The method according to any one of claims 1-5, characterized in that, The determined pre-charge time boundary value is any value between 5 and 20 ns.

10. The method according to any one of claims 1-5, characterized in that, The time required to reverse write the second data in the first storage unit is the same as the time required to reverse write the second data in the second storage unit.

11. The method according to any one of claims 1-5, characterized in that, Writing the first data to the storage array includes: The first data is written into each storage cell of the storage array.

12. The method of any one of claims 1-5, wherein, Writing the first data to the storage array includes: The first data is written into the memory cells on the bit line where the sensing amplifier is located in the memory array.

13. The method of any one of claims 1-5, wherein, The method further includes: During the process of writing the second data back into the first storage cell, the voltage applied to the word line of the first storage cell is reduced so that the voltage of the written second data is insufficient.

14. The method of claim 13, wherein, The voltage applied to the word line of the first memory cell is equal to the voltage applied to the word line of the second memory cell.

15. An inductive amplifier inductive boundary determination apparatus, comprising: The device includes: The data writing module is used to write the first data into the storage array; The data write-back module is used to read the first data in the first storage unit of the storage array and write the second data back in the first storage unit; The data reading module is used to read the first data in the second storage cell on the bit line where the first storage cell is located after a preset row precharge time; The boundary value determination module is used to reverse write the second data in the second storage unit when the first data is read in the second storage unit, and change the preset row precharge time until the sensing amplifier can no longer read the first data correctly on the bit line, and determine the corresponding critical row precharge time as the row precharge time boundary value. During the reverse writing of the second data, the voltage applied to the word line of the first memory cell is reduced so that the voltage of the written second data is insufficient.

16. A computer readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the inductive amplifier sensing boundary determination method according to any one of claims 1 to 14.

17. An electronic device, comprising: include: processor; and memory for storing the executable instructions of the processor; The processor is configured to execute the inductive amplifier sensing boundary determination method according to any one of claims 1 to 14 by executing the executable instructions.

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