Transmitting and receiving circuit
By employing a single analog-to-digital converter and automatic signal selection technology in the low-IF receiver, the area and power consumption issues of the low-IF receiver are solved, while maintaining the image rejection ratio and signal quality, thus achieving efficient signal processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2022-03-25
- Publication Date
- 2026-05-15
AI Technical Summary
Low-IF receivers, due to their inclusion of in-phase and positive-phase channels, complex filters, and two analog-to-digital converters, result in excessive chip area and power consumption, and make it difficult to maintain a good image rejection ratio.
The transceiver circuit design employs a single analog-to-digital converter, which automatically selects the intermediate frequency signal with better signal quality through complex filters and switching modules, and uses digital circuits to calculate the image rejection ratio to select the output signal, thereby reducing circuit redundancy.
It reduces chip area and power consumption while maintaining good image rejection ratio and signal quality, achieving efficient signal processing.
Smart Images
Figure CN116846419B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to transceiver circuits. Background Technology
[0002] Low-IF receivers have been widely used in many electronic devices. In order to achieve a better image rejection ratio (IMR), low-IF receivers generally include two channels, in-phase and quadrature, as well as a complex filter. Each channel also has an analog-to-digital converter (ADC) to perform analog-to-digital conversion. However, this results in low-IF receivers having a large chip area and high power consumption. Summary of the Invention
[0003] Therefore, one of the objectives of this invention is to provide a transceiver circuit that has only a single analog-to-digital converter to save chip area and power consumption, while still maintaining a good image rejection ratio, in order to solve the problems described in the prior art.
[0004] In one embodiment of the present invention, a transceiver circuit is disclosed, comprising a receiving circuit, wherein the receiving circuit includes a first mixer, a second mixer, a complex filter, a switching module, and an analog-to-digital converter. In operation of the transceiver circuit, the first mixer is used to mix an input signal using a first oscillation signal to generate a first mixed signal; the second mixer is used to mix the input signal using a second oscillation signal to generate a second mixed signal; the complex filter is used to generate a first intermediate frequency (IF) signal and a second IF signal based on the first and second mixed signals; the switching module is used to receive the first and second IF signals and select one of the first and second IF signals according to a control signal to generate an output IF signal; and the analog-to-digital converter is used to perform an analog-to-digital conversion operation on the output IF signal to generate a digital signal. Attached Figure Description
[0005] Figure 1 This is a schematic diagram of a transceiver circuit according to an embodiment of the present invention.
[0006] Figure 2 This is a schematic diagram of the desired signal after processing by a mixer and a complex filter.
[0007] Figure 3This is a schematic diagram of the image signal after it has been processed by a mixer and a complex filter.
[0008] Symbol Explanation
[0009] 100: Transceiver circuit
[0010] 102: Antenna
[0011] 104: Matching Circuit
[0012] 110: Receiving circuit
[0013] 111: Low-noise amplifier
[0014] 112, 113: Mixers
[0015] 114: Complex Filter
[0016] 115: Switching Module
[0017] 116: Programmable gain amplifier
[0018] 117: Analog-to-Digital Converter
[0019] 120: Transmission circuit
[0020] 121: Power Amplifier
[0021] 122, 123: Mixers
[0022] 124, 125: Filters
[0023] 126, 127: Digital-to-Analog Converters
[0024] 130: Digital Circuits
[0025] IF_I, IF_Q: Intermediate frequency signals
[0026] RXLO_I, RXLO_Q: Oscillation signals
[0027] TXLO_I, TXLO_Q: Oscillation signals
[0028] SW1, SW2: Switches
[0029] Vc: Control signal
[0030] Vin_I, Vin_Q: Signals after mixing
[0031] DC: Direct Current
[0032] IF: Frequency
[0033] RXLO: Frequency of RXLO_I / RXLO_Q
[0034] TXLO: Frequency of TXLO_I / TXLO_Q Detailed Implementation
[0035] Figure 1 This is a schematic diagram of a transceiver circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the transceiver circuit 100 includes a receiving circuit 110, a transmitting circuit 120, and a digital circuit 130. The receiving circuit 110 includes a low-noise amplifier 110, two mixers 112 and 113, a complex filter 114, a switching module 115, a programmable gain amplifier (PGA) 116, and an analog-to-digital converter 117. The switching module 115 includes two switches SW1 and SW2. The transmitting circuit 120 includes a power amplifier 121, two mixers 122 and 123, two filters 124 and 125, and two digital-to-analog converters 126 and 127. In this embodiment, the receiving circuit 110 and the transmitting circuit 120 are connected to an antenna 102 via a matching circuit 104 for signal reception and transmission. Furthermore, in this embodiment, the receiving circuit 110 is a low-intermediate frequency (IF) receiving circuit.
[0036] In the operation of the receiving circuit 110, the low-noise amplifier 110 receives a received signal from the antenna 102 through the matching circuit 104 and processes the received signal to generate an input signal. Next, mixer 112 uses an oscillation signal RXLO_I to mix the input signal to generate a mixed signal Vin_I, while mixer 114 uses an oscillation signal RXLO_Q to mix the input signal to generate a mixed signal Vin_Q. The oscillation signals RXLO_Q and RXLO_I have the same frequency and a 90-degree phase difference; that is, the mixed signal Vin_I corresponds to an in-phase channel, while the mixed signal Vin_Q corresponds to a quadrature channel. Next, the complex filter 114 receives the mixed signals Vin_I and Vin_Q to generate intermediate frequency signals IF_I and IF_Q, where the intermediate frequency signal IF_I corresponds to the in-phase channel and the intermediate frequency signal IF_Q corresponds to the positive-mode channel. Furthermore, since the operation of the complex filter 114 requires the simultaneous use of signals from both the in-phase channel and the positive-mode channel, the complex filter 114 generates the intermediate frequency signal IF_I based on the mixed signals Vin_I and Vin_Q, and generates the intermediate frequency signal IF_Q based on the mixed signals Vin_I and Vin_Q. Since the complex filter 114 is well known to those skilled in the art, its detailed circuit architecture will not be described in detail here. Next, the switching module 115 receives intermediate frequency (IF) signals IF_I and IF_Q, and selects one of them as an output IF signal according to a control signal Vc. Specifically, when the control signal Vc indicates that the IF signal IF_I should be output, the switching module 115 turns on switch SW1 and turns off switch SW2 to output the IF signal IF_I; and when the control signal Vc indicates that the IF signal IF_Q should be output, the switching module 115 turns on switch SW2 and turns off switch SW1 to output the IF signal IF_Q. Then, the programmable gain amplifier 116 amplifies the output IF signal to generate an amplified IF signal, and the analog-to-digital converter 117 performs an analog-to-digital conversion on the amplified IF signal to generate a digital signal for subsequent processing by the digital circuit 130.
[0037] In the operation of the receiving circuit 110, since the switching module 115 selects only one of the intermediate frequency signals IF_I and IF_Q as the output intermediate frequency signal, the receiving circuit 110 only needs to set up a programmable gain amplifier 116 and an analog-to-digital converter 117 to process the intermediate frequency signal IF_I or the intermediate frequency signal IF_Q, instead of setting up two sets of circuits to process the intermediate frequency signals IF_I and IF_Q simultaneously as in the prior art. Therefore, the receiving circuit 110 of this embodiment can effectively reduce chip area and power consumption.
[0038] However, since the circuitry and signals in the in-phase and positive-path channels of the receiving circuit 110 are not perfectly matched—for example, the phase difference between the oscillation signals RXLO_I and RXLO_Q is not exactly 90 degrees, and the path gains are not exactly the same—the complex filter 114 will have inconsistent responses in the in-phase and positive-path channels, resulting in different signal qualities for the intermediate frequency (IF) signals IF_I and IF_Q. As described above, to enable the receiving circuit 110 to generate a better digital signal for the digital circuit 130, this embodiment further proposes a method that can automatically determine which of the IF signals IF_I and IF_Q has better signal quality, and control the switching module 115 to select the IF signal with better signal quality from the IF signals IF_I and IF_Q.
[0039] Specifically, when the transceiver circuit 100 is in the testing phase or has just been powered on, the transmitting circuit 120 transmits multiple test signals, and the receiving circuit 110 receives these multiple test signals to determine the image rejection ratio of the intermediate frequency signals IF_I and IF_Q, thereby determining which of the intermediate frequency signals IF_I and IF_Q has better signal quality. For more details, please refer to... Figure 1 , Figure 2 First, digital circuit 130 generates two digital test signals to digital-to-analog converters 126 and 127 to generate two analog signals. Then, the two analog signals are processed by filters 124 and 125 to generate a first filtered signal and a second filtered signal, respectively. Mixer 122 uses an oscillation signal TXLO_I to mix the first filtered signal to generate a first mixed signal, while mixer 123 uses an oscillation signal TXLO_Q to mix the second filtered signal to generate a second mixed signal. The oscillation signals TXLO_Q and TXLO_I have the same frequency and a 90-degree phase difference. Next, the first and second mixed signals are combined and processed by power amplifier 121 to generate a first test signal to matching circuit 104. In this embodiment, the first test signal represents a desired signal, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and RXLO_I / RXLO_Q is... Figure 2 The "IF" shown, where Figure 2 The frequencies of the oscillation signals TXLO_I / TXLO_Q are represented by "TXLO" and RXLO_I / RXLO_Q, respectively. Furthermore, the frequency of the desired signal is within the in-band of the complex filter 114.
[0040] Next, the receiving circuit 110 receives the first test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the first test signal as a received signal. At this time, the digital circuit 130 can first generate a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_I. Figure 2 As shown, after processing by mixers 112 / 113 and complex filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "IF", where the intermediate frequency signals IF_I and IF_Q are close to DC. It should be noted that... Figure 2 The response of the complex filter 114 shown is an ideal state. In reality, due to the mismatch between the in-phase and positive-phase channels, the response of the complex filter 114 is not perfectly symmetrical. Next, since the switching module 115 is controlled to output the intermediate frequency signal IF_I, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_I to generate a digital signal for the digital circuit 130, which then determines the strength of the intermediate frequency signal IF_I with the desired signal.
[0041] Next, digital circuit 130 generates two digital test signals again and sends them to transmission circuit 120, which then performs a similar operation to generate a second test signal to matching circuit 104. (See reference) Figure 3 In this embodiment, the second test signal is used to represent the signal corresponding to... Figure 2 The required signal is a mirror image of the signal, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and RXLO_I / RXLO_Q is... Figure 3 The "IF" shown means, if Figure 2 The frequency TXLO of the first test signal shown is "RXLO+IF", then Figure 3 The frequency TXLO of the second test signal shown is "RXLO-IF".
[0042] Next, the receiving circuit 110 receives the second test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the second test signal as a received signal. At this time, the digital circuit 130 has generated a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_I. Figure 3As shown, after processing by mixers 112 / 113 and complex filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "-IF". Next, since the switching module 115 is controlled to output the intermediate frequency signal IF_I, the programmable gain amplifier 116 and analog-to-digital converter 117 process the intermediate frequency signal IF_I to generate a digital signal for the digital circuit 130, so that the digital circuit 130 can determine the strength of the intermediate frequency signal IF_I with a mirror signal.
[0043] As described above, since the digital circuit 130 determines the strength of the desired signal and the strength of the image signal, the image rejection ratio (IMR) of the intermediate frequency signal IF_I can be calculated. The calculation of the IMR can be found by referring to... Figure 3 As shown, this represents the degree to which the mirror signal is attenuated after passing through the complex filter 114.
[0044] It should be noted that, in Figure 2 , Figure 3 In one embodiment, the frequency of the desired signal is "RXLO+IF", and the frequency of the mirror signal is "RXLO-IF", but the invention is not limited thereto. In other embodiments, the frequency of the desired signal can be "RXLO-IF", the frequency of the mirror signal can be "RXLO+IF", and the center frequency of the complex filter 114 can be located near "RXLO-IF". These design variations should fall within the scope of the invention.
[0045] Next, similarly, digital circuit 130 again generates two digital test signals to transmission circuit 120, and transmission circuit 120 performs a similar operation to generate a third test signal to matching circuit 104. (See reference) Figure 3 In this embodiment, the third test signal is used to represent Figure 2 The desired signal is shown, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and RXLO_I / RXLO_Q is... Figure 2 The "IF" shown.
[0046] Next, the receiving circuit 110 receives the third test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the third test signal as a received signal. At this time, the digital circuit 130 can first generate a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_Q. Figure 2As shown, after processing by mixers 112 / 113 and complex filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "IF". Since the switching module 115 has been controlled to output the intermediate frequency signal IF_Q, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_Q to generate a digital signal for the digital circuit 130, so that the digital circuit 130 can determine the strength of the intermediate frequency signal IF_Q with the desired signal.
[0047] Next, digital circuit 130 generates two more digital test signals to transmission circuit 120, which then performs a similar operation to generate a fourth test signal to matching circuit 104. (See reference) Figure 3 In this embodiment, the fourth test signal is used to represent the signal corresponding to... Figure 2 The required signal is a mirror image of the signal, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and RXLO_I / RXLO_Q is... Figure 3 The "IF" shown means, if Figure 2 The frequency TXLO of the third test signal shown is "RXLO+IF", then Figure 3 The frequency TXLO of the fourth test signal shown is "RXLO-IF".
[0048] Next, the receiving circuit 110 receives the fourth test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the fourth test signal as a received signal. At this time, the digital circuit 130 has generated a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_Q. Figure 3 As shown, after processing by mixers 112 / 113 and complex filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "-IF". Next, since the switching module 115 is controlled to output the intermediate frequency signal IF_Q, the programmable gain amplifier 116 and analog-to-digital converter 117 process the intermediate frequency signal IF_Q to generate a digital signal for the digital circuit 130, which then determines the strength of the intermediate frequency signal IF_Q with a mirror signal.
[0049] As described above, since the digital circuit 130 determines the strength of the desired signal and the strength of the image signal, the image rejection ratio of the intermediate frequency signal IF_Q can be calculated.
[0050] After determining the image rejection ratio of the intermediate frequency signal IF_I and the image rejection ratio of the intermediate frequency signal IF_Q, the digital circuit 130 can determine which of the intermediate frequency signals IF_I and IF_Q has better signal quality. In the subsequent operation of the transceiver circuit 100, the digital circuit 130 can generate a control signal Vc to control the switching module 115 to select the intermediate frequency signal with better signal quality as the output intermediate frequency signal for processing by the subsequent programmable gain amplifier 116 and analog-to-digital converter 117.
[0051] It should be noted that the generation and processing order of the first test signal, the second test signal, the third test signal and the fourth test signal is not a limitation of the present invention. That is, the order in which the digital circuit 130 determines the strength of the intermediate frequency signal IF_I with the desired signal, the strength of the intermediate frequency signal IF_I with the mirror signal, the strength of the intermediate frequency signal IF_Q with the desired signal and the strength of the intermediate frequency signal IF_Q with the mirror signal can be arbitrarily changed without affecting the concept of the present invention.
[0052] It should be noted that the above calculation of the image rejection ratio of intermediate frequency signals IF_Q and IF_Q is merely an illustrative example and not a limitation of the present invention. In other embodiments of the present invention, the image rejection ratio can be replaced by any quality parameter that can reflect the attenuation of the image signal of intermediate frequency signals IF_Q and IF_Q, and the digital circuit 130 can determine which of the intermediate frequency signals IF_Q and IF_Q to select for subsequent processing based on the quality parameter of the intermediate frequency signals IF_Q and IF_Q. Related design variations should fall within the scope of the present invention.
[0053] In addition, Figure 1 In the illustrated embodiment, the receiving circuit 110 receives the first test signal, the second test signal, the third test signal, and the fourth test signal generated by the transmitting circuit 120. However, the present invention is not limited thereto. In other embodiments, the first test signal, the second test signal, the third test signal, and the fourth test signal can be generated by an external testing device, and the receiving circuit 110 receives these test signals through the antenna 102. Such design variations should fall within the scope of the present invention.
[0054] In summary, in the transceiver circuit of this invention, only one of the two intermediate frequency (IF) signals generated by the receiving circuit is used as the output IF signal for subsequent operations. Therefore, the receiving circuit only needs one programmable gain amplifier and one analog-to-digital converter to process the IF signal, instead of using two sets of circuits to process both IF signals simultaneously as in the prior art. Thus, this invention can reduce chip area and power consumption. Furthermore, by calculating the quality parameters of the two IF signals to select the IF signal with better quality for subsequent operations, signal quality can be maintained while reducing chip area and power consumption.
[0055] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A transceiver circuit, comprising: A receiving circuit, wherein the receiving circuit includes: A first mixer is used to perform a mixing operation on an input signal using a first oscillation signal to generate a first mixed signal. A second mixer is used to perform a mixing operation on the input signal using a second oscillation signal to generate a second mixed signal; A complex filter is used to generate a first intermediate frequency signal and a second intermediate frequency signal based on the first mixed signal and the second mixed signal. A switching module is used to receive the first intermediate frequency signal and the second intermediate frequency signal, and select one of the first intermediate frequency signal and the second intermediate frequency signal according to a control signal to generate an output intermediate frequency signal. as well as An analog-to-digital converter is used to perform an analog-to-digital conversion operation on the output intermediate frequency signal to generate a digital signal. The control signal is generated based on the signal quality of the first intermediate frequency signal and the second intermediate frequency signal. The switching module selects the intermediate frequency signal with better signal quality from the first intermediate frequency signal and the second intermediate frequency signal based on the control signal to generate the output intermediate frequency signal.
2. The transceiver circuit as claimed in claim 1, wherein the control signal is generated based on the image rejection ratio of the first intermediate frequency signal and the image rejection ratio of the second intermediate frequency signal, and the switching module selects an intermediate frequency signal with a better image rejection ratio from the first intermediate frequency signal and the second intermediate frequency signal based on the control signal to generate the output intermediate frequency signal.
3. The transceiver circuit as claimed in claim 1, wherein the receiving circuit only includes the analog-to-digital converter to receive the output intermediate frequency signal, and does not include other analog-to-digital converters for receiving the first intermediate frequency signal or the second intermediate frequency signal.
4. The transceiver circuit as claimed in claim 1, wherein the receiving circuit further comprises: A programmable gain amplifier is coupled between the switching module and the analog-to-digital converter to amplify the output intermediate frequency signal to generate an amplified intermediate frequency signal. The analog-to-digital converter performs an analog-to-digital conversion operation on the amplified intermediate frequency signal to generate the digital signal; and the receiving circuit only includes the programmable gain amplifier and the analog-to-digital converter to process the output intermediate frequency signal, without including other programmable gain amplifiers and analog-to-digital converters for processing the first intermediate frequency signal or the second intermediate frequency signal.
5. A transceiver circuit, comprising: A receiving circuit, wherein the receiving circuit includes: A first mixer is used to perform a mixing operation on an input signal using a first oscillation signal to generate a first mixed signal. A second mixer is used to perform a mixing operation on the input signal using a second oscillation signal to generate a second mixed signal; A complex filter is used to generate a first intermediate frequency signal and a second intermediate frequency signal based on the first mixed signal and the second mixed signal. A switching module is used to receive the first intermediate frequency signal and the second intermediate frequency signal, and select one of the first intermediate frequency signal and the second intermediate frequency signal according to a control signal to generate an output intermediate frequency signal. as well as An analog-to-digital converter is used to perform an analog-to-digital conversion operation on the output intermediate frequency signal to generate a digital signal: A transmission circuit is used to transmit multiple test signals; as well as A digital circuit; The receiving circuit receives the plurality of test signals and generates a plurality of digital signals to the digital circuit. The digital circuit determines the quality parameters of the first intermediate frequency signal and the second intermediate frequency signal based on the plurality of digital signals, and compares the quality parameters of the first intermediate frequency signal and the second intermediate frequency signal to generate the control signal.
6. The transceiver circuit of claim 5, wherein the digital circuit determines the image rejection ratio of the first intermediate frequency signal and the image rejection ratio of the second intermediate frequency signal based on the plurality of digital signals, and generates the control signal to control the switching module to select an intermediate frequency signal with a better image rejection ratio from the first intermediate frequency signal and the second intermediate frequency signal to generate the output intermediate frequency signal.
7. The transceiver circuit of claim 5, wherein the plurality of test signals includes a first test signal, a second test signal, a third test signal, and a fourth test signal; wherein the receiving circuit receives the first test signal as the input signal, and the switching module selects the first intermediate frequency signal as the output intermediate frequency signal, and the analog-to-digital converter performs an analog-to-digital conversion operation on the output intermediate frequency signal to generate a first digital signal; the receiving circuit receives the second test signal as the input signal, and the switching module selects the first intermediate frequency signal as the output intermediate frequency signal, and the analog-to-digital converter performs an analog-to-digital conversion operation on the output intermediate frequency signal to generate a second digital signal; the receiving circuit The circuit receives the third test signal as the input signal, and the switching module selects the second intermediate frequency signal as the output intermediate frequency signal, and the analog-to-digital converter performs an analog-to-digital conversion operation on the output intermediate frequency signal to generate a third digital signal; the receiving circuit receives the fourth test signal as the input signal, and the switching module selects the second intermediate frequency signal as the output intermediate frequency signal, and the analog-to-digital converter performs an analog-to-digital conversion operation on the output intermediate frequency signal to generate a fourth digital signal; and the digital circuit determines the quality parameters of the first intermediate frequency signal and the quality parameters of the second intermediate frequency signal based on the first digital signal, the second digital signal, the third digital signal and the fourth digital signal.
8. The transceiver circuit of claim 7, wherein the digital circuit determines the quality parameters of the first intermediate frequency signal based on the first digital signal and the second digital signal, and determines the quality parameters of the second intermediate frequency signal based on the third digital signal and the fourth digital signal.
9. The transceiver circuit as claimed in claim 8, wherein the frequency of the first test signal is "RXLO+IF", the frequency of the second test signal is "RXLO-IF", the frequency of the third test signal is "RXLO+IF", and the frequency of the fourth test signal is "RXLO-IF", wherein "RXLO" is the frequency of the first oscillation signal and the second oscillation signal, and "IF" is a frequency value.