Display substrate and display device

Abstract

The display substrate provided by the embodiments of the present disclosure comprises a plurality of gate lines and a plurality of data lines; the plurality of gate lines respectively extend along a first direction; the plurality of data lines respectively extend along a second direction; the plurality of data lines and the plurality of gate lines spatially cross to define a plurality of pixel regions; at least one sub-pixel is arranged in each of the pixel regions; at least three sub-pixels adjacent to each other along the second direction form a pixel; and all the sub-pixels in one pixel are connected to the same data line.

Description

Technical Field

[0001] This disclosure pertains to the field of display technology, specifically relating to a display substrate and a display device. Background Technology

[0002] TDDI (Touch and Display Driver Integration) products have been widely used due to their advantages of simple manufacturing process and low cost. Summary of the Invention

[0003] This disclosure provides a display substrate and a display device.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, including multiple gate lines and multiple data lines;

[0005] The plurality of gate lines extend along a first direction; the plurality of data lines extend along a second direction.

[0006] The multiple data lines and the multiple gate lines intersect to define multiple pixel regions; each pixel region is provided with at least one sub-pixel;

[0007] At least three of the sub-pixels that are adjacent to each other along the second direction constitute a pixel;

[0008] In this case, all the sub-pixels within a pixel are connected to the same data line.

[0009] In some embodiments, a sub-pixel is provided within each pixel region;

[0010] All the sub-pixels of a pixel are arranged sequentially along the second direction;

[0011] All the sub-pixels of a pixel are respectively connected to different gate lines.

[0012] In some embodiments, a substrate is further included; the pixel includes a first electrode and a second electrode disposed above the substrate;

[0013] The first electrode and the second electrode are distributed sequentially away from the substrate;

[0014] The first electrode includes a plurality of first sub-electrodes; the second electrode includes a plurality of second sub-electrodes;

[0015] The orthographic projections of the first sub-electrode and the second sub-electrode onto the substrate at least partially overlap;

[0016] A plurality of second sub-electrodes adjacent to each other along the first direction and / or the second direction are connected to each other to form a second electrode block;

[0017] The second electrode is reused as a touch electrode.

[0018] In some embodiments, there are multiple second electrodes, and the multiple second electrodes are arranged in an array;

[0019] The number of second sub-electrodes forming each second electrode block is equal; the second sub-electrodes forming each second electrode block are arranged in an array.

[0020] Each of the second sub-electrodes has a plurality of slits; the plurality of slits are spaced apart along the second direction; the plurality of slits extend along the first direction respectively;

[0021] In two adjacent rows of the second sub-electrodes among two adjacent second blocks of electrodes along the second direction, one row of the second sub-electrodes is disconnected from the other row of the second sub-electrodes.

[0022] In some embodiments, a plurality of switching transistors are also included, with each sub-pixel including one of the switching transistors;

[0023] The switching transistor is located at the intersection of the data line and the gate line; and the orthographic projection of the switching transistor on the substrate is located between the orthographic projection of the data line connected to the sub-pixel in the sub-pixel opening region and the orthographic projection of the data line connected to the sub-pixel on the substrate.

[0024] The gate of the switch is located close to the gate line to which it is connected; the source of the switch is located close to the data line to which it is connected; the drain of the switch is located close to the gate of another switch adjacent to it along the second direction.

[0025] The drain electrode is connected to the first sub-electrode;

[0026] Two adjacent second sub-electrodes on the second electrode along the first direction are connected by a first connecting portion;

[0027] The first connecting portion extends along the first direction, and the orthographic projection of the first connecting portion on the substrate intersects with the orthographic projection of the data line on the substrate.

[0028] In some embodiments, the first connection portion and the second sub-electrode are located on the same layer.

[0029] In some embodiments, a second connecting portion is further included, which is used to connect two adjacent second sub-electrodes on the second block electrode along the second direction.

[0030] In some embodiments, the system further includes multiple sets of touch signal lines, each set including multiple sets of the touch signal lines;

[0031] Each of the aforementioned touch signal lines extends along the second direction;

[0032] Each group of the touch signal lines corresponds to a column of the second electrode distribution;

[0033] Each of the second electrodes is connected to at least one of the touch signal lines.

[0034] In some embodiments, the plurality of sub-pixels are arranged in an array;

[0035] Between any two adjacent columns of the sub-pixels, there is a data line and a touch signal line.

[0036] In some embodiments, the plurality of sub-pixels are arranged in an array;

[0037] A data line is distributed between any two adjacent columns of the sub-pixels;

[0038] The sub-pixel is divided into two domains along the first direction; the domain boundaries of a column of the sub-pixels are located on the same straight line;

[0039] The orthographic projection of each of the touch signal lines on the substrate overlaps with the orthographic projection of the domain boundary lines of a column of sub-pixels on the substrate.

[0040] In some embodiments, the touch signal line is located on the same layer as the data line, the source and drain of the switching transistor;

[0041] The second electrode is located on the side of the touch signal line opposite to the substrate; a first insulating layer is provided between the second electrode and the touch signal line;

[0042] The second electrode is connected to the touch signal line through a first via formed in the first insulating layer;

[0043] The orthographic projection of the first via on the substrate is located on the side of the sub-pixel opening region away from the switching transistor within the sub-pixel in which it is located.

[0044] In some embodiments, one of the touch signal lines is connected to a second electrode through a plurality of the first vias;

[0045] The plurality of first vias are arranged along the second direction;

[0046] Multiple grid lines are distributed between any two adjacent first vias;

[0047] In a row of pixels arranged along the first direction with the first via provided, the first via and the drain of the switching transistor are located on different straight lines extending along the first direction; the minimum distance of the first via from the gate line is less than the minimum distance of the connection position of the drain of the switching transistor and the first sub-electrode from the gate line.

[0048] In some embodiments, the domain boundary line of a column of the sub-pixels extends along the second direction;

[0049] The touch signal line located on the domain boundary line is connected to the first via through a first connecting line;

[0050] The first connecting line and the touch signal line are located on the same layer; the gate line and the gate of the switching transistor are located on the same layer; the first connecting line is located on the side of the gate line away from the substrate, and a second insulating layer is provided between the first connecting line and the gate line.

[0051] In some embodiments, the first connecting line includes a first sub-connecting line and a second sub-connecting line; the first sub-connecting line connects the touch signal line and the second sub-connecting line; the second connecting line connects the first via.

[0052] The first sub-connecting line extends along the first direction, and the orthographic projection of the first sub-connecting line on the substrate overlaps with the gate line;

[0053] The orthographic projection of the second sub-connecting line on the substrate is located within the pixel area, and the orthographic projection of the second sub-connecting line on the substrate overlaps with the orthographic projection of the first via on the substrate.

[0054] In some embodiments, in the pixel area where the first via is not provided, the plurality of slits on the second sub-electrode are divided into a first group of slits and a second group of slits; the first group of slits and the second group of slits are arranged along the second direction;

[0055] The first set of slits includes at least one of the slits; the second set of slits includes at least one of the slits.

[0056] The second set of slits and the switching transistor are arranged along the first direction;

[0057] The touch signal line located on the domain boundary line divides the first group of slits and the second group of slits into two sub-slits respectively;

[0058] The length of the sub-slit located on the side of the touch signal line closer to the switch transistor in the first set of slits is greater than the length of the sub-slit located on the side of the touch signal line farther from the switch transistor.

[0059] The length of the sub-slit of the second set of slits located on the side of the touch signal line closer to the switch transistor is less than the length of the sub-slit located on the side of the touch signal line farther from the switch transistor.

[0060] In some embodiments, the length of the sub-slit of the first set of slits located on the side of the touch signal line away from the switch transistor is less than the length of the sub-slit of the second set of slits located on the side of the touch signal line away from the switch transistor.

[0061] In some embodiments, within the pixel region where the first via is provided, the plurality of slits on the second sub-electrode are divided into a third group of slits and a fourth group of slits; the third group of slits and the fourth group of slits are arranged along the second direction;

[0062] The third group of slits includes at least one of the slits; the fourth group of slits includes at least one of the slits;

[0063] The third set of slits and the first through hole are arranged along the first direction; the fourth set of slits and the switch tube are arranged along the first direction;

[0064] The touch signal line located on the domain boundary line divides the third group of slits and the fourth group of slits into two sub-slits respectively;

[0065] The length of the sub-slit located on the side of the touch signal line away from the first via is greater than the length of the sub-slit located on the side of the touch signal line closer to the first via.

[0066] The length of the sub-slit located on the side of the touch signal line closer to the switch transistor in the fourth set of slits is less than the length of the sub-slit located on the side of the touch signal line farther from the switch transistor.

[0067] In some embodiments, the length of the sub-slit of the third set of slits located on the side of the touch signal line closer to the first via is less than the length of the sub-slit of the fourth set of slits located on the side of the touch signal line farther from the switch transistor.

[0068] Secondly, embodiments of this disclosure also provide a display device, which includes the aforementioned display substrate. Attached Figure Description

[0069] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0070] Figure 1 This is a schematic diagram of the pixel design of TDDI products in related technologies.

[0071] Figure 2A This is a schematic diagram of the pixel structure and arrangement of a display substrate provided in an embodiment of this disclosure.

[0072] Figure 2B for Figure 2A A schematic diagram of pixel arrangement and working principle on a display substrate.

[0073] Figure 3 This is a schematic diagram of the pixel structure and arrangement of another display substrate provided in an embodiment of this disclosure.

[0074] Figure 4 For along Figure 2A AA section line and Figure 3 A structural sectional view of the section line B'B'.

[0075] Figure 5A This is a schematic diagram showing the segmentation of the second electrode on the display substrate in an embodiment of this disclosure.

[0076] Figure 5B This is a schematic diagram showing the interconnection of multiple second sub-electrodes on the second electrode.

[0077] Figure 6 This is a top view of the structure in an embodiment of the present disclosure, showing the arrangement of adjacent second electrodes along the second direction at intervals.

[0078] Figure 7A For along Figure 2A The CC' section line and along Figure 3 A structural cross-sectional view of the DD' section line in the diagram.

[0079] Figure 7B For along Figure 2A Another structural cross-sectional view of the CC' section line.

[0080] Figure 7C For preparation Figure 7A A flowchart of a display substrate with a mid-pixel structure.

[0081] Figure 7D For preparation Figure 7B A flowchart of a display substrate with a mid-pixel structure.

[0082] Figure 8 This is a top view schematic diagram of the structure of the second electrode in an embodiment of this disclosure.

[0083] Figure 9 This is a schematic diagram showing the distribution of touch signal lines in an embodiment of this disclosure.

[0084] Figure 10 This is a schematic diagram showing the distribution of the second electrode and touch signal lines on the display substrate in an embodiment of this disclosure.

[0085] Figure 11 This is a schematic diagram showing the connection of the touch signal line portion to the data driver chip portion and the connection of the data driver chip portion to the common voltage supply terminal in an embodiment of this disclosure.

[0086] Figure 12 For along Figure 2A A structural cross-sectional view of the EE' section line.

[0087] Figure 13 This is an enlarged top view showing a partial structure of the location of the first via on the substrate, according to an embodiment of this disclosure.

[0088] Figure 14 For along Figure 13 A structural cross-sectional view of the FF' section line.

[0089] Figure 15 This is a top view of the pixel structure within the pixel area on the display substrate where a first via is provided, according to an embodiment of this disclosure.

[0090] Figure 16 This is a schematic diagram showing the distribution of the first via in an embodiment of this disclosure.

[0091] Figure 17 For along Figure 3 A structural cross-sectional view along the GG section line.

[0092] Figure 18 for Figure 2A A simulation diagram of the light effect of the pixel structure of the display substrate.

[0093] Figure 19 for Figure 3 A simulation diagram of the light effect of the pixel structure of the display substrate.

[0094] Figure 20 This is a top view of the structure in this embodiment where the touch signal line located on the domain boundary line is connected to the first via. Detailed Implementation

[0095] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, a display substrate and a display device provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0096] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0097] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on manufacturing processes. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas, but are not intended to be limiting.

[0098] The key technology of TDDI products is that the common electrode is divided into different blocks, and each common electrode is used as a sensing block. Each sensing block is connected to a different touch signal line. When a finger touches the sensor, the capacitance of the sensing block changes. This change in capacitance is transmitted to the processing chip through the touch signal line. Finally, the processing chip accurately determines the position of the touched sensing block and makes a corresponding response.

[0099] Reference Figure 1 This diagram illustrates the pixel design of a TDDI product in related technologies. In this TDDI product, a pixel 4 comprises three sub-pixels 3 (e.g., R, G, B sub-pixels, i.e., red, green, and blue sub-pixels). These three sub-pixels 3 are connected to the same gate line 1 and are driven by scanning through that gate line 1. Each of the three sub-pixels 3 is connected to a different data line 2, which provides data driving signals to each sub-pixel 3. For example, in a 1920×720 resolution product, the number of gate lines 1 is 720, and the number of data lines 2 is 1920×3=5760. The data driving chip (i.e., the source IC) used in this TDDI product has 1920 channels, therefore, a total of three data driving chips are needed to drive all the sub-pixels 3.

[0100] Because the data driver chip in TDDI products integrates touch functionality—meaning it must provide both data drive signals and touch drive signals (data line 2 and touch signal line 7 are both connected to the data driver chip)—this results in a high price for this type of data driver chip, contributing to the high cost of current TDDI products. There is an urgent need for TDDI products that can reduce the number of data driver chips used without changing the resolution.

[0101] In response to the aforementioned problems, referring to Figure 2A and Figure 3 , Figure 2A This is a schematic diagram of the pixel structure and arrangement of a display substrate provided in an embodiment of this disclosure; Figure 3This is a schematic diagram of the pixel structure and arrangement of another display substrate provided in this embodiment of the present disclosure. This embodiment of the present disclosure provides a display substrate including multiple gate lines 1 and multiple data lines 2; the multiple gate lines 1 extend along a first direction X; the multiple data lines 2 extend along a second direction Y; the multiple data lines 2 and the multiple gate lines 1 spatially intersect to define multiple pixel regions 100; each pixel region 100 is provided with at least one sub-pixel 3; at least three sub-pixels 3 adjacent to each other along the second direction Y form a pixel 4; wherein all sub-pixels 3 within a pixel 4 are connected to the same data line 2.

[0102] In some embodiments, the different sub-pixels 3 that make up a pixel 4 are of different colors. For example, three sub-pixels 3 make up a pixel 4, and the colors corresponding to the three sub-pixels 3 are red (R), green (G), and blue (B), respectively. This enables color display of the display substrate. The color corresponding to the sub-pixels 3 within pixel area 100 can also include other colors, such as white. There is no limitation on the color corresponding to the sub-pixels 3 that make up a pixel 4, and any variation in the color corresponding to the sub-pixels 3 contained in any other pixel 4 is within the scope of protection of this disclosure. There is also no limitation on the number of sub-pixels 3 that make up a pixel 4, and any variation in the number of sub-pixels 3 contained in any other pixel 4 is within the scope of protection of this disclosure.

[0103] In some embodiments, each pixel region 100 is provided with a sub-pixel 3; all sub-pixels 3 of a pixel 4 are arranged sequentially along the second direction Y; all sub-pixels 3 of a pixel 4 are respectively connected to different gate lines 1. For example, sub-pixels 3 in three pixel regions 100 form a pixel 4, and the colors corresponding to the sub-pixels 3 in the three pixel regions 100 are red, green and blue, respectively, and the red, green and blue sub-pixels 3 are respectively connected to a gate line 1.

[0104] In this embodiment, the pixel 4 structure of the display substrate is arranged in accordance with the above description. Figure 1 Compared to the pixel design of TDDI products, the number of gate lines 1 is... Figure 1 The number of TDDI products is three times that of data cables 2. Figure 1 This reduces the number of data lines 2 by one-third of the TDDI product, thus greatly reducing the number of data lines 2 used while maintaining the same resolution on the display substrate. Data lines 2 are connected to the data driver chip, which provides data driving signals to them, thereby greatly reducing the number of data driver chips used and thus reducing the cost of using data driver chips.

[0105] In some embodiments, refer to Figure 2B ,for Figure 2AA schematic diagram of pixel arrangement and working principle on a display substrate. Multiple pixels 4 on the display substrate are arranged in an array. Each pixel 4 includes three sub-pixels 3: a red sub-pixel 31, a green sub-pixel 32, and a blue sub-pixel 33. The three sub-pixels 3 are arranged sequentially along the second direction Y. In this pixel array, each row of sub-pixels 3 is arranged along the first direction X; each column of sub-pixels 3 is arranged along the second direction Y. A row of sub-pixels 3 is connected to a gate line 1; a column of sub-pixels 3 is connected to a data line 2. A gate driver chip (not shown) located in the outer bezel area of ​​the display substrate provides a scan signal to the gate line 1; a data driver chip (not shown) located in the outer bezel area of ​​the display substrate provides a data driver signal to the data line 2. When the display substrate is displaying, the gate lines 1 are scanned one by one from top to bottom along the second direction Y. When scanning each gate line 1, all data lines 2 simultaneously input data driver signals to simultaneously illuminate a row of sub-pixels 3. When scanning the last gate line 1, the display substrate completes the display of one frame.

[0106] In some embodiments, refer to Figure 4 and Figure 5A , Figure 4 For along Figure 2A AA section line and Figure 3 A structural sectional view along section line B'B'. Figure 5A This is a schematic diagram showing the segmentation of the second electrode on the display substrate in an embodiment of this disclosure. The display substrate further includes a substrate 5; the pixel 4 includes a first electrode 31 and a second electrode 32 disposed above the substrate 5; the first electrode 31 and the second electrode 32 are sequentially distributed away from the substrate 5; the first electrode 31 includes a plurality of first sub-electrodes 310; the orthographic projection of the first sub-electrodes 310 on the substrate 5 is located in the pixel area; the second electrode 32 includes a plurality of second sub-electrodes 320; the orthographic projection of the second sub-electrodes 320 on the substrate 5 is at least partially located in the pixel area; the orthographic projections of the first sub-electrodes 310 and the second sub-electrodes 320 on the substrate 5 at least partially overlap; the plurality of second sub-electrodes 320 adjacent to each other along the first direction X and the second direction Y are connected to form a second electrode block 321 (i.e., a touch electrode block, such as TX1, TX2, TX3, TX4); the number of second electrodes 321 is less than the number of second sub-electrodes 320; the second electrodes 321 are reused as touch electrodes. This integrates touch functionality into the display substrate.

[0107] In some embodiments, a plurality of second sub-electrodes 320 adjacent to each other along a first direction X are connected to each other to form a second electrode 321. In some embodiments, a plurality of second sub-electrodes 320 adjacent to each other along a second direction Y are connected to each other to form a second electrode 321.

[0108] In some embodiments, refer to Figure 6This is a top view schematic diagram of the structure in this embodiment, showing the spacing between two adjacent second electrodes along the second direction. There are multiple second electrodes 321 arranged in an array; the number of second sub-electrodes 320 forming each second electrode 321 is equal; the second sub-electrodes 320 forming each second electrode 321 are arranged in an array; each second sub-electrode 320 has multiple slits 300; the multiple slits 300 are spaced apart along the second direction Y; the multiple slits 300 extend along the first direction X; in two adjacent rows of second sub-electrodes 320 in two adjacent rows of second electrodes 321 along the second direction Y, one row of second sub-electrodes 320 is disconnected from the other row of second sub-electrodes 320. This achieves mutual disconnection between two adjacent second electrodes 321 along the second direction Y, thereby dividing the second electrode 32 into multiple second electrodes 321 along the second direction Y.

[0109] In some embodiments, the orthographic projection of the gap between two adjacent second electrodes 321 along the second direction Y on the substrate 5 does not overlap with the orthographic projection of the gate line 1 on the substrate 5, and the orthographic projection of the gap between two adjacent second electrodes 321 along the second direction Y on the substrate 5 overlaps with the orthographic projection of the edge of a row of first sub-electrodes 310 located on the edge of one of the second electrodes 321 along the first direction X on the substrate 5.

[0110] In some embodiments, refer to Figure 2A , Figure 3 , Figure 5A , Figure 5B , Figure 7A and Figure 8 , Figure 5B This is a schematic diagram showing the interconnection of multiple second sub-electrodes on the second electrode. Figure 7A For along Figure 2A The CC' section line and along Figure 3 A structural sectional view of the DD' section line; Figure 8 This is a top view schematic diagram of the structure of the second electrode in an embodiment of this disclosure. The display substrate further includes multiple switching transistors 6, with each sub-pixel 3 including one switching transistor 6. The switching transistor 6 is located at the intersection of the data line 2 and the gate line 1. The orthographic projection of the switching transistor 6 on the substrate 5 lies between the opening region of its sub-pixel 3 and the orthographic projection of the data line 2 connected to that sub-pixel 3 on the substrate 5. The gate 61 of the switching transistor 6 is disposed close to the gate line 1 to which it is connected. The source 62 of the switching transistor 6 is disposed close to the data line 2 to which it is connected. The drain 63 of the switching transistor 6 is disposed close to the gate 61 of another switching transistor 6 adjacent to it along the second direction Y. The drain 63 is connected to the first sub-electrode 310. (Refer to...) Figure 5A and Figure 5BTwo adjacent second sub-electrodes 320 on the second electrode 321 along the first direction X are connected by a first connecting portion 322. The first connecting portion 322 extends along the first direction X, and its orthographic projection on the substrate 5 intersects with the orthographic projection of the data line 2 on the substrate 5. The first connecting portion 322 enables the connection between adjacent second sub-electrodes 320 on the second electrode 321 along the first direction X.

[0111] It should be noted that, referring to Figure 5A and Figure 5B No first connection portion is provided between two adjacent second electrodes 321 along the first direction X; thus, the second electrode 32 is divided into multiple second electrodes 321 along the first direction X.

[0112] In some embodiments, the width of the switch 6 along the second direction Y is 28 μm, and the length of the switch 6 along the first direction X is 4 μm. The width and length of the switch 6 are determined after taking into account the aperture ratio of the display substrate and the charging rate of the sub-pixel 3.

[0113] In some embodiments, the first connection portion 322 and the second sub-electrode 320 are located on the same layer.

[0114] In some embodiments, refer to Figure 5A , Figure 5B and Figure 8 It also includes a second connecting portion 323, which is used to connect two adjacent second sub-electrodes 320 on the second electrode 321 along the second direction Y. The second connecting portion 323 realizes the connection between adjacent second sub-electrodes 320 on the second electrode 321 along the second direction Y. In some embodiments, the orthographic projection of the second connecting portion 323 on the substrate 5 overlaps with the gate line 1.

[0115] In some embodiments, refer to Figure 2A , Figure 3 and Figure 9 , Figure 9 This is a schematic diagram of the distribution of touch signal lines in an embodiment of this disclosure. The display substrate further includes multiple sets of touch signal lines 7, each set comprising multiple touch signal lines 7; each touch signal line 7 extends along a second direction Y; each set of touch signal lines 7 corresponds to a column of second electrodes 321; each second electrode 321 is connected to at least one touch signal line 7.

[0116] In some embodiments, each second electrode 321 is connected to two touch signal lines 7.

[0117] In some embodiments, a plurality of second electrodes 321 arranged along the first direction X and the second direction Y respectively form a capacitor with ground. That is, in this embodiment, the second electrodes 321 realize the touch function of the display substrate through the self-capacitance principle. When a finger touches a certain second electrode 321, the capacitance of the finger will be superimposed on the capacitance of the second electrode 321, increasing the capacitance of the second electrode 321. During touch detection, the array of second electrodes 321 arranged along the first direction X and the second direction Y is detected sequentially. Based on the change in capacitance of the second electrodes 321 before and after the touch, the lateral and longitudinal coordinates of the touch position are determined respectively, and then combined into planar touch coordinates.

[0118] It should be noted that the second electrode can also be made into an electrode that intersects horizontally and vertically. The intersecting electrodes form mutual capacitance at the intersection, meaning that these two sets of electrodes constitute the two poles of a capacitor. When a finger touches the mutual capacitance screen, it affects the coupling between the two electrodes near the touch point, thereby changing the capacitance between these two electrodes. This disclosure focuses on structural improvements to the display substrate for self-capacitance touch; the display substrate for mutual capacitance touch will not be described in detail here.

[0119] In some embodiments, refer to Figure 2A Multiple sub-pixels 3 are arranged in an array; a data line 2 and a touch signal line 7 are distributed between any two adjacent columns of sub-pixels 3. This arrangement ensures uniform signal coupling between the data line 2 and the touch signal line 7 between any two adjacent columns of sub-pixels 3, thereby making the display image on the display substrate uniform.

[0120] In some embodiments, the number of touch signal lines can be less than the number of data lines. In this case, one data line and one touch signal line can be distributed between two adjacent columns of sub-pixels; for example, one data line and one touch signal line can be distributed between two adjacent columns of sub-pixels every n columns of sub-pixels. This also ensures that the display image on the display substrate is basically uniform.

[0121] In some embodiments, the linewidth of the gate line 1 is 4-6 μm; the design of the gate line 1 width varies for display substrates with different resolutions. The linewidth of the data line 2 is 3-5 μm; the design of the data line 2 width varies for display substrates with different resolutions. The linewidth of the touch signal line 7 is 3-4 μm; the design of the touch signal line 7 width varies for display substrates with different resolutions. The distance between the touch signal line 7 and the data line 2 located between two adjacent columns of sub-pixels 3 is 4-6 μm; this distance between the touch signal line 7 and the data line 2 is determined by the load of the data line 2. If the distance is too large, it will affect the aperture ratio of the display substrate; if the distance is too small, it will increase the load of the data line 2. Alternatively, if the distance is too small, it may also easily lead to metal residue in the gap between the data line 2 and the touch signal line 7 during the fabrication process, causing a short circuit between the data line 2 and the touch signal line 7.

[0122] For example, refer to Figure 10 and Figure 11 , Figure 10 This is a schematic diagram showing the distribution of the second electrode and touch signal lines on the display substrate in an embodiment of this disclosure. Figure 11This is a schematic diagram showing the connection of the touch signal line portion to the data driver chip portion and the connection of the data driver chip portion to the common voltage supply terminal in this embodiment of the present disclosure. The resolution of the display substrate is 1920×720; each pixel on the display substrate includes one red, one green, and one blue sub-pixel. The second electrode 32 is divided into 48 (arranged along the first direction X) × 18 (arranged along the second direction Y) arrayed second electrode blocks 321; each second electrode block 321 corresponds to 40 (arranged along the first direction X) × 40 (arranged along the second direction Y) arrayed pixels; a touch signal line 7 (i.e., TX line) is distributed between any two adjacent columns of pixels arranged along the second direction Y; each second electrode 321 connects two touch signal lines 7; a set of touch signal lines 7 includes 40 touch... The touch signal lines 7 correspond to a column of second electrodes 321 arranged along the second direction Y. Each column of second electrodes 321 along the second direction Y contains 18 second electrodes 321. These 18 second electrodes 321 in one column are connected to 36 touch signal lines 7 from the set of touch signal lines 7. These 36 touch signal lines 7 are routed from the display area 101 to the fan-shaped wiring area 102 on the display substrate and connected to the data driver chip located in the fan-shaped wiring area 102. The data driver chip provides data driving signals to the data lines 2 and a common voltage signal to the touch signal lines 7 when the display substrate is in use; it also provides touch driving signals to the touch signal lines 7 when the display substrate is touched. The remaining four touch signal lines 7 (i.e., dummy lines) in a set of touch signal lines 7 are not connected to the second electrode 321. These remaining four touch signal lines 7 are routed from the display area 101 on the display substrate to the third region 103 between the display area 101 and the fan-shaped wiring area 102, and are directly connected to the common voltage supply terminal 8 located in the third region 103. The common voltage supply terminal 8 is used to provide a common voltage signal to the remaining four touch signal lines 7 in the set of touch signal lines 7 during display. For example, the remaining four touch signal lines 7 in a set of touch signal lines 7 are distributed on the left and right sides of the 36 touch signal lines 7 in the set along the first direction X, such as two remaining touch signal lines 7 being arranged on each of the left and right sides of the 36 touch signal lines 7 in the set along the first direction X. This ensures that the set of touch signal lines 7 corresponding to a column of the second electrode 321 are evenly distributed.

[0123] It should be noted that the number of touch signal lines 7 in a group of touch signal lines 7 can also be set to an integer multiple of the number of second electrodes 321 in a column of second electrodes 321 distributed along the second direction Y, and all touch signal lines 7 in a group are connected to each of the second electrodes 321 respectively, with no remaining touch signal lines 7 not connected to the second electrodes 321.

[0124] In some embodiments, the number of blocks of the second electrode 32 divided into multiple second electrodes 321 can be adjusted according to the touch control of the specific display substrate; the number of touch signal lines 7 can also be adjusted according to the number of second electrodes 321; in this embodiment, the number of second electrodes 321 and the number of touch signal lines 7 are not limited, as long as each second electrode 321 is connected to at least one touch signal line 7, the sensing of touch signals on each second electrode 321 can be realized.

[0125] As shown in Table 1, these are the parameter settings for the second electrode and the touch signal line on the display substrate with a resolution of 1920×720 in this embodiment of the present disclosure.

[0126]

[0127] Table 1

[0128] In this embodiment, the data driver chip integrates both display driving and touch driving functions. While the cost of this data driver chip is relatively high, the number of data lines on the display substrate of this embodiment is only 1 / 3 of that in the disclosed technology, and the number of touch signal lines on the display substrate of this embodiment is also only 1 / 3 of that in the disclosed technology, thus significantly reducing the number of channels connected to the data lines and the number of channels connected to the touch signal lines in the data driver chip compared to the disclosed technology. This greatly reduces the amount of data driver chips with a fixed number of channels used, thereby significantly reducing the cost of using the data driver chip.

[0129] In some embodiments, refer to Figure 12 , Figure 13 , Figure 14 and Figure 15 , Figure 12 For along Figure 2A A structural sectional view along the EE' section line; Figure 13 This is a magnified top view of a portion of the structure at the location of the first via on the substrate, according to an embodiment of this disclosure. Figure 14 For along Figure 13 A structural sectional view along the FF' section line; Figure 15 This is a top view of the pixel structure within a pixel region on a substrate where a first via is provided, according to an embodiment of this disclosure. The touch signal line 7, data line 2, and the source and drain of the switching transistor are located on the same layer. The second electrode 321 is located on the side of the touch signal line 7 facing away from the substrate 5. A first insulating layer 9 is provided between the second electrode 321 and the touch signal line 7. The second electrode 321 is connected to the touch signal line 7 through a first via 10 formed in the first insulating layer 9. The orthographic projection of the first via 10 onto the substrate 5 is located on the side of the sub-pixel 3 opening region away from the switching transistor 6 within the sub-pixel 3 where it is located.

[0130] In some embodiments, refer to Figure 7A , Figure 12 , Figure 14 and Figure 15 The first insulating layer 9 includes an organic insulating layer 91 disposed between the drain 63 of the switching transistor and the first sub-electrode 310 along a direction away from the substrate 5, and an inorganic insulating layer 92 disposed between the first sub-electrode 310 and the second electrode 321. The drain 63 of the switching transistor is connected to the first sub-electrode 310 through a drain via 90 formed in the organic insulating layer 91 to provide a data drive signal to the first sub-electrode 310. The first via 90 penetrates the organic insulating layer 91 and the inorganic insulating layer 92.

[0131] In some embodiments, refer to Figure 7B , for along Figure 2A Another structural cross-sectional view along the CC' section line. In this view, the first insulating layer consists only of an inorganic insulating layer 92 disposed between the first sub-electrode 310 and the second electrode 321. The drain 63 of the switching transistor 6 is in direct contact with and connected to the first sub-electrode 310; the touch signal line can be connected to the second electrode 321 through a first via penetrating the inorganic insulating layer 92. Figure 7B The pixel structure of the display substrate in the image is only applicable to Figure 2A The pixel structure shown, in which the touch signal line 7 and data line 2 are located in parallel between two adjacent columns of sub-pixels arranged along the second direction Y, is not applicable to... Figure 3 The pixel structure scheme in which the touch signal line 7 is located on the domain boundary of the sub-pixel; because if the touch signal line is located on the domain boundary of the sub-pixel, since the touch signal line and the drain 63 of the switching transistor are on the same layer, and the drain 63 is directly connected to the first sub-electrode 310; therefore, the touch signal line will directly contact the first sub-electrode and short-circuit.

[0132] In some embodiments, the opening size of the drain via 90 ranges from 7 to 10 μm. The opening size of the first via 10 ranges from 4 to 5 μm. The drain via 90 has an inverted trapezoidal cross-sectional shape perpendicular to the substrate 5, and the opening size of the drain via 90 is the opening diameter of the upper opening with the larger opening area. The first via 10 has an inverted trapezoidal cross-sectional shape perpendicular to the substrate 5, and the opening size of the first via 10 is the opening diameter of the upper opening with the larger opening area.

[0133] In some embodiments, refer to Figure 7A , Figure 7B , Figure 12 and Figure 14The active layer 64 of the switching transistor 6 is located on the side of the touch signal line 7, data line 2, source 62 and drain 63 of the switching transistor 6 that are disposed on the same layer, close to the substrate 5; the source 62 and drain 63 are respectively in contact with the opposite ends of the active layer 64; the gate 61 of the switching transistor 6 is located on the side of the active layer 64 close to the substrate 5, and a gate insulating layer 65 is also disposed between the active layer 64 and the gate 61.

[0134] In some embodiments, refer to Figure 7C For the preparation Figure 7A A flowchart of a display substrate with a pixel structure. Specifically, using conventional patterning processes, the gate electrode, gate insulating layer, active layer, source and drain electrodes, touch signal lines and data lines, organic insulating layer, first electrode, inorganic insulating layer, and second electrode are sequentially fabricated on the substrate. The gate insulating layer is formed over the entire surface of the substrate, so its fabrication does not require a mask. However, the fabrication of all other layers on the substrate, except for the gate insulating layer, requires a mask. Figure 7A The display substrate with a medium pixel structure uses a 7-mask process. It should be noted that if the gate insulating layer also needs to form a partial pattern that does not cover the entire surface, then the fabrication of the gate insulating layer also requires a masking process, i.e., fabrication... Figure 7A Display substrates with medium pixel structure can also use the 8mask process.

[0135] In some embodiments, refer to Figure 7D For the preparation Figure 7B A flowchart of a display substrate with a pixel structure. Specifically, using conventional patterning processes, the gate electrode, gate insulating layer, active layer, source and drain electrodes, touch signal lines and data lines, first electrode, inorganic insulating layer, and second electrode are sequentially fabricated on the substrate. The gate insulating layer is formed over the entire surface of the substrate, so its fabrication does not require a mask. However, the fabrication of all other layers on the substrate, except for the gate insulating layer, requires a mask. Figure 7B The display substrate with a medium pixel structure uses a 6mask process.

[0136] In some embodiments, the active layer 64 may be made of amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor material.

[0137] In some embodiments, refer to Figure 13 , Figure 14 and Figure 16 , Figure 16This is a schematic diagram of the distribution of the first vias in this embodiment. A touch signal line 7 is connected to a second electrode 321 through multiple first vias 10; the multiple first vias 10 are arranged along the second direction Y; multiple gate lines 1 are distributed between any two adjacent first vias 10; in a row of pixel areas arranged along the first direction X with first vias 10, the first vias 10 and the drain 63 of the switching transistor 6 are located on different straight lines extending along the first direction X; the minimum distance a between the first via 10 and the gate line 1 is less than the minimum distance b between the connection position of the drain 63 of the switching transistor 6 and the first sub-electrode 310 and the gate line 1.

[0138] In some embodiments, a touch signal line 7 is connected to a second electrode 321 through 5-15 first vias 10. The arrangement of multiple first vias 10 reduces the resistance of the second electrode 321, thereby reducing or avoiding signal attenuation when the common voltage signal or touch signal is transmitted over the second electrode 321. It also reduces or avoids losses when the common voltage signal or touch signal is transmitted to the distant second electrode 321, improving the touch and display performance of the display substrate. It should be noted that the number and distribution of the first vias 10 can be adjusted according to specific products (such as products with different resolutions), and are not limited here.

[0139] For example, refer to Figure 10 and Figure 16 The resolution of the display substrate is 1920×720; each pixel on the display substrate includes one red, one green, and one blue sub-pixel. The second electrode 32 is divided into 48 (arranged along the first direction X) × 18 (arranged along the second direction Y) second electrode blocks 321 arranged in an array; each second electrode block 321 corresponds to 40 (arranged along the first direction X) × 40 (arranged along the second direction Y) pixels arranged in an array; a touch signal line 7 is distributed between any two adjacent columns of pixels arranged along the second direction Y; each second electrode 321 is connected to two touch signal lines 7. Each common electrode block 321 corresponds to 40 rows of pixels arranged along the first direction X. Each pixel is connected to three gate lines 1. One second electrode block 321 corresponds to 120 gate lines 1. A first via 10 is set every 6 gate lines 1. One second electrode 321 corresponds to 20 first vias 10. That is, the two touch signal lines 7 connected to the second electrode 321 are connected to the second electrode 321 through 10 first vias 10.

[0140] In some embodiments, refer to Figure 3 and Figure 17 , Figure 17 For along Figure 3A cross-sectional view of the structure of the GG section line. Multiple sub-pixels 3 are arranged in an array; a data line 2 is distributed between any two adjacent columns of sub-pixels 3; the sub-pixels 3 are divided into two domains along the first direction X; the domain boundaries of a column of sub-pixels 3 are located on the same straight line; the orthographic projection of each touch signal line 7 on the substrate 5 overlaps with the orthographic projection of the domain boundary line of a column of sub-pixels 3 on the substrate 5. In this embodiment, multiple touch signal lines 7 correspond one-to-one with the domain boundaries of multiple columns of sub-pixels 3.

[0141] Reference Figure 18 and Figure 19 , Figure 18 for Figure 2A A simulation diagram of the light effect of the pixel structure of the display substrate;

[0142] Figure 19 for Figure 3 A simulation diagram of the light effect of the pixel structure of the display substrate. The electric field formed between the first and second electrodes at the domain boundary of sub-pixel 3 is different from the electric field formed between the first and second electrodes in other areas of sub-pixel 3. This causes the liquid crystal deflection angle at the domain boundary to be different from other areas, resulting in a lower display brightness at the domain boundary of sub-pixel 3 compared to other areas. For example, if other areas of sub-pixel 3 have a brightness of 255 gray levels, the brightness at the domain boundary will not reach 255 gray levels. Therefore, the domain boundary of sub-pixel 3 appears darker during display, forming a dark area. By placing the touch signal line 7 at the domain boundary position, relative to... Figure 2A The pixel structure in the image can effectively improve the aperture ratio of sub-pixels. For example, calculations show that... Figure 2A The sub-pixel aperture ratio of the medium pixel structure can reach 50%; Figure 3 The sub-pixel aperture ratio of the medium pixel structure can reach 53%. Figure 3 Medium pixel structure relative to Figure 2A The reason for the increased sub-pixel aperture ratio in the mid-pixel structure is: Figure 2A The touch signal line 7 is placed next to and parallel to the data line 2. The touch signal line 7 and the data line 2 are made of the same metal layer. A certain distance needs to be maintained between them, otherwise it is easy to cause a short circuit between them. This distance is usually designed to be about 5μm, which will result in a waste of the sub-pixel aperture ratio.

[0143] In some embodiments, the number of touch signal lines may be less than the number of data lines. In this case, touch signal lines may be distributed on the domain boundaries of some columns of sub-pixels; for example, one touch signal line may be distributed on the domain boundaries of a column of sub-pixels every n columns of sub-pixels.

[0144] In some embodiments, for display substrates with a resolution greater than 280, a non-domain subpixel design can be used; for display substrates with a resolution less than 280, a domain-divided subpixel design can be used, such as dividing one subpixel into two domains, i.e., 1P2D. Subpixel domain division can prevent horizontal stripes from appearing on the display substrate.

[0145] In some embodiments, refer to Figure 3 , Figure 17 and Figure 20 , Figure 20 This is a top view of the structure in this embodiment where a touch signal line located on a domain boundary line is connected to a first via. The domain boundary line of a column of sub-pixels 3 extends along a second direction Y; the touch signal line 7 located on the domain boundary line is connected to the first via 10 via a first connecting line 70; the first connecting line 70 and the touch signal line 7 are located on the same layer; the gate line 1 and the gate of the switching transistor 61 are located on the same layer; the first connecting line 70 is located on the side of the gate line 1 facing away from the substrate 5, and a second insulating layer is provided between the first connecting line 70 and the gate line 1. In some embodiments, the first connection line 70 includes a first sub-connection line 701 and a second sub-connection line 702; the first sub-connection line 701 is connected to the control signal line 7 and the second sub-connection line 702; the second sub-connection line 702 is connected to the first via 10; the first sub-connection line 701 extends along the first direction X, and the orthographic projection of the first sub-connection line 701 on the substrate 1 overlaps with the gate line 1; the orthographic projection of the second sub-connection line 702 on the substrate 5 is located within the pixel region 100, and the orthographic projection of the second sub-connection line 702 on the substrate 5 overlaps with the orthographic projection of the first via 10 on the substrate 5.

[0146] In some embodiments, the second insulating layer is a gate insulating layer 65.

[0147] In some embodiments, refer to Figure 20 The distance between the grid line 1, which overlaps with the orthographic projection of the first sub-connecting line 701, and the first via 10 is the minimum distance a between the grid line 1 and the first via 10.

[0148] In some embodiments, refer to Figure 15In the pixel area where the first via is not provided, the multiple slits 300 on the second sub-electrode 320 are divided into a first group of slits 301 and a second group of slits 302; the first group of slits 301 and the second group of slits 302 are arranged along the second direction Y; the first group of slits 301 includes at least one slit 300; the second group of slits 302 includes at least one slit 300; the second group of slits 302 and the switch tube 6 are arranged along the first direction X; the touch signal line 7 located on the domain boundary line divides the first group of slits 301 and the second group of slits 302 into two sub-slits respectively; the length c of the sub-slit of the first group of slits 301 located on the side of the touch signal line 7 closer to the switch tube 6 is greater than the length d of the sub-slit located on the side of the touch signal line 7 away from the switch tube 6; the length e of the sub-slit of the second group of slits 302 located on the side of the touch signal line 7 closer to the switch tube 6 is less than the length f of the sub-slit located on the side of the touch signal line 7 away from the switch tube 6. Since the second sub-electrode 320 does not extend into the area where the switch tube 6 is located, the length e of the sub-slit of the second set of slits 302 located on the side of the touch signal line 7 closer to the switch tube 6 is less than the length f of the sub-slit located on the side of the touch signal line 7 away from the switch tube 6.

[0149] In some embodiments, refer to Figure 15 The first group of slits 301 includes one slit 300; the second group of slits 302 includes three slits 300 arranged sequentially along the second direction Y.

[0150] In some embodiments, refer to Figure 15 The length d of the sub-slit of the first group of slits 301 located on the side of the touch signal line 7 away from the switch tube 6 is less than the length f of the sub-slit of the second group of slits 302 located on the side of the touch signal line 7 away from the switch tube 6.

[0151] In some embodiments, for example, the length d of the sub-slit of the first set of slits 301 located on the side of the touch signal line 7 away from the switch tube 6 is 43 μm; the length f of the sub-slit of the second set of slits 302 located on the side of the touch signal line 7 away from the switch tube 6 is 53 μm.

[0152] In some embodiments, refer to Figure 15Within the pixel area where the first via 10 is located, multiple slits 300 on the second sub-electrode 320 are divided into a third group of slits 303 and a fourth group of slits 304; the third group of slits 303 and the fourth group of slits 304 are arranged along the second direction Y; the third group of slits 303 includes at least one slit 300; the fourth group of slits 304 includes at least one slit 300; the third group of slits 303 and the first via 10 are arranged along the first direction X; the fourth group of slits 304 and the switching transistor 6 are arranged along the first direction X; The touch signal line 7 on the domain boundary divides the third group of slits 303 and the fourth group of slits 304 into two sub-slits. The length g of the sub-slit of the third group of slits 303 located on the side of the touch signal line 7 away from the first via 10 is greater than the length h of the sub-slit located on the side of the touch signal line 7 close to the first via 10. The length i of the sub-slit of the fourth group of slits 304 located on the side of the touch signal line 7 close to the switch tube 6 is less than the length j of the sub-slit located on the side of the touch signal line 7 away from the switch tube 6. Since the portion of the second sub-electrode 320 extending into the area where the first via 10 is located covers the first via 10, no slit is formed in this portion of the second sub-electrode 320 covering the first via 10. Therefore, the length g of the sub-slit of the third group of slits 303 located on the side of the touch signal line 7 away from the first via 10 is greater than the length h of the sub-slit located on the side of the touch signal line 7 close to the first via 10.

[0153] In some embodiments, refer to Figure 15 The third group of slits 303 includes one slit 300; the fourth group of slits 302 includes three slits 300 arranged sequentially along the second direction Y.

[0154] In some embodiments, refer to Figure 15 The length h of the sub-slit of the third group slit 303 located on the side of the touch signal line 7 near the first via 10 is less than the length j of the sub-slit of the fourth group slit 304 located on the side of the touch signal line 7 away from the switch tube 6.

[0155] In some embodiments, for example, the length h of the sub-slit of the third group of slits 303 located on the side of the touch signal line 7 near the first via 10 is 43 μm; the length j of the sub-slit of the fourth group of slits 304 located on the side of the touch signal line 7 away from the switch tube 6 is 53 μm.

[0156] In some embodiments, in any set of slits, the angle between the extension direction of the sub-slit near the switch tube 6 and the second direction Y is -83°, and the angle between the extension direction of the sub-slit away from the switch tube 6 and the second direction Y is 83°. The angle between the extension direction of the sub-slit and the second direction Y can be adjusted. For example, the angle between the extension direction of the sub-slit near the switch tube 6 and the second direction Y can also be any one of -5°, -7°, -10°, -15°, and -20°, and the angle between the extension direction of the sub-slit away from the switch tube 6 and the second direction Y can also be any one of 5°, 7°, 10°, 15°, and 20°. The larger the angle between the extension direction of the sub-slit and the second direction Y, the faster the response time of the display substrate. Such display substrates are mainly used in products with high response speed requirements, such as game consoles. The smaller the angle between the extension direction of the sub-slit and the second direction Y, the smaller the driving voltage of the electrode electric field on the liquid crystal, and the better the transmittance of the display substrate. Such display substrates are mainly used in products with high transmittance requirements.

[0157] This disclosure also provides a display device, including the display substrate described in the above embodiments.

[0158] In some embodiments, the display device further includes a cell substrate, which is mated with the display substrate to form a cell gap, and liquid crystal is injected into the cell gap, i.e., the display device is a liquid crystal display panel.

[0159] In some embodiments, the display substrate further includes a color filter layer located on the side of the display substrate closest to the cell substrate. The display substrate is in COA (color on array) mode.

[0160] In some embodiments, the cell substrate includes a substrate and a color filter layer, the color filter layer being located on the side of the substrate closer to the display substrate.

[0161] In some embodiments, the color filter layer includes multiple color resists of different colors, such as red, green, and blue color resists, with each color resist corresponding one-to-one with a sub-pixel on the display substrate. The color resists are not limited to red, green, and blue; other colors (such as white) can also be used as color resists, as long as the combination of various color resists within a pixel can achieve color display for that pixel.

[0162] In some embodiments, a pixel includes three sub-pixels, with red, green, and blue color resists each corresponding to one sub-pixel, and the red, green, and blue color resists arranged along a second direction of the three sub-pixels. The order in which the red, green, and blue color resists are arranged along the second direction within a pixel is not limited; they can be arranged sequentially, or they can be arranged sequentially.

[0163] In some embodiments, the color filter layer further includes a black matrix, which corresponds to the area outside the sub-pixel opening area on the display substrate, and is used to block the area outside the sub-pixel opening area on the display substrate (i.e., the non-display area), thereby realizing the color display of the display device.

[0164] In some embodiments, the display panel may also be a Mini LED, Micro LED, or OLED display panel. Further details will not be elaborated upon.

[0165] By using the display substrate in the above embodiments, the number of data lines used is greatly reduced while ensuring that the display panel resolution remains unchanged. The data lines are connected to the data driver chip, which provides data driving signals to them, thereby greatly reducing the number of data driver chips used and thus reducing the cost of using the data driver chips.

[0166] The display panel can be any product or component with display function, such as LCD panel, LCD TV, Mini LED panel, Micro LED panel, OLED panel, mobile phone, tablet computer, laptop computer, monitor, digital photo frame, navigator, etc.

[0167] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising multiple gate lines and multiple data lines; The plurality of gate lines extend along a first direction; the plurality of data lines extend along a second direction. The multiple data lines and the multiple gate lines intersect to define multiple pixel regions; each pixel region is provided with at least one sub-pixel; At least three of the sub-pixels that are adjacent to each other along the second direction constitute a pixel; Wherein, all the sub-pixels within a pixel are connected to the same data line; Each pixel region is provided with a sub-pixel; All the sub-pixels of a pixel are arranged sequentially along the second direction; All the sub-pixels of a pixel are respectively connected to different gate lines; The display substrate further includes a substrate; the pixel includes a first electrode and a second electrode disposed above the substrate; The first electrode and the second electrode are distributed sequentially away from the substrate; The first electrode includes a plurality of first sub-electrodes; the second electrode includes a plurality of second sub-electrodes; The orthographic projections of the first sub-electrode and the second sub-electrode onto the substrate at least partially overlap; A plurality of second sub-electrodes adjacent to each other along the first direction and / or the second direction are connected to each other to form a second electrode block; The second electrode is reused as a touch electrode; There are multiple second electrodes, and these multiple second electrodes are arranged in an array; The display substrate also includes multiple sets of touch signal lines, each set including multiple touch signal lines; Each of the aforementioned touch signal lines extends along the second direction; Each group of the touch signal lines corresponds to a column of the second electrode distribution; Each of the second electrodes is connected to at least one of the touch signal lines; The sub-pixels are arranged in an array; A data line is distributed between any two adjacent columns of the sub-pixels; The sub-pixel is divided into two domains along the first direction; the domain boundaries of a column of the sub-pixels are located on the same straight line; The orthographic projection of each of the touch signal lines on the substrate overlaps with the orthographic projection of the domain boundary lines of a column of sub-pixels on the substrate. 2.The display substrate of claim 1, wherein, The number of second sub-electrodes forming each second electrode block is equal; the second sub-electrodes forming each second electrode block are arranged in an array. Each of the second sub-electrodes has a plurality of slits; the plurality of slits are spaced apart along the second direction; the plurality of slits extend along the first direction respectively; In two adjacent rows of the second sub-electrodes among two adjacent second blocks of electrodes along the second direction, one row of the second sub-electrodes is disconnected from the other row of the second sub-electrodes. 3.The display substrate of claim 2, wherein, It also includes multiple switching transistors, with each sub-pixel including one of the switching transistors; The switching transistor is located at the intersection of the data line and the gate line; and the orthographic projection of the switching transistor on the substrate is located between the opening region of the sub-pixel where it is located and the orthographic projection of the data line connected to the sub-pixel on the substrate. The gate of the switch is located close to the gate line to which it is connected; the source of the switch is located close to the data line to which it is connected; the drain of the switch is located close to the gate of another switch adjacent to it along the second direction. The drain electrode is connected to the first sub-electrode; Two adjacent second sub-electrodes on the second electrode along the first direction are connected by a first connecting portion; The first connecting portion extends along the first direction, and the orthographic projection of the first connecting portion on the substrate intersects with the orthographic projection of the data line on the substrate. 4.The display substrate of claim 3, wherein, The first connecting portion and the second sub-electrode are located on the same layer. 5.The display substrate of claim 4, wherein, It also includes a second connecting portion, which is used to connect two adjacent second sub-electrodes on the second block electrode along the second direction. 6.The display substrate of claim 3, wherein, The touch signal line, the data line, and the source and drain of the switching transistor are located on the same layer; The second electrode is located on the side of the touch signal line opposite to the substrate; a first insulating layer is provided between the second electrode and the touch signal line; The second electrode is connected to the touch signal line through a first via formed in the first insulating layer; The orthographic projection of the first via on the substrate is located on the side of the sub-pixel opening region away from the switching transistor within the sub-pixel in which it is located. 7.The display substrate of claim 6, wherein, One of the touch signal lines is connected to a second electrode through multiple first vias; The plurality of first vias are arranged along the second direction; Multiple grid lines are distributed between any two adjacent first vias; In a row of pixels arranged along the first direction with the first via provided, the first via and the drain of the switching transistor are located on different straight lines extending along the first direction; the minimum distance of the first via from the gate line is less than the minimum distance of the connection position of the drain of the switching transistor and the first sub-electrode from the gate line. 8.The display substrate of claim 7, wherein, The domain boundary line of one column of the sub-pixels extends along the second direction; The touch signal line located on the domain boundary line is connected to the first via through a first connecting line; The first connecting line and the touch signal line are located on the same layer; the gate line and the gate of the switching transistor are located on the same layer; the first connecting line is located on the side of the gate line away from the substrate, and a second insulating layer is provided between the first connecting line and the gate line. 9.The display substrate of claim 8, wherein, The first connecting line includes a first sub-connecting line and a second sub-connecting line; the first sub-connecting line connects the touch signal line and the second sub-connecting line; the second sub-connecting line connects to the first via. The first sub-connecting line extends along the first direction, and the orthographic projection of the first sub-connecting line on the substrate overlaps with the gate line; The orthographic projection of the second sub-connecting line on the substrate is located within the pixel area, and the orthographic projection of the second sub-connecting line on the substrate overlaps with the orthographic projection of the first via on the substrate. 10.The display substrate of claim 6, wherein, In the pixel area where the first via is not provided, the plurality of slits on the second sub-electrode are divided into a first group of slits and a second group of slits; the first group of slits and the second group of slits are arranged along the second direction; The first set of slits includes at least one of the slits; the second set of slits includes at least one of the slits. The second set of slits and the switching transistor are arranged along the first direction; The touch signal line located on the domain boundary line divides the first group of slits and the second group of slits into two sub-slits respectively; The length of the sub-slit located on the side of the touch signal line closer to the switch transistor in the first set of slits is greater than the length of the sub-slit located on the side of the touch signal line farther from the switch transistor. The length of the sub-slit of the second set of slits located on the side of the touch signal line closer to the switch transistor is less than the length of the sub-slit located on the side of the touch signal line farther from the switch transistor. 11.The display substrate of claim 10, wherein, The length of the sub-slit of the first set of slits located on the side of the touch signal line away from the switch transistor is less than the length of the sub-slit of the second set of slits located on the side of the touch signal line away from the switch transistor. 12.The display substrate of claim 6, wherein, Within the pixel region where the first via is provided, the plurality of slits on the second sub-electrode are divided into a third group of slits and a fourth group of slits; the third group of slits and the fourth group of slits are arranged along the second direction; The third group of slits includes at least one of the slits; the fourth group of slits includes at least one of the slits; The third set of slits and the first through hole are arranged along the first direction; the fourth set of slits and the switch tube are arranged along the first direction; The touch signal line located on the domain boundary line divides the third group of slits and the fourth group of slits into two sub-slits respectively; The length of the sub-slit located on the side of the touch signal line away from the first via is greater than the length of the sub-slit located on the side of the touch signal line closer to the first via. The length of the sub-slit located on the side of the touch signal line closer to the switch transistor in the fourth set of slits is less than the length of the sub-slit located on the side of the touch signal line farther from the switch transistor. 13.The display substrate of claim 12, wherein, The length of the sub-slit in the third set of slits located on the side of the touch signal line closer to the first via is less than the length of the sub-slit in the fourth set of slits located on the side of the touch signal line farther from the switch transistor.

14. A display device, wherein, Includes the display substrate as described in any one of claims 1-13.

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