A three-phase interleaved three-level converter current sampling method and system

Abstract

The application discloses a current sampling method and system of a three-phase interleaved parallel three-level converter, and relates to the technical field of power electronics. The method comprises the following steps: obtaining driving signals of each switch tube in the three-phase interleaved parallel three-level converter, and determining a switching period; calculating inductance-free current overlapping time in the switching period of the switch tube by using geometric relations; determining a duty cycle interval according to the inductance-free current overlapping time in the switching period; and driving by using carrier phase-shifted control in the duty cycle interval to obtain sampled current. In a certain duty cycle interval, the application realizes current sampling by using a lower ratio of the number of current sensors to the number of inductors, thereby reducing cost and computation.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a current sampling method and system for a three-phase interleaved parallel three-level converter. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Under the vision of "carbon neutrality," new energy sources, represented by photovoltaics and wind power, will become the main energy sources in the future. Energy storage has become a key technological support for solving the problems of stable grid connection and consumption of new energy sources. Energy storage systems need to achieve bidirectional energy flow between the grid and storage devices. Bidirectional DC-DC power converters are the core equipment of energy storage systems, and related topologies and control schemes have become research hotspots in recent years. Among bidirectional DC-DC converters, the non-isolated interleaved parallel three-level bidirectional DC / DC converter has been widely studied due to its characteristics of low current stress on switching devices, low total output current ripple, low voltage stress on switching transistors, and high power density. The paper "Coupled Inductors in Interleaved Multiphase Three-Level DC–DC Converter for High-Power Applications" published in IEEE Transactions by Lu Sizhao et al. provides a detailed analysis of the current waveforms of this converter topology under different control methods and gives the corresponding expressions.

[0004] However, this topology has a large number of inductors, requiring an inductor current balancing strategy to achieve current sharing. In Sun Wen's master's thesis, "Design of an Interleaved Parallel Bidirectional DC / DC Converter for Electric Vehicles," current sharing was achieved using multiple current loops. However, this method involved numerous current sensors, increasing cost; and the controller employed multiple PI controllers, significantly increasing the computational load on the digital signal processor (DSP). Therefore, reducing the number of components in the current sampling process of a three-phase interleaved parallel three-level converter has become a pressing issue that needs to be addressed in current technology. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a current sampling method and system for a three-phase interleaved parallel three-level converter. By defining a sampling interval, the average current of six inductors can be sampled using two current sensors within a certain duty cycle interval, thereby further reducing the ratio of the number of current sensors to the number of inductors.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] The first aspect of this invention provides a current sampling method for a three-phase interleaved parallel three-level converter, comprising the following steps:

[0008] Obtain the drive signals of each switch in the three-phase interleaved parallel three-level converter and determine the switching period;

[0009] Calculate the non-inductor current overlap time during the switching cycle of the switching transistor using geometric relationships;

[0010] The duty cycle range is determined based on the overlap time of the non-inductor current within the switching cycle. Sampling can only be successful if the overlap time of the non-inductor current within the switching cycle is not zero.

[0011] Within the duty cycle range, the sampled current is obtained by using carrier phase shift control for driving.

[0012] Furthermore, the waveforms of the carrier wave and the modulation wave of the three-phase interleaved parallel three-level converter switching transistors are obtained and compared to generate the switching transistor drive signal.

[0013] Furthermore, the sampling point is taken as the lowest point of the carrier wave.

[0014] Furthermore, the switching transistor is a metal-oxide-semiconductor field-effect transistor.

[0015] Furthermore, based on the topology of the three-phase interleaved parallel three-level converter, the 12 switching transistors are divided into six groups: the first group consists of the first and second switching transistors of phase A; the second group consists of the first and second switching transistors of phase B; the third group consists of the first and second switching transistors of phase C; the fourth group consists of the third and fourth switching transistors of phase A; the fifth group consists of the third and fourth switching transistors of phase B; and the sixth group consists of the third and fourth switching transistors of phase C.

[0016] Furthermore, in the first, second, and third groups of switches, if only one of the first switches in phase A, phase B, and phase C is conducting, the sampling is considered successful; otherwise, the sampling fails. In the fourth, fifth, and sixth groups of switches, if only one of the fourth switches in phase A, phase B, and phase C is conducting, the sampling is considered successful; otherwise, the sampling fails.

[0017] Furthermore, the two switches in each group are complementary and have a dead zone.

[0018] Furthermore, the specific steps of carrier phase shift control are as follows: the three groups of signals of the first, second and third groups of switching transistors are shifted by 180° in sequence.

[0019] Furthermore, the sampling interval is determined based on the duty cycle when the overlap time of the non-inductor current during the switching cycle is not zero. The sampling interval is 0≤d≤2 / 3, where d is the duty cycle.

[0020] The second aspect of the present invention provides a sampling system for the current sampling method of the three-phase interleaved parallel three-level converter of the first aspect, including a three-phase interleaved parallel three-level converter, two filter capacitors and two current sensors. The two filter capacitors are connected in series and then connected in parallel with the three-phase interleaved parallel three-level converter. The two current sensors are respectively located at the connection points of the upper and lower bridge arms that are interleaved in parallel on the input side of the three-phase interleaved parallel three-level converter.

[0021] The above one or more technical solutions have the following beneficial effects:

[0022] This invention discloses a current sampling method and system for a three-phase interleaved parallel three-level converter. It addresses the shortcomings of existing technologies, such as high cost and large computational load due to the large number of current sensors and complex control. The new sampling method performs current sampling and calculates the sampling interval based on the overlap time of the inductor current using geometric relationships. Within a certain duty cycle interval, the average current of the six inductors is obtained by sampling with two current sensors, which further reduces the ratio of the number of current sensors to the number of inductors.

[0023] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0025] Figure 1 This is a topology diagram of the three-phase interleaved parallel three-level converter current sampling system in Embodiment 1 of the present invention;

[0026] Figure 2 This is a schematic diagram of the phase-shifting control principle in Embodiment 2 of the present invention;

[0027] Figure 3 This is a schematic diagram of the PWM and inductor current waveforms when the duty cycle d = 0.2 in Embodiment 2 of the present invention;

[0028] Figure 4 This is a schematic diagram of the PWM and inductor current waveforms when the duty cycle d = 0.5 in Embodiment 2 of the present invention;

[0029] Figure 5 This is a schematic diagram of the PWM and inductor current waveforms when the duty cycle d = 0.8 in Embodiment 2 of the present invention;

[0030] Figure 6 This is a schematic diagram of error analysis under the condition of non-ideal modulation wave in Embodiment 2 of the present invention;

[0031] Figure 7 This is a simulation verification control block diagram in Embodiment 2 of the present invention;

[0032] Figure 8 This is a dynamic comparison diagram of the actual current and the sampled current in Embodiment 2 of the present invention;

[0033] Figure 9 This is a comparison chart of the dynamic performance of the sampling method under sudden load increase and decrease in Embodiment 2 of the present invention. Detailed Implementation

[0034] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0035] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0036] Example 1:

[0037] Embodiment 1 of the present invention provides a current sampling system for a three-phase interleaved parallel three-level converter, such as... Figure 1 As shown, it includes a three-phase interleaved parallel three-level converter, two filter capacitors and two current sensors. The two filter capacitors are connected in series and then in parallel with the three-phase interleaved parallel three-level converter. The two current sensors are located at the connection points of the upper and lower bridge arms that are interleaved in parallel on the input side of the three-phase interleaved parallel three-level converter, respectively.

[0038] Specifically, the two filter capacitors are the first filter capacitor C p Second filter capacitor C n The two current sensors, K1 and K2, respectively sample the current i. sam_p and i sam_n .

[0039] The three-phase interleaved parallel three-level converter includes a DC power supply U dc A capacitor C L A load resistor R L It has six inductors and twelve switching transistors. The six inductors are: Phase A, First Inductor L... a Phase B, first inductor L bC-phase first inductor L c Phase A second inductor L a’ Phase B second inductor L b’ and the second inductor L of phase C c’ .

[0040] All twelve switches are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on the three-phase interleaved parallel three-level converter topology, the twelve switches are divided into six groups. The first group consists of the first switch S of phase A. a1 and the second switch S of phase A a2 The second group is the first switch S of phase B. b1 and the second switch S of phase B b2 The third group is the first switch S of phase C. c1 and the second switch S of phase C c2 The fourth group is the third switch S of phase A. a3 and the fourth switch S of phase A a4 The fifth group is the third switch S of phase B. b3 and the fourth switch S of phase B b4 The sixth group is the third switch S of phase C. c3 and the fourth switch S of phase C c4 Each switching transistor is connected in anti-parallel to a diode, S a1 S a2 S b1 S b2 S c1 S c2 S a3 S a4 S b3 S b4 S c3 S c4 The corresponding diodes are: D a1 D a2 D b1 D b2 D c1 D c2 D a3 D a4 D b3 D b4 D c3 D c4 .

[0041] The DC power supply's positive terminal is connected to the positive terminal of the first filter capacitor, the negative terminal of the first filter capacitor is connected to the positive terminal of the second filter capacitor, and the negative terminal of the second filter capacitor is connected to the negative terminal of the DC power supply. One end of the first current sensor is connected to the positive terminal of the first filter capacitor, and the other end is connected to the drain of the first switch transistor in phase A. One end of the second current sensor is connected to the negative terminal of the second filter capacitor, and the other end is connected to the source of the fourth switch transistor in phase A. The drain of the first switch transistor in phase A is also connected to the drains of the first switch transistors in phase B and phase C; the source of the first switch transistor in phase A is connected to the drain of the second switch transistor in phase A, the source of the second switch transistor in phase A is connected to the drain of the third switch transistor in phase A, and the source of the third switch transistor in phase A is connected to the drain of the fourth switch transistor in phase A; the source of the fourth switch transistor in phase A is also connected to the sources of the fourth switch transistors in phase B and phase C. Similarly, the source of the first switch in phase B is connected to the drain of the second switch in phase B, the source of the second switch in phase B is connected to the drain of the third switch in phase B, and the source of the third switch in phase B is connected to the drain of the fourth switch in phase B. The source of the first switch in phase C is connected to the drain of the second switch in phase C, the source of the second switch in phase C is connected to the drain of the third switch in phase C, and the source of the third switch in phase C is connected to the drain of the fourth switch in phase C. One end of the first inductor in phase A is connected to the source of the first switch in phase A, and the other end is connected to one end of the first inductor in phase B and the first inductor in phase C. The other end of the first inductor in phase B is connected to the source of the first switch in phase B. One end of the first inductor in phase C is connected to the source of the first switch in phase C. Similarly, one end of the second inductor in phase A is connected to the source of the third switch in phase A, and the other end is connected to one end of the second inductor in phase B and the second inductor in phase C. The other end of the second inductor in phase B is connected to the source of the third switch in phase B. One end of the second inductor in phase C is connected to the source of the third switch in phase C. The other end of the first inductor in phase B is also connected to capacitor C. L The positive terminal connection, C L The negative terminal is connected to one end of the second inductor of phase B. The load resistor is connected in parallel with the capacitor CL.

[0042] Because interleaved parallel converters have a large number of inductors and require current sharing, it is necessary to sample the current of each inductor. The sampled value is fed back to the controller for closed-loop control to maintain the balance of inductor current. To sample each inductor, existing technologies employ three sampling methods: sampling with a sampling resistor, inductor DCR sampling, and Hall sensor sampling. Sampling with a sampling resistor has disadvantages such as high loss, large computational load, and many ADC sampling channels (a three-phase interleaved parallel three-level DC / DC converter requires 6 ADC channels), but its advantage is low cost. Inductor DCR sampling is lossless and low-cost, but it requires many ADC sampling channels (a three-phase interleaved parallel three-level DC / DC converter requires 6 ADC channels) and has a large computational load. Hall sensor sampling is lossless, but it requires many ADC sampling channels (a three-phase interleaved parallel three-level DC / DC converter requires 6 ADC channels), has a large computational load, and is costly. Furthermore, the inductor DCR sampling principle utilizes the internal resistance of the inductor and an external loop, limiting the sampling location to the inductor itself, making it impossible to achieve the connection point sampling described in this application.

[0043] Therefore, in this embodiment, a Hall sensor is used as the current sensor, and a new method is designed to reduce the number of sensors in the three-phase interleaved parallel three-level DC / DC converter to two, which greatly reduces the cost of the Hall sensor; and the number of ADC channels is reduced to two, which reduces the cost of the ADC module.

[0044] Example 2:

[0045] Embodiment 2 of the present invention provides a current sampling method for a three-phase interleaved parallel three-level converter, based on the three-phase interleaved parallel three-level converter current sampling system described in Embodiment 1, including the following steps:

[0046] Step 1: Obtain the drive signals of each switch in the three-phase interleaved parallel three-level converter and determine the switching period.

[0047] In one specific implementation, the waveforms of the carrier wave and the modulation wave of the switching transistors of a three-phase interleaved parallel three-level converter are acquired and compared to generate a switching transistor drive signal.

[0048] Step 2: Calculate the non-inductor current overlap time during the switching cycle of the switching transistor using geometric relationships.

[0049] In one specific implementation, all twelve switches are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on the three-phase interleaved parallel three-level converter topology, the twelve switches are divided into six groups. The first group consists of the first switch S of phase A. a1 and the second switch S of phase A a2 The second group is the first switch S of phase B. b1 and the second switch S of phase Bb2 The third group is the first switch S of phase C. c1 and the second switch S of phase C c2 The fourth group is the third switch S of phase A. a3 and the fourth switch S of phase A a4 The fifth group is the third switch S of phase B. b3 and the fourth switch S of phase B b4 The sixth group is the third switch S of phase C. c3 and the fourth switch S of phase C c4 Each switching transistor is connected in anti-parallel to a diode, S a1 S a2 S b1 S b2 S c1 S c2 S a3 S a4 S b3 S b4 S c3 S c4 The corresponding diodes are: D a1 D a2 D b1 D b2 D c1 D c2 D a3 D a4 D b3 D b4 D c3 D c4 The two switches in each group are complementary and have a dead time.

[0050] In the first, second, and third groups of switches, when only one of the first switches in phase A, phase B, and phase C is conducting, i sam_p The sampled value is the instantaneous inductor current corresponding to the conducting MOSFET, and the sampling is considered successful. When two or three MOSFETs are turned on, i sam_p The sampled value is the sum of multiple inductor current values; if this occurs, the sampling is considered a failure. For the fourth, fifth, and sixth groups of switches, if only one of the fourth switches in phase A, phase B, and phase C is conducting, the sampling is considered successful; otherwise, the sampling fails.

[0051] Due to the symmetry of the circuit topology, the first, second, and third groups of switching transistors and their corresponding first inductors La (phase A), Lb (phase B), and Lc (phase C) are analyzed.

[0052] like Figure 3 As shown, u PWMare the waveforms of carrier waves and modulation waves of the first, second and third groups of switching tubes, and the MOSFET drive signal u is generated by comparison ga te. Since the switching frequency of the MOSFET is very high, the change of the modulation wave within the switching period is ignored. The inductor current i Lp 's waveform shows that when the corresponding MOSFET is turned on, the inductor current rises; when the corresponding MOSFET is turned off, the inductor current falls, and it works in the freewheeling conduction state of the MOSFET's parasitic diode. When the duty cycle d=0.2, take i La as an example, during the conduction period of S a1 (t1<t<t2), the inductor current i La rises, i Lb , i Lc falls. At this time, the sampled value of the current is the same as the instantaneous current value on L a , that is, i sam_p (t)=i La (t), and this entire interval is a successful sampling interval. The sampling point is taken at the lowest point of the carrier of S a1 , and the sampled current value at this time is the average value of L a , and the average values of the other two inductor currents are obtained by sampling at the lowest points of the other two carriers.

[0053] i sam_i =(i Limin +i Limax ) / 2=I Li_ave , i=a,b,c

[0054] as Figure 4 shown, when the duty cycle d=0.5, take S b1 as an example, the u gate signal partially overlaps among phases a, b and c. Within the interval t1<t<t2, i sam_p (t)=i La (t)+i Lb (t), the sampled value is the sum of the currents of L a and L b , and sampling fails in this interval; within the interval t3<t<t4, i sam_p (t)=i Lb (t)+i Lc (t), the sampled value is the sum of the currents of L b and L c , and sampling fails in this interval. When t2<t<t3, i sam_p (t)=i Lb (t), and sampling succeeds in this interval. Therefore, the sampling interval is reduced from t1<t<t4 to t2<t<t3. At this time, the lowest point of the carrier of S b1 is still the midpoint of the reduced sampling interval, and the average value i still obtained by sampling is i sam_b =(iLbmin +i Lbmax ) / 2 = I Lb_ave .

[0055] As shown in Figure 5 , when the duty cycle d = 0.8, take S b1 as an example, u gate signals have full overlapping of a, b and c phases. The three intervals t1<t<t2, t3<t<t4 and t5<t<t6 are full overlapping intervals, where i sam_p (t) = i La (t) + i Lb (t) + i Lc (t); the two intervals t2<t<t3 and t4<t<t5 are two-phase overlapping intervals respectively. Based on the above analysis, sampling fails in all cases, and single-phase current cannot be obtained, so this sampling method has a certain samplable interval.

[0056] Step 3: Determine the duty cycle interval according to the non-overlapping time of inductor currents within the switching cycle, where sampling can only succeed when the non-overlapping time of inductor currents within the switching cycle is not zero.

[0057] In a specific embodiment, the sampling interval is determined according to the duty cycle when the non-overlapping time of inductor currents within the switching cycle is not zero, and the sampling interval is 0 ≤ d ≤ 2 / 3, where d is the duty cycle.

[0058] The specific analysis process is as follows:

[0059] When 0 ≤ d ≤ 1 / 3, according to Figure 3 , it can be known that there is no overlap among the three-phase drive signals. When the drive signal is positive, the conduction interval is the successful sampling interval, and there is no sampling failure; t2 - t1 = dT sw , T sw is the switching period of the MOSFET.

[0060] When 1 / 3 < d ≤ 2 / 3, according to Figure 4 , it can be known that the three-phase drive signals are partially overlapped, and calculated through the geometric relationship in the figure the overlapping time of two inductor currents is (t2-t1)+(t4-t3) = T sw (2d - 2 / 3), and the non-overlapping time of inductor currents is (t3-t2) = T sw (2 / 3 - d).

[0061] When 2 / 3 < d ≤ 1, according to Figure 5 , it can be known that the conduction interval is divided into three-inductor current overlapping and two-inductor current overlapping, whose corresponding times are T sw (3d - 2) and 2T sw (1 - d) respectively. At this time, a single inductor current value cannot be obtained by sampling, and sampling fails.

[0062] Table 1 summarizes the results, T 1s T is the time of overlap of inductor-free currents within one switching cycle; 2s T is the overlap time of the two inductor currents within one switching cycle. 3s This is the overlap time of the three inductor currents within one switching cycle. There exists a time T. 1s The proposed sampling method can only be used when the value is not equal to 0. Therefore, the condition for using the proposed sampling method is 0 ≤ d ≤ 2 / 3.

[0063] Table 1. Relationship of Inductor Current Overlap Time During Switching Cycles in Duty Cycle Intervals

[0064]

[0065] Step 4: Within the duty cycle range, drive the sampled current using carrier phase shift control.

[0066] In one specific implementation, such as Figure 2 As shown, the specific steps of carrier phase shift control are as follows: the three groups of signals of the first, second and third groups of switching transistors are shifted by 180° in sequence.

[0067] The sampling method in this embodiment achieves zero-error sampling by ignoring changes in the modulation wave. If the modulation wave changes within one switching cycle, such as Figure 6 As shown, the modulated wave rises at a constant slope, and the sampled current value will be lower than the actual average current value. Figure 6 The geometric relationship yields the following equation:

[0068]

[0069] Where Δi error The sampling error Δi in this case is error =i L -i sam ;Δi ripple It is the ripple Δi of the inductor current. ripple =i max -i min d1 and d2 are already... Figure 6 The bid was successful.

[0070] When the slope of the modulation wave is positive, Δi error >0; When the slope of the modulating wave is negative, Δi error <0; High switching ripple can also lead to increased sampling error.

[0071] Depend on Figure 7 The control block diagram shown illustrates the construction of a dual closed-loop controller for voltage and current. Control parameters are shown in Table 2. A comparison between the sampling method in this embodiment and conventional sampling is verified, yielding the following results. Figure 8As shown, the sampling method in this embodiment produces a current waveform that is smaller than the actual current ripple and closer to the average value of the switching cycle.

[0072] Table 2. Control Parameters of Voltage and Current Dual Closed-Loop Controller

[0073]

[0074] Figure 8 It can be seen that when the modulated wave changes dynamically, the sampled current waveform is slightly delayed compared to the actual current waveform. When the current is in steady state, there is no delay between the sampled current waveform and the actual waveform. Figure 9 To compare the dynamic performance of the sampling method under sudden load increases and decreases, at t = 0.05s, the load changed abruptly from 10Ω to 5Ω; at t = 0.1s, the load changed abruptly from 5Ω to 10Ω. Where I ACSM The results are simulation results of the sampling method in this embodiment. Figure 9 It can be shown that, compared with conventional sampling methods, the sampling method in this embodiment has a negligible impact on the system's speed after load changes, meaning that the sampling method in this embodiment has the same good dynamic characteristics as conventional sampling methods.

[0075] The steps and methods involved in the above embodiment two correspond to those in embodiment one. For specific implementation details, please refer to the relevant description section of embodiment one.

[0076] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A current sampling method for a three-phase interleaved parallel three-level converter, characterized in that, Includes the following steps: In the three-phase interleaved parallel three-level converter, the 12 switching transistors are divided into six groups according to the topology of the three-phase interleaved parallel three-level converter. The first group consists of the first and second switching transistors of phase A, the second group consists of the first and second switching transistors of phase B, the third group consists of the first and second switching transistors of phase C, the fourth group consists of the third and fourth switching transistors of phase A, the fifth group consists of the third and fourth switching transistors of phase B, and the sixth group consists of the third and fourth switching transistors of phase C. For the first, second, and third groups of switches, if only one of the first switches in phase A, phase B, and phase C is conducting, the sampling is considered successful; otherwise, the sampling fails. For the fourth, fifth, and sixth groups of switches, if only one of the fourth switches in phase A, phase B, and phase C is conducting, the sampling is considered successful; otherwise, the sampling fails. The method includes the following steps: Obtain the drive signals of each switch in the three-phase interleaved parallel three-level converter and determine the switching period; Calculate the non-inductor current overlap time during the switching cycle of the switching transistor using geometric relationships; The duty cycle range is determined based on the overlap time of the non-inductor current within the switching cycle. Sampling can only be successful if the overlap time of the non-inductor current within the switching cycle is not zero. Within the duty cycle range, the sampled current is obtained by using carrier phase shift control for driving.

2. The current sampling method for a three-phase interleaved parallel three-level converter as described in claim 1, characterized in that, Obtain the waveforms of the carrier wave and the modulation wave of the switching transistors of the three-phase interleaved parallel three-level converter, compare them, and generate the switching transistor drive signal.

3. The current sampling method for a three-phase interleaved parallel three-level converter as described in claim 2, characterized in that, The sampling point is taken as the lowest point of the carrier wave.

4. The current sampling method for a three-phase interleaved parallel three-level converter as described in claim 1, characterized in that, The switching transistor is a metal-oxide-semiconductor field-effect transistor.

5. The current sampling method for a three-phase interleaved parallel three-level converter as described in claim 1, characterized in that, The two switches in each group are complementary and have a dead zone.

6. The current sampling method for a three-phase interleaved parallel three-level converter as described in claim 1, characterized in that, The specific steps of carrier phase shift control are as follows: the three groups of signals of the first, second and third groups of switching transistors are shifted by 180° in sequence.

7. The current sampling method for a three-phase interleaved parallel three-level converter as described in claim 1, characterized in that, The sampling interval is determined based on the duty cycle when the overlap time of the non-inductor current during the switching cycle is not zero. The sampling interval is: , where d is the duty cycle.

8. A sampling system for the current sampling method of a three-phase interleaved parallel three-level converter according to any one of claims 1-7, characterized in that, It includes a three-phase interleaved parallel three-level converter, two filter capacitors and two current sensors. The two filter capacitors are connected in series and then in parallel with the three-phase interleaved parallel three-level converter. The two current sensors are located at the upper and lower bridge arm connections on the input side of the three-phase interleaved parallel three-level converter, respectively.

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