Current mirror circuit, chip and electronic device
By combining a reference current unit, a current feedback loop unit, and an output-stage transistor unit, and utilizing a current mirror unit composed of a field-effect transistor and a bipolar junction transistor, the problems of inaccurate current transmission and complex structure in traditional current mirror circuits are solved, and higher output stability and response speed are achieved.
Patent Information
- Application Number
- CN202310891258.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-19
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2043-07-19
Smart Images
Figure CN116880655B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuits, in particular to a current mirror circuit, a chip and an electronic device. BACKGROUND
[0002] A current mirror is a commonly used module in the design of analog integrated circuits, which can be used to generate a required current source or transmit a current signal. When designing a current mirror, it is desirable to have higher performance, such as higher output impedance, larger output voltage swing range, more accurate current transmission relationship and faster response time.
[0003] In the application of a conventional current mirror, a transistor is used to design a current mirror, which can achieve better matching characteristics in the same area, and the output impedance and voltage swing are greatly improved. However, due to the inaccuracy of the current transmission relationship caused by the base current, an additional branch to compensate for the base current is usually required, and the circuit structure is relatively complex. SUMMARY
[0004] In view of this, the present application provides a current mirror circuit, a chip and an electronic device, which can further simplify the structure of the current mirror circuit and improve the overall output performance of the current mirror circuit.
[0005] A current mirror circuit, comprising:
[0006] a reference current unit for generating and outputting a reference current signal;
[0007] a current feedback loop unit comprising a first current mirror unit and a second current mirror unit electrically connected, the first current mirror unit being a field effect transistor structure, the second current mirror unit being a bipolar junction transistor structure, the first current mirror unit and the second current mirror unit forming a current feedback loop, the first current mirror unit being electrically connected to an output end of the reference current unit for receiving the reference current signal output by the reference current unit, the first current mirror unit being configured to generate and output a first bias control signal, the second current mirror unit being configured to generate and output a second bias control signal;
[0008] an output stage transistor unit electrically connected to the first current mirror unit and the second current mirror unit, respectively, for receiving the first bias control signal output by the first current mirror unit and the second bias control signal output by the second current mirror unit, and generating at least one target current source according to the first bias control signal and the second bias control signal.
[0009] In one embodiment, the first current mirror unit comprises a first transistor and a second transistor, and the second current mirror unit comprises a third transistor and a fourth transistor.
[0010] The first electrode of the first transistor is connected to a preset voltage or to ground, the control electrode of the first transistor is electrically connected to the control electrode of the second transistor, the first electrode of the second transistor is electrically connected to the reference current unit and the control electrode of the second transistor respectively, and the control electrode of the second transistor is further electrically connected to the first input end of the output stage transistor unit to output a first bias control signal to the first input end of the output stage transistor unit.
[0011] The control electrode of the third transistor is electrically connected to the control electrode of the fourth transistor, the first electrode of the third transistor is electrically connected to the control electrode of the third transistor, the second electrode of the first transistor and the second input end of the output stage transistor unit respectively, and the first electrode of the third transistor is used to output a second bias control signal to the second input end of the output stage transistor unit, and the first electrode of the fourth transistor is electrically connected to the second electrode of the second transistor.
[0012] In one embodiment, when the first electrode of the first transistor is connected to a preset voltage, the second electrode of the third transistor, the second electrode of the fourth transistor and the other output end of the output stage transistor unit are all directly grounded or grounded through respective corresponding decoupling resistors.
[0013] In one embodiment, the output stage transistor unit includes at least one output stage transistor sub-unit, each output stage transistor sub-unit includes a fifth transistor and a sixth transistor, the control electrode of each fifth transistor serves as the first input end of each output stage transistor sub-unit, the control electrode of each sixth transistor serves as the second input end of each output stage transistor sub-unit, the first electrode of each fifth transistor is used to output a corresponding target current source, the second electrode of each fifth transistor is electrically connected to the first electrode of each sixth transistor, and the second electrode of each sixth transistor is directly grounded or the second electrode of each sixth transistor is grounded through a corresponding decoupling resistor.
[0014] In one embodiment, the first transistor, the second transistor and the fifth transistor are all N-type field effect transistors, and the third transistor, the fourth transistor and the sixth transistor are all NPN-type triodes.
[0015] In one embodiment, when the first electrode of the first transistor is connected to ground, the second electrode of the third transistor, the second electrode of the fourth transistor and the other output end of the output stage transistor unit are all connected to a preset voltage or are connected to a preset voltage through respective corresponding decoupling resistors respectively.
[0016] In one embodiment, the output stage transistor unit comprises at least one output stage transistor subunit, each output stage transistor subunit comprises a seventh transistor and an eighth transistor, a control electrode of each seventh transistor is a first input end of each output stage transistor subunit, a control electrode of each eighth transistor is a second input end of each output stage transistor subunit, a first electrode of each seventh transistor is used for outputting a corresponding target current source, a second electrode of each seventh transistor is electrically connected with a first electrode of each eighth transistor, and a second electrode of each eighth transistor is directly connected to a preset voltage or connected to the preset voltage through a corresponding decoupling resistor.
[0017] In one embodiment, the first transistor, the second transistor and the seventh transistor are P-type field effect transistors, and the third transistor, the fourth transistor and the eighth transistor are PNPN type triodes.
[0018] In addition, the application further provides a chip comprising the current mirror circuit.
[0019] In addition, the application further provides an electronic device comprising the chip.
[0020] The current mirror circuit comprises a reference current unit, a current feedback loop unit and an output stage transistor unit. The reference current unit is used for generating and outputting a reference current signal. The current feedback loop unit comprises a first current mirror unit and a second current mirror unit which are electrically connected. The first current mirror unit is a MOS tube structure, and the second current mirror unit is a bipolar junction transistor structure. The first current mirror unit is electrically connected with an output end of the reference current unit, and is used for receiving the reference current signal output by the reference current unit. The first current mirror unit is used for generating and outputting a first bias control signal. The second current mirror unit is used for generating and outputting a second bias control signal. The output stage transistor unit is electrically connected with the first current mirror unit and the second current mirror unit respectively, and is used for receiving the first bias control signal output by the first current mirror unit and the second bias control signal output by the second current mirror unit. The output stage transistor unit generates at least one target current source according to the first bias control signal and the second bias control signal. The current mirror circuit does not need to additionally and separately set a bias circuit structure, and the circuit structure is simplified. Only the first bias control signal and the second bias control signal need to be generated and output by the current feedback loop unit. When the working condition of the bias circuit changes, the current feedback loop unit can quickly respond, so that the generated first bias control signal and second bias control signal remain stable and unchanged, and the output of the current mirror circuit has more consistent matching under different temperatures and process angles, thereby ensuring the stability and reliability of the operation of the entire current mirror circuit. BRIEF DESCRIPTION OF DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application. Based on these drawings, other drawings can be obtained by one skilled in the art without any creative effort.
[0022] Figure 1 is a circuit schematic diagram of a conventional current mirror structure provided by an embodiment of the present application;
[0023] Figure 2 is a circuit schematic diagram of a current mirror structure provided by an embodiment of the present application;
[0024] Figure 3 is a control working process schematic diagram of a current feedback loop unit in a current mirror structure provided by an embodiment of the present application;
[0025] Figure 4 is a circuit schematic diagram of another current mirror structure provided by an embodiment of the present application;
[0026] Figure 5 is a comparison schematic diagram of respective output target current sources of the current mirror structure provided by an embodiment of the present application and a conventional current mirror structure in Figure 1
[0027] Figure 6 is a circuit schematic diagram of still another current mirror structure provided by an embodiment of the present application. DETAILED DESCRIPTION
[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, each of the following embodiments and technical features can be combined with each other without conflict.
[0029] As shown in the current mirror structure in Figure 1 , switches M01, M02, Q01, Q02 and M03 are provided (the connection relationship between the switches is shown in Figure 1 ), wherein M01 and M02 are N-type MOS switches, Q01 and Q02 are NPN-type triodes, the gate of M01 is electrically connected with the gate of M02, the base of Q01 is electrically connected with the base of Q02, the drain of M01 is connected with a constant current source, the drain of M02 is used for outputting current, the collector of Q01 is electrically connected with the gate of M03, the base of Q01 is electrically connected with the source of M03, the drain of M03 is connected with a power supply voltage, and the gates of M01 and M02 are both connected with a separately provided voltage source V0.
[0030] Figure 1 In the current mirror circuit shown, the bias voltage of the MOS switch tube is generated by a separately configured bias circuit (i.e., a bias voltage source). When the operating conditions of the bias circuit change, such as temperature, process angle, and branch current fluctuations, a large amount of current may flow into the base of transistor Q02, which serves as the mirror transistor in the current mirror. As a result, transistor Q02 enters the saturation region, and the amplification capability of transistor Q02 is severely reduced. At this time, this means that the operating state of the current mirror circuit may enter an erroneous state, and the large current may cause irreversible damage to the current mirror circuit.
[0031] like Figure 2 As shown, a current mirror circuit 100 is provided, comprising:
[0032] The reference current unit 110 is used to generate and output a reference current signal.
[0033] The current feedback loop unit 120 includes a first current mirror unit 121 and a second current mirror unit 122 that are electrically connected. The first current mirror unit 121 has a field-effect transistor structure, and the second current mirror unit 122 has a bipolar junction transistor structure. The first current mirror unit 121 and the second current mirror unit 122 form a current feedback loop. The input end of the first current mirror unit 121 is electrically connected to the output end of the reference current unit 110 and is used to receive the reference current signal output by the reference current unit 110. The first current mirror unit 121 is used to generate and output a first bias control signal, and the second current mirror unit 122 is used to generate and output a second bias control signal.
[0034] The output-stage transistor unit 130 is electrically connected to the first current mirror unit 121 and the second current mirror unit 122, respectively, and is configured to receive a first bias control signal output by the first current mirror unit 121 and a second bias control signal output by the second current mirror unit 122, and generate at least one target current source I according to the first bias control signal and the second bias control signal. OUT .
[0035] In this embodiment, the reference current unit 110 is a current source I IN .
[0036] The current mirror circuit 100, through the cooperation of the reference current unit 110, the current feedback loop unit 120 and the output stage transistor unit 130, does not need to set up an additional bias circuit structure. It only needs to generate the first bias control signal and the second bias control signal according to the reference current signal through the current feedback loop unit 120, and control the output of the corresponding target current source I according to the first bias control signal and the second bias control signal. OUT , compared to Figure 1The current mirror circuit 100 only needs two current branches among the three current branches shown, saves the design cost, reduces the design difficulty, and when the working condition of the bias circuit changes, the current feedback loop unit 120 can quickly respond, so that the generated first bias control signal and second bias control signal remain stable and unchanged, thereby making the output of the current mirror circuit 100 have more consistent matching under different temperatures and process angles, and ensuring the stability and reliability of the entire current mirror circuit 100.
[0037] In one embodiment, as shown in Figure 2 The first current mirror unit 121 includes a first transistor M1 and a second transistor M2, and the second current mirror unit 122 includes a third transistor Q1 and a fourth transistor Q2.
[0038] The first electrode of the first transistor M1 is connected to a preset voltage, the control electrode of the first transistor M1 is electrically connected to the control electrode of the second transistor M2, the first electrode of the second transistor M2 is electrically connected to the reference current unit 110 and the control electrode of the second transistor M2 respectively, and the control electrode of the second transistor M2 is also electrically connected to the first input end of the output stage transistor unit 130 to output the first bias control signal to the first input end of the output stage transistor unit 130.
[0039] The first electrode of the first transistor M1 is connected to a preset voltage, the preset voltage can be a fixed voltage that can satisfy the working of the first transistor M1 in the saturation region and the working of the third transistor Q1 in the linear region, and can include an externally connected power supply voltage.
[0040] The control electrode of the third transistor Q1 is electrically connected to the control electrode of the fourth transistor Q2, the first electrode of the third transistor Q1 is electrically connected to the control electrode of the third transistor Q1, the second electrode of the first transistor M1 and the second input end of the output stage transistor unit 130 respectively, the first electrode of the third transistor Q1 is used to output the second bias control signal to the second input end of the output stage transistor unit 130, and the first electrode of the fourth transistor Q2 is electrically connected to the second electrode of the second transistor M2.
[0041] In one embodiment, the second electrode of the third transistor Q1, the second electrode of the fourth transistor Q2 and the other output end of the output stage transistor unit 130 are directly grounded or grounded through respective corresponding decoupling resistors.
[0042] In this embodiment, the first transistor M1, the second transistor M2, the third transistor Q1 and the fourth transistor Q2 constitute a loop control structure, the input of the loop control structure is I IN , the first bias control signal is a voltage control signal, and the second bias control signal includes a voltage control signal and a current control signal.
[0043] Take an example to illustrate this loop control structure, such as Figure 2 As shown, the first transistor M1, the second transistor M2 and the fifth transistor are all N-type field effect transistors, the third transistor Q1, the fourth transistor Q2 and the sixth transistor are all NPN-type triodes, and the output-stage transistor unit 130 includes an output-stage transistor sub-unit. For example, the following description is made:
[0044] The second transistor M2 and the first transistor M1 form a current mirror (i.e., a first current mirror unit 121), and the second transistor M2 controls the drain current of the first transistor M1. The third transistor Q1 and the fourth transistor Q2 form another current mirror (i.e., a second current mirror unit 122), and the third transistor Q1 controls the collector current of the fourth transistor Q2.
[0045] The control process in this loop control structure can be found in Figure 2 and Figure 3 , where V GS1 represents the gate-source voltage of the first transistor M1 (i.e., the first bias control signal, V GS1 At the same time, the fifth transistor M3 is controlled. DS1 represents the drain-source current of the first transistor M1, I CE1 represents the collector current of the third transistor Q1, V BE2 represents the base-emitter voltage of the fourth transistor Q2, I CE2 Represents the collector current of the fourth transistor Q2. Ultimately, under loop control, the current flowing through the fourth transistor Q2 is the same as the current flowing through the second transistor M2. The base currents of the third transistor Q1 and the fourth transistor Q2 serve as errors. V in the loop GS1 and I DS1 The adjustment becomes larger, and the first transistor M1 passes a larger current, compensating the base current of the third transistor Q1 and the fourth transistor Q2. When the output stage transistor unit 130 is connected, a second bias control signal is generated to provide voltage and current control signals to control the sixth transistor Q3.
[0046] In this embodiment, the first bias control signal V is generated by the cooperation of the first transistor M1, the second transistor M2, the third transistor Q1 and the fourth transistor Q2. GS1 The second bias control signal remains stable and unchanged, thereby making the output of the current mirror circuit 100 have more consistent matching under different temperatures and process angles, and can effectively combine the advantages of triode transistors and MOS transistors when applied to current mirror circuits, ensuring the stability and reliability of the operation of the entire current mirror circuit 100.
[0047] In one embodiment, Figure 2As shown, the fifth transistor M3 is an N-type field effect transistor, and the sixth transistor Q3 is an NPN-type transistor, at this time, V GS1 As the first bias control signal and output to the fifth transistor M3, the gate node of the first transistor M1 and the second transistor M2 outputs the second bias control signal to the base of the sixth transistor Q3 to provide the base voltage and the base current control signal to control the sixth transistor Q3.
[0048] In one embodiment, as Figure 2 shown, the output stage transistor unit 130 includes at least one output stage transistor sub-unit, each of which includes a fifth transistor M3 and a sixth transistor Q3, the control electrode of each fifth transistor M3 is the first input terminal of each output stage transistor sub-unit, the control electrode of each sixth transistor Q3 is the second input terminal of each output stage transistor unit 130, the first electrode of each fifth transistor M3 is used to output the corresponding target current source I OUT , the second electrode of each fifth transistor M3 is electrically connected to the first electrode of each sixth transistor Q3, and the second electrode of each sixth transistor Q3 is directly grounded or connected to the ground through a corresponding decoupling resistor.
[0049] In this embodiment, as Figure 4 shown, when the second electrode of each sixth transistor Q3 is connected to the ground through a corresponding decoupling resistor, the noise performance of the entire current mirror circuit can be further improved, wherein the emitter of the third transistor Q1 is connected to the ground through a resistor R1, the emitter of the fourth transistor Q2 is connected to the ground through a resistor R2, and the emitter of the sixth transistor Q3 is connected to the ground through a resistor R3.
[0050] In this embodiment, each output stage transistor sub-unit is electrically connected to the current feedback loop unit 120 through the first input terminal and the second input terminal respectively, and each output stage transistor sub-unit forms a corresponding current mirror structure with the current feedback loop unit 120, wherein the sixth transistor Q3 and the third transistor Q1 form a group of current mirrors, the fifth transistor M3 and the first transistor M1 form another group of current mirrors, and the two groups of current mirrors are electrically connected to form each output stage transistor sub-unit. In other words, each output stage transistor sub-unit as a whole forms a corresponding current mirror structure with the first transistor M1 and the third transistor Q1 as a whole, and the first electrode of each fifth transistor M3 is used to output the corresponding target current source I OUT .
[0051] , the control electrode of the fifth transistor M3 is the first input terminal of the output stage transistor sub-unit, the control electrode of the sixth transistor Q3 is the second input terminal of the output stage transistor unit 130, and the first electrode of the fifth transistor M3 outputs the corresponding target current source I OUT.
[0052] In the embodiment, the voltage output range of the current mirror can be as low as V3CE~(V3DS+ V3CE), wherein V3CE represents the collector-emitter voltage of the sixth transistor Q3, and V3DS represents the drain-source voltage of the sixth transistor M3.
[0053] In one embodiment, as shown in Figure 2 , the first transistor M1, the second transistor M2 and the fifth transistor are all N-type field effect transistors, and the third transistor Q1, the fourth transistor Q2 and the sixth transistor are all NPN-type triodes.
[0054] In one embodiment, the N-type field effect transistor can include an N-type MOS tube, an N-type JFET and an N-type DMOS tube.
[0055] In the embodiment, the output stage transistor unit 130 includes one output stage transistor sub-unit, the first transistor M1, the second transistor M2 and the fifth transistor are all N-type field effect transistors, the third transistor Q1, the fourth transistor Q2 and the sixth transistor are all NPN-type triodes, and the first pole of the fifth transistor M3 is used to output the target current source I OUT , as shown in Figure 5 , the curve H1 is an output schematic diagram of the target current source I OUT in the embodiment, and the curve H2 is an output schematic diagram of the target current source I Figure 1 , wherein the unit value of the ordinate is microampere μA, and the abscissa is time, with the unit value being μs. OUT
[0056] Obviously, by comparing the curves H1 and H2, the output response speed of the target current source I OUT in the curve H1 is faster, in other words, through the cooperation of the first transistor M1, the second transistor M2, the third transistor Q1 and the fourth transistor Q2, the entire current mirror circuit 100 can respond quickly, so that the generated first bias control signal and the second bias control signal remain stable and unchanged, thereby making the output of the current mirror circuit 100 have more consistent matching under different temperatures and process angles, effectively combining the advantages of the respective applications of the triode transistor and the MOS transistor in the current mirror circuit, and ensuring the stability and reliability of the entire current mirror circuit 100.
[0057] In another embodiment, as shown in Figure 6 , a current mirror circuit 100 is provided, the first pole of the first transistor M1 is grounded, the second pole of the third transistor Q1, the second pole of the fourth transistor Q2 and the other output end of the output stage transistor unit 130 are all connected to a preset voltage or respectively connected to a preset voltage through respective corresponding decoupling resistors.
[0058] The first transistor M1 and the second transistor M2 are usually P-type field effect transistors, and the third transistor Q1 and the fourth transistor Q2 are usually PNP-type transistors.
[0059] In one embodiment, the P-type field effect transistor may include a P-type MOS transistor, a P-type JFET, and a P-type DMOS transistor.
[0060] In this embodiment, Figure 2 Compared with the embodiment shown in the figure, the first transistor M1, the second transistor M2, the third transistor Q1 and the fourth transistor Q2 are all replaced by corresponding P-type field effect transistors from the N-type field effect transistors shown in the figure. Although the types of the various transistors are different, the corresponding control and working principles are essentially the same and will not be repeated here.
[0061] In one embodiment, Figure 6 As shown, the output-stage transistor unit 130 includes at least one output-stage transistor sub-unit, each of which includes a seventh transistor M4 and an eighth transistor Q4. The control electrode of each seventh transistor M4 serves as the first input terminal of each output-stage transistor sub-unit, and the control electrode of each eighth transistor Q4 serves as the second input terminal of each output-stage transistor unit 130. The first electrode of each seventh transistor M4 is used to output the corresponding target current source I OUT The second electrode of each seventh transistor M4 is electrically connected to the first electrode of each eighth transistor Q4, and the second electrode of each eighth transistor Q4 is directly connected to the preset voltage or the second electrode of each eighth transistor Q4 is connected to the preset voltage through the corresponding decoupling resistor.
[0062] In this embodiment, when the second electrode of each eighth transistor Q4 is connected to the preset voltage through the corresponding decoupling resistor, the noise performance of the entire current mirror circuit 100 can be further improved.
[0063] In one embodiment, Figure 6 As shown, the first transistor M1 , the second transistor M2 and the seventh transistor M3 are all P-type field effect transistors, and the third transistor Q1 , the fourth transistor Q2 and the eighth transistor Q3 are all PNP-type transistors.
[0064] In addition, a chip is also provided, which includes the above-mentioned current mirror circuit 100.
[0065] In addition, an electronic device is provided, comprising the above chip.
[0066] That is, the above merely describes the embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process conversion using the content of the present application specification and drawings, such as the mutual combination of technical features between embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
[0067] In addition, for structural elements with the same or similar characteristics, the same or different reference numerals can be used for identification in the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.
[0068] In the present application, the word "for example" is used to indicate "as an example, illustration or description". Any embodiment described as "for example" in the present application is not necessarily interpreted as more preferred or more advantageous than other embodiments. In order to enable any person skilled in the art to implement and use the present application, the present application is described above. In the above description, various details are listed for the purpose of explanation.
[0069] It should be understood that those of ordinary skill in the art can realize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid unnecessary details making the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope in accordance with the principles and characteristics disclosed in the present application.
Claims
1. A current mirror circuit, characterized in that: include: A reference current unit, used to generate and output a reference current signal; a current feedback loop unit, comprising a first current mirror unit and a second current mirror unit electrically connected, wherein the first current mirror unit is a field effect transistor structure, and the second current mirror unit is a bipolar junction transistor structure, the first current mirror unit and the second current mirror unit forming a current feedback loop, the first current mirror unit being electrically connected to an output end of the reference current unit and being configured to receive a reference current signal output by the reference current unit, the first current mirror unit being configured to generate and output a first bias control signal, and the second current mirror unit being configured to generate and output a second bias control signal; an output-stage transistor unit, electrically connected to the first current mirror unit and the second current mirror unit, respectively, configured to receive a first bias control signal output by the first current mirror unit and a second bias control signal output by the second current mirror unit, and generate at least one target current source according to the first bias control signal and the second bias control signal; The first current mirror unit includes a first transistor and a second transistor, and the second current mirror unit includes a third transistor and a fourth transistor; the first electrode of the first transistor is used to access a preset voltage or for grounding, the control electrode of the first transistor is electrically connected to the control electrode of the second transistor, the first electrode of the second transistor is electrically connected to the reference current unit and the control electrode of the second transistor, respectively, and the control electrode of the second transistor is also electrically connected to the first input end of the output-stage transistor unit to output the first bias control signal to the first input end of the output-stage transistor unit; the control electrode of the third transistor is electrically connected to the control electrode of the fourth transistor, the first electrode of the third transistor is electrically connected to the control electrode of the third transistor, the second electrode of the first transistor and the second input end of the output-stage transistor unit, respectively, the first electrode of the third transistor is used to output the second bias control signal to the second input end of the output-stage transistor unit, and the first electrode of the fourth transistor is electrically connected to the second electrode of the second transistor.
2. The current mirror circuit according to claim 1, wherein: When the first electrode of the first transistor is used to access a preset voltage, the second electrode of the third transistor, the second electrode of the fourth transistor and the other output end of the output-stage transistor unit are directly grounded or grounded through their respective corresponding decoupling resistors.
3. The current mirror circuit according to claim 2, wherein: The output-stage transistor unit includes at least one output-stage transistor sub-unit, each of the output-stage transistor sub-units includes a fifth transistor and a sixth transistor, the control electrode of each of the fifth transistors serves as the first input terminal of each of the output-stage transistor sub-units, the control electrode of each of the sixth transistors serves as the second input terminal of each of the output-stage transistor sub-units, the first electrode of each of the fifth transistors is used to output the corresponding target current source, the second electrode of each of the fifth transistors is electrically connected to the first electrode of each of the sixth transistors, and the second electrode of each of the sixth transistors is directly grounded or the second electrode of each of the sixth transistors is grounded through a corresponding decoupling resistor.
4. The current mirror circuit according to claim 3, wherein: The first transistor, the second transistor, and the fifth transistor are all N-type field effect transistors, and the third transistor, the fourth transistor, and the sixth transistor are all NPN-type triodes.
5. The current mirror circuit according to claim 1, wherein: When the first electrode of the first transistor is used for grounding, the second electrode of the third transistor, the second electrode of the fourth transistor and the other output end of the output stage transistor unit are all connected to a preset voltage or are respectively connected to an external power supply voltage through their respective corresponding decoupling resistors.
6. The current mirror circuit according to claim 5, wherein: The output-stage transistor unit includes at least one output-stage transistor sub-unit, each of the output-stage transistor sub-unit includes a seventh transistor and an eighth transistor, the control electrode of each of the seventh transistors serves as the first input terminal of each of the output-stage transistor sub-unit, the control electrode of each of the eighth transistors serves as the second input terminal of each of the output-stage transistor sub-unit, the first electrode of each of the seventh transistors is used to output the corresponding target current source, the second electrode of each of the seventh transistors is electrically connected to the first electrode of each of the eighth transistors, the second electrode of each of the eighth transistors is directly connected to the external power supply voltage or the second electrode of each of the eighth transistors is connected to the external power supply voltage through a corresponding decoupling resistor.
7. The current mirror circuit according to claim 6, wherein: The first transistor, the second transistor and the seventh transistor are all P-type field effect transistors, and the third transistor, the fourth transistor and the eighth transistor are all PNP-type triodes.
8. A chip, characterized in that: A current mirror circuit comprising the current mirror circuit according to any one of claims 1 to 7.
9. An electronic device, characterized in that: Comprising the chip according to claim 8.
Citation Information
Patent Citations
Reference current adjusting circuit and reference current generating circuit
CN113359943A
Current control circuit and chip
CN218995943U