A neural network accelerator and soft error handling apparatus and method thereof

Abstract

The application discloses a neural network accelerator and a soft error processing device and method thereof, and applies to the technical field of machine learning, and comprises: a loading device configured to group original filters and configure a check filter for each group; weight loading of each group is sequentially performed in a systolic array, and the check filter of the group is deployed in the first column of the group during loading; the systolic array comprises a check row comprising M check units connected in sequence; the check unit is configured to: when connected with the check filter, pass check data to a next-stage check unit; when connected with the original filter, pass check data to the next-stage check unit, and compare each calculation result output by the original filter with a corresponding check value for error; and an error recovery device configured to perform error processing based on an error comparison result and an error recovery rule. The scheme of the application effectively realizes soft error processing, saves hardware resources and computing resources, and avoids overprotection.

Description

Technical Field

[0001] This invention relates to the field of machine learning technology, and in particular to a neural network accelerator and its soft error handling apparatus and method. Background Technology

[0002] In recent years, CNNs (Convolutional Neural Networks) have emerged as an important deep learning model, widely applied in image recognition, video classification, and natural language processing due to their efficiency and accuracy. A typical CNN consists of convolutional layers, pooling layers, and fully connected layers. The convolutional layers include several three-dimensional filters, each containing specific feature information. When convolved with the input feature map, these filters extract the corresponding features and form the output feature map, which serves as the input to the next layer. As the main functional layer, the computation of the convolutional layer is usually transformed into matrix multiplication, accounting for over 90% of the total network computation. Pooling layers reduce the number of network parameters, and fully connected layers output the final result.

[0003] As the accuracy requirements of models gradually increase, the number of layers and parameters in the latest CNN models are also increasing significantly, leading to higher computational and storage demands. Consequently, computing platforms for performing CNN computation tasks are increasingly shifting towards domain-specific neural network accelerators. Among these, neural network accelerators employing systolic array architectures leverage their pipelined execution mode to reuse data, significantly reducing energy consumption and increasing execution speed during the main multiplication and addition operations in convolutional neural networks. A systolic array consists of a set of highly parallel multiply-accumulate computation units, and its working principle under a fixed-weight data flow is as follows: Figure 1 As shown, a filter is loaded onto a corresponding column of computation units. The organized input is fed in from the left side of the pulsating array. In each clock cycle, the computation unit receives the input feature data from the left, multiplies it with the fixed weights in this computation unit, and adds the calculation result to the partial sum received from above, completing one multiplication-addition operation. Then, the newly generated partial sum is passed to the computation unit below, and the input feature data is passed to the computation unit on the right.

[0004] As chip integration increases and device size decreases, research has revealed that current highly integrated neural network accelerators are susceptible to impacts from high-energy radiation particles and alpha particles in space, causing instantaneous bit flips in the data, resulting in jumps between 0 and 1, such as 010 to 011. This instantaneous data error is called a soft error. Soft errors in critical parameters can cause significant deviations in network output. In safety-critical applications such as drones, autonomous driving, and assisted medical devices, soft errors can lead to catastrophic consequences such as misidentification or non-identification of targets.

[0005] One current solution to this problem is based on redundancy check, which requires two identical systolic arrays and a comparator. The neural network performs computation layer by layer on the systolic arrays. When performing computation on a certain layer, firstly, the same weight matrix is ​​repeatedly loaded onto both systolic arrays; secondly, the input flows into the arrays in the same format for computation; finally, the output values ​​of both arrays flow into the comparator simultaneously. If the output values ​​of the two arrays are consistent, it is considered error-free (due to the randomness of soft errors, it is assumed that soft errors cannot occur at the same location on the two systolic arrays). If the output values ​​of the two arrays are inconsistent, an error is considered to have occurred, and error recovery is required. During error recovery, due to the high data reuse and high pipeline characteristics of the systolic arrays, soft errors propagate rapidly within the arrays. When a soft error is detected, multiple data points may have already been contaminated. In this case, the entire round of computation is restarted to eliminate the impact of soft errors on the data and ensure the reliability of the computation.

[0006] This dual-mode redundancy approach requires copying the weight matrix and input, necessitating additional hardware resources and data transfer overhead. Furthermore, since it requires copying all computations within the neural network, it doubles the computational cost, contradicting the energy-efficient design philosophy of neural network accelerators. Moreover, this approach fails to consider the error-masking characteristics and error tolerance inherent in convolutional neural networks; that is, only soft errors occurring in error-sensitive regions of the network will cause errors in the final output. Layer-by-layer dual-mode redundancy leads to overprotection of the network, introducing excessive and unnecessary computational restarts.

[0007] In summary, how to effectively implement soft error handling in neural network accelerators, save hardware and computing resources, and avoid overprotection are technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to provide a neural network accelerator and its soft error handling device and method, so as to effectively realize soft error handling of the neural network accelerator, save hardware resources and computing resources, and avoid over-protection.

[0009] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0010] A soft error handling device for a neural network accelerator, comprising:

[0011] The loading device is used to group the original filters in the target convolutional layer based on the similarity between the filters, and configure a verification filter for each group; the weights of each group are loaded sequentially in the systolic array, and when loading the weights of any group, the verification filter of the group is deployed in the first column of the group, so that the verification filter of the group receives the input feature data before each original filter of the group.

[0012] A systolic array comprising N×M computational units is used to receive input feature data for convolution computation and output the corresponding computation results through the computational units in its last row.

[0013] The system includes a check row consisting of M check units connected in sequence, and the check row is connected to the last row of the pulsation array to receive the calculation results output by the pulsation array.

[0014] Any one of the M verification units is used to: when connected to the verification filter, sequentially pass the verification values ​​output by the verification filter to the next level verification unit; when connected to any of the original filters, sequentially pass the verification values ​​received from the previous level verification unit to the next level verification unit, and compare the received calculation results output by the original filter with the corresponding verification values ​​received from the previous level verification unit for error.

[0015] The error recovery device connected to the verification line is used to perform error processing based on the error comparison results of each verification unit and the preset error recovery rules;

[0016] Wherein, N and M are the number of rows and columns of the pulsation array, respectively.

[0017] In one embodiment, the verification unit is specifically used for:

[0018] When it connects to the verification filter, it sequentially passes the verification values ​​output by the verification filter to the next level verification unit.

[0019] When connected to any of the original filters, it sequentially transmits the verification values ​​received from the previous verification unit to the next verification unit. It also compares the received calculation results output by the original filter with the corresponding verification values ​​received from the previous verification unit. When the error does not exceed the error threshold configured for the group to which the original filter is located, it sequentially transmits the received calculation results output by the original filter to the error recovery device. When the error exceeds the error threshold, it outputs an error signal and replaces the erroneous calculation result with the corresponding verification value before transmitting it to the error recovery device.

[0020] In one embodiment, the verification unit includes: a first multiplexer, a first register, a second register, a second multiplexer, a control unit, and a comparison unit;

[0021] The first input terminal and the second input terminal of the first multiplexer are respectively connected to the loading device and the pulse array, and the first output terminal and the second output terminal of the first multiplexer are respectively connected to the first input terminal of the first register and the data input terminal of the second register; the first input terminal and the second input terminal of the control unit are respectively connected to the loading device and the previous stage verification unit, and the output terminal of the control unit is connected to the second input terminal of the first register;

[0022] The first, second, and third outputs of the first register are respectively connected to the first input of the second multiplexer, the first input of the comparison unit, and the subsequent verification unit; the first and second outputs of the second register are respectively connected to the second input of the comparison unit and the second input of the second multiplexer; the first and second outputs of the comparison unit are respectively connected to the third input of the second multiplexer and the error recovery device; and the output of the second multiplexer is connected to the error recovery device.

[0023] When the verification unit is connected to the verification filter, the first input terminal of the first multiplexer and the first input terminal of the control unit both receive the first signal sent by the loading device, so that the first multiplexer will sequentially pass the various verification values ​​received by the verification filter through its own second input terminal to the first register, and pass the various verification values ​​to the next-level verification unit through the second output terminal of the first register.

[0024] When the verification unit is connected to any original filter, the first input terminal of the first multiplexer and the first input terminal of the control unit both receive the second signal sent by the loading device, so that the control unit sends each verification value sent by the previous verification unit to the comparison unit and the next verification unit through the first register, and the first multiplexer sequentially transmits each calculation result output by the original filter received through its own second input terminal to the second register, so as to send it to the comparison unit through the second register;

[0025] The comparison unit is used to calculate the error between each calculation result sent by the second register and the corresponding check value sent by the first register. When the error exceeds the error threshold of this group, it outputs an error signal to the second multiplexer and the error recovery device respectively.

[0026] When the second multiplexer does not receive the error signal, the second multiplexer sequentially transmits each calculation result output by the second register to the error recovery device; when the second multiplexer receives the error signal, the second multiplexer replaces the erroneous calculation result with the corresponding check value output by the first register and then transmits it to the error recovery device.

[0027] In one implementation, for any one group, the error threshold configured for that group is the relative error extreme value of the verification filter of that group and the output of each original filter of that group during the forward inference process of a set number of rounds.

[0028] In one embodiment, the loading device includes:

[0029] The validation group partitioning unit is used to group the original filters in the target convolutional layer based on the similarity between filters using the mean-shift clustering algorithm;

[0030] A verification filter generation unit is used to configure one verification filter for each group;

[0031] The filter rearrangement unit is used to load the weights of each group sequentially in the pulsating array. When loading the weights of any one group, the verification filter of that group is deployed in the first column of that group so that the verification filter of that group receives the input feature data before the original filters of that group.

[0032] In one embodiment, the verification filter generation unit is specifically used for:

[0033] For any given group, the verification filter configured for that group is obtained by calculating the average parameter value of each original filter in that group.

[0034] In one implementation, the preset error recovery rules include:

[0035] If a single verification unit reports an error within a single clock cycle, it is determined that the error occurred in the calculation result output by a single raw filter, and the erroneous calculation result is replaced with the corresponding verification value.

[0036] If a single verification unit reports an error within K consecutive clock cycles, it is determined that the error occurred in the weight of a single original filter. The weights of the group containing the original filter that caused the error are then reloaded, and the calculation is restarted from the location of the error.

[0037] If multiple error detection units report errors in adjacent clock cycles, it is determined that the error occurred in the weight of the verification filter or in the input feature data. The weight of the group containing the erroneous verification filter is then reloaded, and the calculation is restarted from the error location.

[0038] A neural network accelerator includes a soft error handling device as described above for a neural network accelerator.

[0039] In one implementation, the neural network accelerator is specifically a convolutional neural network accelerator.

[0040] A soft error handling method for a neural network accelerator, applied in the soft error handling device of the neural network accelerator as described above, includes:

[0041] The loading device groups the original filters in the target convolutional layer based on the similarity between the filters and configures one validation filter for each group;

[0042] The loading device sequentially loads the weights of each group in the pulse array, and when loading the weights of any one group, it deploys the verification filter of that group in the first column of that group, so that the verification filter of that group receives the input feature data before each original filter of that group.

[0043] The pulsating array receives input feature data to perform convolution calculations and outputs the corresponding calculation results through the calculation units in its last row.

[0044] When the verification unit is connected to the verification filter, the verification unit will sequentially pass the verification values ​​output by the verification filter to the next level verification unit.

[0045] When the verification unit is connected to the original filter, the verification unit will sequentially pass the verification values ​​received from the previous verification unit to the next verification unit, and compare the error between the calculation results received from the original filter and the corresponding verification values ​​received from the previous verification unit.

[0046] The error recovery device performs error processing based on the error comparison results of each verification unit and the preset error recovery rules;

[0047] Wherein, N and M are the number of rows and columns of the pulsation array, respectively.

[0048] By applying the technical solution provided in the embodiments of the present invention, the original filters in the target convolutional layer are divided into multiple verification groups by utilizing the error resilience of the neural network itself and the similarity characteristics of the filters within the layer. Inaccurate verification is performed within each group, thereby ensuring that serious errors are detected and recovered while avoiding overprotection of minor errors that occur in the neural network.

[0049] Specifically, the loading device groups the original filters in the target convolutional layer based on the similarity between filters and configures one verification filter for each group. This means that, under normal circumstances, the calculation result of the same group should be close to that of the verification filter. When loading the weights of each group sequentially in the systolic array, for any given group, in this application's scheme, the verification filter for that group is deployed in the first column of that group. This allows the verification filter of that group to receive the input feature data before the original filters of that group, meaning that the verification values ​​output by the verification filter can be transmitted through the verification unit. In this application, one verification row includes M sequentially connected verification units, and the verification row is connected to the last row of the systolic array, thus enabling the reception of the calculation results output by the systolic array. For any one of the M verification units, if the verification unit is connected to a verification filter, it will sequentially pass the verification values ​​output by the verification filter to the next-level verification unit. If the verification unit is connected to any original filter, it will not only sequentially pass the verification values ​​received from the previous-level verification unit to the next-level verification unit, but also compare the received calculation results output by the original filter with the corresponding verification values ​​received from the previous-level verification unit for error. The error recovery device can then perform error handling based on the error comparison results of each verification unit and preset error recovery rules. It is understood that if the error between the calculation results output by the original filter and the corresponding verification value is small, it can be considered that no error occurred during the calculation process, or the error has a small impact on the network. That is, this application does not require that the calculation results output by the original filter be completely consistent with the corresponding verification value, thus avoiding over-protection. Of course, if the error is large, appropriate error handling can be performed.

[0050] As can be seen, in the scheme of this application, the original filters in the target convolutional layer need to be divided into multiple verification groups, and then one verification filter is configured for each group. In terms of hardware, a row of verification lines including M sequentially connected verification units needs to be set to realize error comparison. Compared with the traditional dual-mode redundancy method, which requires twice the computational overhead and hardware resources, the scheme of this application requires very few hardware and computational resources.

[0051] In summary, the solution proposed in this application can effectively implement soft error handling for neural network accelerators, saving hardware and computing resources and avoiding over-protection. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram illustrating the working principle of a pulsating array.

[0054] Figure 2 This is a schematic diagram of the structure of a soft error handling device for a neural network accelerator according to the present invention;

[0055] Figure 3a This is a schematic diagram of the input feature map and two filters required for convolution calculation in a specific scenario.

[0056] Figure 3b This is a schematic diagram illustrating the conversion of an input feature map into vector form of input feature data in one specific implementation method.

[0057] Figure 3c This is a schematic diagram illustrating the calculation of the pulsating array in the first clock cycle in one specific implementation.

[0058] Figure 3d This is a schematic diagram illustrating the calculation of the pulsating array in the second clock cycle in one specific implementation.

[0059] Figure 3e This is a schematic diagram illustrating the calculation of the pulsating array in the third clock cycle in one specific implementation.

[0060] Figure 3f This is a schematic diagram illustrating the calculation of the pulsating array in the fourth clock cycle in one specific implementation.

[0061] Figure 3g This is a schematic diagram illustrating the calculation of the pulsating array in the fifth clock cycle in one specific implementation.

[0062] Figure 4 This is a schematic diagram illustrating the connection between the pulsating array and the check row in one specific implementation.

[0063] Figure 5 This is a schematic diagram of the structure of a verification unit in one specific embodiment;

[0064] Figure 6This is a schematic diagram of the structure of a neural network accelerator in one specific embodiment;

[0065] Figure 7 This is a flowchart illustrating the implementation of a soft error handling method for a neural network accelerator according to the present invention. Detailed Implementation

[0066] The core of this invention is to provide a soft error handling device for neural network accelerators, which can effectively realize soft error handling of neural network accelerators, save hardware and computing resources, and avoid over-protection.

[0067] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0068] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a soft error processing device for a neural network accelerator according to the present invention. The soft error processing device for the neural network accelerator may include:

[0069] The loading device 10 is used to group the original filters in the target convolutional layer based on the similarity between the filters, and configure a verification filter for each group; the weights of each group are loaded sequentially in the systolic array 20, and when loading the weights of any group, the verification filter of the group is deployed in the first column of the group, so that the verification filter of the group receives the input feature data before each original filter of the group.

[0070] A systolic array 20 comprising N×M computing units is used to receive input feature data for convolution calculation and output the corresponding calculation results through the computing units in its last row.

[0071] The system includes a check row 30 consisting of M check units connected in sequence, and the check row 30 is connected to the last row of the pulsation array 20 to receive the calculation results output by the pulsation array 20.

[0072] Any one of the M verification units is used to: when connected to a verification filter, pass the verification values ​​output by the verification filter to the next level verification unit in sequence; when connected to any original filter, pass the verification values ​​received from the previous level verification unit to the next level verification unit in sequence, and compare the error between the calculation results received from the original filter and the corresponding verification values ​​received from the previous level verification unit.

[0073] The error recovery device 40, connected to the check line 30, is used to perform error processing based on the error comparison results of each check unit and the preset error recovery rules;

[0074] Where N and M are the number of rows and columns of the pulsating array 20, respectively.

[0075] Specifically, in the solution of this application, the weights of the filters are loaded through the loading device 10, and the original filters in the target convolutional layer are pre-grouped. The specific hardware configuration of the loading device 10 can be set and adjusted according to actual needs, as long as it can meet the functional requirements of the loading device 10 of this application.

[0076] The target convolutional layer can be any one convolutional layer in the neural network. In other words, the neural network accelerator of this application can realize the convolution calculation of any one convolutional layer.

[0077] The target convolutional layer includes one or more filters, usually multiple filters. In this application, these filters are referred to as the original filters of the target convolutional layer.

[0078] Neural networks inherently possess redundancy, meaning that the same layer of a network typically contains filters with similar structures and functions. Since filters in the same convolutional layer share the same input, the feature maps generated by similar filters are also similar. In this application's solution, filters are grouped based on their similarity. That is, similar filters are grouped into the same group, so that in subsequent processes, error detection can be achieved by using a single validation filter configured for that group for each original filter within the same group.

[0079] After grouping the original filters in the target convolutional layer, a verification filter needs to be configured for each group. The specific weight configuration of the verification filter can be set and adjusted according to actual needs. However, it is understood that the verification filter should have a general error detection capability for each original filter in the group. For example, a simple and convenient implementation is to calculate the average parameter value of each original filter in the group to generate the verification filter for that group.

[0080] Furthermore, it should be noted that for a trained neural network, since the weights of each original filter are deterministic, the original filters in the target convolutional layer can be grouped offline, and a corresponding validation filter can be configured for each group. After obtaining the validation filters for each group, the weights of each group can be loaded sequentially in the systolic array 20. When loading the weights of any group, the validation filter for that group needs to be deployed in the first column of that group, so that the validation filter of that group receives the input feature data before the original filters of that group.

[0081] For easier understanding, please refer to Figures 3a to 3g The calculation principle of convolution calculation for pulsating array 20 is explained. Figure 3a This diagram illustrates the input feature map requiring convolution calculations and two filters. The input feature map is a 1-channel, 3×3 matrix, while both filters are 1-channel, 2×2 matrices. Figure 3a The image shows the output results of the two filters after the convolution calculation.

[0082] Figure 3b This is a schematic diagram of converting the input feature map into input feature data in vector form. Both filters are loaded into the systolic array 20. Each filter occupies one column of the systolic array 20, that is, it occupies four computing units in the systolic array 20.

[0083] Figure 3c This is a schematic diagram of the calculation of the pulsating array 20 in the first clock cycle. At this time, the first calculation unit of the first column filter performs a 1*A calculation.

[0084] Figure 3d The diagram illustrates the calculation of the systolic array 20 in the second clock cycle. The first calculation unit of the first column filter calculates A in the first clock cycle, which needs to be passed down to the second calculation unit of the first column filter. At this time, the second calculation unit of the first column filter performs the calculation A + 2 * B. Furthermore, the first calculation unit of the first column filter needs to pass the input feature data 1 to the right to the first calculation unit of the second column filter, so that in the second clock cycle, the first calculation unit of the second column filter performs the calculation 1 * a.

[0085] Figure 3e This is a calculation diagram of the pulsating array 20 in the third clock cycle. At this time, the third calculation unit of the first column filter performs the calculation of A+2B+4*C. Figure 3f This is a schematic diagram of the calculation of the pulsating array 20 in the fourth clock cycle. At this time, the fourth calculation unit of the first column filter performs the calculation of A+2B+4C+5*D. Figure 3g This is a calculation diagram of the systolic array 20 in the fifth clock cycle. At this time, the fourth calculation unit of the first column filter outputs A+2B+4C+5D, which can be combined with... Figure 3a As can be seen, this value is one of the values ​​in the 2×2 matrix result that the first column filter needs to output. It can be understood that in the following 3 clock cycles, the 4th calculation unit of the first column filter will output 2A+3B+5C+6D, 4A+6B+7C+8D, and 5A+6B+8C+9D in sequence.

[0086] In the scheme of this application, a verification row 30 is set up, which includes M verification units connected in sequence. The verification row 30 is connected to the last row of the pulsation array 20 to receive the calculation results output by the pulsation array 20.

[0087] See also Figure 4 This illustrates a schematic diagram of the connection between the pulsating array 20 and the check row 30 in a specific scenario. Figure 4 In the implementation, Fc represents the verification filter configured for a certain group, while F1, F2 and F3 are the three original filters for the same group. Figure 4 The last line in the table is check line 30, which consists of four check units connected in sequence.

[0088] As described above, when loading weights for any group, the validation filter for that group is deployed in the first column of that group. This ensures that the validation filter for that group receives the input feature data before the original filters for that group. Figure 4 In this context, the validation filter is deployed in the first column of the group, so that the validation filter is calculated before other original filters in the group.

[0089] For the verification unit of this application, the column where the verification unit is located may be the column where the verification filter is located or the column where the original filter is located. That is, the verification unit may be connected to the verification filter or the original filter.

[0090] When a verification unit is connected to a verification filter, the verification unit will sequentially pass the verification values ​​output by the verification filter to the next-level verification unit. Figure 4 For example, to facilitate description, Figure 4 The four check units from left to right in check row 30 are called check units 1 to 4, respectively. Figure 4 During clock cycle 1, the check value output by the check filter Fc is C1, and check unit 1 receives the check value C1. Figure 4During clock cycle 2, the verification value output by the verification filter Fc is C2, and the verification unit 1 passes the verification value C1 received in the previous clock cycle to the next-level verification unit, namely the next-level verification unit 2.

[0091] Figure 4 In the process, except for verification unit 1 which is connected to the verification filter, verification units 2-4 are all connected to the original filter.

[0092] Since verification unit 2 is connected to the original filter F1, it sequentially transmits the verification values ​​received from the previous verification unit 1 to the next verification unit. Furthermore, verification unit 2 compares the received calculation results output by the original filter with the corresponding verification values ​​received from the previous verification unit for error correction. Figure 4 With a clock cycle of 2, the calculated result of the original filter F1 output is O. 11 Verification unit 2 will calculate the result O 11 Compare the error with the check value C1.

[0093] Similarly, in Figure 4 In clock cycle 3, the check value output by check filter Fc is C3, and check unit 1 passes the check value C2 received in clock cycle 2 to check unit 2, while check unit 2 passes the check value C1 received in clock cycle 2 to check unit 3. The calculation result output by the original filter F1 is O. 12 Verification unit 2 will calculate the result O 12 The error is compared with the check value C2, and the calculated result of the original filter F2 is O. 21 Verification unit 2 will calculate the result O 21 Compare the error with the check value C1.

[0094] As can be seen, the verification value C1 output by the verification filter Fc is sequentially passed from verification unit 1 to verification unit 4. Each time it is passed to a verification unit, that unit compares the verification value C1 with the calculation result currently output by the connected original filter, thus achieving real-time verification. Similarly, the verification values ​​C2 to C4 output by the verification filter Fc are also sequentially passed from verification unit 1 to verification unit 4, performing error comparisons with the corresponding calculation results of each original filter, thereby realizing real-time verification.

[0095] The error recovery device 40 is connected to the verification line 30 and can perform error processing based on the error comparison results of each verification unit and preset error recovery rules. The specific content of the error recovery rules can be set and adjusted according to actual needs. However, it is understood that when the error between a certain calculation result of a certain original filter and the corresponding verification value is small, it can be considered that no error occurred during the calculation process or that the impact of the error is minimal, having no effect on the result of the neural network. This avoids overprotecting minor errors in the neural network, thus reducing the overhead of error recovery. Only when the error is large will appropriate error processing be performed.

[0096] In one specific embodiment of the present invention, the verification unit may be specifically used for:

[0097] When it connects to the verification filter, it sequentially passes the verification values ​​output by the verification filter to the next level verification unit.

[0098] When connected to any original filter, it sequentially transmits the verification values ​​received from the previous verification unit to the next verification unit. It also compares the error of the calculation results received from the original filter with the corresponding verification values ​​received from the previous verification unit. When the error does not exceed the error threshold configured for the group to which the original filter is located, it sequentially transmits the calculation results received from the original filter to the error recovery device 40. When the error exceeds the error threshold, it outputs an error signal and replaces the erroneous calculation result with the corresponding verification value before transmitting it to the error recovery device 40.

[0099] This implementation takes into account that when the verification unit is connected to the original filter, the verification unit needs to receive each verification value from the previous verification unit and pass it sequentially to the next verification unit. Simultaneously, the verification unit also needs to compare the received calculation results output by the original filter with the corresponding verification values ​​received from the previous verification unit to determine the error.

[0100] When performing any one error comparison, if the error does not exceed the error threshold configured for the group containing the original filter, it can be considered that no error occurred during the calculation process or that the impact of the error is minimal and has no effect on the result of the neural network. Therefore, the verification unit can sequentially transmit the received calculation results output by the original filter to the error recovery device 40. In other words, if the error does not exceed the error threshold, the verification unit of this application will not change the output of the original filter.

[0101] Correspondingly, if the error exceeds the error threshold, the verification unit will output an error signal, and will replace the erroneous calculation result with the corresponding verification value before transmitting it to the error recovery device 40. In other words, if the error exceeds the error threshold, the verification unit of this application will use the verification value to replace the original filter output and transmit it to the error recovery device 40.

[0102] For each group, the error threshold setting can be adjusted according to the actual situation. In a specific embodiment of the present invention, for any one group, the error threshold configured for that group is the relative error extreme value output by the verification filter of that group and each original filter of that group during the forward inference process of a set number of rounds.

[0103] In this implementation, considering that a certain number of rounds of forward inference can be performed on the trained network, and during this process, the extreme value of the relative error between the output of the verification filter and the original filter can be set as the verification threshold. Since the relative error is used, the influence of different input vector magnitudes on the threshold can be reduced.

[0104] The specific hardware configuration of the verification unit in this application can be set and adjusted according to actual needs, as long as it can achieve the functional requirements of the verification unit in this application. For example, in a specific embodiment of this invention, please refer to... Figure 5 The verification unit includes: a first multiplexer 31, a first register 33, a second register 34, a second multiplexer 32, a control unit 35, and a comparison unit 36;

[0105] The first input terminal and the second input terminal of the first multiplexer 31 are respectively connected to the loading device 10 and the pulse array 20, and the first output terminal and the second output terminal of the first multiplexer 31 are respectively connected to the first input terminal of the first register 33 and the data input terminal of the second register 34; the first input terminal and the second input terminal of the control unit 35 are respectively connected to the loading device 10 and the previous stage verification unit, and the output terminal of the control unit 35 is connected to the second input terminal of the first register 33;

[0106] The first, second, and third outputs of the first register 33 are respectively connected to the first input of the second multiplexer 32, the first input of the comparison unit 36, and the subsequent verification unit; the first and second outputs of the second register 34 are respectively connected to the second input of the comparison unit 36 ​​and the second input of the second multiplexer 32; the first and second outputs of the comparison unit 36 ​​are respectively connected to the third input of the second multiplexer 32 and the error recovery device 40; the output of the second multiplexer 32 is connected to the error recovery device 40.

[0107] When the verification unit is connected to the verification filter, the first input terminal of the first multiplexer 31 and the first input terminal of the control unit 35 both receive the first signal sent by the loading device 10, so that the first multiplexer 31 will sequentially transmit the various verification values ​​received by the verification filter through its own second input terminal to the first register 33, and transmit the various verification values ​​to the next-level verification unit through the second output terminal of the first register 33.

[0108] When the verification unit is connected to any original filter, the first input terminal of the first multiplexer 31 and the first input terminal of the control unit 35 both receive the second signal sent by the loading device 10, so that the control unit 35 sends each verification value sent by the previous verification unit to the comparison unit 36 ​​and the next verification unit through the first register 33, and the first multiplexer 31 transmits each calculation result received by the original filter through its own second input terminal to the second register 34 in sequence, so as to send it to the comparison unit 36 ​​through the second register 34;

[0109] The comparison unit 36 ​​is used to calculate the error between each calculation result sent by the second register 34 and the corresponding check value sent by the first register 33. When the error exceeds the error threshold of this group, it outputs an error signal to the second multiplexer 32 and the error recovery device 40 respectively.

[0110] When the second multiplexer 32 does not receive an error signal, it sequentially transmits the calculation results output by the second register 34 to the error recovery device 40; when the second multiplexer 32 receives an error signal, it replaces the erroneous calculation result with the corresponding check value output by the first register 33 and then transmits it to the error recovery device 40.

[0111] In this embodiment, a specific hardware configuration of the verification unit is given. The verification unit includes a first multiplexer 31, a first register 33, a second register 34, a second multiplexer 32, a control unit 35, and a comparison unit 36. The structure is relatively simple, the reliability is high, and it is easy to implement.

[0112] When a verification unit is connected to a verification filter, the verification unit is in value-passing mode. This means that the verification unit only needs to sequentially pass the verification values ​​output by the verification filter to the next-level verification unit. Figure 5 In this case, the data transmission path is: verification filter - first multiplexer 31 - first register 33 - control unit 35 of the next level verification unit.

[0113] The first input terminal of the first multiplexer 31 is connected to the loading device 10, and the first input terminal of the control unit 35 is also connected to the loading device 10. When the verification unit is in the value transmission mode, both the first input terminal of the first multiplexer 31 and the first input terminal of the control unit 35 receive the first signal sent by the loading device 10, for example... Figure 5 In specific situations, the first signal can be a high-level electrical signal 1.

[0114] Correspondingly, when the verification unit is connected to the original filter, the verification unit is in verification mode. At this time, the first input terminal of the first multiplexer 31 and the first input terminal of the control unit 35 both receive the second signal sent by the loading device 10, for example, the second signal can be a low-level electrical signal 0.

[0115] In the verification mode, the control unit 35 will send each verification value sent by the previous level verification unit to the first register 33 in sequence, and then send it to the comparison unit 36 ​​through the first register 33. At the same time, the first register 33 will pass each verification value to the next level verification unit in sequence, that is, to the second input terminal of the control unit in the next level verification unit.

[0116] In the verification mode, the second input of the first multiplexer 31 receives the calculation results output by the original filter. The first multiplexer 31 will pass each calculation result to the second register 34 in sequence, and then send it to the comparison unit 36 ​​through the second register 34.

[0117] As can be seen, in the verification mode, the comparison unit 36 ​​can receive the calculation results sent by the second register 34 and the corresponding verification value sent by the first register 33. Therefore, the comparison unit 36 ​​can calculate the error between the two and determine whether the error exceeds the error threshold of this group.

[0118] If the error exceeds the error threshold of this group, it indicates that the error is large. The comparison unit 36 ​​will output error signals to the second multiplexer 32 and the error recovery device 40 respectively. Since the second multiplexer 32 receives the error signal, it will replace the erroneous calculation result with the corresponding check value output by the first register 33. That is, at this time, the second multiplexer 32 selects the value sent by the first register 33 as the output and passes it to the error recovery device 40.

[0119] Of course, if the second multiplexer 32 does not receive an error signal, it means that no error occurred during the calculation process, or the error had a minor impact on the network. In this case, the second multiplexer 32 selects the data sent by the second register 34 as its output, thereby transmitting the calculation results of the original filter to the error recovery device 40 in sequence.

[0120] In one specific embodiment of the present invention, the preset error recovery rules may include:

[0121] If a single verification unit reports an error within a single clock cycle, it is determined that the error occurred in the calculation result output by a single raw filter, and the erroneous calculation result is replaced with the corresponding verification value.

[0122] If a single verification unit reports an error within K consecutive clock cycles, it is determined that the error occurred in the weight of a single original filter. The weights of the group containing the original filter that caused the error are then reloaded, and the calculation is restarted from the location of the error.

[0123] If multiple error detection units report errors in adjacent clock cycles, it is determined that the error occurred in the weight of the verification filter or in the input feature data. The weight of the group containing the erroneous verification filter is then reloaded, and the calculation is restarted from the location of the error.

[0124] In this implementation, considering that the error exceeds the error threshold of this group, it indicates that the error is large, and the corresponding processing strategy can be selected according to the specific situation.

[0125] Specifically, if a single verification unit reports an error within a single clock cycle, it indicates that the error occurred in the calculation result output by a single raw filter. In this case, the erroneous calculation result can be directly replaced with the corresponding verification value.

[0126] For example, in one implementation described above, if the error exceeds the error threshold of this group, the second multiplexer 32 selects the value sent by the first register 33 as the output, which means that the operation of replacing the erroneous calculation result with the corresponding check value has been completed.

[0127] By directly replacing the erroneous calculation result with the checksum, the data error caused by the error is reduced to an acceptable range. Furthermore, it can be seen that the calculation process is not interrupted in this case, thus ensuring the data processing efficiency of the neural network accelerator.

[0128] If a single verification unit reports an error within K consecutive clock cycles, it indicates that the error occurred in the weights of a single original filter. In this case, the error location can be recorded, allowing the weight loading phase to be re-executed. This refreshes the erroneous weights within the computation unit, eliminates the impact of soft errors, and restarts the current computation cycle from the error location. Because the computation cycle restarts from the error location, rather than performing a full cycle restart, it also helps ensure the data processing efficiency of the neural network accelerator. K is a positive integer, typically set to 2 or 3.

[0129] This implementation takes into account that, since the solution of this application introduces the concept of grouping and configures a verification filter for each group, the verification filter itself may also err. Therefore, this implementation considers this situation. Specifically, if multiple verification units report errors in adjacent clock cycles, that is, if the same bit output of multiple filters sharing the same set of inputs shows an error, it indicates that the error occurs in the weights of the verification filter, making the verification value unreliable, or it occurs in the input feature data, which propagates to multiple original filters through multiplexing. In this case, the weights of the group containing the erroneous verification filter can be reloaded, and the calculation can be restarted from the error position. That is, the first error position can be recorded and the weights of the current round of calculation can be reloaded, and the current round of calculation can be restarted from the error position to eliminate the impact of soft errors.

[0130] For multiple consecutive error detection units reporting errors within adjacent clock cycles, numerical limits can also be imposed. For example, in one scenario, if three consecutive error detection units report errors within adjacent clock cycles, it is considered that the above-mentioned situation of multiple consecutive error detection units reporting errors within adjacent clock cycles has occurred.

[0131] In one specific embodiment of the present invention, the loading device 10 may include:

[0132] The validation group partitioning unit is used to group the original filters in the target convolutional layer based on the similarity between filters using the mean-shift clustering algorithm;

[0133] A verification filter generation unit is used to configure one verification filter for each group;

[0134] The filter rearrangement unit is used to load the weights of each group sequentially in the pulsating array 20, and when loading the weights of any one group, it deploys the verification filter of that group in the first column of that group, so that the verification filter of that group receives the input feature data before each original filter of that group.

[0135] In this embodiment, the loading device 10 includes a verification group partitioning unit, a verification filter generation unit, and a filter rearrangement unit. When performing grouping s, the verification group partitioning unit uses the mean-shift clustering algorithm to group the original filters in the target convolutional layer. Using the mean-shift clustering algorithm to cluster the original filters does not impose constraints on the number of clusters or the number of filters within each cluster, ensuring that the most similar filters are assigned to the same verification group, thereby effectively guaranteeing the validity of error checking within the group.

[0136] Of course, in other specific situations, other grouping methods can be selected as needed, such as the K-means grouping algorithm.

[0137] Furthermore, the verification filter generation unit can be specifically used for:

[0138] For any given group, the verification filter configured for that group is obtained by calculating the average parameter value of each original filter in that group.

[0139] In this implementation, for any given group, in order to ensure that all original filters within the group have a common error detection capability, a verification filter is generated by calculating the average parameter value of the original filters. This method is relatively simple to implement, and the resulting verification filter can effectively meet the requirements.

[0140] By applying the technical solution provided in the embodiments of the present invention, the original filters in the target convolutional layer are divided into multiple verification groups by utilizing the error resilience of the neural network itself and the similarity characteristics of the filters within the layer. Inaccurate verification is performed within each group, thereby ensuring that serious errors are detected and recovered while avoiding overprotection of minor errors that occur in the neural network.

[0141] Specifically, the loading device 10 groups the original filters in the target convolutional layer based on the similarity between filters, and configures one verification filter for each group. This means that, under normal circumstances, the calculation result of the same group should be close to that of the verification filter. When loading the weights of each group sequentially in the systolic array 20, for any given group, in this application's scheme, the verification filter of that group is deployed in the first column of that group. This allows the verification filter of that group to receive the input feature data before the original filters of that group, meaning that the verification values ​​output by the verification filter can be transmitted through the verification unit. The verification row 30 in this application includes M sequentially connected verification units, and the verification row 30 is connected to the last row of the systolic array 20, thereby receiving the calculation results output by the systolic array 20. For any one of the M verification units, if the verification unit is connected to a verification filter, it will sequentially pass the verification values ​​output by the verification filter to the next-level verification unit. If the verification unit is connected to any original filter, it will not only sequentially pass the verification values ​​received from the previous-level verification unit to the next-level verification unit, but also compare the received calculation results output by the original filter with the corresponding verification values ​​received from the previous-level verification unit for error. The error recovery device 40 can then perform error processing based on the error comparison results of each verification unit and the preset error recovery rules. It is understood that if the error between the calculation results output by the original filter and the corresponding verification value is small, it can be considered that no error occurred during the calculation process, or the error has a small impact on the network. That is, this application does not require that the calculation results output by the original filter be completely consistent with the corresponding verification value, which can avoid over-protection. Of course, if the error is large, corresponding error processing can be performed.

[0142] As can be seen, in the scheme of this application, the original filters in the target convolutional layer need to be divided into multiple verification groups, and then a verification filter is configured for each group. In terms of hardware, a verification row 30 including M verification units connected in sequence needs to be set to realize error comparison. Compared with the traditional dual-mode redundancy method, which requires twice the computational overhead and hardware resources, the scheme of this application requires very few hardware and computational resources.

[0143] In summary, the solution proposed in this application can effectively implement soft error handling for neural network accelerators, saving hardware and computing resources and avoiding over-protection.

[0144] Corresponding to the embodiments of the soft error handling device for the neural network accelerator described above, this embodiment of the invention also provides a neural network accelerator that may include the soft error handling device for the neural network accelerator as described in any of the above embodiments.

[0145] For example Figure 6 This is a schematic diagram of the structure of a neural network accelerator in one specific embodiment. Figure 6 In this implementation, the feature map buffer can buffer both the input and output feature maps. For the input feature map, through the organization of units, it can be converted into vector-like input feature data and sent to the systolic array. The error recovery device can send the output data to the accumulator, which then passes it to the activation pooling unit. In other implementations, the neural network accelerator can have other structures; for example, in some cases, when the systolic array is large, the accumulator in the diagram may not be necessary. Furthermore, it is understood that the error recovery device can output the individual calculation results of the original filter, or it can output a checksum. That is, as described above, if no error exceeds the corresponding error threshold, the error recovery device outputs the individual calculation results of the original filter. Conversely, if a single checksum unit reports an error within a single clock cycle, the error recovery device replaces the erroneous calculation result with the corresponding checksum and outputs it to the appropriate checksum. Figure 6 The accumulator in the middle.

[0146] Furthermore, the neural network accelerator of this application can typically be specifically a convolutional neural network accelerator.

[0147] Corresponding to the embodiments of the neural network accelerator and its soft error handling device described above, this invention also provides a soft error handling method for a neural network accelerator. This method can be applied to the soft error handling device of the neural network accelerator as described in any of the embodiments. See also... Figure 7 This may include the following steps:

[0148] Step S701: The loading device groups the original filters in the target convolutional layer based on the similarity between the filters, and configures one validation filter for each group;

[0149] Step S702: The loading device loads the weights of each group sequentially in the pulse array, and when loading the weights of any one group, the verification filter of that group is deployed in the first column of that group, so that the verification filter of that group receives the input feature data before each original filter of that group.

[0150] Step S703: The pulsating array receives input feature data to perform convolution calculations, and outputs the corresponding calculation results through each calculation unit in its last row;

[0151] Step S704: When the verification unit is connected to the verification filter, the verification unit will sequentially pass the verification values ​​output by the verification filter to the next level verification unit; when the verification unit is connected to the original filter, the verification unit will sequentially pass the verification values ​​received from the previous level verification unit to the next level verification unit, and compare the error between the calculation results received from the original filter and the corresponding verification values ​​received from the previous level verification unit.

[0152] Step S705: The error recovery device performs error processing based on the error comparison results of each verification unit and the preset error recovery rules;

[0153] Where N and M are the number of rows and columns of the pulsating array, respectively.

[0154] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0155] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0156] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A soft error handling device for a neural network accelerator, characterized in that, include: The loading device is used to group the original filters in the target convolutional layer based on the similarity between the filters, and configure one validation filter for each group; In the pulsating array, the weights of each group are loaded sequentially. When loading the weights of any one group, the verification filter of that group is deployed in the first column of that group, so that the verification filter of that group receives the input feature data before the original filters of that group. A systolic array comprising N×M computational units is used to receive input feature data for convolution computation and output the corresponding computation results through the computational units in its last row. The system includes a check row consisting of M check units connected in sequence, and the check row is connected to the last row of the pulsation array to receive the calculation results output by the pulsation array. Any one of the M verification units is used to: when connected to the verification filter, sequentially pass the verification values ​​output by the verification filter to the next level verification unit; when connected to any of the original filters, sequentially pass the verification values ​​received from the previous level verification unit to the next level verification unit, and compare the received calculation results output by the original filter with the corresponding verification values ​​received from the previous level verification unit for error. The error recovery device connected to the verification line is used to perform error processing based on the error comparison results of each verification unit and the preset error recovery rules; Wherein, N and M are the number of rows and columns of the pulsation array, respectively.

2. The soft error handling device for a neural network accelerator according to claim 1, characterized in that, The verification unit is specifically used for: When it connects to the verification filter, it sequentially passes the verification values ​​output by the verification filter to the next level verification unit. When connected to any of the original filters, it sequentially transmits the verification values ​​received from the previous verification unit to the next verification unit. It also compares the received calculation results output by the original filter with the corresponding verification values ​​received from the previous verification unit. When the error does not exceed the error threshold configured for the group to which the original filter is located, it sequentially transmits the received calculation results output by the original filter to the error recovery device. When the error exceeds the error threshold, it outputs an error signal and replaces the erroneous calculation result with the corresponding verification value before transmitting it to the error recovery device.

3. The soft error handling device for a neural network accelerator according to claim 2, characterized in that, The verification unit includes: a first multiplexer, a first register, a second register, a second multiplexer, a control unit, and a comparison unit; The first input terminal and the second input terminal of the first multiplexer are respectively connected to the loading device and the pulse array, and the first output terminal and the second output terminal of the first multiplexer are respectively connected to the first input terminal of the first register and the data input terminal of the second register; the first input terminal and the second input terminal of the control unit are respectively connected to the loading device and the previous stage verification unit, and the output terminal of the control unit is connected to the second input terminal of the first register; The first, second, and third outputs of the first register are respectively connected to the first input of the second multiplexer, the first input of the comparison unit, and the subsequent verification unit; the first and second outputs of the second register are respectively connected to the second input of the comparison unit and the second input of the second multiplexer; the first and second outputs of the comparison unit are respectively connected to the third input of the second multiplexer and the error recovery device; and the output of the second multiplexer is connected to the error recovery device. When the verification unit is connected to the verification filter, the first input terminal of the first multiplexer and the first input terminal of the control unit both receive the first signal sent by the loading device, so that the first multiplexer will sequentially pass the various verification values ​​received by the verification filter through its own second input terminal to the first register, and pass the various verification values ​​to the next-level verification unit through the second output terminal of the first register. When the verification unit is connected to any original filter, the first input terminal of the first multiplexer and the first input terminal of the control unit both receive the second signal sent by the loading device, so that the control unit sends each verification value sent by the previous verification unit to the comparison unit and the next verification unit through the first register, and the first multiplexer sequentially transmits each calculation result output by the original filter received through its own second input terminal to the second register, so as to send it to the comparison unit through the second register; The comparison unit is used to calculate the error between each calculation result sent by the second register and the corresponding check value sent by the first register. When the error exceeds the error threshold of this group, it outputs an error signal to the second multiplexer and the error recovery device respectively. When the second multiplexer does not receive the error signal, the second multiplexer sequentially transmits each calculation result output by the second register to the error recovery device; when the second multiplexer receives the error signal, the second multiplexer replaces the erroneous calculation result with the corresponding check value output by the first register and then transmits it to the error recovery device.

4. The soft error handling device for a neural network accelerator according to claim 2, characterized in that, For any given group, the error threshold configured for that group is the relative error extreme value of the output of the verification filter and each original filter of that group during the forward inference process of a set number of rounds.

5. The soft error handling device for a neural network accelerator according to claim 1, characterized in that, The loading device includes: The validation group partitioning unit is used to group the original filters in the target convolutional layer based on the similarity between filters using the mean-shift clustering algorithm; A verification filter generation unit is used to configure one verification filter for each group; The filter rearrangement unit is used to load the weights of each group sequentially in the pulsating array. When loading the weights of any one group, the verification filter of that group is deployed in the first column of that group so that the verification filter of that group receives the input feature data before the original filters of that group.

6. The soft error handling apparatus for a neural network accelerator according to claim 5, characterized in that, The verification filter generation unit is specifically used for: For any given group, the verification filter configured for that group is obtained by calculating the average parameter value of each original filter in that group.

7. The soft error handling apparatus for a neural network accelerator according to any one of claims 1 to 6, characterized in that, The preset error recovery rules include: If a single verification unit reports an error within a single clock cycle, it is determined that the error occurred in the calculation result output by a single raw filter, and the erroneous calculation result is replaced with the corresponding verification value. If a single verification unit reports an error within K consecutive clock cycles, it is determined that the error occurred in the weight of a single original filter. The weights of the group containing the original filter that caused the error are then reloaded, and the calculation is restarted from the location of the error. If multiple verification units report errors in adjacent clock cycles, and it is determined that the error occurred in the weight of the verification filter or in the input feature data, the weight of the group containing the erroneous verification filter is reloaded, and the calculation is restarted from the error location.

8. A neural network accelerator, characterized in that, Includes a soft error handling device for a neural network accelerator as described in any one of claims 1 to 7.

9. The soft error handling apparatus for a neural network accelerator according to claim 8, characterized in that, The neural network accelerator is specifically a convolutional neural network accelerator.

10. A soft error handling method for a neural network accelerator, characterized in that, A soft error handling apparatus for a neural network accelerator as described in any one of claims 1 to 7 includes: The loading device groups the original filters in the target convolutional layer based on the similarity between the filters and configures one validation filter for each group; The loading device sequentially loads the weights of each group in the pulse array, and when loading the weights of any one group, it deploys the verification filter of that group in the first column of that group, so that the verification filter of that group receives the input feature data before each original filter of that group. The pulsating array receives input feature data to perform convolution calculations and outputs the corresponding calculation results through the calculation units in its last row. When the verification unit is connected to the verification filter, the verification unit will sequentially pass the verification values ​​output by the verification filter to the next level verification unit. When the verification unit is connected to the original filter, the verification unit will sequentially pass the verification values ​​received from the previous verification unit to the next verification unit, and compare the error between the calculation results received from the original filter and the corresponding verification values ​​received from the previous verification unit. The error recovery device performs error processing based on the error comparison results of each verification unit and the preset error recovery rules; Wherein, N and M are the number of rows and columns of the pulsation array, respectively.

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