A three-dimensional chip packaging structure and a manufacturing method thereof

Abstract

The present invention discloses a three-dimensional chip packaging structure and a manufacturing method thereof, belonging to the field of semiconductor technology. The packaging structure includes: a first chip, including a plurality of first signal regions and a plurality of hot spot regions; a second chip, including a plurality of second signal regions, and the second signal regions are correspondingly arranged with the first signal regions; a first connection pad, arranged on the first signal regions and the second signals; a second connection pad, arranged on the hot spot regions and the second chip corresponding to the hot spot regions; a signal connection column, arranged in the first chip and connected to the first connection pad; a heat dissipation unit, arranged on the second chip, and the heat dissipation unit includes a heat dissipation connection column, and the heat dissipation connection column is arranged in the second chip and connected to the second connection pad. Through the three-dimensional chip packaging structure and the manufacturing method thereof provided by the present invention, the system integration and heat dissipation characteristics of the three-dimensional chip packaging structure are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a three-dimensional chip packaging structure and a manufacturing method thereof. Background Art

[0002] With the continuous increase in the number of system I / Os (input / outputs), the two-dimensional packaging structure can no longer meet the requirements, and a three-dimensional stacked packaging structure with higher density is needed. However, the current three-dimensional chip packaging structure is limited by the packaging process and cannot meet the demand for high-density I / Os. Moreover, as the I / O density of the packaging continues to increase, the chip system structure needs to be continuously integrated, and the system power consumption per unit area increases significantly. Due to different functions within the chip, their respective heat dissipation powers are different, resulting in the phenomenon of excessive temperature in local areas, which affects the safety of the packaging structure. Summary of the Invention

[0003] The purpose of the present invention is to provide a three-dimensional chip packaging structure and a manufacturing method thereof. Through the three-dimensional chip packaging structure and the manufacturing method provided by the present invention, the chip can be integrated in the three-dimensional direction, the packaging size can be reduced, and the system integration can be improved. While ensuring high-density interconnection, the heat dissipation characteristics of the system are effectively improved.

[0004] To solve the above technical problems, the present invention provides a three-dimensional chip packaging structure, which at least includes:

[0005] A first chip, including a plurality of first signal regions and a plurality of hot spots;

[0006] A second chip, including a plurality of second signal regions, and the second signal regions are correspondingly arranged with the first signal regions;

[0007] A first connection pad, arranged on the first signal region and the second signal;

[0008] A second connection pad, arranged on the hot spot region and the second chip corresponding to the hot spot region;

[0009] A signal connection column, arranged in the first chip and connected to the first connection pad; and

[0010] A heat dissipation unit, arranged on the second chip, and the heat dissipation unit includes a heat dissipation connection column, and the heat dissipation connection column is arranged in the second chip and connected to the second connection pad.

[0011] In an embodiment of the present invention, the first connection pad on the first chip is electrically connected to the first connection pad on the second chip.

[0012] In an embodiment of the present invention, the second connection pad on the first chip is electrically connected to the second connection pad on the second chip.

[0013] In an embodiment of the present invention, a molding matrix is filled between the second chip and the first chip, and the opposite faces of the first chip and the second chip are completely encapsulated in the molding matrix.

[0014] In an embodiment of the present invention, the three-dimensional chip packaging structure further includes a metal layer and solder balls. The metal layer is disposed at an end of the signal connection column away from the first connection pad, and the solder balls are disposed on a side of the metal layer away from the signal connection column.

[0015] In an embodiment of the present invention, the heat dissipation unit further includes a heat conduction layer, and the heat conduction layer is continuously disposed on the heat dissipation connection column and on a side of the second chip away from the second connection pad.

[0016] In an embodiment of the present invention, the heat dissipation unit further includes a heat sink, and the heat sink is disposed on a side of the heat conduction layer away from the second chip.

[0017] In an embodiment of the present invention, the heat conduction layer and the heat dissipation connection column are made of a metal material.

[0018] The invention also provides a manufacturing method of a three-dimensional chip packaging structure, which at least includes the following steps:

[0019] Provide a first chip, which includes a plurality of first signal regions and a plurality of hot spots regions;

[0020] Provide a second chip, which includes a plurality of second signal regions, and the second signal regions are correspondingly arranged with the first signal regions;

[0021] Form first connection pads on the first signal regions and the second signals;

[0022] Form second connection pads on the hot spots regions and on the second chip corresponding to the hot spots regions;

[0023] Form signal connection columns in the first chip, and the signal connection columns are connected to the first connection pads; and

[0024] Form a heat dissipation unit on the second chip, and the heat dissipation unit includes heat dissipation connection columns, and the heat dissipation connection columns are disposed in the second chip and are connected to the second connection pads.

[0025] In an embodiment of the present invention, when forming the heat dissipation connection columns, a heat conduction layer is synchronously formed on a side of the second chip away from the first chip.

[0026] In summary, the present invention provides a three-dimensional chip packaging structure and a manufacturing method thereof, which can centrally package a chip group in a single package body, achieve three-dimensional integration of chips, reduce the packaging size, and improve system integration. By adopting a wafer-level packaging form, the production efficiency is improved, and the cost advantage of the three-dimensional chip packaging structure is enhanced. It can reduce the path of chip signal transmission and meet the requirements of high frequency and high speed. The heat dissipation path of the heat dissipation unit is short, which can effectively reduce the heat dissipation path. Moreover, the thermal conductivity coefficient of the heat dissipation unit is relatively good, which can meet the requirements of high-power heat dissipation. By adopting the method of directly bonding chips face to face, the heat dissipation characteristics of the system are effectively improved while ensuring high-density interconnection.

[0027] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the above-mentioned advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0029] Figure 1 Schematic diagram of the first chip and the second chip in an embodiment of the present invention.

[0030] Figure 2 Schematic diagram of the plastic encapsulation of the first chip and the second chip in an embodiment of the present invention.

[0031] Figure 3 Schematic diagram of thinning the first chip in an embodiment of the present invention.

[0032] Figure 4 Schematic diagram of forming the first through hole in an embodiment of the present invention.

[0033] Figure 5 Schematic diagram of forming signal connection posts in an embodiment of the present invention.

[0034] Figure 6 Schematic diagram of forming a metal layer and solder balls on the first chip in an embodiment of the present invention.

[0035] Figure 7 Schematic diagram of thinning the second chip in an embodiment of the present invention.

[0036] Figure 8 Schematic diagram of forming the second through hole in an embodiment of the present invention.

[0037] Figure 9Schematic diagram of forming heat dissipation connection posts and a heat conduction layer in an embodiment of the present invention.

[0038] Figure 10 Schematic diagram of a three-dimensional chip packaging structure formed in an embodiment of the present invention.

[0039] Label description:

[0040] 100, first chip; 200, second chip; 11, first connection pad; 12, second connection pad; 13, hot spot area; 14, plastic package substrate; 15, first photoresist layer; 151, first opening; 16, first through hole; 17, signal connection post; 18, metal layer; 19, solder ball; 20, second photoresist layer; 201, second opening; 21, second through hole; 22, heat dissipation connection post; 23, heat conduction layer; 24, heat sink; 241, heat dissipation fin; 242, heat dissipation groove. Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0042] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0043] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes, and cannot be understood as indicating or implying relative importance.

[0044] Please refer to Figure 10As shown, the present invention provides a three-dimensional chip packaging structure, including a first chip 100 and a second chip 200. Among them, a plurality of first connection pads 11 are arranged at corresponding positions in the signal areas of the first chip 100 and the second chip 200. The first connection pads 11 are respectively arranged in the signal areas of the first chip 100 and the second chip 200 to connect the signal areas of the first chip 100 and the second chip 200. The chip group can be centrally packaged in a single package, reducing the volume. By integrating the chips in the three-dimensional direction, it is ensured that the package size is reduced, the system integration is improved, and the device performance is more excellent. The first chip 100 includes a plurality of hot spot areas 13. Second connection pads 12 are arranged on the hot spot areas 13, and second connection pads 12 are arranged at positions corresponding to the hot spot areas 13 of the second chip 200. The second connection pads 12 are connected to each other and then connected to the heat dissipation unit, effectively improving the heat dissipation characteristics of the system. Specifically, the specific structure of the three-dimensional chip packaging structure of the present application and the manufacturing method of the three-dimensional chip packaging structure are as Figures 1 to 10 shown. Through the three-dimensional chip packaging structure and its manufacturing method provided by the present application, the integration of the system can be improved, and it can be widely applied to fields such as artificial intelligence, autonomous driving, 5G network or Internet of Things.

[0045] Please refer to Figure 1 As shown, in an embodiment of the present invention, a first chip 100 is provided. The first chip 100 includes a plurality of first signal areas (not shown in the figure) and a plurality of hot spot areas 13. A plurality of first connection pads 11 are arranged on the surface of the first chip 100, and the first connection pads 11 are arranged on the first signal areas on the first chip 100. A plurality of second connection pads 12 are arranged on the surface of the first chip 100, and the second connection pads 12 are arranged on the hot spot areas 13 of the first chip 100 to prevent the phenomenon of excessive local temperature. Among them, the second connection pads 12 and the first connection pads 11 are arranged on the same surface of the first chip 100. In this embodiment, the first chip 100 is, for example, a logic chip, a power chip or a control chip, etc. In other embodiments, the first chip 100 can be selected according to the usage requirements.

[0046] Please refer to Figure 1As shown, in an embodiment of the present invention, the present invention further provides a second chip 200. The second chip 200 includes a plurality of second signal regions (not shown in the figure), and the second signal regions are arranged corresponding to the first signal regions. A plurality of first connection pads 11 are arranged on the surface of the second chip 200. The first connection pads 11 are arranged on the second signal regions on the second chip 200, and the first connection pads 11 on the first chip 100 and the second chip 200 are arranged at corresponding positions. During packaging, the first connection pads 11 on the first chip 100 and the second chip 200 can be correspondingly connected. A plurality of second connection pads 12 are arranged on the surface of the second chip 200. The second connection pads 12 are arranged at positions corresponding to the hot spot regions 13 on the first chip 100. During packaging, the second connection pads 12 on the second chip 200 and the first chip 100 can be correspondingly connected. Among them, the second connection pads 12 and the first connection pads 11 are arranged on the same surface of the second chip 200. In this embodiment, the second chip 200 is, for example, a memory chip, a CPU chip, or a GUP chip, etc. In other embodiments, the second chip 200 can be selected according to the usage requirements.

[0047] Please refer to Figure 1 As shown, in an embodiment of the present invention, the first connection pads 11 are used for signal transmission. Conductive materials are selected, such as copper, aluminum, or tungsten, etc., conductive materials or alloys. The second connection pads 12 are used for heat transfer. For example, materials with high thermal conductivity are selected, such as copper, aluminum, or indium, etc. Among them, the first connection pads 11 and the second connection pads 12 are, for example, fabricated by a photolithography, development, and electroplating process, and the shapes of the first connection pads 11 and the second connection pads 12 are, for example, circular, square, or rectangular, etc. The present invention does not limit the specific number of the first connection pads 11 and the second connection pads 12, which are arranged according to the signal regions and hot spot regions on the chip. The present invention also does not limit the shapes and materials of the first connection pads 11 and the second connection pads 12. In this embodiment, the number of the first connection pads 11 and the second connection pads 12 on the second chip 200 and the first chip 100 is equal, and the shapes and materials of the first connection pads 11 and the second connection pads 12 can be the same or different.

[0048] Please refer to Figure 2As shown, in an embodiment of the present invention, the sides of the first chip 100 and the second chip 200 with connection pads are placed opposite to each other for bonding. Among them, the first connection pad 11 on the first chip 100 is electrically connected to the first connection pad 11 on the second chip 200, and the second connection pad 12 on the first chip 100 is electrically connected to the second connection pad 12 on the second chip 200. In other embodiments, the bonding method can also be wafer-to-wafer or chip-to-wafer bonding. After the first chip 100 and the second chip 200 are bonded, a molding matrix 14 is filled between the second chip 200 and the first chip 100, and the opposite surfaces of the first chip 100 and the second chip 200 are completely encapsulated in the molding matrix 14. Among them, the molding matrix 14 includes epoxy resin, silicone-based encapsulant, polyurethane-based encapsulant, etc. By bonding and encapsulating the first chip 100 and the second chip 200, the chip group is concentratedly encapsulated in one package body, that is, the chips are integrated in the three-dimensional direction, the package size is reduced, and the system integration degree is improved. That is, the present application adopts a wafer-level packaging form, which improves production efficiency and the cost advantage of the three-dimensional chip packaging structure is improved.

[0049] Please refer to Figures 2 to 3 As shown, in an embodiment of the present invention, after the molding matrix 14 is formed, the substrate of the first chip 100 is thinned on the side of the first chip 100 away from the molding matrix 14. Among them, the substrate of the first chip 100 is, for example, a silicon substrate, and other types of substrates can also be selected according to different types of chips. In this embodiment, for example, thinning is performed by grinding, or for example, thinning is performed by Chemical Mechanical Polish (CMP). The present invention does not limit the thickness of the substrate thinning. According to the manufacturing requirements of the subsequent first through holes, it is only necessary to ensure that the remaining thickness of the substrate meets the manufacturing requirements. In this embodiment, the thickness of the thinned substrate of the first chip 100 is, for example, 50 μm to 100 μm. A first photoresist layer 15 is formed on the thinned first chip 100, and the first photoresist layer 15 is disposed on the side of the first chip 100 away from the molding matrix 14. Through processes such as exposure and development, a plurality of first openings 151 are formed on the first photoresist layer 15 to locate the positions of the first through holes.

[0050] Please refer to Figures 3 to 4As shown, in an embodiment of the present invention, after forming the first opening 151, using the first photoresist layer 15 as a mask, the first chip 100 is etched by dry etching, wet etching, or a combination of dry etching and wet etching to form a first through hole 16. The size of the first through hole 16 is selected according to manufacturing requirements, for example, smaller than the size of the first connection pad 11. In this embodiment, the opening size of the first through hole 16 is, for example, 5 μm to 10 μm, and the first through hole 16 is formed by dry etching, and the etching gas is, for example, a fluorine-containing gas. Among them, the first through hole 16 is provided on the first connection pad 11 and exposes part of the first connection pad 11. The position of the first through hole 16 on the first connection pad 11 is not specifically limited, for example, it is located at the center position of the first connection pad 11.

[0051] Please refer to Figures 4 to 5 As shown, in an embodiment of the present invention, after forming the first through hole 16, a conductive material is deposited in the first through hole 16 to form a signal connection column 17, so as to lead the signals of the first chip 100 and the second chip 200 to one side of the first chip 100 relative to the first connection pad 11. Among them, the conductive material is formed by, for example, electroplating, and the conductive material is, for example, a conductive material or alloy such as copper, aluminum, or tungsten, or for example, the same as the material of the first connection pad 11 to reduce the contact resistance. During the deposition process of the conductive material, part of the conductive material will be deposited on the first chip 100. Therefore, after the conductive material is deposited, the conductive material on the first chip 100 is removed by methods such as grinding or etching, and only the conductive material in the first through hole 16 is retained to form the signal connection column 17.

[0052] Please refer to Figures 5 to 6 As shown, in an embodiment of the present invention, after forming the signal connection column 17, a metal layer 18 is formed at one end of the signal connection column 17 away from the first connection pad 11, and a solder ball 19 is formed on the side of the metal layer 18 away from the signal connection column 17. Specifically, for example, a metal is deposited on the substrate of the first chip 100 and the signal connection column 17 by processes such as atomic layer deposition (ALD) or physical vapor deposition, and the deposited metal is, for example, copper or aluminum, etc., and is adaptively electrically connected to the signal connection column 17. Then, through etching, only the signal connection column 17 and the metal on both sides are retained to form the metal layer 18, which is used to lead out the signals in the signal area on the chip, and the center of the metal layer 18 corresponds to the center of the signal connection column 17. Then, a solder ball 19 is formed on the metal layer 18. The solder ball 19 is, for example, a tin-silver ball, etc., for connecting the three-dimensional chip packaging structure to the subsequent substrate. Among them, the solder ball 19 is located at the center position of the metal layer 18, and the solder ball 19 and the metal layer 18 are in one-to-one correspondence. In this embodiment, through the adaptive electrical connection of the solder ball 19, the metal layer 18, the signal connection column 17, and the first connection pad 11, it is used to transmit chip signals, and the interconnection length is short, which can meet the requirements of high frequency and high speed.

[0053] Please refer to Figures 6 to 7 As shown, in an embodiment of the present invention, after the solder balls 19 are formed, the entire structure is flipped. For example, the second chip 200 is located above and the first chip 100 is located below, which is beneficial for the processing of the second chip 200. Then, the substrate on the side of the second chip 200 away from the plastic package substrate 14 is thinned. Among them, the substrate of the second chip 200 is, for example, a silicon substrate. According to different types of chips, other types of substrates can also be selected. In this embodiment, for example, thinning is performed by grinding, or by chemical mechanical polishing. The present invention does not limit the thickness of the substrate thinning. According to the manufacturing requirements of the subsequent second vias, it is only necessary to ensure that the remaining thickness of the substrate meets the manufacturing requirements. In this embodiment, the thickness of the substrate of the thinned second chip 200 is, for example, 40 μm to 60 μm, and a second photoresist layer 20 is formed on the thinned second chip 200. The second photoresist layer 20 is disposed on the side of the second chip 200 away from the plastic package substrate 14. Through processes such as exposure and development, a plurality of second openings 201 are formed on the second photoresist layer 20 to locate the positions of the second vias.

[0054] Please refer to Figures 7 to 8 As shown, in an embodiment of the present invention, after the second openings 201 are formed, using the second photoresist layer 20 as a mask, the second chip 200 is etched by a dry etching process, a wet etching process, or a combination of dry etching and wet etching processes to form second vias 21. The size of the second vias 21 is selected according to the manufacturing requirements. For example, it is smaller than the size of the second connection pads 12. In this embodiment, the opening size of the second vias 21 is, for example, 25 μm to 35 μm, and the second vias 21 are formed by dry etching, and the etching gas is, for example, a fluorine-containing gas. Among them, the second vias 21 are disposed on the second connection pads 12 and expose a part of the second connection pads 12. The position of the second vias 21 on the second connection pads 12 is not specifically limited. For example, it is located at the center of the second connection pads 12.

[0055] Please refer to Figures 8 to 9As shown, in an embodiment of the present invention, after the second through-hole 21 is formed, a heat-conducting material is deposited in the second through-hole 21 to form a heat-dissipating connection column 22, so as to dissipate the heat generated by the hot spot region 13 of the first chip 100 through the heat-dissipating connection column 22 from the side of the second chip 200 away from the first chip 100. Among them, the heat-conducting material is formed by means such as electroplating. The heat-conducting material includes, for example, a metal material. The metal material is, for example, a high heat-conducting material such as copper, aluminum or indium. For another example, it is the same as the material of the second connection pad 12, or it can be different from the material of the second connection pad 12, and it is selected according to the heat-dissipation requirements. During the deposition process of the heat-conducting material, the heat-conducting material will be deposited on the second chip 200 until the second through-hole 21 is completely filled and the surface of the second chip 200 is covered. After the heat-conducting material is deposited, the conductive material on the second chip 200 is planarized by methods such as grinding or etching, and the heat-conducting material in the second through-hole 21 is retained to form a heat-dissipating connection column 22, and the heat-conducting material on the second chip 200 and the heat-dissipating connection column 22 is retained to form a continuous heat-conducting layer 23, so as to facilitate connection with a subsequent heat-conducting sheet.

[0056] Please refer to Figures 9 to 10 As shown, in an embodiment of the present invention, after the heat-conducting layer 23 is formed, a heat sink 24 is formed on the side of the heat-conducting layer 23 away from the second chip 200. The bottom of the heat sink 24 is fixedly assembled on the second chip 200 through the heat-conducting layer 23, for example, connected by welding or gluing. Among them, the heat sink 24 includes a plurality of heat dissipation fins 241, and the adjacent heat dissipation fins 241 of the heat-conducting layer 23 are separated by heat dissipation grooves 242. In this embodiment, the heat-dissipating connection column 22, the heat-conducting layer 23 and the heat sink 24 are defined as a heat-dissipating unit to meet the heat-dissipation requirements of the packaging structure. In this application, the heat sink 24 can also be replaced with a heat-dissipating structure of other structures as long as the heat-dissipation requirements are met.

[0057] Please refer to Figure 10As shown, in an embodiment of the present invention, the heat dissipation connection column 22 made of a metal material is connected to the second connection pad 12 to transfer the heat generated in the hot spot area 13 on the first chip 100, thereby improving the heat conduction efficiency relative to the substrate. A heat conduction layer 23 is provided on the heat dissipation connection column 22 and the second chip, which can disperse the heat conducted by the heat dissipation connection column 22 to achieve the purpose of rapid heat transfer. On the heat conduction layer 23, a heat sink 24 is provided. By using the form of alternately distributed intervals between the heat dissipation fins 241 and the heat dissipation grooves 242, the efficient heat dissipation requirements can be achieved. Moreover, the heat dissipation path of this application is short, which can effectively reduce the heat dissipation path. And the thermal conductivity coefficient of the heat dissipation unit is relatively good, which can meet the requirements of high-power dissipation. That is, in this application, a local heat dissipation structure is set up. By setting a second connection pad with high thermal conductivity on the hot spot area and bonding it to the first chip. The first chip conducts heat to the back of the second chip through the heat dissipation connection column, and then the heat sink conducts the final heat dissipation. The present invention adopts the direct face-to-face bonding method of chips, which effectively improves the heat dissipation characteristics of the system while ensuring high-density interconnection.

[0058] In summary, the present invention provides a three-dimensional chip packaging structure and its manufacturing method. By centrally packaging the chip group in a single package, the chips are integrated in three dimensions, reducing the package size and improving system integration. By adopting the wafer-level packaging form, the production efficiency is improved, and the cost advantage of the three-dimensional chip packaging structure is enhanced. It can reduce the path of chip signal transmission and meet the requirements of high frequency and high speed. Through local heat dissipation, the heat dissipation path is short, which can effectively reduce the heat dissipation path. And the thermal conductivity coefficient of the heat dissipation unit is relatively good, which can meet the requirements of high-power dissipation. By adopting the direct face-to-face bonding method of chips, the heat dissipation characteristics of the system are effectively improved while ensuring high-density interconnection.

[0059] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the relevant technical fields can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A manufacturing method of a three-dimensional chip packaging structure, characterized in that At least include the following steps: Provide a first chip, the first chip includes a plurality of first signal regions and a plurality of hot spot regions; the first chip is a logic chip, a power chip or a control chip; Provide a second chip, the second chip includes a plurality of second signal regions, and the second signal regions are correspondingly arranged with the first signal regions; the second chip is a memory chip, a CPU chip or a GUP chip; Form first connection pads on the first signal regions and the second signals; Form second connection pads on the hot spot regions and the second chip corresponding to the hot spot regions; Electrically connect the first connection pads on the first chip to the first connection pads on the second chip, and electrically connect the second connection pads on the first chip to the second connection pads on the second chip; The second chip and the first chip are directly face-to-face bonded and a molding matrix is filled between the second chip and the first chip to completely encapsulate the opposite faces of the first chip and the second chip in the molding matrix; Thin the first chip, and through etching and deposition, form signal connection posts in the first chip, and the signal connection posts are connected to the first connection pads; the thickness of the substrate of the first chip after thinning is 50 μm to 100 μm; form a metal layer and solder balls on the signal connection posts, the metal layer is formed at one end of the signal connection posts away from the first connection pads, and the solder balls are formed on one side of the metal layer away from the signal connection posts and Thin the second chip, and through etching and deposition, form a heat dissipation unit on the second chip, the heat dissipation unit includes heat dissipation connection posts, the heat dissipation connection posts are arranged in the second chip and are connected to the second connection pads; the thickness of the substrate of the second chip after thinning is 40 μm to 60 μm; the heat dissipation unit further includes a heat conduction layer, the heat conduction layer is continuously arranged on the heat dissipation connection posts and on the side of the second chip away from the second connection pads, and the heat conduction layer and the heat dissipation connection posts include metal materials; the heat dissipation connection posts and the heat conduction layer are formed synchronously.

2. The manufacturing method of the three-dimensional chip packaging structure according to claim 1, wherein The heat dissipation unit further includes a heat sink, and the heat sink is arranged on the side of the heat conduction layer away from the second chip.

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