Frequency synthesizer with selectable modes

Abstract

A frequency synthesizer system can include a first voltage controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry can be configured to select an output of the first VCO circuit or an output of the second VCO circuit in response to a mode selection signal.

Description

Technical Field

[0001] This disclosure relates to wireless communication, and more specifically to frequency synthesizer circuitry in radio frequency transceivers. Background Technology

[0002] Energy efficiency is an important consideration in portable communication devices such as mobile phones. In low-power mode, a reduced power level can be provided to certain transmitter and / or receiver components in portable communication devices.

[0003] A voltage-controlled oscillator (VCO) is a frequency synthesizer commonly used in circuits such as phase-locked loops (PLLs). RF receivers can utilize a PLL in a local oscillator (LO) signal generator circuit, which is part of a circuit system that down-converts the received RF signal to the baseband frequency by providing the RF signal and the LO signal to the corresponding inputs of a mixer. In some receiver architectures, occasional operation in a low-power mode is advantageous, for example, to save power and extend the amount of time that a portable device including the receiver can operate. Summary of the Invention

[0004] Various implementations of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, none of which alone is responsible for the desired properties described herein. Some prominent features are described herein without limiting the scope of the appended claims.

[0005] Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the specification, drawings, and claims. Note that the relative dimensions of the elements shown in the drawings may not be to scale.

[0006] In one aspect of this disclosure, a frequency synthesizer system may include a first VCO circuit, a second VCO circuit, and a multiplexing circuit system. The first VCO circuit may include an inductor-capacitor (LC) VCO. The second VCO circuit may include a ring oscillator. The multiplexing circuit system may be configured to select the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.

[0007] In another aspect of this disclosure, a frequency synthesizer system may include a first VCO circuit, a second VCO circuit, a multiplexing circuit system, and a frequency divider circuit. The input of the frequency divider circuit may be coupled to the output of the first VCO circuit. The output of the frequency divider circuit may be coupled to the input of the multiplexing circuit system. The multiplexing circuit system may be configured to select either the output of the frequency divider circuit or the output of the second VCO circuit in response to a mode selection signal.

[0008] In another aspect of this disclosure, a frequency synthesizer system for generating a local oscillator (LO) signal may include a first VCO circuit configured to generate a first output signal having a first frequency, a second VCO circuit configured to generate a second output signal having a second frequency, and a multiplexing circuit system. The first frequency may be a multiple of the second frequency. The multiplexing circuit system may be configured to generate the LO signal by selecting either the first output signal or the second output signal in response to a mode selection signal.

[0009] In another aspect of this disclosure, a method for selecting a chosen frequency synthesizer in an RF receiver may include receiving a mode selection signal and selecting the output of a first VCO circuit or the output of a second VCO circuit in response to the mode selection signal. The first VCO circuit may include an LC VCO, and the second VCO circuit may include a ring oscillator.

[0010] In another aspect of this disclosure, an apparatus for selecting a frequency synthesizer in an RF receiver may include components for receiving a mode selection signal and components for selecting the output of a first VCO circuit or the output of a second VCO circuit in response to the mode selection signal. The first VCO circuit may include an LC VCO, and the second VCO circuit may include a ring oscillator.

[0011] In another aspect of this disclosure, a frequency synthesizer system in an RF receiver may include a first VCO circuit, a second VCO circuit, and a multiplexing circuit system. The first VCO circuit may include an LC VCO. The second VCO circuit may include a ring oscillator. The multiplexing circuit system may be configured to select the output of the first VCO circuit in response to a mode selection signal indicating that the RF receiver is operating in a higher power mode, and to select the output of the second VCO circuit in response to a mode selection signal indicating that the RF receiver is operating in a lower power mode. Attached Figure Description

[0012] In the accompanying drawings, unless otherwise specified, similar reference numerals refer to similar parts in the various views. For reference numerals with letter character names (such as "102A" or "102B"), the letter character names can distinguish two similar parts or elements in the same figure. When the reference numerals include all parts with the same reference numerals in all figures, the letter character names of the reference numerals may be omitted.

[0013] Figure 1 This is a block diagram of a wireless communication system according to various aspects of this disclosure.

[0014] Figure 2This is a block diagram of the transceiver-related parts of a wireless device according to various aspects of this disclosure.

[0015] Figure 3A This is a block diagram illustrating a frequency synthesizer system with selectable low-power modes according to various aspects of this disclosure.

[0016] Figure 3B This is a block diagram illustrating another frequency synthesizer system with selectable low-power modes according to various aspects of this disclosure.

[0017] Figure 3C This is a block diagram illustrating yet another frequency synthesizer system with selectable low-power modes according to various aspects of this disclosure.

[0018] Figure 4 This is a block diagram of a local oscillator signal generator according to various aspects of this disclosure.

[0019] Figure 5 This is the circuit diagram of a ring oscillator (VCO).

[0020] Figure 6 This is the circuit diagram of an LC VCO.

[0021] Figure 7 This is a flowchart illustrating a method for selecting a frequency synthesizer based on a mode selection signal according to various aspects of this disclosure.

[0022] Figure 8 This is a flowchart illustrating another method for selecting a frequency synthesizer based on a mode selection signal, according to various aspects of this disclosure.

[0023] Figure 9 This is a flowchart illustrating yet another method for selecting a frequency synthesizer based on a mode selection signal, according to various aspects of this disclosure.

[0024] Figure 10 This is a functional block diagram of an apparatus for selecting a frequency synthesizer based on a mode selection signal, according to various aspects of this disclosure.

[0025] Figure 11 This is a functional block diagram of another device for selecting a frequency synthesizer based on a mode selection signal, according to various aspects of this disclosure.

[0026] Figure 12 This is a functional block diagram of another apparatus for selecting a frequency synthesizer based on a mode selection signal, according to various aspects of this disclosure. Detailed Implementation

[0027] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects.

[0028] The following description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be appropriately omitted, substituted, or added to the examples. For example, the methods described herein may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined in other examples.

[0029] Energy efficiency is an important consideration in portable communication devices, such as the wireless device 110 described below. Under certain operating conditions, radio frequency (RF) transmitters and / or receivers can tolerate a lower signal-to-noise ratio (SNR), and the wireless device can be configured to operate with a lower SNR in a low-power mode. For example, in a low-power mode, a reduced power level can be provided to certain receiver and / or transmitter components compared to a mode in which a higher power level is provided to maintain a higher SNR.

[0030] A voltage-controlled oscillator (VCO) is a frequency synthesizer commonly used in circuits such as phase-locked loops (PLLs). An RF receiver can use a PLL in a local oscillator (LO) signal generator circuit, which is part of a circuit system that down-converts the received RF signal to a baseband frequency by providing the RF signal and LO signal to the corresponding inputs of a mixer. Similarly, an RF transmitter can use a PLL in a local oscillator (LO) signal generator circuit, which is part of a circuit system that up-converts a baseband signal to an RF frequency for transmission by providing the baseband signal and LO signal to the corresponding inputs of a mixer. In some receiver and / or transmitter architectures, a frequency divider circuit can operate on the output signals of one or more VCOs to generate different frequency bands and / or signals with lower frequencies and multiple phases. These signals can then be provided to a mixer.

[0031] In receiver and / or transmitter architectures where the output of one or more VCOs is divided and provided in a multiphase configuration, significant power reduction can be difficult to achieve in low-power mode because reducing the supply voltage can adversely affect VCO startup gain, multiphase divider circuitry functionality, or other aspects. Certain embodiments described herein provide a VCO that can operate in low-power mode and / or overcome some of the aforementioned challenges.

[0032] Figure 1An example of a wireless device 110 operating in a wireless communication system 120 is shown. The wireless communication system 120 may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G system, or some other wireless system. The CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For clarity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. More generally, such a wireless communication system may include any number of such base stations and any set of network entities.

[0033] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, tablet computer, cordless phone, medical device, device configured to connect to one or more other devices (e.g., via the Internet of Things), wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 can communicate bidirectionally with base stations 130 and 132, one or more access points, and / or one or more other wireless or mobile devices. Wireless device 110 can receive signals from a broadcast station (e.g., broadcast station 134). Wireless device 110 can also receive signals from one or more satellites in a Global Navigation Satellite System (GNSS), such as satellite 150. Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0034] Wireless device 110 may support carrier aggregation, such as that described in one or more LTE or 5G standards. In some embodiments, a single data stream is transmitted over multiple carriers using carrier aggregation, which differs from using a separate carrier for each data stream. Wireless device 110 may be able to operate over a wide range of communication bands, including those used by LTE, WiFi, 5G, or other communication bands.

[0035] Figure 2 A wireless device 200 is shown in which exemplary circuits, devices, systems, methods, apparatuses, etc., according to this disclosure may be embodied or implemented. Wireless device 200 may be the aforementioned wireless device 110 ( Figure 1 Examples of ).

[0036] Wireless device 200 may include transceiver 220 having transmitter 230 and receiver 250. Typically, the conditioning of signals in transmitter 230 and receiver 250 may be performed by one or more stages of amplifiers, filters, upconverters, downconverters or other circuit blocks. Figure 2 The arrangement or configuration of the circuit blocks shown is intended as an example, and in other embodiments, such an arrangement or configuration of the circuit system may differ. In such other embodiments (not shown), additional circuitry may be included to regulate signals in transmitter 230 and receiver 250. Similarly, in such other embodiments, [the circuitry may be omitted]. Figure 2 One or more of the circuit blocks shown. Furthermore, unless otherwise stated, Figure 2 Any signal shown in any other figure in the attached diagram can be a single-ended or differential signal.

[0037] exist Figure 2 In the example shown, wireless device 200 typically includes a transceiver 220 and a data processor 210. Data processor 210 may include a processor 296 operatively coupled to memory 298. Memory 298 may be configured to store data and program code and may typically include analog and / or digital processing elements. Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. Typically, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0038] Transmitters or receivers can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between radio frequency (RF) and baseband in multiple stages; for example, for a receiver, it might be converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 2 In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0039] In the transmission path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b to convert digital signals generated by data processor 210 into I and Q analog output signals, such as I and Q output currents, for further processing. In other embodiments (not shown), DACs 214a and 214b may be included in transceiver 220, and data processor 210 may provide data (e.g., for I and Q) digitally to transceiver 220.

[0040] Within transmitter 230, low-pass filters 232a and 232b filter the I and Q analog transmission (communication) signals, respectively, to remove unwanted images caused by the previous digital-to-analog conversion. Amplifiers (Amps) 234a and 234b amplify the signals from low-pass filters 232a and 232b, respectively, and provide I and Q baseband signals. Upconverter 240 upconverts the I and Q baseband signals using the I and Q TX LO signals from the transmission (TX) local oscillator (LO) signal generator 290, and provides the upconverted signal. Filter 242 filters the upconverted signal to remove unwanted images caused by the upconversion, as well as noise in the receive band. Power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provides the transmission RF signal. Depending on various factors, power amplifier 244 can be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and can be configured to provide linearity, efficiency, or a combination of linearity and efficiency. The transmitted RF signal is routed through a duplexer or switch 246 and transmitted via antenna 248. Although the examples discussed herein utilize I and Q signals, those skilled in the art will understand that elements of the transceiver can be configured to utilize polarity modulation.

[0041] In the receiving path, antenna 248 receives the communication signal and provides the received RF signal, which is routed through duplexer or switch 246 and provided to low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate at a specific RX to TX duplexer frequency interval, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal. Downconverter mixers 261a and 261b in downconverter 260 mix the output of filter 254 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain I and Q analog input signals, which are provided to data processor 210. In the exemplary embodiment shown, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b to convert analog input signals into digital signals for further processing by the data processor 210. In other embodiments (not shown), ADCs 216a and 216b may be included in transceiver 220 and provide data digitally to the data processor 210.

[0042] TX LO signal generator 290 generates I and Q TX LO signals for up-conversion, while RX LO signal generator 280 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific fundamental frequency. Although in Figure 2 In the illustrated embodiment, the circuit system of the TX LO signal generator 290 is different from that of the RX LO signal generator 280. However, in other embodiments (not shown), the common circuit system of both the RX LO signal generator 280 and the TX LO signal generator 290 can be set in the combined LO generator circuit system, and the remaining circuit systems of the RX LO signal generator 280 and the TX LO signal generator 290 can share this common circuit system.

[0043] Figure 2The transceiver 220 is functionally illustrated in the diagram, and the configuration shown may or may not represent the physical device configuration in some implementations. For example, as described above, the transceiver 220 may be implemented in various integrated circuits (ICs), RFICs, mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board, such as a printed circuit board (PCB) having various modules. For example, the power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as discrete components, while the remaining components shown in the transceiver 220 may be implemented in a single transceiver chip.

[0044] Figure 3A A frequency synthesizer system 302A is shown, comprising a first voltage-controlled oscillator (VCO) circuit 306A, a second VCO circuit 308A, and a multiplexing circuit system 304A. The multiplexing circuit system 304A is configured to select either the output of the first VCO circuit 306A or the output of the second VCO circuit 308A in response to a mode selection signal 310A. The mode selection signal 310A can be, for example, as described above... Figure 2 The data processor 210 described herein provides the signal. The mode selection signal 310A may, for example, be the power mode selection signal as described below. In some embodiments, one or both of the VCO circuits 306A and 308A are included in the PLL.

[0045] Figure 3BA frequency synthesizer system 302B is shown, comprising a first VCO circuit 306B, a second VCO circuit 308B, a multiplexing circuit system 304B, and a frequency divider circuit 311. The frequency synthesizer system 302B can be configured to generate an LO signal having an LO frequency. The first VCO circuit 306B can be configured to generate an output signal having a frequency that is a multiple (M) of the frequency of the output signal generated by the second VCO circuit 308B. The frequency of the output signal generated by the second VCO circuit 308B can be the LO frequency. The output of the first VCO circuit 306B is coupled to the input of the frequency divider circuit 311. The frequency divider circuit 311 can be configured to perform an M-division. Alternatively, the frequency divider circuit 311 can be configured to perform another number-division. The output of the frequency divider circuit 311 is coupled to one input of the multiplexing circuit system 304B. The output of the second VCO circuit 308B is coupled to another input of the multiplexing circuit system 304B, without an intermediate frequency divider. The multiplexing circuit system 304B is configured to select either the output of the frequency divider circuit 311 or the output of the second VCO circuit 308B in response to the mode selection signal 310B. The multiplexing circuit system 304B therefore outputs an LO signal, in which, in an embodiment where the frequency divider circuit 311 is configured to perform M-division, the LO signal has the same LO frequency regardless of whether the first VCO circuit 306B or the second VCO circuit 308B is selected. The mode selection signal 310B can be, for example, as described above regarding... Figure 2 The data processor 210 described herein provides the signal. The mode selection signal 310B may be, for example, the power mode selection signal as described below. In some embodiments, one or both of the VCO circuits 306B and 308B are included in the PLL. Although the frequency divider circuit 311 is shown as different from the VCO circuit 306B, in some embodiments, the frequency divider circuit 311 is integrated into the VCO circuit 306B. In other embodiments, the frequency divider circuit 311 is included within the PLL in which the VCO circuit 306 is implemented. Furthermore, although the frequency divider circuit 311 is shown as being connected in series between the output of the VCO circuit 306 and the multiplexing circuit system 304B, in some embodiments, the frequency of the generated signal is otherwise divided within the VCO circuit 306B or within the PLL in which the VCO circuit 306B is implemented.

[0046] Figure 3C A frequency synthesizer system 302C coupled to a mixer 312 is shown. In the illustrated embodiment, the frequency synthesizer system 302C and the mixer 312 can be respectively described above regarding... Figure 2The described example is an RX LO signal generator 280 and a downconverter 260. However, in other embodiments (not shown), such a frequency synthesizer system and mixer may be an example of a TX LO signal generator and an upconverter. The frequency synthesizer system 302C includes a first VCO circuit 306C, a second VCO circuit 308C, and a multiplexing circuit system 304C. The first VCO circuit 306C includes or is based on an inductor-capacitor (LC) VCO (in... Figure 3C (Not shown separately). The second VCO circuit 308C includes or is based on a ring oscillator (in... Figure 3C (Not shown separately), instead of an LCVCO or other inductive or capacitive oscillator circuit system. As described in further detail below, while LC VCOs are generally high-performance, low-noise type VCOs, ring oscillator VCOs are generally more noise-tolerant than LC VCOs and can operate at lower power levels than LC VCOs. In some embodiments, one or both of the VCO circuits 306C and 308C are included in a PLL. Furthermore, a frequency divider circuit may be implemented in the signal path between the output of VCO circuit 306C and multiplexing circuit system 304C, or another component for dividing the signal frequency may be implemented within VCO 306C or within a PLL in which VCO 306C is implemented.

[0047] The frequency synthesizer system 302C features a selectable low-power mode. The multiplexing circuit system 304C is configured to select either the output of the first VCO circuit 306C or the output of the second VCO circuit 308C in response to the mode selection signal 310C. The multiplexing circuit system 304C provides the selected circuit output to the input of the mixer 312. The selected VCO circuit output may include two or more signals of different phases. The mode selection signal 310C may be, for example, derived from the above-mentioned... Figure 2 The data processor 210 described herein is provided.

[0048] In this disclosure, the term "low power mode" or "lower power mode" refers to an operating mode in which the RF receiver (e.g., Figure 2 One or more components of the receiver 250 are supplied with a lower power level than they are supplied with in another operating mode. This other operating mode may be referred to as a high-power mode, a higher-power mode, a normal operating mode, a task mode, etc. For convenience, these different terms are used only to distinguish at least two power levels relative to each other, and not to associate the power levels with or describe any other aspect. That is, whichever or all of the terms may be used, the term simply indicates that a lower power level is supplied to the RF receiver in one mode than in another.

[0049] Similarly, in this disclosure, the mode selection signal 310 may also be referred to as a low-power mode selection signal, a lower-power mode selection signal, etc. Regardless of the terminology used, it should be understood that the mode selection signal 310 has at least two states: a first state indicating that the RF receiver operates in a first mode, in which one or more components of the RF receiver are provided with a lower power level than they are provided in a second operating mode; and a second state indicating that the RF receiver operates in a second mode, in which one or more components of the RF receiver are provided with a higher power level than they are provided in the first operating mode. As understood by those skilled in the art, the data processor 210 of the wireless device 200 ( Figure 2 A power controller (not shown) can control the power level supplied to the RF receiver in response to various operating conditions. In some embodiments, more than two VCOs with different power, frequency outputs, and / or other operating characteristics are implemented. For example, a high-power (and / or low SNR) VCO, a low-power (and / or low SNR) VCO, and a low-power (and / or even further low SNR) VCO can all be implemented and output to the multiplexing circuit system 304. A mode selection signal 310 can be used to control the multiplexing circuit system 304 to selectively pass the output of one of the VCOs to a mixer, such as mixer 312.

[0050] Figure 4 A frequency synthesizer 402 with a selectable low-power mode and other components are shown. In the illustrated embodiment, the frequency synthesizer 402 may be included in the RX LO signal generator 400. However, in other embodiments (not shown), such a frequency synthesizer may be included in the TX LO signal generator or other circuitry. The frequency synthesizer 402 may be the frequency synthesizer system 302A described above. Figure 3A ), 302B ( Figure 3B ), 302C Figure 3C Examples of any of the above, such as RX LO signal generator 400. Figure 2 Examples of ).

[0051] Among other components, the frequency synthesizer 402 includes a multiplexer 404, an LC VCO 406, and a ring oscillator VCO 408 (also referred to as a ring VCO). The multiplexer 404 is configured to selectively couple either the output of the LC VCO 406 or the output of the ring oscillator VCO 408 to the multiplexer output in response to a mode selection signal 410. The LC VCO 406 is included in a first phase-locked loop (PLL) circuit 412. The ring oscillator VCO 408 is included in a second PLL circuit 414. Therefore, the multiplexer 404 is configured to selectively couple either the output of the first PLL circuit 412 or the output of the second PLL circuit 414 to the multiplexer output in response to the mode selection signal 410. The mode selection signal 410 may be similar to the above description. Figure 3C The described mode selection signal is 310C.

[0052] exist Figure 4 In the example shown, the first PLL circuit 412 may include a phase / frequency detector (PFD) 416, a charge pump (CHP) 418, a loop filter 420, the aforementioned LC VCO 406, and a feedback circuit, which may include a programmable divider or an N-divider circuit (NDIV) 422. The programmable divider 422 may be an integer N-divider or a fractional N-divider. The value of N may be determined by, for example, a data processor 210 (…). Figure 2 The loop filter 420 can be programmed using [the appropriate programming language].

[0053] The PFD 416 can be generated from, for example, a reference signal generator 294 in the data processor 210. Figure 2 The reference (clock) signal 424 is received. In other embodiments, the reference signal element 294 is implemented separately from the data processor 210 and / or configured to generate the reference signal based on a signal from an oscillator (e.g., a crystal oscillator). The PFD 416 may include, for example, a comparator or other circuitry configured to compare the phase and frequency of the reference clock signal 424 with a feedback signal 426, which represents the PLL output (voltage) signal 428 after processing by the programmable divider 422. Based on this comparison, the PFD 416 generates two signals whose rising edges differ in time, representing a timing error. The charge pump 418 receives these two signals from the PFD 416.

[0054] The charge pump 418 can operate as a time-to-voltage converter, thus converting timing errors into control voltages. The charge pump 418 can increase or decrease its output signal DC voltage based on whether the timing error is increasing or decreasing. If the timing error is zero, the output of the charge pump 418 is constant. The output of the charge pump 418 is coupled to the input of the loop filter 420. In an example where the loop filter 420 is a low-pass filter, the loop filter 420 removes high-frequency noise from the output signal of the charge pump 418 and provides a stable DC-level VCO tuning voltage to the tuning input of the LC VCO 406. It should be understood that the above-described PLL architecture based on PFD 416, CHP 418, loop filter 420, etc., is merely an example, and other embodiments may have different PLL architectures, such as digital PLL architectures.

[0055] LC VCO 406 generates a VCO output signal with a frequency proportional to the tuning voltage. The VCO output signal can pass through buffer 430 to provide PLL output signal 428. The aforementioned comparison and adjustment based on the feedback loop continues until the frequency of PLL output signal 428 equals the frequency of reference clock signal 424.

[0056] The output of LC VCO 406 is coupled to the input of LO divider 411. LO divider 411 can be the divider circuit 311 described above. Figure 3B Examples of LO dividers. For example, LO divider 411 may be a divide-by-two (DIV / 2) circuit configured to reduce the frequency of PLL output signal 428 by a factor of 2, or it may be a divider configured to reduce the frequency of PLL output signal 428 by another factor. Furthermore, LO divider 411 may be configured to provide the divided PLL output signal (i.e., the output of the first PLL circuit 412) in the form of multiple signals with different phases. For example, the output of LO divider 411 may include in-phase LO signals and quadrature LO signals separated by 90 degrees. Alternatively or additionally, the output of LO divider 411 may include signals separated by other amounts (such as 45 degrees). Mixer 312 ( Figure 3C Some examples may require such multiphase LO signals (e.g., 45 degrees apart) to perform harmonic suppression mixing (HRM). The output of LO divider 411 (i.e., the output of the first PLL circuit 412) is coupled to one of the two selectable multiphase inputs of multiplexer 404.

[0057] exist Figure 4In the example shown, the second PLL circuit 414 may include a PFD 434, a charge pump 436, and a loop filter 438, which may be similar to the PFD 416, charge pump 418, and loop filter 420 of the first PLL circuit 412 described above. The second PLL circuit 414 may also include the aforementioned ring oscillator VCO 408 and a feedback circuit, which includes a programmable frequency divider 440. The same reference clock signal 424 provided to the PFD 416 of the first PLL circuit 412 may be provided to the PFD 434 of the second PLL circuit 414 via a buffer 442.

[0058] Unless otherwise stated in this disclosure, the second PLL circuit 414 may be configured and operated as described above with respect to the first PLL circuit 412. However, a significant difference is that while the first PLL circuit 412 includes an LO divider 432 that downdivides the high-frequency output of the LC VCO 406 to the target LO frequency, the second PLL circuit 414 does not include such an LO divider.

[0059] Instead, as those skilled in the art will understand, the ring oscillator VCO 408 can operate at a lower target LO frequency. To reduce electromagnetic coupling between the inductive components of the LO signal generator and sensitive RF components such as low-noise amplifiers, the LC VCO of the LO signal generator may operate at a higher frequency than the received RF frequency, and then its output signal is frequency-divided. Operating the ring oscillator VCO 408 at the target LO frequency instead of at a higher frequency (or operating the LC VCO at a higher frequency) saves power.

[0060] In some embodiments (not explicitly shown), however, circuitry 411 is configured to convert the output of buffer 430 into a plurality of signals with different phases, but is not configured to divide the frequency of the output of buffer 430. For example, the plurality of signals with different phases may have the same frequency as the output of buffer 430. In such embodiments, the input of programmable divider 422 may be coupled to one of the outputs of circuitry 411. In these embodiments, in some implementations, programmable divider 440 may be omitted.

[0061] In some embodiments, the ring oscillator VCO 408 in the second PLL circuit 414 can operate from a significantly reduced supply voltage (e.g., in low-power mode) without degrading its functionality. Conversely, in some embodiments, a low supply voltage may impair the startup gain of the LC VCO 406 and / or impair the functionality of the LO divider 432. To avoid this potential adverse effect, the exemplary embodiments described herein are configured to operate the first PLL circuit 412 at a higher power level and operate the second PLL circuit only at a lower power level associated with the low-power mode. Furthermore, the second PLL circuit 414 may occupy a much smaller chip area (not shown) than the first PLL circuit 412.

[0062] like Figure 5 As shown, the ring oscillator VCO 500 can directly provide outputs in the form of multiple signals 502 with different phases, because such output signals can be provided by corresponding stages 504, 506, 508, etc. of the ring topology. Each stage 504, 506, 508, etc. of the ring oscillator VCO 500 may include an inverter circuit. For clarity, stages 504, 506, 508, etc. are not shown at the transistor level, but as those skilled in the art will understand, each stage may include a pair of transistors. Although in Figure 5 In the example shown, the ring oscillator VCO 500 has three stages, but such a ring oscillator VCO can have more stages (typically an odd number), a more complex ring topology, or otherwise differ from the example shown, as will be understood by those skilled in the art. The frequency of the output signal 502 can be adjusted or tuned in various ways depending on the topology. One approach is to use a variable voltage controlled by a control signal (V_TUNE) to drive each stage 504, 506, 508, etc. The variable voltage can be based on the supply voltage, which can be reduced when operating in low-power mode.

[0063] like Figure 6 As shown, the LC VCO 600 may include one or more inductors 602 and variable capacitors 604, 606, etc. A first pair of cross-coupled transistors 608 and 610, and / or a second pair of cross-coupled transistors 612 and 614 are configured to maintain the oscillation of the output signal, such as... Figure 5 As shown, the output signals are differential signals (V_OUT_P and V_OUT_M). The frequency of the output signals can be adjusted or tuned by changing the control signal (V_TUNE). The VCO 600 (e.g., the source of transistors 608 and 610) can be coupled to the power supply voltage (VDD).

[0064] Refer again Figure 4The ring oscillator VCO 408 of the second PLL circuit 414 can be configured to directly provide a set of LO signals corresponding to the set provided by the LO divider 432 of the first PLL circuit 412, including in-phase and quadrature LO signals spaced 90 degrees apart, signals spaced by other amounts (such as 45 degrees), etc. A buffer 444 can be coupled between the output of the ring oscillator VCO 408 and another selectable multiphase input of the multiplexer 404 to buffer the multiphase divider PLL output signal.

[0065] As described above, multiplexer 404 is configured to select one of its two multiphase inputs in response to mode selection signal 410. Therefore, when the state of mode selection signal 410 indicates operation in normal or higher power mode, the multiphase output of first PLL circuit 412 is provided at the multiphase output of multiplexer 404, while when the state of mode selection signal 410 indicates operation in lower power mode, the multiphase output of second PLL circuit 414 is provided at the multiphase output of multiplexer 404. Duty cycle generator 446 can be coupled to the output of multiplexer 404 to provide a multiphase LO signal with a uniform duty cycle (e.g., 25%). The multiphase output of duty cycle generator 446 can be coupled to the multiphase input of mixer 304 (FIG. 3) via buffer 448.

[0066] Figure 7 An exemplary method 700 for selecting a frequency synthesizer is illustrated. As shown in block 702, method 700 may include receiving a mode selection signal indicating a lower power receiver mode or a higher power receiver mode. As shown in block 704, method 700 may further include selecting the output of a first VCO circuit or the output of a second VCO circuit in response to the mode selection signal.

[0067] Figure 8 An exemplary method 800 for selecting a frequency synthesizer signal is illustrated. As shown in block 802, method 800 may include receiving a mode selection signal indicating a lower power receiver mode or a higher power receiver mode. As shown in block 804, method 800 may further include dividing the output of a first VCO circuit to generate a divided signal. As shown in block 806, method 800 may further include selecting the divided signal or the undivided output of a second VCO circuit in response to the mode selection signal. The frequency of the output of the first VCO circuit may be a multiple of the frequency of the output of the second VCO circuit.

[0068] Figure 9An exemplary method 900 for coupling a selected LO frequency synthesizer to a mixer input in, for example, an RF receiver is illustrated. As shown in block 902, method 900 may include receiving a mode selection signal indicating a lower power receiver mode or a higher power receiver mode. As shown in block 904, method 900 may further include selecting the output of an LC-based VCO circuit or the output of a ring oscillator-based VCO circuit in response to the mode selection signal.

[0069] Method 700 ( Figure 7 ), 800 Figure 8 ) or 900 Figure 9 Any one of them can be generated by the aforementioned wireless device 200. Figure 2 ) or a portion thereof to perform or control. For example, receiver 250 ( Figure 2 ), RX LO signal generator 280 ( Figure 2 ), Multiplexer 304A ( Figure 3A ), 304B Figure 3B ), 304C Figure 3C ) or 404 Figure 4 Any one of them can be obtained from, for example, data processor 210 ( Figure 2 Receive mode selection signal. Multiplexer 304A ( Figure 3A ), 304B Figure 3B ), 304C Figure 3C ) or 404 Figure 4 Any one of them can select the output of the first VCO circuit 306A, 306B, 306C, or the output of the second VCO circuit 308A, 308B, or 308C, or select the output of the first PLL circuit 412 or the output of the second PLL circuit 414.

[0070] Instructions or code embodying any one of methods 700, 800, or 900 may be stored in memory in a computer-readable form (i.e., firmware or software), such as memory 298. Figure 2 This memory is intended for execution by, for example, a processor 296 of a data processor 210. Any such memory having firmware or software stored therein in a computer-readable form for execution by a processor can be an example of "computer program product," "computer-readable medium," etc., as such terms are understood in patent dictionaries.

[0071] Figure 10An apparatus 1000 for selecting a frequency synthesizer is shown. As shown in block 1002, the apparatus 1000 may include components for receiving a mode selection signal indicating a lower power receiver mode or a higher power receiver mode. As shown in block 1004, the apparatus 1000 may also include components for selecting the output of a first VCO circuit or the output of a second VCO circuit in response to the mode selection signal.

[0072] Figure 11 An exemplary apparatus 1100 for selecting a frequency synthesizer signal is shown. As shown in block 1102, apparatus 1100 may include components for receiving a mode selection signal indicating a lower power receiver mode or a higher power receiver mode. As shown in block 1104, apparatus 1100 may further include components for dividing the output of a first VCO circuit to generate a divided signal. As shown in block 1106, apparatus 1100 may further include components for selecting the divided signal or the output of an undivided second VCO circuit in response to the mode selection signal. The frequency of the output of the first VCO circuit may be a multiple of the frequency of the output of the second VCO circuit.

[0073] Figure 12 A device 1200 is shown for coupling a selected LO frequency synthesizer to a mixer input in, for example, an RF receiver. As shown in block 1202, the device 1200 may include components for receiving a mode selection signal indicating a lower power receiver mode or a higher power receiver mode. As shown in block 1204, the device 1200 may also include components for selecting the output of an LC-based VCO circuit or the output of a ring oscillator-based VCO circuit in response to the mode selection signal.

[0074] In the manner described above, the frequency synthesizer system according to this disclosure, the method for coupling the selected frequency synthesizer, and the like can provide various benefits, including significant power savings and thus extended battery life. For example, a ring oscillator-based VCO circuit can operate at supply voltages below levels that might degrade the performance of an LC-based VCO circuit. While some embodiments described herein may provide specific advantages with respect to the RF receiver, implementation is not limited to such embodiments. The configurations described herein can be used to implement the frequency synthesizer system in other contexts and have other benefits.

[0075] While aspects and embodiments are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented on many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, embodiments and / or uses may be implemented via integrated chip embodiments and other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial devices, retail / procurement devices, medical devices, AI-implemented devices, etc.). While some examples may or may not be specific to use cases or applications, a wide variety of applicability to the described innovations may emerge. Implementations can range from chip-level or modular components to non-modular, non-chip-level implementations and further to aggregated, distributed, or OEM devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described embodiments. For example, the transmission and reception of wireless signals necessarily involve many components for analog and digital purposes (e.g., hardware components, including antennas, RF chains, power amplifiers, modulators, buffers, processors (multiple), interleavers, adders / adders, etc.). The intention is that the innovations described herein can be implemented in a wide variety of devices, chip-level components, systems, distributed deployments, end-user equipment, etc., of various sizes, shapes, and constructions.

[0076] The detailed description above, taken in conjunction with the accompanying drawings, describes examples and is not intended to represent the only examples that can be implemented or that fall within the scope of the claims. The terms “example” and “exemplary” as used herein mean “serving as an example, instance, or illustration” and not “preferred” or “superior to other examples.” The detailed description includes specific details intended to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0077] Information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0078] The various illustrative boxes and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, digital signal processor (DSP), ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0079] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, these functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope and spirit of this disclosure and the appended claims. For example, due to the nature of software, the aforementioned functions may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including being distributed such that portions of the function are implemented in different physical locations. As used herein, including in the claims, when used in a list of two or more items, the term “and / or” means that any one of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a combination is described as comprising components A, B, and / or C, the combination may comprise a single A; a single B; a single C; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein, including in the claims, the use of "or" in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates a disjunctive list, such that, for example, the list "at least one of A, B or C" means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0080] Non-transitory computer-readable media include computer storage media and communication media, including any non-transitory media that facilitates the transfer of computer programs from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, computer-readable media can include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. As used herein, “disk” and “optical disc” include laser discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable media.

[0081] The foregoing is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0082] Therefore, although the selected aspects have been described and detailed, it should be understood that various substitutions and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A frequency synthesizer system, comprising: The first voltage-controlled oscillator (VCO) circuit includes an inductor and a capacitor VCO; The second VCO circuit includes a ring oscillator; The multiplexing circuit system is configured to select one of the outputs of the first VCO circuit and the second VCO circuit in response to a mode selection signal; as well as A frequency divider circuit having an input coupled to the output of the first VCO circuit and an output coupled to the input of the multiplexing circuit system, wherein the multiplexing circuit system is configured to select one of the outputs of the frequency divider circuit and the second VCO circuit in response to the mode selection signal.

2. The frequency synthesizer system according to claim 1, wherein: The first VCO circuit is included in the first phase-locked loop (PLL) circuit; and The second VCO circuit is included in the second PLL circuit.

3. The frequency synthesizer system of claim 2 further includes a mixer, wherein the output of the multiplexing circuit system is coupled to the input of the mixer.

4. The frequency synthesizer system of claim 2, wherein the first VCO circuit and the second VCO circuit are included in the RF receiver local oscillator (LO) circuit.

5. The frequency synthesizer system of claim 4, wherein a first state of the mode selection signal indicates a lower power operating mode of the RF receiver, and a second state of the mode selection signal indicates a higher power operating mode of the RF receiver.

6. The frequency synthesizer system of claim 1, wherein the output of the frequency divider circuit comprises a first plurality of phase signals with phases different from each other.

7. The frequency synthesizer system according to claim 6, wherein: The first VCO circuit is included in the first phase-locked loop (PLL) circuit; and The second VCO circuit is included in the second PLL circuit.

8. The frequency synthesizer system of claim 7, wherein the output of the ring oscillator includes a second plurality of phase signals with phases different from each other, and the multiplexing circuit system is configured to select one of the first plurality of phase signals and the second plurality of phase signals in response to the mode selection signal.

9. A method for selecting a frequency synthesizer in an RF receiver, comprising: Receive mode selection signal; In response to the mode selection signal, one of the outputs of a first voltage-controlled oscillator (VCO) circuit and a second VCO circuit is selected. The first VCO circuit includes an inductor-capacitor VCO, and the second VCO circuit includes a ring oscillator. The frequency of the output of the first VCO circuit is divided to provide a frequency-divided output, wherein selecting one of the outputs of the first VCO circuit and the second VCO circuit includes selecting one of the frequency-divided output and the output of the second VCO circuit in response to the mode selection signal.

10. The method of claim 9, wherein selecting one of the outputs of the first VCO circuit and the second VCO circuit comprises: Choose one of the outputs of the first phase-locked loop (PLL) circuit and the second PLL circuit.

11. The method of claim 10, further comprising: The output of the first VCO circuit and the output of the second VCO circuit are selected and coupled to the input of the mixer.

12. The method of claim 10, wherein selecting one of the outputs of the first VCO circuit and the second VCO circuit comprises: Provide the selected VCO circuit output in the RF receiver local oscillator (LO) circuit.

13. The method of claim 12, wherein selecting one of the outputs of the first VCO circuit and the second VCO circuit comprises: When the state of the mode selection signal indicates a higher power operation mode for the RF receiver, the output of the first VCO circuit is selected; when the state of the mode selection signal indicates a lower power operation mode for the RF receiver, the output of the second VCO circuit is selected.

14. The method of claim 9, wherein dividing the frequency of the output of the first VCO circuit to provide a divided output comprises: Provides a first plurality of phase signals with phases different from each other.

15. The method of claim 14, wherein selecting one of the outputs of the first VCO circuit and the second VCO circuit comprises: Choose one of the outputs of the first phase-locked loop (PLL) circuit and the second PLL circuit.

16. The method of claim 15, wherein the output of the ring oscillator includes a second plurality of phase signals with phases different from each other, and selecting one of the outputs of the first VCO circuit and the second VCO circuit includes selecting one of the first plurality of phase signals and the second plurality of phase signals in response to the mode selection signal.

17. An apparatus for selecting a frequency synthesizer in a radio frequency receiver, comprising: Components used to receive mode selection signals; A component for selecting one of the outputs of a first voltage-controlled oscillator (VCO) circuit and a second VCO circuit in response to the mode selection signal, the first VCO circuit comprising an inductor-capacitor VCO, and the second VCO circuit comprising a ring oscillator; and The component for dividing the frequency of the output of the first VCO circuit and providing the divided output to the input of the multiplexing circuit system, wherein the component for selecting one of the outputs of the first VCO circuit and the second VCO circuit includes: a component for selecting one of the divided outputs and the output of the second VCO circuit in response to the mode selection signal.

18. The apparatus of claim 17, wherein the component for selecting one of the outputs of the first VCO circuit and the second VCO circuit comprises: A component used to select one of the outputs of the first phase-locked loop (PLL) circuit and the second PLL circuit.

19. The apparatus of claim 18, further comprising: A component used to couple the output of a multiplexer circuit system to the input of a mixer.

20. The apparatus of claim 18, wherein the component for selecting one of the outputs of the first VCO circuit and the second VCO circuit comprises: A component used to provide the output of a selected VCO circuit in the local oscillator (LO) circuit of an RF receiver.

21. The apparatus of claim 17, wherein the components for frequency division and provision include: A component for providing a plurality of phase signals that have different phases from each other.

22. The apparatus of claim 21, wherein the component for selecting one of the outputs of the first VCO circuit and the second VCO circuit comprises: A component used to select one of the outputs of the first phase-locked loop (PLL) circuit and the second PLL circuit.

23. An apparatus for processing communication signals, comprising: A mixer is configured to mix a communication signal with a local oscillator signal having a first frequency; as well as Local oscillators, including A first voltage-controlled oscillator (VCO) circuit is configured to output a first signal at the first frequency. The second VCO circuit is configured to output a second signal at a second frequency higher than the first frequency. The frequency divider circuit is configured to receive the second signal at the second frequency and output a third signal at the first frequency. The multiplexing circuit system is configured to selectively couple either the first signal or the third signal to the output of the local oscillator in response to a mode selection signal.

24. The apparatus according to claim 23, wherein: The first VCO circuit is included in the first phase-locked loop (PLL) circuit; and The second VCO circuit is included in the second PLL circuit.

25. The apparatus of claim 23, further comprising a duty cycle generator coupled between the output of the multiplexing circuit system and the output of the local oscillator, the duty cycle generator being configured to provide the local oscillator signal based on the first signal or the third signal.

26. The apparatus of claim 23, wherein the mixer and the local oscillator are included in a radio frequency (RF) receiver, wherein a first state of the mode selection signal indicates a low-power operating mode of the RF receiver, and a second state of the mode selection signal indicates a high-power operating mode of the RF receiver.

27. The apparatus of claim 26, wherein the multiplexing circuitry is configured to couple the first signal to the output of the local oscillator in response to the mode selection signal being in the first state, and wherein the multiplexing circuitry is configured to couple the third signal to the output of the local oscillator in response to the mode selection signal being in the second state.

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