Column asil circuit for multiple bit lines in an image sensor

Abstract

This invention provides a fault detection circuit for an image sensor and a method for detecting faults in bit lines. The fault detection circuit for the image sensor includes a first input node, an array of second input nodes, and an output stage. The first input node is coupled to a reference voltage. The array of second input nodes has each input node coupled to receive signals from bit lines of a bit line array in an image sensor comprising an array of pixels, wherein each pixel is coupled to at least one bit line of the bit line array. The output stage is coupled to generate an output voltage indicating that any of the second input nodes is below the reference voltage.

Description

Technical Field

[0001] This invention relates to the field of automotive image sensors, and more particularly to a fault detection circuit for an image sensor and a method for detecting faults in bit lines. Background Technology

[0002] Modern vehicles are increasingly equipped with Advanced Driver Assistance Systems (ADAS). ADAS enhances the comfort and safety of driving, providing features such as collision warning, proximity warning, and blind spot warning. ADAS can also include active autonomous components for additional levels of driving safety, such as adaptive cruise control, automatic braking, automatic steering, and collision avoidance. While ADAS relies on and processes input from multiple data sources, such as light detection and ranging (LIDAR), radar, and computer vision, the primary sensor in most ADAS systems remains the image sensor. As ADAS incorporates more active and autonomous functions, vehicle safety depends increasingly on the reliability of the imaging system.

[0003] For automotive image sensor design, there are standards that meet the requirements of the Automotive Safety Integrity Level (ASIL). ASIL specifies the safety level for the automotive industry and uses a risk classification scheme defined by ISO 26262. ASIL is established by examining the risks associated with potential hazards through analysis of the severity of a failure, the probability of its occurrence, and the ability to control its impact. The standard defines ASIL as four levels: ASIL A, ASIL B, ASIL C, and ASIL D. ASIL D represents the highest integrity requirement for a product, while ASIL A represents the lowest requirement. For image sensors, to meet the requirements of the ASIL D standard, each individual circuit block should have a detection mechanism to detect operational faults, including (i) signal dips to low / high levels, (ii) transient signal faults, and (iii) undervoltage / overvoltage. Failure to detect such faults can lead to image quality degradation / image corruption, which poses safety issues for automotive applications. Summary of the Invention

[0004] Image sensors include an array of pixels, each pixel including one or more photodiodes that generate image charge in response to incident light. The image charge is transferred from the photodiodes to a floating diffuser and, upon triggering, to a readout circuit via bit lines. Some embodiments of this disclosure have two bit lines for each pixel. Conventional methods for fault detection in a column of pixels may include fault detection circuitry for each bit line. With two bit lines, the additional fault detection circuitry requires more space and power than a conventional one bit line per pixel design. This disclosure describes a fault detection circuit that includes more than one bit line input without requiring additional space and power.

[0005] In a first aspect, a fault detection circuit for an image sensor includes a first input node, an array of second input nodes, and an output stage. The first input node is coupled to a reference voltage. The array of second input nodes has each input node coupled to receive signals from bit lines of a bit line array in an image sensor comprising an array of pixels, wherein each pixel is coupled to at least one bit line of the bit line array. The output stage is coupled to generate an output voltage indicating that any of the second input nodes is below the reference voltage.

[0006] In some embodiments, each of the second input nodes is coupled to the gate of an input transistor, and all input transistors of the fault detection circuit have a source connected to a common source node and a drain connected to a common drain node.

[0007] In some embodiments, there are at least two input transistors, each of which is coupled to a second input node.

[0008] In some embodiments, there are at least three input transistors, each of which is coupled to a second input node.

[0009] In some embodiments, the fault detection circuit further includes a self-test circuit that simulates a fault in the signal from the bit lines of the bit line array.

[0010] In some embodiments, the self-test circuit includes at least one transistor having a source connected to the common source node and a drain connected to the common drain node.

[0011] In some embodiments, the bit line array includes at least two bit lines.

[0012] In some embodiments, the two bit lines include a first bit line coupled to receive a sample and hold reset voltage and a second bit line coupled to receive a sample and hold signal voltage from each pixel of the array of pixels.

[0013] In a second aspect, a method for detecting faults in bit lines includes: (i) receiving an array of input voltages, wherein each input voltage is received from a corresponding bit line of the bit line array; (ii) comparing each input voltage in the array of received input voltages with a reference voltage to generate a comparison result; and (iii) outputting a combination result from an OR gate, wherein each input corresponds to a comparison result generated for each input voltage.

[0014] In some embodiments, in the step of comparing each input voltage, the comparison result is an output voltage indicating that each input voltage is lower than the reference voltage. Attached Figure Description

[0015] Figure 1 The illustration shows a vehicle safety system in an embodiment.

[0016] Figure 2 The illustration shows a schematic diagram of pixels in an embodiment.

[0017] Figure 3 The illustration shows a simplified schematic diagram of the image sensor array in the embodiment, which illustrates the fault detection circuit.

[0018] Figure 4 The illustration shows a schematic diagram of a fault detection circuit for bit lines in an embodiment.

[0019] Figure 5 The illustration shows a simplified schematic diagram of a fault detection circuit for a two-bit line in an embodiment.

[0020] Figure 6 The illustration shows a schematic diagram of the dual-line fault detection circuit in the embodiment. Detailed Implementation

[0021] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one example of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same example. Furthermore, in one or more examples, particular features, structures, or characteristics may be combined in any suitable manner.

[0022] Several technical terms are used throughout this specification. These terms should be used in their ordinary sense in the field of their respective domains, unless specifically defined herein or the context of their use explicitly implies otherwise. It should be noted that element names and symbols are used interchangeably in this document (e.g., Si vs. silicon); however, they have exactly the same meaning.

[0023] The use of terms such as "first," "second," and "third" in this specification is to avoid confusion between components and does not restrict the order, etc. Therefore, for example, the term "first" may be replaced by the terms "second," "third," etc., where appropriate. Furthermore, when the following description refers to the accompanying drawings, unless otherwise indicated, the same reference numerals in different drawings denote the same or similar elements.

[0024] Figure 1An example vehicle safety system 100 is depicted. Vehicle safety system 100 may be part of an ADAS (Advanced Driver Assistance System). Vehicle safety system 100 includes multiple cameras 190. Cameras 190 may be distributed around the vehicle, such that each camera has a different view of the vehicle's surroundings. For example, camera 190(1) may be a rear-view camera mounted at the rear of the vehicle, while camera 190(2) may be a lane-tracking camera mounted on the side of the vehicle. Camera 190 includes an image sensor 192, which includes a pixel array 194A. Image sensor 192 may be part of a chip-scale package or an on-board chip package. Image sensor 192 is shown as a component of a vehicle camera, but it should be appreciated that other devices, such as safety devices, drone cameras, etc., may utilize image sensor 192 without departing from its scope.

[0025] The vehicle safety system 100 also includes a camera monitoring system (CMS) 110. The CMS 110 is configured to receive fault signs from each camera 190 and includes a fault detection flag 112, which is set when a fault is detected in any camera 190. The fault detection flag 112 can trigger an alarm to vehicle occupants, which may be in the form of a warning light and may additionally disable part of the ADAS. The fault signs from the cameras 190 can be generated by an image sensor 192, as discussed below.

[0026] Figure 2 An example schematic diagram of pixel 200 is shown. Pixel 200 is an example of pixels forming pixel array 194A. Pixel 200 may be part of a global shutter image sensor. In some embodiments, an image sensor such as image sensor 192 includes pixel chip 201 and logic chip 203. Pixel 200 may include portions of both pixel chip 201 and logic chip 203. For example, pixel 200 may include one or more of photodiodes 210 and transistors in pixel chip 201: transfer (TX) transistor 220, reset (RST) transistor 222, source follower (SF) transistor 226, and gate select (GS) transistor 228. Pixel 200 may also include one or more transistors in logic chip 203: load transistor 230, sample and hold switches 232 and 234, SF transistors 236 and 238, and row select (RS) transistors 237 and 239. Pixel chip 201 and logic chip 203 may be connected via hybrid bonding (HB) 204.

[0027] In operation, image charge from photodiode 210 is connected to floating diffusion (FD) node 251 via TX transistor 220, which is controlled by TX select line 261. FD node 251 can be connected to reset voltage power supply line 250, such as a power supply line for analog circuitry (AVDD), via RST transistor 222, which can selectively reset photodiode 210 to a predefined reset level, such as AVDD. RST transistor 222 can be controlled by RST control signal 253. FD node 251 also controls SF transistor 226. SF transistor 226 is coupled in series with GS transistor 228, which is coupled to logic chip 203 via HB 204. In some embodiments, HB 204 is coupled to load transistor 230 and pixel bias current source 215 in logic chip 203. Load transistor 230 is controlled by Vctrl_en signal 263 and coupled to voltage reference (Vref) 280.

[0028] In some global shutter designs, sample-and-hold switches are used for sample-and-hold signal (SHS) readings and sample-and-hold reset (SHR) readings from the image sensor. The SHS and SHR switches are controlled to sample the corresponding signal and reset levels. In operation, during the global sampling phase, all sample-and-hold switches switch simultaneously to sample the entire frame from the image sensor into the storage capacitor. When global sampling is complete, line-by-line data is read out and reset, and the signal levels are digitized. For example, a first sample-and-hold switch 232 is controlled by a sample-and-hold reset enable (SHR_en) signal 265 to sample and hold the reset level from FD node 251 into a first storage capacitor (C1) 240. A second sample-and-hold switch 234 is controlled by a sample-and-hold signal enable (SHS_en) signal 267 to sample and hold the signal level from FD node 251 into a second storage capacitor (C2) 242.

[0029] The first terminal of C1 240 controls SF transistor 236, and C2 242 controls SF transistor 238. SF transistors 236 and 238 are coupled in series with RS transistors 237 and 239, respectively. RS transistors 237 and 239 are controlled by row selection signal 254. After shutter operation, the reset and signal readouts stored in the corresponding capacitors C1 240 and C2 242 are read out row by row to the column readout circuit in rolling shutter mode. For example, transistors 236 and 237 can be used to transfer the image charge stored in C1 240 to the first data bit line via connection point 216. Similarly, transistors 238 and 239 can be used to transfer the image charge stored in C2 242 to the second data bit line via connection point 218.

[0030] Control signals for the transistors can be provided by control circuitry to control the operation of any pixel in order to reset the pixel and read out image charge from one or more photodiodes 210. Pixel configuration is not limited to... Figure 2 The example shown illustrates this. For instance, one or more photodiodes can share the same FD node, RST transistor, SF transistor, and RS transistor.

[0031] Figure 3 This is a simplified schematic diagram of an image sensor array 300. An image sensor (such as image sensor 192) may include an array of image sensor array 300. Image sensor array 300 includes an array of pixels 200 and column bit lines 312 and 314. Image sensor array 300 may also include readout circuitry 390. Readout circuitry 390 is coupled to one or more bit lines including bit lines 312 and 314 and can convert image charge from the array of pixels into image data by using the digital difference between the sampled reset and signal levels.

[0032] Image sensor array 300 may also include a global fault detection circuit or a global ASIL circuit 371. The global ASIL circuit 371 can be coupled to a load transistor (e.g., load transistor 230) in each pixel by sampling Vref 380, which is an example of Vref 280. The global ASIL circuit 371 can detect faults in each pixel circuit (such as pixel 200 in image sensor array 300), including an interrupted HB 204 and transistor inputs for transistors 222 and 228 falling low or high. For example, if either transistor 222 or 228 falls low when the transistor is set high, then pixel bias current from pixel bias current source 215 flows through load transistor 230 by setting Vctrl_en 263 to a specific low level, thus generating a fault signal. Importantly in this example, the level of Vctrl_en 263 set for fault detection does not interfere with normal pixel operation. Similarly, for open circuit HB 204, the pixel bias current from pixel bias current source 215 flows through load transistor 230 and also generates a fault signal through global ASIL circuit 371.

[0033] Image sensor column 300 also includes column ASIL circuitry 370. Column ASIL circuitry 370 is coupled to one or more of the column bit lines, such as bit lines 312 and 314 with corresponding coupling points 382 and 384. Column ASIL circuitry 370 can detect faults that may exist in the bit lines. For example, two types of faults may exist in the bit lines: (i) a break in one or more bit lines and (ii) a break between one or more pixels and one or more bit lines. In fault (i), if a bit line becomes open, for example at break point 317 or 315, all pixel connections above break point 317 or 315, including pixel 200(0), will fail. In fault (ii), one or more row selection connections (such as connection points 316 and 318 as corresponding examples of connection points 216 and 218) become open. Any fault mode will cause column ASIL circuitry 370 to issue a fault flag. Since pixels are read line by line, the physical location of an open connection is unique, and the location of a faulty connection is easily obtained.

[0034] Figure 4 This is an example schematic diagram of an ASIL circuit 470. The ASIL circuit 470 includes a comparator 488, which includes a first input device 476 coupled to Vref 462. Figure 4 The power supply line (Vdd) 458 is represented. Comparator 488 also includes a second input device 472 having a gate terminal coupled to bit line 414. Bit line 414 is an example of bit line 312 or 314. In the depicted example, the first and second input devices 476 and 472 are PMOS transistors. In another example, the first and second input devices 476 and 472 can be NMOS transistors. NMOS current mirrors including transistors 463 and 473 are coupled to the respective input devices 476 and 472. The ASIL circuit 470 also includes an output (ASIL_fail) node 478 that can couple the output of the fault detection circuit to an asynchronous static random access memory (ASRAM) in a readout circuit such as readout circuit 390. In operation, the ASIL_fail node 478 is set high to indicate a fault when the voltage on bit line 414 drops below Vref 462.

[0035] Figure 5This is an example schematic diagram of a dual-bit-line column ASIL circuit 500, hereinafter referred to as column ASIL circuit 500. Column ASIL circuit 500 can represent a conventional method for detecting faults in an image sensor characterized by more than one bit line per column and thus including an array of column ASIL circuits 470. The array of column ASIL circuits 470 may include one column ASIL circuit 470(i) for each bit line. In the depicted example, column ASIL circuits 470(1) and 470(2) are coupled to bit lines 314 and 312, respectively. Column ASIL circuit 500 also includes an OR gate 519. The OR gate 519 has inputs to ASIL_fail nodes 478(1) and 478(2) from column ASIL circuits 470(1) and 470(2), respectively. The output 579 of column ASIL circuit 500 is the result of an OR operation, such that when one or both of column ASIL circuits 470(1) and 470(2) indicate a fault, output 579 also issues a fault flag.

[0036] exist Figure 5 In the example depicted, each bit line requires a column ASIL circuit 470 for fault detection. Therefore, for an image sensor with two bit lines per column, the space and additional power requirements for accommodating the column ASIL circuitry for each bit line are contrary to the latest demands for more compact and lower-power image sensors. However, Figure 6 The example shown is improved in the following ways Figure 5 Example: Almost no additional space and power is required for fault detection in each column of dual-bit line image sensors.

[0037] Figure 6 This is an example schematic diagram of a dual-bit line array ASIL circuit 670, hereinafter referred to as the column ASIL circuit 670. The column ASIL circuit 670 can be used in image sensors comprising arrays of dual-bit line pixels, such as pixel 200, or arrays of image sensor columns, such as image sensor column 300. Advantageously, the column ASIL circuit 670 can replace... Figure 5 The two column ASIL circuits 470(1) and 470(2) are depicted. Column ASIL circuit 670 includes a comparator that compares at least two bit line voltages with a reference voltage. For example, a first set of input devices includes input device 672 coupled to bit line 314 and input device 673 coupled to bit line 312. A second input device 676 is coupled to Vref 662, which is an example of Vref 462. Column ASIL circuit 670 also includes an output (ASIL_fail) node 679, which can couple the output of a fault detection circuit to, for example,... Figure 3The asynchronous static random access memory (ASRAM) in the readout circuit, such as readout circuit 390. During operation, if a fault occurs, such as an open connection of either bit line 312 or 314 (e.g., ...), Figure 3 If the disconnection points 317 and 315 or the open connection points 316 and 318 are reached, then the ASIL_fail node 679 is set high to indicate a fault. Since pixels are read line by line, the physical location of the open connection is unique and the location of the faulty connection is easily obtained.

[0038] The column ASIL circuit 670 may also include an ASIL test transistor 681, which may be a PMOS transistor, for a self-test function. For example, the self-test function may check the functionality of the column ASIL circuit 670. In this example, during the self-test, the ASIL test transistor 681 is pulled low by the a_asil_tst_enb switch 665, simulating fault conditions (such as a break in the bit line) and causing the ASIL_fail node 679 to be set high.

[0039] Combination of features

[0040] The features described above and claimed below can be combined in various ways without departing from the scope of the invention. The examples listed below illustrate some possible, non-limiting combinations.

[0041] (A1) A fault detection circuit for an image sensor includes a first input node, an array of second input nodes, and an output stage. The first input node is coupled to a reference voltage. The array of second input nodes has each input node coupled to receive signals from bit lines of a bit line array in an image sensor comprising an array of pixels, wherein each pixel is coupled to at least one bit line of the bit line array. The output stage is coupled to generate an output voltage indicating that any of the second input nodes is below the reference voltage.

[0042] (A2) In an embodiment of the fault detection circuit (A1), each of the second input nodes is coupled to the gate of an input transistor, and all input transistors of the fault detection circuit have a source connected to a common source node and a drain connected to a common drain node.

[0043] (A3) In an embodiment of the fault detection circuit (A2), there are at least two input transistors, each of which is coupled to a second input node.

[0044] (A4) In an embodiment of the fault detection circuit (A3), there are at least three input transistors, each of which is coupled to a second input node.

[0045] (A5) An embodiment of any one of the fault detection circuits (A2)-(A4) also includes a self-test circuit that simulates a fault in a signal from a bit line of the bit line array.

[0046] (A6) In an embodiment of the fault detection circuit (A5), the self-test circuit includes at least one transistor having a source connected to a common source node and a drain connected to a common drain node.

[0047] (A7) In any embodiment of the fault detection circuits (A1)–(A6), the bit line array includes at least two bit lines.

[0048] (A8) In an embodiment of the fault detection circuit (A7), the two bit lines include a first bit line coupled to receive a sampled and held reset voltage and a second bit line coupled to receive a sampled and held signal voltage from each pixel of the pixel array.

[0049] (B1) A method for detecting faults in a bit line includes: (i) receiving an array of input voltages, wherein each input voltage is received from a corresponding bit line of the bit line array; (ii) comparing each input voltage in the array of received input voltages with a reference voltage to generate a comparison result; and (iii) outputting a combination result from an OR gate, wherein each input corresponds to a comparison result generated for each input voltage.

[0050] (B2) In an embodiment of method (B1), in the step of comparing each input voltage, the comparison result is an output voltage indicating that each input voltage is lower than a reference voltage.

[0051] Modifications may be made to the methods and systems described above without departing from the scope of these embodiments. Therefore, it should be noted that the content contained in the above description or shown in the accompanying drawings should be interpreted as illustrative rather than restrictive. In this document, and unless otherwise stated, the phrase "in embodiments" is equivalent to the phrase "in some embodiments" and does not refer to all embodiments. The following claims are intended to cover all general and specific features described herein, as well as all statements regarding the scope of the methods and systems that may be considered linguistically intermediate between the two.

Claims

1. A fault detection circuit for an image sensor, comprising: The first input node is coupled to the reference voltage; An array of second input nodes, each second input node being coupled to receive a signal from a bit line of a bit line array in an image sensor comprising an array of pixels, wherein each pixel is coupled to at least one bit line of the bit line array; as well as The output stage is coupled to generate an output voltage that indicates any of the second input nodes is below the reference voltage; Each of the second input nodes in the array of second input nodes is coupled to the gate of an input transistor, all input transistors of the fault detection circuit have a source connected to a common source node and a drain connected to a common drain node; and wherein the first input node is coupled to the gate of a reference transistor, the reference transistor having a source connected to the common source node.

2. The fault detection circuit of claim 1, wherein there are at least two input transistors, each of the input transistors having a gate of a second input node coupled to an array of the second input nodes.

3. The fault detection circuit as claimed in claim 2, wherein there are at least three input transistors, each input transistor being coupled to a second input node.

4. The fault detection circuit of claim 1 further includes a self-test circuit that simulates a fault in the signal from the bit lines of the bit line array.

5. The fault detection circuit of claim 4, wherein the self-test circuit includes at least one transistor having a source connected to the common source node and a drain connected to the common drain node.

6. The fault detection circuit of claim 1, wherein the bit line array comprises at least two bit lines.

7. The fault detection circuit of claim 6, wherein the two bit lines include a first bit line coupled to receive a sampled and held reset voltage and a second bit line coupled to receive a sampled and held signal voltage from each pixel of the array of pixels.

8. A method for detecting faults in a bit line, comprising: An array that receives input voltages, each input voltage being received from a corresponding bit line of a bit line array; Each input voltage in the array of received input voltages is compared with a reference voltage to generate a comparison result; as well as The OR gate outputs a combination result, where each input corresponds to a comparison result generated for each input voltage; The comparison is performed in a circuit, wherein for each input voltage in the array of input voltages, the circuit has an input transistor having a gate coupled to each input voltage and a source coupled to a common source node, the common source node being coupled to the source of a reference transistor having a gate coupled to the reference voltage.

9. The method of claim 8, wherein in the step of comparing each input voltage, the comparison result is an output voltage indicating that each input voltage is lower than the reference voltage.

10. The method of claim 8, wherein there are multiple input voltages.

11. The method of claim 8, further comprising simulating a fault in a bit line by applying a voltage to the gate of a test transistor having a source coupled to the common source node.

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