Display substrate and manufacturing method therefor, display device

Abstract

A display substrate and a manufacturing method thereof, and a display device, wherein the display substrate comprises a substrate and a plurality of pixel units arranged on the substrate, wherein: at least one of the plurality of pixel units comprises a plurality of sub-pixels of different colors, and at least one of the plurality of sub-pixels comprises a plurality of sub-pixels of the same color; an anode of the sub-pixel is electrically connected to a driving circuit, the driving circuits are independent of each other, in a plane perpendicular to the display substrate, at least a partial surface of a side of the anode of the sub-pixel away from the substrate comprises a normal line which is not perpendicular to the substrate.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] The main principle of 3D display technology is to allow the viewer's left and right eyes to receive different images. These two images are then analyzed and superimposed by the brain, allowing the viewer to perceive a sense of depth in the image and thus create a sense of three-dimensionality. Among these technologies, 3D glasses-free display technology is a hot research topic in 3D display technology.

[0003] Based on different display principles, 3D glasses-free display technology can be divided into lenticular lens 3D technology and lenticular lens 3D technology. Lens 3D technology uses a parallax barrier similar to a lenticular lens or a lenticular lens to form a left and right view. Since the left and right views seen by the viewer's two eyes are two images with parallax, these parallaxed left and right views are superimposed and regenerated in the viewer's brain, allowing the viewer to see a 3D display image without glasses. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate, including a substrate and a plurality of pixel units disposed on the substrate, wherein:

[0006] At least one of the multiple pixel units includes multiple sub-pixels of different colors, and at least one of the multiple sub-pixels includes multiple sub-pixels of the same color;

[0007] The anode of the sub-pixel is electrically connected to the driving circuit, which is independent of each other. In a plane perpendicular to the display substrate, the side of the anode of the sub-pixel away from the substrate includes at least a partial surface, and the normal of the partial surface is not perpendicular to the substrate.

[0008] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a substrate and a planarization layer, an anode, an organic light-emitting layer and a cathode sequentially stacked on the substrate. In at least one of the sub-pixel regions, the planarization layer includes a plurality of protrusions corresponding one-to-one with the plurality of sub-pixels.

[0009] The substrate includes multiple driving circuits, and multiple vias are provided on the planarization layer. The anode of the sub-pixel is electrically connected to one of the driving circuits through the vias on the planarization layer.

[0010] In an exemplary embodiment, within at least one of the subpixel regions, the plurality of protrusions are a plurality of spherical protrusions arranged in an array or staggered row by row on the substrate.

[0011] In an exemplary embodiment, within one of the subpixel regions, the radius of the spherical protrusion of one of the crown-shaped protrusions is 300 nanometers to 1800 nanometers.

[0012] In an exemplary embodiment, the anode of at least one sub-pixel is shaped as a first spherical shell covering the planar layer, the organic light-emitting layer of at least one sub-pixel is shaped as a second spherical shell covering the anode, and the anodes of adjacent sub-pixels are isolated from each other by the organic light-emitting layers; within at least one sub-pixel region, the organic light-emitting layers of multiple sub-pixels are continuous.

[0013] In an exemplary embodiment, the distance between the centers of the anodes of adjacent sub-pixels is 2 micrometers to 100 micrometers;

[0014] The radius of the first spherical shell corresponding to the anode of at least one of the sub-pixels is 100 nanometers to 8000 nanometers.

[0015] In an exemplary embodiment, the radian of the first spherical shell corresponding to the anode of at least one of the sub-pixels is π / 6 to 3π / 2.

[0016] In an exemplary embodiment, the anode includes a first conductive layer, a reflective layer, and a second conductive layer stacked together;

[0017] The thicknesses of the first conductive layer and the second conductive layer are 10 nanometers to 50 nanometers, respectively.

[0018] The thickness of the reflective layer is 80 nanometers to 200 nanometers.

[0019] In an exemplary embodiment, within at least one of the subpixel regions, the plurality of protrusions are a plurality of semi-cylindrical protrusions arranged in rows or columns on the substrate.

[0020] In an exemplary embodiment, within one of the subpixel regions, the base radius of one of the semi-cylindrical protrusions is 600 nanometers to 700 nanometers.

[0021] In an exemplary embodiment, the anode of at least one sub-pixel is shaped as a first annular column covering the planar layer, the organic light-emitting layer of at least one sub-pixel is shaped as a second annular column covering the anode, and the anodes of adjacent sub-pixels are isolated from each other by the organic light-emitting layers; within at least one sub-pixel region, the organic light-emitting layers of multiple sub-pixels are continuous.

[0022] In an exemplary embodiment, the distance between the bottom center of the anode of adjacent sub-pixels is 2 micrometers to 100 micrometers;

[0023] The bottom radius of the first annular column corresponding to the anode of at least one of the sub-pixels is 100 nanometers to 8000 nanometers.

[0024] In an exemplary embodiment, the radian of the first annular cylinder corresponding to the anode of at least one of the sub-pixels is π / 6 to 3π / 2.

[0025] In an exemplary embodiment, the anode includes a first conductive layer, a reflective layer, and a second conductive layer stacked together;

[0026] The thicknesses of the first conductive layer and the second conductive layer are 10 nanometers to 50 nanometers, respectively.

[0027] The thickness of the reflective layer is 80 nanometers to 200 nanometers.

[0028] This disclosure also provides a display device, including: a display substrate as described in any of the above embodiments.

[0029] This disclosure also provides a method for preparing a display substrate, the method comprising:

[0030] A substrate is formed, the substrate comprising a plurality of independent driving circuits;

[0031] Multiple pixel units are formed on the substrate. At least one pixel unit includes multiple sub-pixels of different colors. At least one sub-pixel includes multiple sub-pixels of the same color. The anode of the sub-pixel is electrically connected to a driving circuit. In a plane perpendicular to the display substrate, the side of the anode of the sub-pixel away from the substrate includes at least a partial surface. The normal of the partial surface is not perpendicular to the substrate.

[0032] In an exemplary embodiment, a plurality of pixel units are formed on the substrate, including:

[0033] A planarization layer is formed on the substrate. In at least one sub-pixel region, the planarization layer includes a plurality of protrusions corresponding one-to-one with a plurality of sub-pixels, and a plurality of vias are provided on the planarization layer.

[0034] An anode is formed on the planar layer, the anode of the sub-pixel covers the plurality of protrusions, and the anode of at least one sub-pixel is electrically connected to at least one of the driving circuits through a via on the planar layer;

[0035] An organic light-emitting layer and a cathode are formed sequentially on the anode.

[0036] In an exemplary embodiment, the anode includes a first conductive layer, a reflective layer, and a second conductive layer; forming the anode on the planarization layer includes:

[0037] A first conductive thin film is deposited, and a first conductive layer pattern is formed through a first patterning process;

[0038] A reflective thin film is deposited, and a reflective layer pattern is formed through a second patterning process;

[0039] A second conductive thin film is deposited, and a second conductive layer pattern is formed through a third patterning process.

[0040] In an exemplary embodiment, the thickness of the reflective layer is 80 nanometers to 200 nanometers; the thicknesses of the first conductive layer and the second conductive layer are 10 nanometers to 50 nanometers, respectively.

[0041] In an exemplary embodiment, within at least one of the subpixel regions, the plurality of protrusions are a plurality of spherical protrusions arranged in an array or staggered row by row on the substrate.

[0042] In an exemplary embodiment, within at least one of the subpixel regions, the plurality of protrusions are a plurality of semi-cylindrical protrusions arranged in rows or columns on the substrate.

[0043] Other aspects will become clear after reading and understanding the accompanying drawings and embodiments of this disclosure. Attached Figure Description

[0044] Figure 1 A schematic diagram illustrating the principle of 3D glasses-free display using a display substrate;

[0045] Figure 2 This is a schematic diagram of a cross-sectional shape structure of a display substrate according to an embodiment of the present disclosure;

[0046] Figure 3 This is a three-dimensional structural diagram of a display substrate according to an embodiment of the present disclosure;

[0047] Figure 4 for Figure 3 A schematic diagram of the cross-sectional shape of region AA' of the display substrate;

[0048] Figure 5 This is a schematic diagram of another three-dimensional structure of the display substrate according to an embodiment of the present disclosure;

[0049] Figure 6 for Figure 5 A schematic diagram showing the location of the planarization layer vias on the display substrate;

[0050] Figure 7 This is a schematic diagram of the cross-sectional shape of a sub-pixel of the display substrate according to an embodiment of the present disclosure;

[0051] Figure 8 This is a schematic diagram of the cross-sectional shape of a display substrate;

[0052] Figure 9 This is a schematic diagram of the subpixel arrangement structure of the display substrate according to an embodiment of the present disclosure;

[0053] Figure 10 for Figure 9 The diagram shows a schematic of the cross-sectional shape of the BB' region of the display substrate.

[0054] Figure 11 This is a schematic diagram showing the substrate after a planarization layer has been formed, according to an embodiment of this disclosure;

[0055] Figure 12 This is a schematic diagram showing the substrate after anodizing according to an embodiment of the present disclosure;

[0056] Figure 13 This is a schematic diagram of the display substrate after the organic light-emitting layer has been formed, according to an embodiment of this disclosure;

[0057] Figure 14 This is a schematic flowchart illustrating the method for preparing a display substrate according to an embodiment of the present disclosure. Detailed Implementation

[0058] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0059] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, embodiments of this disclosure are not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0060] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0061] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0062] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0063] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0064] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0065] In this specification, "connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0066] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0067] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0068] Naked-eye 3D display technologies mainly include holographic 3D display technology, volumetric 3D display technology, and free-form stereoscopic 3D display technology. Among them, free-form stereoscopic 3D display technology, due to its ability to achieve dynamic, colorful, and wide-field-of-view 3D display effects, has long been considered the naked-eye 3D display technology that is likely to be commercialized the fastest. Free-form stereoscopic 3D display technology includes naked-eye 3D display technologies based on geometric optics, such as cylindrical lens array technology, parallax barrier technology, and microlens array technology. These technologies are mainly based on the principles of rectilinear propagation, reflection, and refraction of light. Through structural design, the emission direction of each pixel in the display screen is changed, projecting images from different perspectives onto different viewpoints, allowing the left and right eyes to see images from different perspectives, thus creating a stereoscopic visual effect.

[0069] Optical screens used for glasses-free 3D displays typically need to display multi-viewpoint images with parallax. Optical separation components separate the multiple viewpoint images displayed on the screen into different viewing zones. Viewers can only observe one viewpoint image within a given viewing zone. When the viewer's left and right eyes are simultaneously in two different viewing zones, the horizontal parallax between the left and right viewpoint images is fused by the brain to generate correct depth information. Glasses-free stereoscopic display technology can interweave and render multi-viewpoint images through spatial multiplexing. This involves first dividing the multiple viewpoint images into multiple strip-shaped sub-images, then interweaving them (selecting a portion of the strip-shaped sub-images from each viewpoint image according to a certain rule) to merge them into a single image for stereoscopic display. Figure 1 As shown.

[0070] Existing display products, especially mobile phone displays, suffer from drawbacks in achieving glasses-free 3D effects, such as low PPI, limited information content, and narrow 3D viewing angles, which can easily cause dizziness and result in a poor user experience. To address these issues in mobile phone glasses-free 3D display technology, RGB pixels can be re-patterned and a multilayered anode structure can be used to achieve high-resolution glasses-free 3D display. However, some display panel technologies, when dividing the RGB pixel anodes, have too many sub-pixel dividing lines and excessive gaps between sub-pixel anodes, resulting in large blank areas and moiré patterns. Furthermore, achieving seamless splicing of sub-pixel anodes using a multilayered anode structure is difficult and subject to numerous technological limitations.

[0071] This disclosure provides a display substrate comprising a plurality of pixel units, wherein at least one pixel unit comprises a plurality of subpixels of different colors, and at least one subpixel comprises a plurality of subpixels of the same color; the anode of at least one subpixel is electrically connected to a driving circuit, the plurality of driving circuits are independent of each other, and in a plane perpendicular to the display substrate, the side of the anode of at least one subpixel away from the substrate includes at least a partial surface, the normal of the partial surface being not perpendicular to the substrate.

[0072] This disclosure also provides, in some embodiments, a display device and a method for manufacturing a display substrate corresponding to the above-described display substrate.

[0073] The display substrate provided in the above embodiments of this disclosure divides pixel units into multiple sub-pixels, at least one sub-pixel into multiple sub-pixels, and at least one sub-pixel has at least a partial surface on the side of its anode away from the substrate. The normal of the partial surface is not perpendicular to the substrate, which reduces etching deviation and thus significantly reduces the anode spacing between adjacent sub-pixels, improving PPI. Furthermore, the display substrate of this disclosure has a small anode step difference between sub-pixels, which enables continuous light emission between sub-pixels, thereby reducing the influence of moiré patterns and improving the naked-eye 3D display effect.

[0074] Figure 2 This is a schematic diagram of the structure of a display substrate according to an embodiment of this disclosure. Figure 2 As shown, in this embodiment, in a plane perpendicular to the display substrate, the display substrate includes a substrate 10 and a planarization layer 20, an anode 30, an organic light-emitting layer 40 and a cathode 50 sequentially stacked on the substrate 10. In at least one sub-pixel region, the planarization layer 20 includes a plurality of protrusions corresponding one-to-one with a plurality of sub-pixels.

[0075] The substrate 10 includes multiple driving circuits (not shown in the figure), and the planarization layer 20 is provided with multiple vias (not shown in the figure). The anode 30 of at least one sub-pixel is electrically connected to a driving circuit through the vias on the planarization layer 20.

[0076] In this embodiment of the disclosure, the number of sub-pixels included in a sub-pixel varies depending on the usage requirements. The more refined the display effect, the more sub-pixels a sub-pixel contains. In an exemplary embodiment, a sub-pixel may include 1*n sub-pixels or n*n sub-pixels, where n is a natural number greater than or equal to 1.

[0077] In one exemplary embodiment, subpixel anodes of the same row and the same view are connected to the same scan line; subpixel anodes of the same column and the same view are connected to the same data line.

[0078] In one exemplary embodiment, the anode holes of subpixels of the same View are arranged on the same straight line.

[0079] In one exemplary embodiment, such as Figure 3 and Figure 4 As shown, within at least one subpixel region, the multiple protrusions are multiple spherical protrusions arranged in an array or staggered row by row on the substrate 10.

[0080] In one exemplary embodiment, the spherical protrusion may be a quarter sphere, a hemisphere, or a spherical protrusion of any other size, or it may be a similar spherical protrusion, such as an arc-shaped protrusion.

[0081] In one exemplary embodiment, within a subpixel region, the radius of a spherical protrusion can be from 300 nanometers to 1800 nanometers. For example, within a subpixel region, the radius of a spherical protrusion can be from 600 nanometers to 700 nanometers, such as 650 nanometers.

[0082] In one exemplary embodiment, the sphere radius of all the crown-shaped protrusions is kept consistent in order to achieve uniformity in display effect and reduce process complexity.

[0083] In one exemplary embodiment, the anode 30 of at least one sub-pixel is shaped as a first spherical shell covering the planarization layer 20, the organic light-emitting layer 40 of at least one sub-pixel is shaped as a second spherical shell covering the anode 30, and the anodes 30 of adjacent sub-pixels are isolated from each other by the organic light-emitting layer 40. In at least one sub-pixel region, the organic light-emitting layers 40 of multiple sub-pixels are continuous.

[0084] The spherical anode 30 of the display substrate in this embodiment can reflect light in all directions, realizing continuous light emission of sub-pixels in a single-layer anode structure, increasing the light-emitting area of ​​the sub-pixels, and minimizing the influence of moiré patterns after passing through the metasurface sub-pixel cylindrical lens; it solves the problems of low visual resolution and discontinuous view in current naked-eye 3D display technology, making the 3D view area larger and closer to the real world.

[0085] In one exemplary embodiment, any one or more of the first spherical shell and the second spherical shell can be a spherical crown-shaped or similar structure. The spherical crown shape can be a quarter sphere, a hemisphere, or a spherical crown shape of any other size. The similar spherical crown shape can be an arc shape, etc.

[0086] In one exemplary embodiment, within a subpixel region, the distance between the centers of the anodes 30 of adjacent subpixels can be from 2 micrometers to 100 micrometers (including high PPI microdisplays and large-size TV displays, etc.). For example, the adjacent distance can be 4 micrometers.

[0087] In theory, within a subpixel region, the smaller the distance between the anodes of adjacent subpixels, provided that they are disconnected, the better for achieving a 3D display effect.

[0088] In one exemplary embodiment, the radius of the first spherical shell corresponding to the anode 30 of at least one sub-pixel can be from 100 nanometers to 8000 nanometers. For example, the radius of the first spherical shell corresponding to the anode 30 of at least one sub-pixel can be 1200 nanometers.

[0089] In one exemplary embodiment, the radian of the first spherical shell corresponding to the anode 30 of at least one sub-pixel is between π / 6 and 3π / 2. For example, the radian of the first spherical shell corresponding to the anode 30 of at least one sub-pixel can be π / 2.

[0090] In another exemplary embodiment, such as Figure 5 As shown, within at least one subpixel region, multiple protrusions are semi-cylindrical protrusions arranged in rows or columns on the substrate 10.

[0091] In one exemplary embodiment, the cross-sectional shape of the semi-cylindrical protrusion can be a semi-circle, a quarter circle, or a crown of any other size.

[0092] In some other exemplary embodiments, within at least one subpixel region, the plurality of protrusions may also be polygonal prism protrusions arranged in rows or columns on the substrate 10, in which case the cross-sectional shape of the polygonal prism protrusions may be a polygon.

[0093] Since a subpixel can include hundreds of subpixels, Figure 4 and Figure 5 Not all bumps are drawn within a subpixel region; only a portion of them are shown. Figure 4 and Figure 5 The number of bumps shown in the diagram does not represent the actual number of bumps contained within a subpixel region.

[0094] In one exemplary embodiment, within a subpixel region, the base radius of a semi-cylindrical protrusion can be 600 nanometers to 700 nanometers. For example, within each subpixel region, the base radius of a semi-cylindrical protrusion can be 650 nanometers.

[0095] In one exemplary embodiment, the anode 30 of at least one sub-pixel is shaped as a first annular column covering the planarization layer 20, the organic light-emitting layer 40 of at least one sub-pixel is shaped as a second annular column covering the anode 30, and the anodes 30 of adjacent sub-pixels are isolated from each other by the organic light-emitting layer 40. In at least one sub-pixel region, the organic light-emitting layers 40 of multiple sub-pixels are continuous.

[0096] In one exemplary embodiment, within a subpixel region, the distance between the centers of the bottom surfaces of the anodes 30 of adjacent subpixels can be from 2 micrometers to 100 micrometers (including high PPI microdisplays and large-size TV displays, etc.). For example, the distance between the centers of the bottom surfaces of the anodes 30 of adjacent subpixels can be 4 micrometers.

[0097] In one exemplary embodiment, the base radius of the annular column corresponding to the anode 30 of at least one sub-pixel can be from 100 nanometers to 8000 nanometers. For example, the base radius of the annular column corresponding to the anode 30 of at least one sub-pixel is 1200 nanometers.

[0098] In one exemplary embodiment, the radian of the annulus corresponding to the anode 30 of at least one sub-pixel is π / 6 to 3π / 2.

[0099] The display substrate of this embodiment is constructed by etching the planarization layer 20 into a semi-cylindrical structure, and then depositing an anode 30 on the planarization layer 20. The material of the anode 30 can be ITO / Ag / ITO. Actual verification results show that after adopting the planarization layer 20 and anode 30 structure of this embodiment, the annular cylindrical anode 30 of the display substrate can reflect light to both sides, and can also achieve continuous light emission of sub-pixels in a single-layer anode structure, increasing the light-emitting area of ​​the sub-pixels. After passing through the metasurface sub-pixel cylindrical lens, the influence of moiré patterns is also minimized. This solves the problems of low visual resolution and discontinuous view in current naked-eye 3D display technology, making the 3D view area larger and closer to the real world.

[0100] In one exemplary embodiment, such as Figure 6As shown, a via 21 is provided on the planarization layer 20. The planarization layer 20 inside the via 21 is etched away, exposing the surface of the drain electrode of the thin-film transistor. The via 21 can be positioned around the perimeter of the semi-cylindrical protrusion. For example... Figure 2 The spherical protrusion shown can have its via 21 positioned around its perimeter.

[0101] In one exemplary embodiment, such as Figure 7 As shown, the anode 30 includes a first conductive layer 31, a reflective layer 32, and a second conductive layer 33 stacked together. The material of the first conductive layer 31 can be indium tin oxide (ITO) or molybdenum (Mo), and the material of the second conductive layer 33 can also be indium tin oxide (ITO) or molybdenum (Mo). The material of the second conductive layer 33 can be the same as or different from that of the first conductive layer 31. The material of the reflective layer 32 can be silver (Ag), molybdenum (Mg), aluminum (Al), or aluminum-neodymium alloy (AlNd), etc. The thicknesses of the first conductive layer 31 and the second conductive layer 33 are 10 nanometers to 50 nanometers, respectively. For example, the thicknesses of the first conductive layer 31 and the second conductive layer 33 can be 15 nanometers each. The thickness of the reflective layer 32 (such as Ag or AlNd, etc.) can be 80 nanometers to 200 nanometers, respectively. For example, the thickness of the reflective layer 32 can be 100 nanometers. The thickness can be set according to actual conditions.

[0102] like Figure 8 As shown, the conventional horizontal anode 30 structure includes a first conductive layer 31, a reflective layer 32, and a second conductive layer 33. The reflective layer 32 is usually made of metal. Since the sides of the reflective layer 32 are exposed, the metal is prone to oxidation and corrosion, resulting in low luminous efficiency and leakage in the OLED device. It is not suitable for sub-pixel anode structures without pixel definition layer (PDL) protection. In addition, the conventional horizontal anode structure has a large anode discontinuity, which can easily cause film layer breakage during the deposition process of the OLED device, making it impossible to achieve continuous light emission between sub-pixels (the light emission brightness in the blank area between sub-pixels is much lower than the intrinsic brightness), and easily producing moiré defects.

[0103] In this embodiment, the display substrate has a planarization layer 20 etched into multiple raised structures. Then, the corresponding sub-pixel anodes 30 can be deposited on the multiple raised structures through a layer-by-layer etching process. The anode 30 can be a multi-layer structure including a first conductive layer 31, a reflective layer 32, and a second conductive layer 33. By etching the first conductive layer 31, the reflective layer 32, and the second conductive layer 33 in a layer-by-layer manner, the conductive layers on both sides can effectively cover the metal of the middle reflective layer 32, preventing oxidation of the metal sides of the middle reflective layer 32. In addition, by etching the planarization layer 20 into raised structures, the critical dimension bias (CD bias) is reduced, the blank area between the sub-pixel anodes 30 is reduced, and moiré defects are eliminated. In this embodiment, the CD bias is ≤0.6 micrometers, and the blank area between the sub-pixel anodes 30 is ≤2.5 micrometers.

[0104] In this embodiment, in order to achieve the coating of the anode 30 onto the spherical flat layer 20, the reflective layer 32 of the anode 30 and the conductive layers on both sides are 80 nanometers to 200 nanometers thick, and the thickness of the conductive layers on both sides can be 10 nanometers to 50 nanometers.

[0105] In one exemplary embodiment, such as Figures 9 to 10 As shown, each pixel unit includes three sub-pixels of different colors, and each sub-pixel is shared by adjacent pixel units. In some possible implementations, each pixel unit may include four, five, or more sub-pixels of different colors, which can be designed and determined according to the actual application environment, and is not limited here.

[0106] In one exemplary embodiment, the three sub-pixels of different colors can be a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.

[0107] In one exemplary embodiment, the sub-pixels in the red sub-pixel R, green sub-pixel G, and blue sub-pixel B are all the same size and are arranged in an array.

[0108] In one exemplary embodiment, such as Figures 9 to 10As shown, each sub-pixel 11 of the red sub-pixel R forms a first microcavity structure, each sub-pixel 12 of the green sub-pixel G forms a second microcavity structure, and each sub-pixel 13 of the blue sub-pixel B forms a third microcavity structure. Each microcavity structure includes an anode 30, a cathode 50, and an organic light-emitting layer 40 disposed between the anode 30 and the cathode 50. The organic light-emitting layer 40 can be formed by vapor deposition. The optical thickness percentage of the organic light-emitting layer 40 of the first microcavity structure in the first microcavity is greater than that of the organic light-emitting layer 40 of the second microcavity structure in the second microcavity, and the optical thickness percentage of the organic light-emitting layer 40 of the second microcavity structure in the second microcavity is greater than that of the organic light-emitting layer 40 of the third microcavity structure in the third microcavity.

[0109] In one exemplary embodiment, such as Figure 10 As shown, in the direction from the anode 30 to the cathode 50, the organic light-emitting layer 40 includes a hole injection layer (HIL) 41, a hole transport layer (HTL) 42, an electron blocking layer (EBL) 43, a light-emitting layer (EML) 44, a hole blocking layer (HBL) 45, an electron transport layer (ETL) 46, and an electron injection layer (EIL) 47 arranged sequentially; wherein, the optical thickness of the microcavity can be adjusted by adjusting the optical thickness of any film layer (e.g., hole injection layer 41) of the organic light-emitting layer 40 between the anode 30 and the cathode 50.

[0110] Figure 10 The organic light-emitting layer 40 shown is merely an example structure, and this disclosure does not limit it. In actual implementation, the structure of the organic light-emitting layer 40 can be designed according to actual needs.

[0111] In practical applications, the substrate 10 may also include structures such as GOA (Gate Driver On Array), EOA (EM GOA), driving circuit and compensation circuit disposed on the substrate.

[0112] In one exemplary embodiment, the cathode 50 is prepared by vapor deposition or sputtering, forming a film over the entire surface, and the morphology of the cathode 50 is the same as the undulations of the surface of the anode 30.

[0113] The structure of a display substrate is illustrated below using an example of the fabrication process of the display substrate. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying and spin coating; and etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. The phrase "the orthographic projection of A includes the orthographic projection of B" in this disclosure means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0114] (1) A driving structure layer pattern is fabricated on the substrate 10. The driving structure layer includes multiple gate lines and multiple data lines. The multiple gate lines and multiple data lines intersect perpendicularly to define multiple pixel units arranged in an array or staggered row by row. Each pixel unit includes at least 3 sub-pixels, each sub-pixel includes multiple sub-pixels, and each sub-pixel includes a thin-film transistor (TFT). In this embodiment, a pixel unit includes 3 sub-pixels, namely a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, this embodiment is also applicable to the case where a pixel unit includes 4 or more sub-pixels. In this embodiment, the fabrication process may include, for example, cleaning the substrate 10, then fabricating an active layer on the substrate 10 through a patterning process, subsequently forming a first insulating layer covering the active layer, forming gate lines and gate electrodes on the first insulating layer, subsequently forming a second insulating layer covering the gate lines and gate electrodes, and forming data lines, source electrodes, and drain electrodes on the second insulating layer. The thin-film transistor can be a bottom-gate structure or a top-gate structure, and can be an amorphous silicon (a-Si) thin-film transistor, a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor; no specific limitation is made here. In actual implementation, the substrate 10 can be made of high light transmittance materials such as glass, quartz, polyolefin resin, polyethylene naphthalate resin, polyimide resin, polyethylene terephthalate plastic, phenolic resin, or a surface-treated polymer soft film.

[0115] (2) A first planar thin film is coated on the substrate 10 on which the aforementioned pattern is formed, forming a planar (PLN) layer 20 covering the entire flexible substrate 10, and then... Figure 6 and Figure 11 The planarization layer 20 is etched into multiple spherical crown-shaped protrusions arranged in an array or staggered row by row (or semi-cylindrical protrusions arranged in rows or columns). Vias 21 are formed on the planarization layer 20 through a patterning process. The planarization layer 20 inside the via 21 is etched away, exposing the surface of the drain electrode of the thin film transistor. The via 21 can be located around the spherical crown-shaped protrusions or semi-cylindrical protrusions.

[0116] (3) An anode 30 pattern is formed on the substrate 10 on which the aforementioned pattern is formed, and combined with Figure 7 and Figure 12 The formation of the anode 30 pattern includes:

[0117] A first conductive film is deposited on the substrate 10 on which the aforementioned pattern is formed. A layer of photoresist is coated on the first conductive film. The photoresist is exposed using a monochrome mask. An unexposed area is formed at the location of the first conductive layer 31, and a fully exposed area is formed at other locations. The photoresist in the fully exposed area is removed by development. Then the first conductive film in the fully exposed area is etched away. After the photoresist is stripped off, the pattern of the first conductive layer 31 is formed.

[0118] A reflective film is deposited on the substrate 10 on which the aforementioned pattern is formed. A layer of photoresist is coated on the reflective film. The photoresist is exposed using a monochrome mask. An unexposed area is formed at the location of the reflective layer 32, and a fully exposed area is formed at other locations. The photoresist in the fully exposed area is removed by development. Then the reflective film in the fully exposed area is etched away. After the photoresist is stripped off, the pattern of the reflective layer 32 is formed.

[0119] A second conductive film is deposited on the substrate 10 on which the aforementioned pattern is formed. A layer of photoresist is coated on the second conductive film. The photoresist is exposed using a monochrome mask. An unexposed area is formed at the location of the second conductive layer 33, and a fully exposed area is formed at other locations. The photoresist in the fully exposed area is removed by development. Then, the second conductive film in the fully exposed area is etched away. After the photoresist is stripped off, the pattern of the second conductive layer 33 is formed.

[0120] The first conductive layer 31 of each sub-pixel is connected to the drain electrode of the thin-film transistor in that sub-pixel. In this embodiment, the display substrate achieves excellent coverage of the intermediate reflective layer 32 metal by etching the anode pattern in layers and steps, thus preventing oxidation of the intermediate reflective layer 32 metal sides.

[0121] (4) A pixel definition layer pattern is formed on the substrate 10 on which the aforementioned pattern is formed. Forming the pixel definition layer pattern includes: coating a pixel defining film on the substrate 10 on which the aforementioned pattern is formed; exposing and developing the pixel defining film using a monochrome mask to form the pixel definition layer pattern; the pixel definition layer includes a plurality of spaced-apart opening regions, each opening region containing a sub-pixel. The pixel definition layer is used to define a light-emitting region within each sub-pixel region, the light-emitting region exposing the anode 30 of a plurality of sub-pixels. In this embodiment, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate.

[0122] (5) An organic light-emitting layer 40 pattern is formed on the substrate 10 on which the aforementioned pattern is formed, combined with Figure 10 and Figure 13 The formation of the organic light-emitting layer 40 pattern includes: sequentially forming a hole injection layer 41 and a hole transport layer (HTL) 42 pattern on the substrate 10 on which the aforementioned pattern is formed; sequentially forming an electron blocking layer 43 and a light-emitting layer 44 pattern on the hole transport layer 42 of multiple sub-pixels; and sequentially forming a hole blocking layer 45, an electron transport layer 46 and an electron injection layer 47 on the substrate 10 on which the light-emitting layer 44 pattern is formed.

[0123] (6) A cathode 50 pattern is formed on the substrate 10 on which the aforementioned pattern is formed. Forming the cathode 50 pattern includes: depositing a cathode metal thin film on the substrate 10 on which the aforementioned pattern is formed, and patterning the cathode metal thin film using a patterning process to form the cathode 50 pattern, such as... Figure 2 As shown. In this embodiment, the cathode 50 is prepared by vapor deposition or sputtering, forming a film over the entire surface. The morphology of the cathode 50 is the same as the surface undulations of the anode 30. Since the OLED panel in this embodiment is a top-emitting structure, the cathode 50 can be a transmission electrode or a semi-transmissive electrode. The transmission electrode can be one of the following metal materials: magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), lithium (Li), or an alloy of the above metals. The semi-transmissive electrode can be a semi-transmissive metal material.

[0124] (7) A pattern of encapsulation layer 70 is formed on the substrate 10 on which the aforementioned pattern is formed, such as Figure 10 As shown. Forming the encapsulation layer 70 pattern includes: coating an organic material film, such as tetrafluoroethylene (TFE), onto the substrate 10 on which the aforementioned pattern is formed, with the film covering the entire substrate 10, forming an encapsulation layer 70 to protect the OLED panel, thus completing the OLED substrate structure of this embodiment.

[0125] In one exemplary embodiment, such as Figure 10As shown, a capping layer (CPL) is also disposed between the encapsulation layer 70 and the cathode 50, covering the cathode 50 to improve the light extraction efficiency. The capping layer can be a double-layer structure, including a first capping layer (CPL1) 61 and a second capping layer (CPL2) 62. CPL1 is made of a high-refractive-index material with a refractive index between 1.5 and 2.3, while CPL2 is made of a low-refractive-index material with a refractive index between 1.3 and 1.7. The combination of high and low refractive indices of CPL1 and CPL2 can better achieve light extraction.

[0126] As can be seen from the above preparation process, the display substrate provided in this embodiment divides the pixel unit into multiple sub-pixels, and each sub-pixel into multiple sub-pixels. The cross-sectional shape of the anode 30 of each sub-pixel is designed as a convex arc surface, which reduces etching deviation and thus significantly reduces the anode spacing between adjacent sub-pixels, improving PPI. Moreover, the anode step difference of the convex arc surface is small, which can realize continuous light emission between sub-pixels, thereby reducing the influence of moiré patterns and improving the naked-eye 3D display effect. The preparation process is simple, the production efficiency is high, and it has the advantages of low production cost and high yield, and has good application prospects.

[0127] Although the display substrate in this embodiment is described with a top-emitting structure, the solution in this embodiment is also applicable to bottom-emitting structures or double-sided emitting structures, and is also applicable to large-size or small-size OLED panels.

[0128] In subsequent processes, a sealing process is used to form a cover plate, which is then fixed to the substrate 10 with sealant. Since the substrate 10, the cover plate, and the sealant together form a closed space, they provide protection against water and oxygen, thus significantly extending the lifespan of the display substrate.

[0129] This disclosure also provides a method for fabricating a display substrate, the display substrate including a plurality of pixel units, at least one of the pixel units including a plurality of sub-pixels of different colors, and at least one of the sub-pixels including a plurality of sub-pixels of the same color. Figure 14 As shown, the preparation method includes:

[0130] S1. Forming a substrate, wherein the substrate includes multiple independent driving circuits;

[0131] S2. A plurality of pixel units are formed on the substrate. At least one of the pixel units includes a plurality of sub-pixels of different colors. At least one of the sub-pixels includes a plurality of sub-pixels of the same color. The anode of the sub-pixel is electrically connected to the driving circuit. In a plane perpendicular to the display substrate, the side of the anode of the sub-pixel away from the substrate includes at least a partial surface. The normal of the partial surface is not perpendicular to the substrate.

[0132] In one exemplary embodiment, a plurality of pixel units are formed on the substrate, including:

[0133] S21. A planarization layer is formed on the substrate. In at least one sub-pixel region, the planarization layer includes a plurality of protrusions corresponding one-to-one with a plurality of sub-pixels. A plurality of vias are provided on the planarization layer.

[0134] S22. An anode is formed on the planarization layer, the anode of the sub-pixel is covered on a plurality of protrusions, and the anode of at least one of the sub-pixels is electrically connected to at least one of the driving circuits through a via on the planarization layer.

[0135] S23. An organic light-emitting layer and a cathode are formed sequentially on top of the anode.

[0136] In one exemplary embodiment, the anode includes a first conductive layer, a reflective layer, and a second conductive layer; forming the anode on the planarization layer includes:

[0137] A first conductive thin film is deposited, and a first conductive layer pattern is formed through a first patterning process;

[0138] A reflective thin film is deposited, and a reflective layer pattern is formed through a second patterning process;

[0139] A second conductive thin film is deposited, and a second conductive layer pattern is formed through a third patterning process.

[0140] In one exemplary embodiment, the thickness of the reflective layer is 80 nanometers to 200 nanometers; the thicknesses of the first conductive layer and the second conductive layer are 10 nanometers to 50 nanometers, respectively.

[0141] In one exemplary embodiment, within at least one subpixel region, the plurality of protrusions are multiple crown-shaped protrusions arranged in an array or staggered row by row on the substrate.

[0142] In one exemplary embodiment, within at least one of the subpixel regions, the plurality of protrusions are a plurality of semi-cylindrical protrusions arranged in rows or columns on the substrate.

[0143] This embodiment provides a method for fabricating a display substrate. By dividing a pixel unit into multiple sub-pixels, and each sub-pixel into multiple sub-pixels, the cross-sectional shape of the anode of each sub-pixel is designed as a convex arc surface, which reduces etching deviation and thus significantly reduces the anode spacing between adjacent sub-pixels, improving PPI. Furthermore, the small anode step difference of the convex arc surface enables continuous light emission between sub-pixels, thereby reducing the influence of moiré patterns and improving the naked-eye 3D display effect. The fabrication process is simple, has high production efficiency, and has advantages such as low production cost and high yield, showing good application prospects.

[0144] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0145] In one exemplary embodiment, the display device may include various types. For example, based on the direction of light emission, the display device may be classified as a top-emitting OLED device or a bottom-emitting OLED device. In a top-emitting OLED device, the anode grown on the substrate is set as an opaque electrode, and the cathode at the top is set as a transparent electrode or a semi-transparent electrode. When a voltage is applied, light is emitted from the top cathode. In contrast, in a bottom-emitting OLED device, the anode grown on the substrate is set as a transparent electrode or a semi-transparent electrode, and the cathode at the top is set as an opaque electrode. When a voltage is applied, light is emitted from the bottom anode.

[0146] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a substrate and a plurality of pixel units disposed on the substrate, wherein: At least one of the multiple pixel units includes multiple sub-pixels of different colors, and at least one of the multiple sub-pixels includes multiple sub-pixels of the same color; The anode of the sub-pixel is electrically connected to the driving circuit, and the driving circuits are independent of each other. In a plane perpendicular to the display substrate, the side of the anode of the sub-pixel away from the substrate includes at least a partial surface, and the normal of the partial surface is not perpendicular to the substrate. Wherein, in a plane perpendicular to the display substrate, the display substrate includes a substrate and a planarization layer, an anode, an organic light-emitting layer and a cathode stacked sequentially on the substrate, and in at least one of the sub-pixel regions, the planarization layer includes a plurality of protrusions corresponding one-to-one with the plurality of sub-pixels; Wherein, in at least one of the sub-pixel regions, the plurality of protrusions are a plurality of spherical protrusions arranged in an array or staggered row by row on the substrate; Wherein, the anode of at least one of the sub-pixels is shaped as a first spherical shell covering the planar layer, the organic light-emitting layer of at least one of the sub-pixels is shaped as a second spherical shell covering the anode, and the anodes of adjacent sub-pixels are isolated from each other by the organic light-emitting layer; in at least one of the sub-pixel regions, the organic light-emitting layers of multiple sub-pixels are continuous.

2. The display substrate according to claim 1, wherein, The substrate includes multiple driving circuits, and multiple vias are provided on the planarization layer. The anode of the sub-pixel is electrically connected to one of the driving circuits through the vias on the planarization layer.

3. The display substrate according to claim 2, wherein, Within one of the subpixel regions, the radius of the sphere of one of the spherical protrusions is 300 nanometers to 1800 nanometers.

4. The display substrate according to claim 2, wherein, The distance between the centers of the anodes of adjacent sub-pixels is 2 micrometers to 100 micrometers; The radius of the first spherical shell corresponding to the anode of at least one of the sub-pixels is 100 nanometers to 8000 nanometers.

5. The display substrate according to claim 2, wherein, The radian of the first spherical shell corresponding to the anode of at least one of the sub-pixels is π / 6 to 3π / 2.

6. The display substrate according to any one of claims 1 to 5, wherein, The anode includes a first conductive layer, a reflective layer, and a second conductive layer stacked together. The thicknesses of the first conductive layer and the second conductive layer are 10 nanometers to 50 nanometers, respectively. The thickness of the reflective layer is 80 nanometers to 200 nanometers.

7. A display substrate, comprising a substrate and a plurality of pixel units disposed on the substrate, wherein: At least one of the multiple pixel units includes multiple sub-pixels of different colors, and at least one of the multiple sub-pixels includes multiple sub-pixels of the same color; The anode of the sub-pixel is electrically connected to the driving circuit, and the driving circuits are independent of each other. In a plane perpendicular to the display substrate, the side of the anode of the sub-pixel away from the substrate includes at least a partial surface, and the normal of the partial surface is not perpendicular to the substrate. Wherein, in a plane perpendicular to the display substrate, the display substrate includes a substrate and a planarization layer, an anode, an organic light-emitting layer and a cathode stacked sequentially on the substrate, and in at least one of the sub-pixel regions, the planarization layer includes a plurality of protrusions corresponding one-to-one with the plurality of sub-pixels; Wherein, in at least one of the sub-pixel regions, the plurality of protrusions are a plurality of semi-cylindrical protrusions arranged in rows or columns on the substrate; Wherein, the anode of at least one of the sub-pixels is shaped as a first annular column covering the planar layer, the organic light-emitting layer of at least one of the sub-pixels is shaped as a second annular column covering the anode, and the anodes of adjacent sub-pixels are isolated from each other by organic light-emitting layers; in at least one of the sub-pixel regions, the organic light-emitting layers of multiple sub-pixels are continuous.

8. The display substrate according to claim 7, wherein, Within one of the subpixel regions, the base radius of one of the semi-cylindrical protrusions is 600 nanometers to 700 nanometers.

9. The display substrate according to claim 7, wherein, The distance between the centers of the bottom surfaces of the anodes of adjacent sub-pixels is 2 micrometers to 100 micrometers; The bottom radius of the first annular column corresponding to the anode of at least one of the sub-pixels is 100 nanometers to 8000 nanometers.

10. The display substrate according to claim 7, wherein, The radian of the first annular cylinder corresponding to the anode of at least one of the sub-pixels is π / 6 to 3π / 2.

11. The display substrate according to any one of claims 7 to 10, wherein, The anode includes a first conductive layer, a reflective layer, and a second conductive layer stacked together. The thicknesses of the first conductive layer and the second conductive layer are 10 nanometers to 50 nanometers, respectively. The thickness of the reflective layer is 80 nanometers to 200 nanometers.

12. A display device, comprising: The display substrate as described in any one of claims 1 to 11.

13. A method for preparing a display substrate, the method comprising: A substrate is formed, the substrate comprising a plurality of independent driving circuits; Multiple pixel units are formed on the substrate. At least one pixel unit includes multiple sub-pixels of different colors. At least one sub-pixel includes multiple sub-pixels of the same color. The anode of the sub-pixel is electrically connected to a driving circuit. In a plane perpendicular to the display substrate, the side of the anode of the sub-pixel away from the substrate includes at least a partial surface. The normal of the partial surface is not perpendicular to the substrate. Among them, a plurality of pixel units are formed on the substrate, including: A planarization layer is formed on the substrate, and in at least one sub-pixel region, the planarization layer includes a plurality of protrusions corresponding one-to-one with a plurality of sub-pixels; An anode is formed on the flat layer, and the anode of the sub-pixel covers the plurality of protrusions; An organic light-emitting layer and a cathode are sequentially formed on the anode; Wherein, in at least one of the sub-pixel regions, the plurality of protrusions are a plurality of spherical protrusions arranged in an array or staggered row by row on the substrate; Wherein, the anode of at least one of the sub-pixels is shaped as a first spherical shell covering the planar layer, the organic light-emitting layer of at least one of the sub-pixels is shaped as a second spherical shell covering the anode, and the anodes of adjacent sub-pixels are isolated from each other by the organic light-emitting layer; in at least one of the sub-pixel regions, the organic light-emitting layers of multiple sub-pixels are continuous.

14. The preparation method according to claim 13, wherein, The planarization layer has multiple vias; the anode of at least one sub-pixel is electrically connected to at least one driving circuit through the vias on the planarization layer.

15. The preparation method according to claim 14, wherein, The anode includes a first conductive layer, a reflective layer, and a second conductive layer; the anode is formed on the planarization layer, including: A first conductive thin film is deposited, and a first conductive layer pattern is formed through a first patterning process; A reflective thin film is deposited, and a reflective layer pattern is formed through a second patterning process; A second conductive thin film is deposited, and a second conductive layer pattern is formed through a third patterning process.

16. The preparation method according to claim 15, wherein, The thickness of the reflective layer is 80 nanometers to 200 nanometers; the thicknesses of the first conductive layer and the second conductive layer are 10 nanometers to 50 nanometers, respectively.

Images