Solar cell, method for manufacturing same, photovoltaic module, and photovoltaic system

Abstract

The present invention relates to a solar cell, a manufacturing method thereof, a photovoltaic module, and a photovoltaic system. The solar cell includes a substrate, a first passivation contact layer and a second passivation contact layer, a first passivation film layer and a first dielectric layer, and a first electrode. The first passivation film layer is laminated on the first passivation contact layer, in the insulating isolation groove, and on the second passivation contact layer. First through grooves are formed in the regions of the first passivation film layer corresponding to the respective first polysilicon doped conductive layers. One end of the first electrode passes through the first through groove and makes an ohmic contact with the first polysilicon doped conductive layer; the first dielectric layer covers the first passivation film layer and covers a first region on the first passivation contact layer; wherein, the first region is the region between the side wall of the first through groove and the first electrode on the surface of the first passivation contact layer exposed from the first through groove. The solar cell, the manufacturing method thereof, the photovoltaic module, and the photovoltaic system in the present invention have less recombination loss and higher efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly to a solar cell, a manufacturing method thereof, a photovoltaic module, and a photovoltaic system. Background Art

[0002] IBC (Interdigitated Back Contact) cells emerged in the 1970s. Local phosphorus and boron diffusions are respectively carried out on the back of the cells to form finger-like cross-arranged P regions and N regions; the positive and negative electrodes of IBC cells are both on the back of the cells, and there is no metal shading on the front, which greatly improves the optical absorption of the cells. TOPCon (Tunnel Oxide Passivated Contact) cells are a new type of silicon solar cell proposed by the Fraunhofer Institute in Germany in 2013. It uses a tunneling oxide layer stacked with a doped polysilicon layer to form a passivated contact structure, effectively reducing the recombination rate between the silicon wafer surface and the metal contact. Currently, a new type of TBC cell that combines TOPCon and IBC technologies has become a hot topic. After forming the aluminum oxide passivation layer and silicon nitride antireflection layer on the back of the TBC cell, grooves are generally opened by laser, and electrode paste is printed in the opened grooves, and electrodes are formed by sintering. However, in the related technology of TBC cells, there are often problems of poor passivation effect on the back of the cell and large recombination loss, resulting in low efficiency of the solar cell. Summary of the Invention

[0003] Based on this, it is necessary to provide a solar cell, a manufacturing method thereof, a photovoltaic module, and a photovoltaic system with less recombination loss and higher efficiency.

[0004] In the first aspect of the embodiments of the present application, a solar cell is provided, including a substrate, a first passivated contact layer and a second passivated contact layer, a first passivation film layer and a first dielectric layer, and a first electrode;

[0005] The first passivated contact layer and the second passivated contact layer are alternately arranged on the first surface of the substrate. The first passivated contact layer includes a first polysilicon doped conductive layer, and the second passivated contact layer includes a second polysilicon doped conductive layer. The doping concentration of the second polysilicon doped conductive layer is greater than that of the first polysilicon doped conductive layer, and the doping type is opposite to that of the first polysilicon doped conductive layer; an insulating isolation groove is formed between each adjacent first passivated contact layer and second passivated contact layer;

[0006] The first passivation film layer is laminated on the first passivated contact layer, in the insulating isolation groove, and the second passivated contact layer. A first through groove is opened in the region of the first passivation film layer corresponding to each first polysilicon doped conductive layer, and one end of the first electrode passes through the first through groove to be in ohmic contact with the first polysilicon doped conductive layer;

[0007] The first dielectric layer covers the first passivation film layer and covers the first area on the first passivation contact layer;

[0008] The first region is a region on the surface of the first passivation contact layer exposed from the first through-groove and located between the sidewall of the first through-groove and the first electrode.

[0009] In one embodiment, a difference ΔH between a width of the first through-groove along the first direction and a width of the first electrode along the first direction satisfies:

[0010] 15μm≤ΔH≤25μm;

[0011] The first direction is an alternating arrangement direction of the first passivation contact layer and the second passivation contact layer, and the first direction is parallel to the first surface.

[0012] In one embodiment, the first through groove is arranged to extend along the second direction;

[0013] The second direction is an extending direction of the first electrode, and the second direction is parallel to the first surface.

[0014] In one embodiment, a portion of the first dielectric layer located in the first through groove is provided with a through first electrode accommodating groove, and an end of the first electrode facing the substrate is located in the first electrode accommodating groove and is in close contact with two side walls of the first electrode accommodating groove along the first direction;

[0015] The first direction is an alternating arrangement direction of the first passivation contact layer and the second passivation contact layer, and the first direction is parallel to the first surface.

[0016] In one embodiment, the thickness of the first dielectric layer is 50 nm-120 nm; and / or

[0017] The thickness of the first passivation film layer is 5nm-12nm.

[0018] In one embodiment, the solar cell further includes a second electrode, the second electrode penetrates the first dielectric layer and the first passivation film layer, and is in ohmic contact with the second polysilicon doped conductive layer;

[0019] The first passivation contact layer further comprises a first transparent conductive oxide layer, the first transparent conductive oxide layer is arranged on a side of the first polysilicon doped conductive layer away from the substrate, and the first electrode is in ohmic contact with the first transparent conductive oxide layer;

[0020] The second passivation contact layer further includes a second transparent conductive oxide layer, which is disposed on a side of the second polysilicon-doped conductive layer away from the substrate, and the second electrode is in ohmic contact with the second transparent conductive oxide layer.

[0021] In one embodiment, the first transparent conductive oxide layer is located between the first polysilicon doped conductive layer and the first passivation film layer; the second transparent conductive oxide layer is located between the second polysilicon doped conductive layer and the first passivation film layer;

[0022] The first region is located on the surface of the first transparent conductive oxide layer facing away from the substrate.

[0023] In one embodiment, the thickness of the first transparent conductive oxide layer is 30 nm - 150 nm.

[0024] In one embodiment, the substrate includes a second surface opposite to the first surface;

[0025] The solar cell further includes a second passivation film layer and a second dielectric layer stacked in sequence on the second surface of the substrate;

[0026] The thickness of the second dielectric layer is 180 nm - 220 nm;

[0027] The thickness of the second passivation film layer is 11 nm - 15 nm.

[0028] The second aspect of the embodiments of the present application provides a method for manufacturing a solar cell, including:

[0029] Providing a substrate, the substrate includes a substrate, a first passivation contact layer and a second passivation contact layer, the first passivation contact layer and the second passivation contact layer are alternately arranged on the first surface of the substrate, the first passivation contact layer includes a first polysilicon doped conductive layer, the second passivation contact layer includes a second polysilicon doped conductive layer, the doping concentration of the second polysilicon doped conductive layer is greater than that of the first polysilicon doped conductive layer, and the doping type is opposite to that of the first polysilicon doped conductive layer; an insulating isolation groove is formed between each adjacent first passivation contact layer and second passivation contact layer;

[0030] Forming a first passivation film layer on the first passivation contact layer, in the insulating isolation groove and on the second passivation contact layer, and opening a first through groove in the region of the first passivation film layer corresponding to each first polysilicon doped conductive layer;

[0031] Forming a first dielectric layer on the first passivation film layer, so that the first dielectric layer covers the first passivation film layer and covers the surface of the first passivation contact layer exposed from the first through groove;

[0032] Forming a first electrode on the part of the first dielectric layer located in the first through groove, and making the first electrode penetrate the first dielectric layer to have an ohmic contact with the first polysilicon doped conductive layer.

[0033] In one embodiment, the step of opening a first through groove in the region of the first passivation film layer corresponding to each first polysilicon doped conductive layer specifically includes:

[0034] A first through - groove is formed in the first passivation film layer by means of a photolithography process.

[0035] In one embodiment, before the step of forming the first passivation film layer on the first passivation contact layer, within the insulating isolation groove, and on the second passivation contact layer, further included are:

[0036] A matte structure and a second passivation film layer are formed on the second surface of the substrate of the base, and the second surface is disposed opposite to the first surface.

[0037] In one embodiment, the step of forming the first dielectric layer on the first passivation film specifically includes:

[0038] A second dielectric layer is formed on the second passivation film layer, the first dielectric layer is formed on the first passivation film layer, and the first dielectric layer is deposited and covers the first through - groove.

[0039] In one embodiment, after the step of forming the first passivation film layer and the second passivation film layer, before the step of forming a first through - groove in each region of the first passivation film layer corresponding to each first polysilicon - doped conductive layer, further included is: annealing the first passivation film layer and the second passivation film layer to activate the first passivation film layer and the second passivation film layer.

[0040] In one embodiment, after forming the matte structure, before forming the second passivation film layer and the first passivation film layer, further included is:

[0041] A first transparent conductive oxide layer is formed on the first polysilicon - doped conductive layer, and a second transparent conductive oxide layer is formed on the second polysilicon - doped conductive layer.

[0042] In one embodiment, after the step of forming the first electrode, further included is:

[0043] A second electrode receiving groove penetrating through is formed in the regions of the first dielectric layer and the first passivation film layer corresponding to the second polysilicon - doped conductive layer, a second electrode is formed in the second electrode receiving groove, and the second electrode is brought into contact with the second transparent conductive oxide layer.

[0044] In one embodiment, the outermost film layer of the first passivation contact layer facing away from the substrate is the first polysilicon - doped conductive layer;

[0045] The step of forming a first electrode on the portion of the first dielectric layer within the first through - groove and making the first electrode penetrate the first dielectric layer to have an ohmic contact with the first polysilicon - doped conductive layer includes:

[0046] A first paste is printed on the portion of the first dielectric layer within the first through - groove and sintered, such that the first paste penetrates the first dielectric layer and contacts the first polysilicon - doped conductive layer.

[0047] The third aspect of the embodiments of the present application provides a photovoltaic module, which includes at least one battery string, and the battery string includes at least two of the above-mentioned solar cells.

[0048] The fourth aspect of the embodiments of the present application provides a photovoltaic system, which includes the above-mentioned photovoltaic module.

[0049] Advantages of the above-mentioned solar cell, its manufacturing method, photovoltaic module and photovoltaic system:

[0050] By covering the first region on the first passivation contact layer with the first dielectric layer, where the first region is the region between the side wall of the first through groove and the first electrode on the surface of the first passivation contact layer exposed from the first through groove. In this way, in the surface of the first passivation contact layer exposed from the first through groove, except for the region in contact with the first electrode, the entire region is covered by the first dielectric layer, and there is no situation where the first passivation contact layer is directly exposed, resulting in a better passivation effect, reducing recombination losses, and improving the efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic structural diagram of the solar cell provided by the embodiments of the present application;

[0052] Figure 2 It is a schematic diagram of another structure of the solar cell provided by the embodiments of the present application;

[0053] Figure 3 It is a schematic flowchart of the manufacturing method of the solar cell provided by the embodiments of the present application;

[0054] Figure 4 It is a schematic structural diagram of the substrate formed in the manufacturing method of the solar cell provided by the embodiments of the present application;

[0055] Figure 5 It is a schematic structural diagram of forming the first through groove in the manufacturing method of the solar cell provided by the embodiments of the present application;

[0056] Figure 6 It is a schematic structural diagram of the solar cell formed in the manufacturing method of the solar cell provided by the embodiments of the present application.

[0057] Description of the reference numerals in the drawings:

[0058] 100, solar cell; 101, substrate; 102, wafer;

[0059] 10. First passivation contact layer; 11. First tunneling oxide layer; 12. First polysilicon doped conductive layer; 20. Second passivation contact layer; 21. Second tunneling oxide layer; 22. Second polysilicon doped conductive layer; 30. First passivation film layer; 31. First through groove; 40. First dielectric layer; 41. First electrode receiving groove; 42. Second electrode receiving groove; 50. First electrode; 60. Second electrode; 70. First transparent conductive oxide layer; 80. Second transparent conductive oxide layer; 90. Second passivation film layer; 91. Second dielectric layer; 92. Textured structure.

[0060] A. Insulating isolation groove; F. First surface; S. Second surface; D. First direction; E. First region. Detailed implementation manners

[0061] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following will describe the detailed implementation manners of the present invention with reference to the accompanying drawings. Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0062] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0063] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0064] In the present invention, unless otherwise clearly specified or defined, the terms "mounted", "connected", "coupled", "fixed", etc. shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0065] In the present invention, unless otherwise clearly specified or defined, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0066] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for the purpose of illustration and do not represent the only implementation.

[0067] The solar cell and its manufacturing method, photovoltaic module and photovoltaic system according to the embodiments of the present application will be described below with reference to the accompanying drawings.

[0068] The solar cell 100 provided by the embodiment of the present application includes a substrate 101, a first passivation contact layer 10 and a second passivation contact layer 20, a first passivation film layer 30 and a first dielectric layer 40, and a first electrode 50.

[0069] The first passivation contact layer 10 and the second passivation contact layer 20 are alternately arranged on the first surface F of the substrate 101. The first passivation contact layer 10 includes a first polysilicon doped conductive layer 12, and the second passivation contact layer 20 includes a second polysilicon doped conductive layer 22. The doping concentration of the second polysilicon doped conductive layer 22 is greater than that of the first polysilicon doped conductive layer 12, and the doping type is opposite to that of the first polysilicon doped conductive layer 12; an insulating isolation groove A is formed between each adjacent first passivation contact layer 10 and second passivation contact layer 20.

[0070] The first passivation film layer 30 is stacked on the first passivation contact layer 10, inside the insulating isolation groove A, and the second passivation contact layer 20. First through grooves 31 are formed in the regions of the first passivation film layer 30 corresponding to the respective first polysilicon doped conductive layers 12. One end of the first electrode 50 passes through the first through groove 31 and is in ohmic contact with the first polysilicon doped conductive layer 12.

[0071] The first dielectric layer 40 covers the first passivation film layer 30 and covers the first region E on the first passivation contact layer 10. Here, the first region E is the region between the sidewall of the first through groove 31 and the first electrode 50 in the surface of the first passivation contact layer 10 exposed from the first through groove 31, as Figure 1 shown by the dashed line.

[0072] In the manufacturing process of the related art, in order to increase the contact between the electrode paste and the polysilicon doped conductive layer and reduce the contact resistance, grooves are often formed in the back passivation film layer of the solar cell, and the electrode paste is printed in the grooves to form an electrode. However, since the electrode paste cannot fill the formed grooves completely, part of the polysilicon doped conductive layer is exposed, resulting in poor passivation effect, increased recombination loss, and thus reduced efficiency of the solar cell.

[0073] In the embodiment of the present application, the first dielectric layer 40 covers the first region E on the first passivation contact layer 10. Here, the first region E is the region between the sidewall of the first through groove 31 and the first electrode 50 in the surface of the first passivation contact layer 10 exposed from the first through groove 31. In this way, in the surface of the first passivation contact layer 10 exposed from the first through groove 31, except for the region in contact with the first electrode 50, the remaining regions are all covered by the first dielectric layer 40, and there is no situation where the first passivation contact layer 10 is directly exposed, resulting in a good passivation effect, reduced recombination loss, and improved efficiency of the solar cell 100.

[0074] Here, the first polysilicon doped conductive layer 12 may be doped with P-type elements, and the second polysilicon doped conductive layer 22 may be doped with N-type elements.

[0075] The first passivation film layer 30 may be a film layer such as aluminum oxide that plays a passivation role. The first dielectric layer 40 is an antireflection layer. The first dielectric layer 40 may be a film layer such as silicon nitride that plays a passivation role. Both the first passivation film layer 30 and the first dielectric layer 40 may be single-layer or multi-layer film structures.

[0076] The first passivation contact layer 10 and the second passivation contact layer 20 are alternately arranged on the first surface F of the substrate 101, and for example, they can be alternately arranged in a certain direction parallel to the first surface F. The first passivation contact layer 10 may further include a first tunneling oxide layer 11, and the second passivation contact layer 20 may further include a second tunneling oxide layer 21. The first tunneling oxide layer 11 and the first polysilicon-doped conductive layer 12 are sequentially stacked on the first surface F, and the second tunneling oxide layer 21 and the second polysilicon-doped conductive layer 22 are sequentially stacked on the first surface F.

[0077] In addition, the insulating isolation groove A means that the adjacent first passivation contact layer 10 and the second passivation contact layer 20 are insulated from each other by the insulating isolation groove A.

[0078] In Figure 1 In the illustrated example, the outermost layer of the first passivation contact layer 10 facing away from the substrate 101 is the first polysilicon-doped conductive layer 12. Therefore, the surface of the first passivation contact layer 10 exposed from the first through groove 31 is also the surface of the first polysilicon-doped conductive layer 12 exposed from the first through groove 31. Specifically, it refers to the region corresponding to the first through groove 31 in the surface of the first polysilicon-doped conductive layer 12 facing away from the substrate 101. In this region, the region between the side wall of the first through groove 31 and the first electrode 50 is the first region E.

[0079] The first dielectric layer 40 covers the first region E on the first polysilicon-doped conductive layer 12, which means that the first dielectric layer 40 is directly stacked on the first region E and completely covers the first region E. In this way, all the parts of the first passivation contact layer 10 that may be exposed through the first through groove 31 can be covered and protected.

[0080] In the embodiments of the present application, for the convenience of description, the two opposite surfaces of the substrate 101 are respectively defined as the first surface F and the second surface S. One of the first surface F and the second surface S may be the front surface (for example, the light-receiving surface), and the other may be the back surface (for example, the light-blocking surface). The alternating arrangement direction of the first passivation contact layer 10 and the second passivation contact layer 20 is defined as the first direction D, and the extending direction of the first electrode 50 is defined as the second direction. In some embodiments, the first direction D and the second direction are perpendicular to each other and both parallel to the first surface F.

[0081] In the embodiments of the present application, the first through groove 31 may extend along the second direction, that is, the same as the extending direction of the first electrode 50.

[0082] Further, the width of the first through groove 31 in the first direction D is greater than the width of the first electrode 50 in the first direction. The difference ΔH between the width of the first through groove 31 in the first direction D and the width of the first electrode 50 in the first direction satisfies:

[0083] 15μm ≤ ΔH ≤ 25μm. Preferably, ΔH can be 20μm. When the first through groove 31 is grooved, it is necessary to make the position of the first through groove 31 correspond to the area where the first electrode 50 will be printed. Setting the width of the first through groove 31 wider than the width of the first electrode 50 can avoid the first electrode 50 being unable to be printed at the predetermined position due to grooving errors. Further, setting the first through groove 31 wider is also convenient for aligning with the first through groove 31 when printing the paste of the first electrode 50, and facilitating the printing of the paste of the first electrode 50 into the first through groove 31.

[0084] Further, a first electrode receiving groove 41 penetrating through is provided in a portion of the first dielectric layer 40 located in the first through groove 31. One end of the first electrode 50 facing the substrate 101 is located in the first electrode receiving groove 41 and is in close contact with two side walls of the first electrode receiving groove 41 along the first direction D. In this way, a gap between the first dielectric layer 40 and the first electrode 50 is avoided, and the first polysilicon doped conductive layer 12 is exposed.

[0085] In the embodiment of the present application, the thickness of the first dielectric layer 40 is 50nm - 120nm. Preferably, the thickness of the first dielectric layer 40 can be 100nm. Further, the thickness of the first passivation film layer 30 is 5nm - 12nm. Preferably, the thickness of the first passivation film layer 30 can be 10nm.

[0086] In the embodiment of the present application, the solar cell 100 further includes a second electrode 60. The second electrode 60 penetrates through the first dielectric layer 40 and the first passivation film layer 30 and is in ohmic contact with the second polysilicon doped conductive layer 22.

[0087] Further, the solar cell 100 further includes a second passivation film layer 90 and a second dielectric layer 91 stacked in sequence on the second surface S of the substrate 101.

[0088] Further, the thickness of the second dielectric layer 91 can be 180nm - 220nm. Preferably, the thickness of the second dielectric layer 91 can be 200nm.

[0089] The thickness of the second passivation film layer 90 can be 11nm - 15nm. Preferably, the thickness of the second passivation film layer 90 can be 13nm.

[0090] In the embodiment of the present application, as described above, the first tunneling oxide layer 11 is stacked between the first surface F of the substrate 101 and the first polysilicon-doped conductive layer 12. The second tunneling oxide layer 21 is stacked between the first surface F of the substrate 101 and the second polysilicon-doped conductive layer 22. The first polysilicon-doped conductive layer 12 is the film layer in the first passivation contact layer 10 that is farthest from the substrate 101, and the second polysilicon-doped conductive layer 22 is the film layer in the second passivation contact layer 20 that is farthest from the substrate 101.

[0091] Figure 2 It is a schematic diagram of another structure of the solar cell provided by the embodiment of the present application.

[0092] Referring to Figure 2 , on the basis of the foregoing embodiment, the first passivation contact layer 10 further includes a first transparent conductive oxide layer 70. The first transparent conductive oxide layer 70 is disposed on the side of the first polysilicon-doped conductive layer 12 facing away from the substrate 101, and the first electrode 50 is in ohmic contact with the first transparent conductive oxide layer 70. The second passivation contact layer 20 further includes a second transparent conductive oxide layer 80. The second transparent conductive oxide layer 80 is disposed on the side of the second polysilicon-doped conductive layer 22 facing away from the substrate 101, and the second electrode 60 is in contact with the second transparent conductive oxide layer.

[0093] By providing the first transparent conductive oxide layer 70 and the second transparent conductive oxide layer 80 with good lateral conductivity, while satisfying the passivation performance, they also have the characteristics of high charge carrier mobility and low carrier density. This also reduces the contact resistance between the first polysilicon-doped conductive layer 12 and the first electrode 50, and the contact resistance between the second polysilicon-doped conductive layer 22 and the second electrode 60, improving the efficiency of the solar cell 100. On the other hand, the first transparent conductive oxide layer 70 and the second transparent conductive oxide layer 80 also have ideal anti-reflection characteristics and do not affect the normal efficiency of the solar cell 100.

[0094] Furthermore, the first transparent conductive oxide layer 70 and the second transparent conductive oxide layer 80 allow the H element in the first dielectric layer 40 to enter the first polysilicon-doped conductive layer 12 and the second polysilicon-doped conductive layer 22. After sintering, the H element carried in the first dielectric layer 40 can diffuse into the substrate 101 during the sintering process to passivate the silicon crystal defects in the substrate 101.

[0095] In addition, precisely because of the provision of the first transparent conductive oxide layer 70 and the second transparent conductive oxide layer 80, the thicknesses of the first polysilicon-doped conductive layer 12 and the second polysilicon-doped conductive layer 22 can be set thinner, making them have a higher sheet resistance.

[0096] In specific implementation, the first transparent conductive oxide layer 70 is located between the first polysilicon doped conductive layer 12 and the first passivation film layer 30, and the second transparent conductive oxide layer 80 is located between the second polysilicon doped conductive layer 22 and the first passivation film layer 30. The first region E is located on the surface of the first transparent conductive oxide layer 70 facing away from the substrate 101. In Figure 2 In the illustrated example, the outermost layer of the first passivation contact layer 10 facing away from the substrate 101 is the first transparent conductive oxide layer 70. Therefore, the surface of the first passivation contact layer 10 exposed from the first through groove 31 is also the surface of the first transparent conductive oxide layer 70 exposed from the first through groove 31. Specifically, it refers to the region of the surface of the first transparent conductive oxide layer 70 facing away from the substrate 101 corresponding to the first through groove 31. In this region, the region between the sidewall of the first through groove 31 and the first electrode 50 is the first region E.

[0097] Furthermore, the thickness of the first transparent conductive oxide layer 70 is 30 nm - 150 nm. With such a setting, the contact resistance can be made smaller without affecting the passivation performance of the battery.

[0098] Figure 3 It is a schematic flow chart of the manufacturing method of the solar cell provided by the embodiment of the present application. Figure 4 It is a schematic structural diagram of the substrate formed in the manufacturing method of the solar cell provided by the embodiment of the present application. Figure 5 It is a schematic structural diagram of forming the first through groove in the manufacturing method of the solar cell provided by the embodiment of the present application. Figure 6 It is a schematic structural diagram of the solar cell formed in the manufacturing method of the solar cell provided by the embodiment of the present application.

[0099] In the second aspect of the embodiment of the present application, a manufacturing method of a solar cell is provided. This method is used to manufacture the solar cell 100 of the above embodiment.

[0100] Referring to Figures 3 - 6 , the manufacturing method of the solar cell includes:

[0101] S10. Provide a substrate 102, where the substrate 102 includes a substrate 101, a first passivation contact layer 10, and a second passivation contact layer 20. The first passivation contact layer 10 and the second passivation contact layer 20 are alternately arranged on the first surface F of the substrate 101. The first passivation contact layer 10 includes a first polysilicon doped conductive layer 12, and the second passivation contact layer 20 includes a second polysilicon doped conductive layer 22. The doping concentration of the second polysilicon doped conductive layer 22 is greater than that of the first polysilicon doped conductive layer 12, and the doping type is opposite to that of the first polysilicon doped conductive layer 12; an insulating isolation groove A is formed between each adjacent first passivation contact layer 10 and second passivation contact layer 20.

[0102] S20. A first passivation film layer 30 is formed on the first passivation contact layer 10, inside the insulating isolation groove A, and on the second passivation contact layer 20, and first through grooves 31 are formed in regions of the first passivation film layer 30 corresponding to the respective first polysilicon doped conductive layers 12.

[0103] S30. A first dielectric layer 40 is formed on the first passivation film layer 30, such that the first dielectric layer 40 covers the first passivation film layer 30 and covers the surface of the first passivation contact layer 10 exposed from the first through grooves 31.

[0104] S40. A first electrode 50 is formed on the part of the first dielectric layer 40 located inside the first through grooves 31, and the first electrode 50 penetrates the first dielectric layer 40 to make an ohmic contact with the first polysilicon doped conductive layer 12.

[0105] By forming the first dielectric layer 40 on the first passivation film layer 30, such that the first dielectric layer 40 covers the surface of the first passivation contact layer 10 exposed from the first through grooves 31, and forming the first electrode 50 on the part of the first dielectric layer 40 located inside the first through grooves 31, thus, among the surfaces of the first passivation contact layer 10 exposed from the first through grooves 31, the regions other than the regions in contact with the first electrode 50 are all covered by the first dielectric layer 40, and the surface of the first passivation contact layer 10 facing away from the substrate 101 is not directly exposed, resulting in a better passivation effect, reducing the recombination loss, and improving the efficiency of the solar cell 100.

[0106] Forming the first through grooves 31 in regions of the first passivation film layer 30 corresponding to the respective first polysilicon doped conductive layers 12 means that there are corresponding first through grooves 31 on each of the first polysilicon doped conductive layers 12, so that partial regions of the first passivation contact layer 10 corresponding to the respective first polysilicon doped conductive layers 12 can be exposed through the first through grooves 31 to facilitate an ohmic contact with the first electrode 50.

[0107] The first dielectric layer 40 covers the surface of the first passivation contact layer 10 exposed from the first through grooves 31 means that the surface of the first passivation contact layer 10 exposed from the first through grooves 31 is completely covered by the first dielectric layer 40.

[0108] It should be noted that the first electrode 50 can be formed by printing a metal paste of the first electrode 50 on the first dielectric layer 40 and then sintering. Of course, the present application is not limited thereto, and it can also be formed by other means.

[0109] In step S20, the step of forming the first through grooves 31 in regions of the first passivation film layer 30 corresponding to the respective first polysilicon doped conductive layers 12 specifically includes:

[0110] Use a lithography process to open a first through groove 31 in the first passivation film layer 30. The width of the first through groove 31 in the first direction can be, for example, 30 μm. Forming the first through groove 31 using a lithography process has a high positioning accuracy, which is beneficial for accurately forming the first electrode 50 at a preset position. The lithography method can not only ensure the accuracy of patterning, but also the organic solvent for cleaning the photoresist does not react with the first passivation film layer 30 in the remaining areas, fully ensuring the passivation performance of the first passivation film layer 30 for the non-lithography areas.

[0111] It can be understood that in the above substrate 102, a matte structure 92 can be formed on the second surface S of the substrate 101, and a second passivation film layer 90 can be formed on the matte structure 92. Alternatively, in the above substrate 102, the second surface S of the substrate 101 can also be exposed, and no film layer is formed thereon.

[0112] In the substrate 102, in the case where no film layer is formed on the second surface S of the substrate 101, it can be considered to form the second passivation film layer 90 on the second surface S before forming the first passivation film layer 30.

[0113] In specific implementation, in step S20, before the step of forming the first passivation film layer 30 on the first passivation contact layer 10, in the insulating isolation groove A, and on the second passivation contact layer 20, it further includes:

[0114] Form a matte structure 92 and a second passivation film layer 90 on the second surface S of the substrate 101.

[0115] Further, in step S30, the step of forming the first dielectric layer 40 on the first passivation film layer 30 specifically includes:

[0116] Form a second dielectric layer 91 on the second passivation film layer 90, form the first dielectric layer 40 on the first passivation film layer 30, and make the first dielectric layer 40 deposit and cover the first through groove 31. Among them, both the first dielectric layer 40 and the second dielectric layer 91 can be antireflection layers. The first dielectric layer 40 can be, for example, silicon nitride, and the second dielectric layer 91 can include, for example, silicon nitride and silicon dioxide. In addition, a part of the first dielectric layer 40 can also cover the side groove walls of the first through groove 31.

[0117] Further, after the steps of forming the first passivation film layer 30 and the second passivation film layer 90, before the step of opening the first through groove 31 in the regions of the first passivation film layer 30 corresponding to the first polysilicon doped conductive layers 12, it further includes: annealing the first passivation film layer 30 and the second passivation film layer 90 to activate the first passivation film layer 30 and the second passivation film layer 90 and remove the hydrogen elements included in the first passivation film layer 30 and the second passivation film layer 90.

[0118] In an embodiment of the present application, after forming the matte structure 92 and before forming the second passivation film layer 90 and the first passivation film layer 30, the following steps are further included:

[0119] A first transparent conductive oxide layer 70 is formed on the first polysilicon doped conductive layer 12, and a second transparent conductive oxide layer 90 is formed on the second polysilicon doped conductive layer 22. The first transparent conductive oxide layer 70 is formed on a side of the first polysilicon doped conductive layer 12 facing away from the substrate 101, and the second transparent conductive oxide layer 90 is formed on a side of the second polysilicon doped conductive layer 22 facing away from the substrate 101.

[0120] Of course, the first transparent conductive oxide layer 70 and the second transparent conductive oxide layer 90 can be formed through a mask plate (such as a hard mask plate). The materials of the first transparent conductive oxide layer 70 and the second transparent conductive oxide layer 90 can be, for example, indium tin oxide ITO, aluminum-doped zinc oxide AZO, etc.

[0121] In an embodiment of the present application, in step S40, after the step of forming the first electrode 50, the following steps are further included:

[0122] A second electrode receiving groove 42 is formed through the corresponding regions of the first dielectric layer 40 and the first passivation film layer 30 corresponding to the second polysilicon doped conductive layer 22. A second electrode 60 is formed in the second electrode receiving groove 42, and the second electrode 60 is brought into contact with the second transparent conductive oxide layer 80.

[0123] Further, referring to Figure 1 the structure as described above, the outermost film layer of the first passivation contact layer 10 facing away from the substrate 101 is the first polysilicon doped conductive layer 12.

[0124] The steps of forming the first electrode 50 on a part of the first dielectric layer 40 located in the first through groove 31 and making the first electrode 50 penetrate the first dielectric layer 40 and be in ohmic contact with the first polysilicon doped conductive layer 12 include:

[0125] Printing a first paste on a part of the first dielectric layer 40 located in the first through groove 31 and sintering it, so that the first paste penetrates the first dielectric layer 40 and contacts the first polysilicon doped conductive layer 12, thereby enabling the formed first electrode 50 to be in ohmic contact with the first polysilicon doped conductive layer 12.

[0126] In an embodiment of the present application, in step S10, when no film layer is provided on the second surface S of the substrate 101 in the substrate 102, the steps of providing the substrate 102 include:

[0127] Stacking a tunneling material layer, an amorphous silicon material layer, a borosilicate glass BSG film layer, and a mask layer in sequence on the first surface F of the substrate 101;

[0128] Partially remove the borosilicate glass (BSG) film layer and the mask layer on the first surface F, and make the remaining BSG film layer and the mask layer in the first layout area on the amorphous silicon material layer correspond to the setting area of the first polysilicon doped conductive layer 12 with a lower doping concentration in the solar cell 100;

[0129] Through the remaining BSG film layer, form the first polysilicon doped conductive layer 12 in the area of the amorphous silicon material layer corresponding to the first layout area. For example, the boron element in the BSG film layer can be pushed into the amorphous silicon material layer under high-temperature conditions to form the P-type first polysilicon doped conductive layer 12.

[0130] Form the second polysilicon doped conductive layer 22 in the area of the amorphous silicon material layer corresponding to the second layout area, and the second layout area corresponds to the setting area of the second polysilicon doped conductive layer 22 with a higher doping concentration in the solar cell 100. For example, after depositing a film layer containing N-type doping elements, the N-type doping elements are pushed into the amorphous silicon material layer at high temperature to form the N-type second polysilicon doped conductive layer 22.

[0131] Open an insulating isolation groove A between adjacent first polysilicon doped conductive layers 12 and second polysilicon doped conductive layers 22.

[0132] The following gives a specific example to illustrate the manufacturing method of the solar cell according to the embodiment of the present application. The method includes:

[0133] Step 1: Select an N-type silicon substrate as the substrate 101 and perform double-sided polishing to remove the damaged layer. Place the substrate 101 into the reaction chamber of the LP furnace, and sequentially stack a tunneling material layer and an intrinsic amorphous silicon material layer on the first surface F of the substrate 101.

[0134] Step 2: Prepare a BSG film layer and a mask layer (such as silicon dioxide) on the surface (the first surface F) of the intrinsic amorphous silicon material layer facing away from the substrate 101 in an APCVD device.

[0135] Step 3: Partially remove the BSG film layer and the mask layer on the first surface F by a green outer skin picosecond laser, and make the remaining BSG film layer and the mask layer in the first layout area on the amorphous silicon material layer correspond to the setting area of the first polysilicon doped conductive layer 12 with a lower doping concentration in the solar cell 100, that is, make the remaining BSG film layer and the mask layer correspond to the P-type doping area (that is, the area corresponding to the first polysilicon doped conductive layer 12) to form the first tunneling oxide layer 11.

[0136] Step 4: Clean the semi-finished product obtained in Step 3 and place it in a diffusion furnace. Under high-temperature conditions, push the boron element in the borosilicate glass BSG film layer into the amorphous silicon material layer to form a P-type first polysilicon doped conductive layer 12. Cool down, and after depositing a film layer containing an N-type doping element (such as phosphorus element) on the amorphous silicon material layer exposed to the outside, push the N-type doping element into the amorphous silicon material layer at high temperature to form an N-type second polysilicon doped conductive layer 22.

[0137] Step 5: Use a green-coated picosecond laser to open an insulating isolation groove A (i.e., a non-diffusion area) between adjacent first polysilicon doped conductive layers 12 and second polysilicon doped conductive layers 22. And simultaneously form a second tunneling oxide layer 21.

[0138] Step 6: Remove the oxide layers such as the amorphous silicon material layer and the phosphosilicate glass PSG film layer on the second surface S side and the side of the substrate 101 of the semi-finished product obtained in Step 5 through a chain cleaner, and enter a trough machine for cleaning and texturing to form a textured structure 92 on the second surface S of the substrate 101. Of course, the laser damage in the insulating isolation groove A is also removed simultaneously, thereby forming Figure 4 the structure shown.

[0139] Step 7: Deposit a second passivation film layer 90 and a first passivation film layer 30 on the second surface S side and the first surface F side of the substrate 101 in sequence. The first passivation film layer 30 and the second passivation film layer 90 can both be alumina, and their thicknesses are 10 nm and 13 nm respectively, and an annealing process is performed to activate the first passivation film layer 30 and the second passivation film layer 90.

[0140] Step 8: Use a lithography process to open a first through groove 31 in the area of the first passivation film layer 30 corresponding to each first polysilicon doped conductive layer 12. The width of the first through groove 31 is approximately 30 microns, as Figure 5 shown.

[0141] Step 9: Deposit a first dielectric layer 40 and a second dielectric layer 91 on the first surface F side and the second surface S side of the semi-finished product obtained in Step 8 respectively. The first dielectric layer 40 also covers the surface of the first polysilicon doped conductive layer 12 exposed from the first through groove 31. Print silver paste at the positions corresponding to the first through groove 31 and the second polysilicon doped conductive layer 22 on the first dielectric layer 40, and sinter to form a first electrode 50 and a second electrode 60. The first electrode 50 penetrates through the first dielectric layer 40 to make an ohmic contact with the first polysilicon doped conductive layer 12, and the second electrode 60 penetrates through the first dielectric layer 40 and the first passivation film layer 30 to make an ohmic contact with the second polysilicon doped conductive layer 22, and finally form as Figure 6The solar cell 100 shown. Among them, the first dielectric layer 40 may be, for example, silicon nitride with a thickness of 100 nm. The second dielectric layer 91 may be a stacked film of silicon nitride and silicon oxide, and the thicknesses of silicon nitride and silicon oxide in the second dielectric layer 91 are 60 nm and 140 nm respectively.

[0142] Of course, in some other embodiments, between step six and step seven, there is also a step of forming a first transparent conductive oxide layer 70 on the first polysilicon doped conductive layer 12 and forming a second transparent conductive oxide layer 80 on the second polysilicon doped conductive layer 22.

[0143] The third aspect of the embodiments of the present application further provides a photovoltaic module (not shown).

[0144] The photovoltaic module includes at least one battery string, and the battery string includes at least two solar cells 100 such as those in Embodiment 1 and / or Embodiment 2. The solar cells 100 can be connected together by string soldering.

[0145] The fourth aspect of the embodiments of the present application further provides a photovoltaic module (not shown).

[0146] The photovoltaic system includes the above-mentioned photovoltaic module. The photovoltaic system can be applied in photovoltaic power stations, such as ground power stations, rooftop power stations, water surface power stations, etc., and can also be applied to devices or apparatuses that use solar energy for power generation, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be applied in all fields that require solar power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system can include a photovoltaic array, a busbar box, and an inverter. The photovoltaic array can be an array combination of multiple photovoltaic modules. For example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the busbar box, and the busbar box can collect the current generated by the photovoltaic array. After the collected current flows through the inverter and is converted into alternating current required by the mains power grid, it is connected to the mains network to achieve solar power supply.

[0147] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered as within the scope described in this specification.

[0148] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A solar cell, characterized in that, It includes a substrate, a first passivation contact layer and a second passivation contact layer, a first passivation film layer and a first dielectric layer, and a first electrode; The first passivation contact layer and the second passivation contact layer are alternately arranged on the first surface of the substrate, the first passivation contact layer includes a first polysilicon doped conductive layer, the second passivation contact layer includes a second polysilicon doped conductive layer, the doping concentration of the second polysilicon doped conductive layer is greater than that of the first polysilicon doped conductive layer, and the doping type of the second polysilicon doped conductive layer is opposite to that of the first polysilicon doped conductive layer; an insulating isolation groove is constructed between each adjacent first passivation contact layer and the second passivation contact layer; The first passivation film layer is stacked on the first passivation contact layer and the second passivation contact layer on a side away from the substrate, and is stacked in the insulating isolation groove, and the first passivation film layer is provided with a first through groove in the region corresponding to each of the first polysilicon doped conductive layers, and one end of the first electrode passes through the first through groove to make ohmic contact with the first polysilicon doped conductive layer; The first dielectric layer covers the first passivation film layer and covers the first area on the first passivation contact layer; The first region is a region on the surface of the first passivation contact layer exposed from the first through-groove and located between the sidewall of the first through-groove and the first electrode.

2. The solar cell according to claim 1, characterized in that, A difference ΔH between a width of the first through groove along the first direction and a width of the first electrode along the first direction satisfies: 15μm≤ΔH≤25μm; The first direction is an alternating arrangement direction of the first passivation contact layer and the second passivation contact layer, and the first direction is parallel to the first surface.

3. The solar cell according to claim 1, characterized in that, The first through groove is arranged to extend along the second direction; The second direction is an extension direction of the first electrode, and the second direction is parallel to the first surface.

4. The solar cell according to claim 1, characterized in that, A first electrode accommodating groove is provided in a portion of the first dielectric layer located in the first through groove, and one end of the first electrode facing the substrate is located in the first electrode accommodating groove and is in close contact with two side walls of the first electrode accommodating groove along a first direction; The first direction is an alternating arrangement direction of the first passivation contact layer and the second passivation contact layer, and the first direction is parallel to the first surface.

5. The solar cell according to any one of claims 1 - 4, characterized in that, The thickness of the first dielectric layer is 50nm-120nm; and / or The thickness of the first passivation film layer is 5nm-12nm.

6. The solar cell according to any one of claims 1 - 4, characterized in that, The solar cell further includes a second electrode, the second electrode penetrates the first dielectric layer and the first passivation film layer, and is in ohmic contact with the second polysilicon doped conductive layer; The first passivation contact layer further comprises a first transparent conductive oxide layer, the first transparent conductive oxide layer is arranged on a side of the first polysilicon doped conductive layer away from the substrate, and the first electrode is in ohmic contact with the first transparent conductive oxide layer; The second passivation contact layer further includes a second transparent conductive oxide layer, which is disposed on a side of the second polysilicon doped conductive layer facing away from the substrate, and the second electrode is in ohmic contact with the second transparent conductive oxide layer.

7. The solar cell according to claim 6, characterized in that, The first transparent conductive oxide layer is located between the first polysilicon doped conductive layer and the first passivation film layer; the second transparent conductive oxide layer is located between the second polysilicon doped conductive layer and the first passivation film layer; The first region is located on a surface of the first transparent conductive oxide layer facing away from the substrate.

8. The solar cell according to claim 6, characterized in that, The thickness of the first transparent conductive oxide layer is 30 nm - 150 nm.

9. The solar cell according to any one of claims 1 - 4, characterized in that, The substrate includes a second surface opposite to the first surface; The solar cell further includes a second passivation film layer and a second dielectric layer stacked in sequence on the second surface of the substrate; The thickness of the second dielectric layer is 180 nm - 220 nm; The thickness of the second passivation film layer is 11 nm - 15 nm.

10. A method for manufacturing a solar cell, characterized in that, Comprising: Providing a substrate including a substrate, a first passivation contact layer, and a second passivation contact layer, the first passivation contact layer and the second passivation contact layer are alternately arranged on a first surface of the substrate, the first passivation contact layer includes a first polysilicon doped conductive layer, the second passivation contact layer includes a second polysilicon doped conductive layer, the doping concentration of the second polysilicon doped conductive layer is greater than that of the first polysilicon doped conductive layer, and the doping type is opposite to that of the first polysilicon doped conductive layer; an insulating isolation groove is formed between each adjacent first passivation contact layer and the second passivation contact layer; Forming a first passivation film layer, wherein the first passivation film layer is stacked on a side of the first passivation contact layer and the second passivation contact layer facing away from the substrate, and is stacked in the insulating isolation groove, and a first through groove is opened in a region of the first passivation film layer corresponding to each first polysilicon doped conductive layer; Forming a first dielectric layer on the first passivation film layer, such that the first dielectric layer covers the first passivation film layer and covers a surface of the first passivation contact layer exposed from the first through groove; Forming a first electrode on a portion of the first dielectric layer located in the first through groove, and making the first electrode penetrate through the first dielectric layer to be in ohmic contact with the first polysilicon doped conductive layer.

11. The manufacturing method of the solar cell according to claim 10, wherein, The step of opening the first through groove in the region of the first passivation film layer corresponding to each first polysilicon doped conductive layer specifically includes: Using a photolithography process to open the first through groove in the first passivation film layer.

12. The manufacturing method of the solar cell according to claim 10, wherein, Before the step of forming the first passivation film layer on the first passivation contact layer, in the insulating isolation groove, and on the second passivation contact layer, further includes: Forming a textured structure and a second passivation film layer on a second surface of the substrate of the substrate, the second surface being opposite to the first surface.

13. The manufacturing method of the solar cell according to claim 12, wherein, The step of forming the first dielectric layer on the first passivation film specifically includes: A second dielectric layer is formed on the second passivation film layer, a first dielectric layer is formed on the first passivation film layer, and the first dielectric layer is deposited and covers the first through groove.

14. The manufacturing method of the solar cell according to claim 12, wherein, After the steps of forming the first passivation film layer and the second passivation film layer, before the step of forming the first through grooves in the regions of the first passivation film layer corresponding to the first polysilicon doped conductive layers, the following is further included: annealing the first passivation film layer and the second passivation film layer to activate the first passivation film layer and the second passivation film layer.

15. The manufacturing method of the solar cell according to claim 12, wherein, After forming the textured structure and before forming the second passivation film layer and the first passivation film layer, the following is further included: A first transparent conductive oxide layer is formed on the first polysilicon doped conductive layer, and a second transparent conductive oxide layer is formed on the second polysilicon doped conductive layer.

16. The manufacturing method of the solar cell according to claim 15, wherein, After the step of forming the first electrode, the following is further included: A second electrode receiving groove penetrating through is formed in the regions of the first dielectric layer and the first passivation film layer corresponding to the second polysilicon doped conductive layer, a second electrode is formed in the second electrode receiving groove, and the second electrode is in ohmic contact with the second transparent conductive oxide layer.

17. The manufacturing method of the solar cell according to claim 10, wherein, The outermost film layer of the first passivation contact layer facing away from the substrate is the first polysilicon doped conductive layer; The step of forming a first electrode on the part of the first dielectric layer located in the first through groove and making the first electrode penetrate the first dielectric layer and be in ohmic contact with the first polysilicon doped conductive layer includes: Printing a first paste on the part of the first dielectric layer located in the first through groove and sintering it so that the first paste penetrates the first dielectric layer and contacts the first polysilicon doped conductive layer.

18. A photovoltaic module, wherein, It includes at least one battery string, and the battery string includes at least two solar cells as described in any one of claims 1-9.

19. A photovoltaic system, wherein, It includes a photovoltaic module as described in claim 18.

Images