Power converter and method of controlling the same

Abstract

A power converter and a control method thereof. The power converter includes first to fourth switches, a flying capacitor, an inductor, an output capacitor and a control circuit. The first to fourth switches are sequentially connected in series. The first switch is further configured to receive an input voltage, and the fourth switch is further coupled to a ground terminal. The flying capacitor is connected across the second switch and the third switch. The inductor is coupled to the second switch, the third switch and the output capacitor. The output capacitor is configured to output an output voltage. In a non-regulation mode, the control circuit is configured to switch the first switch, the second switch, the third switch and the fourth switch according to a resonant frequency, and in a regulation mode, the control circuit is configured to switch the first switch, the second switch, the third switch and the fourth switch according to a regulation frequency which is higher than the resonant frequency. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor form a resonant circuit having the resonant frequency.

Description

Technical Field

[0001] This invention relates to electrical energy conversion, and more particularly to a power converter and its control method. Background Technology

[0002] A resonant switched-capacitor converter (RSCC) is a type of power converter that consumes little or no power when transmitting power. It is commonly used in mobile electronic devices such as mobile phones and laptops to provide power.

[0003] A resonant switching capacitor converter converts the input voltage to the output voltage at a fixed conversion ratio. When the input voltage is too high, the resonant switching capacitor converter will still produce an excessively high output voltage at the fixed conversion ratio, causing damage to the electronic device. Conversely, when the input voltage is insufficient, the output voltage produced by the resonant switching capacitor converter at the fixed conversion ratio will be insufficient, resulting in low circuit efficiency. Summary of the Invention

[0004] This invention provides a power converter comprising a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor, and a control circuit. The first switch includes a control terminal, a first terminal for receiving input voltage, and a second terminal. The second switch includes a control terminal, a first terminal, and a second terminal coupled to the second terminal of the first switch. The third switch includes a control terminal, a first terminal, and a second terminal coupled to the second terminal of the second switch. The fourth switch includes a control terminal, a first terminal, and a second terminal coupled to the second terminal of the third switch, and is coupled to a ground terminal. The flying capacitor includes a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch. The output capacitor includes a first terminal coupled to the second terminal of the inductor for outputting an output voltage, and a second terminal coupled to a ground terminal. The control circuit is coupled to the first terminal of the first switch, the control terminal of the first switch, the control terminal of the second switch, the control terminal of the third switch, and the control terminal of the fourth switch. In non-adjustment mode, the control circuit switches the first, second, third, and fourth switches according to the resonant frequency. In adjustment mode, the control circuit switches the first, second, third, and fourth switches according to an adjustment frequency exceeding the resonant frequency. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor form a resonant circuit with the resonant frequency.

[0005] This invention also provides a control method for a power converter. The power converter includes a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor, and a control circuit. The first switch includes a control terminal, a first terminal for receiving input voltage, and a second terminal. The second switch includes a control terminal, a first terminal, and a second terminal coupled to the second terminal of the first switch. The third switch includes a control terminal, a first terminal, and a second terminal coupled to the second terminal of the second switch. The fourth switch includes a control terminal, a first terminal, and a second terminal coupled to the second terminal of the third switch, and is coupled to a ground terminal. The flying capacitor includes a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch. The output capacitor includes a first terminal coupled to the second terminal of the inductor for outputting the output voltage, and a second terminal coupled to a ground terminal. The control circuit is coupled to the first terminal of the first switch, the control terminal of the first switch, the control terminal of the second switch, the control terminal of the third switch, and the control terminal of the fourth switch. The control method includes switching the first, second, third, and fourth switches according to the resonant frequency in non-adjustment mode, and switching the first, second, third, and fourth switches according to an adjustment frequency exceeding the resonant frequency in adjustment mode. When a flying capacitor is coupled to an inductor, the flying capacitor and inductor form a resonant circuit with the resonant frequency. Attached Figure Description

[0006] Figure 1 This is a circuit diagram of a power converter according to an embodiment of the present invention.

[0007] Figure 2 yes Figure 1 The flowchart shows the control method of the power converter in the process.

[0008] Figure 3 yes Figure 1 The waveform of the power converter in non-regulation mode.

[0009] Figure 4 yes Figure 1 Waveform diagram of the power converter in two-stage operation.

[0010] Figure 5 yes Figure 1 Waveform diagram of the power converter in single-stage operation.

[0011] Figure 6A , Figure 6B , Figure 6C , Figure 6D yes Figure 1A schematic diagram of the current of the power converter in a single-stage operation across four time periods.

[0012] Figure 7 yes Figure 1 A schematic diagram of the signal generation circuit of the control circuit in the diagram.

[0013] Figure 8 yes Figure 1 A schematic diagram of the feedback circuit of the control circuit in the diagram.

[0014] Figure 9 yes Figure 8 The waveform diagram of the feedback circuit in the image.

[0015] Figure 10 yes Figure 1 The schematic diagram shows the state detection circuit and closed-loop circuit of the control circuit.

[0016] Figure 11 yes Figure 1 The diagram shows the start circuit and phase circuit of the control circuit.

[0017] Figure 12 yes Figure 1 A schematic diagram of other phase circuits in the control circuit.

[0018] [Symbol Explanation]

[0019] 1: Power Converter

[0020] 10, 20, 30, 40, 120: Switch

[0021] 50: Flying Capacitor

[0022] 60: Inductor

[0023] 70: Output capacitor; 800: Control circuit

[0024] 801: Signal Generation Circuit

[0025] 803: Status Detection Circuit

[0026] 804: Closed-loop circuit

[0027] 805, 806, 807, 808: Phase circuits

[0028] 80 to 83: Buffer

[0029] 84, 85, 86, 88, 89, 263, 315, 318, 415: OR gate

[0030] 111: Transistor

[0031] 112: Current source

[0032] 113 and 152: Capacitors

[0033] 150: Error Amplifier

[0034] 155, 210, 220: Comparators

[0035] 250: Zero-cross detector

[0036] 260, 320, 343, 420, 443: Triggers

[0037] 96 to 98, 261, 267, 311, 313, 411: Inverters

[0038] 223, 265, 330, 345, 430, 445: Pulse generator

[0039] 300: Start-up circuit

[0040] 90 to 95, 225, 310, 312, 316, 317, 321, 322, 341, 410, 412, 421, 422, 441: AND gate

[0041] 110, 325, 425: NOR gates

[0042] 342, 442: NAND gate

[0043] 200: Control Method

[0044] S202 and S204: Procedures

[0045] CLP: Closed-loop signal

[0046] COMP: Error Amplification Signal

[0047] IL: Inductor current

[0048] Imax: Maximum value

[0049] Imin: Minimum value

[0050] MODE: Mode signal

[0051] P1, P2, PA, PB: Phase signals

[0052] Ph1, Ph2: Stages

[0053] Pz1 to Pz3, Pfb1, Pfb2: Pulses

[0054] RAMP: Ramp Signal

[0055] S1 to S4: Switching signals

[0056] SDM: Demagnetizing signal

[0057] Son: Start signal

[0058] SP: Cutoff signal

[0059] SZ: Zero Crossing Signal

[0060] t1 to r9: Time

[0061] T1 to T4: Time Period

[0062] TG1, TG2, TGA, TGB: Trigger signals

[0063] V-: Negative voltage

[0064] Vcc: Supply voltage

[0065] Vin: Input voltage

[0066] VH: High voltage

[0067] VL: Low Voltage

[0068] Vo: Output voltage

[0069] VR: Reference Voltage

[0070] VT: Demagnetization reference voltage

[0071] Vx: Switching voltage

[0072] GND: Grounding voltage

[0073] ZM: Control signal Detailed Implementation

[0074] Figure 1 This is a circuit diagram of a power converter 1 according to an embodiment of the present invention. The power converter 1 can step down the input voltage Vin to generate an output voltage Vo to the load. Both the input voltage Vin and the output voltage Vo can be DC voltages, and the output voltage Vo can be less than or equal to the input voltage Vin. The power converter 1 can operate in either non-regulated or regulated mode. In both non-regulated and regulated modes, the power converter 1 can operate in discontinuous conduction mode (DCM) instead of continuous conduction mode (CCM).

[0075] When the input voltage Vin is between a low voltage threshold and a high voltage threshold, power converter 1 can operate in unregulated mode, where the high voltage threshold can be greater than the low voltage threshold. In unregulated mode, power converter 1 can be considered a voltage divider, and the output voltage Vo can be a voltage divider of the input voltage Vin. In some embodiments, the output voltage Vo in unregulated mode can be equal to half of the input voltage Vin. When the input voltage Vin is less than the low voltage threshold or exceeds the high voltage threshold, power converter 1 can operate in regulated mode to maintain the output voltage Vo within a reasonable range, preventing it from becoming too high or too low. Regulated mode can be implemented in single-phase or two-phase operation. When the input voltage Vin is less than the low voltage threshold, power converter 1 can perform single-phase operation to regulate the output voltage Vo to be less than or equal to the input voltage Vin. In single-phase operation, power converter 1 can be considered a buck converter. When the input voltage Vin exceeds the high voltage threshold, power converter 1 can perform a two-stage operation to adjust the output voltage Vo to be less than or equal to the upper limit of the output voltage. In some embodiments, the upper limit of the output voltage can be equal to half of the high voltage threshold. For example, if the high voltage threshold is 40V, the low voltage threshold is 20V, and the upper limit of the output voltage is 20V, then when the input voltage Vin is 30V, the output voltage Vo generated by power converter 1 can be 15V; when the input voltage Vin is 10V, power converter 1 can adjust the output voltage Vo to 10V; when the input voltage Vin is 60V, power converter 1 can adjust the output voltage Vo to 20V, avoiding damage to the load while improving system efficiency.

[0076] Power converter 1 may include switches 10, 20, 30, and 40, a flying capacitor 50, an inductor 60, an output capacitor 70, and a control circuit 800. Switch 10 includes a control terminal for receiving switch signal S1, a first terminal, and a second terminal. Switch 20 includes a control terminal for receiving switch signal S2, a first terminal, and is coupled to the second terminal of switch 10. Switch 30 includes a control terminal for receiving switch signal S3, a first terminal, and is coupled to the second terminal of switch 20. Switch 40 includes a control terminal for receiving switch signal S4, a first terminal, and is coupled to the second terminal of switch 30 and a ground terminal. Flying capacitor 50 includes a first terminal, coupled to the second terminal of switch 10 and the second terminal of switch 30. Inductor 60 includes a first terminal, coupled to the second terminal of switch 20. The output capacitor 70 includes a first terminal coupled to the second terminal of the inductor 60, and a second terminal coupled to ground. The control circuit 800 can be coupled to the control terminals of switch 10, switch 20, switch 30, and switch 40.

[0077] The first terminal of switch 10 can receive the input voltage Vin, and the first terminal of output capacitor 70 can output the output voltage Vo. The ground terminal can provide a ground voltage GND, such as 0V. The second terminal of switch 20 can provide a switching voltage Vx. The current flowing through inductor 60 can be called the inductor current IL. When the inductor current IL flows from the first terminal to the second terminal of inductor 60, the inductor current IL is a positive current; while when the inductor current IL flows from the second terminal to the first terminal of inductor 60, the inductor current IL is a negative current.

[0078] The control circuit 800 can receive input voltage Vin and / or output voltage Vo to generate switching signals S1 to S4, thereby switching switches 10, 20, 30 and 40 to set the power converter 1 to non-regulation mode or regulation mode. Figure 2 This is a flowchart of a control method 200 for power converter 1, applicable to control circuit 800. Control method 200 includes steps S202 and S204, used to allow control circuit 800 to control power converter 1 to operate in non-regulation mode or regulation mode. Any reasonable technical modifications or adjustments to the steps fall within the scope of this invention. Steps S202 and S204 are explained as follows:

[0079] Step S202: In non-adjustment mode, the control circuit 800 switches 10, 20, 30 and 40 according to the resonant frequency;

[0080] Step S204: In adjustment mode, the control circuit 800 switches 10, 20, 30 and 40 according to the adjustment frequency exceeding the resonant frequency.

[0081] In step S202, power converter 1 operates in non-regulation mode. Control circuit 800 can switch switches 10, 20, 30, and 40 to couple flying capacitor 50 to output capacitor 70 via inductor 60, forming a voltage divider between flying capacitor 50 and output capacitor 70. This divider generates output voltage Vo based on input voltage Vin, and simultaneously forms a resonant circuit between flying capacitor 50 and inductor 60. The resonant circuit generates a resonant frequency. Control circuit 800 switches switches 10, 20, 30, and 40 when the inductor current is 0, based on the resonant frequency, to generate a voltage divider of input voltage Vin as output voltage Vo, thereby achieving zero-current switching (ZCS). Switching signals S1 and S3 can be identical, allowing switches 10 and 30 to switch synchronously according to the resonant frequency. Similarly, switching signals S2 and S4 can be identical, allowing switches 20 and 40 to switch synchronously according to the resonant frequency. In general, power converter 1 can operate alternately in the first stage Ph1 and the second stage Ph2, as follows: Figure 3As shown. In the first stage, Ph1, switches 10 and 30 are on and switches 20 and 40 are off. In the second stage, Ph2, switches 20 and 40 are on and switches 10 and 30 are off.

[0082] Figure 3 This is a waveform diagram of power converter 1 in non-regulation mode, where the horizontal axis represents time and the vertical axis represents voltage or current. See also the following: Figure 1 and Figure 3 The operation of power converter 1 in non-regulation mode will be explained below. In non-regulation mode, control circuit 800 can generate switching signals S1 and S3 using phase signal P1, generate switching signals S2 and S4 using phase signal P2, generate a zero-crossing signal SZ based on inductor current IL, and switch phase signals P1 and P2 based on the zero-crossing signal SZ. The zero-crossing signal SZ can be generated when the inductor current IL is detected to be 0A. Phase signal P1 and switching signals S1 and S3 can be the same, and phase signal P2 and switching signals S2 and S4 can be the same. The generation methods of zero-crossing signal SZ, phase signals P1, and P2 will be explained in subsequent paragraphs.

[0083] At time t1, the inductor current IL reaches 0A, triggering pulse Pz1 on the zero-crossing signal SZ. Simultaneously, pulse Pz1 triggers phase signal P2 to switch from high voltage VH to low voltage VL, while phase signal P1 remains at low voltage VL. Low voltage VL can be ground voltage GND. At time t2, pulse Pz1 triggers phase signal P1 to switch from low voltage VL to high voltage VH, while phase signal P2 remains at low voltage VL, and pulse Pz1 on the zero-crossing signal SZ ends. Pulse Pz1 can have a predetermined width, for example, a predetermined width equal to (t2-t1).

[0084] Between time t2 and time t3, phase signal P1 is maintained at a high voltage VH, phase signal P2 is maintained at a low voltage VL, inductor current IL oscillates at the resonant frequency, and zero-crossing signal SZ is maintained at a low voltage VL. Switch signals S1 and S3 (= phase signal P1) can be at a high voltage VH, switches 10 and 30 are turned on, and switch signals S2 and S4 (= phase signal P2) can be at a low voltage VL, switches 20 and 40 are turned off, so that the first terminal of the flying capacitor 50 receives the input voltage Vin through switch 10, and the second terminal of the flying capacitor 50 is coupled to the first terminal of the inductor 60 through switch 30. Therefore, the input voltage Vin charges the flying capacitor 50 and the output capacitor 70 via inductor 60 and magnetizes and demagnetizes the inductor L. At this time, the flying capacitor 50 and the output capacitor 70 can form a voltage divider to generate the output voltage Vo, and the flying capacitor 50 and the inductor 60 can form a resonant circuit to make the inductor current IL oscillate at the resonant frequency. In some embodiments, the capacitance values ​​of the flying capacitor 50 and the output capacitor 70 can be equal, therefore the voltage across the flying capacitor 50 and the output capacitor 70 are equal, and both the switching voltage Vx and the output voltage Vo are equal to half of the input voltage Vin.

[0085] At time t3, the inductor current IL reaches 0A, triggering pulse Pz2 on the zero-crossing signal SZ. Simultaneously, pulse Pz2 triggers phase signal P1 to switch from high voltage VH to low voltage VL, while phase signal P2 remains at low voltage VL. At time t4, pulse Pz2 triggers phase signal P2 to switch from low voltage VL to high voltage VH, while phase signal P1 remains at low voltage VL, and pulse Pz2 on the zero-crossing signal SZ ends. Pulse Pz2 can have the same predetermined width as pulse Pz1; for example, the predetermined width of pulse Pz2 (t4-t3) is equal to the predetermined width of pulse Pz1 (t2-t1). The time period between t1 and t3 is called the first stage Ph1.

[0086] Between time t4 and time t5, phase signal P1 remains at a low voltage VL, phase signal P2 remains at a high voltage VH, inductor current IL oscillates at the resonant frequency, and zero-crossing signal SZ remains at a low voltage VL. Switch signals S1 and S3 (= phase signal P1) can be at a low voltage VL, switches 10 and 30 are off, and switch signals S2 and S4 can be at a high voltage VH, switches 20 and 40 are on, so that the first terminal of flying capacitor 50 is coupled to the first terminal of inductor 60 through switch 20, and the second terminal of flying capacitor 50 is coupled to ground through switch 40. Flying capacitor 50 can act as a voltage source to charge output capacitor 70 and excite inductor L. Therefore, the voltage across flying capacitor 50 can be equal to the output voltage Vo. If the voltage across flying capacitor 50 is equal to half of the input voltage Vin, then the output voltage Vo is also equal to half of the input voltage Vin. Meanwhile, the flying capacitor 50 and the inductor 60 can form a resonant circuit so that the inductor current IL oscillates at the resonant frequency.

[0087] At time t5, the inductor current IL reaches 0A, triggering pulse Pz3 on the zero-crossing signal SZ. Simultaneously, pulse Pz3 triggers phase signal P2 to switch from high voltage VH to low voltage VL, while phase signal P1 remains at low voltage VL. At time t6, pulse Pz3 triggers phase signal P1 to switch from low voltage VL to high voltage VH, while phase signal P2 remains at low voltage VL, and pulse Pz3 on the zero-crossing signal SZ ends. Pulse Pz3 can have the same predetermined width as pulse Pz1; for example, the predetermined width of pulse Pz1 (t6-t5) is equal to the predetermined width of pulse Pz1 (t2-t1). The time period between t3 and t5 is called the second stage Ph2.

[0088] Subsequently, if the control circuit 800 continues to determine that the power converter 1 can operate in the non-adjustment mode, the power converter 1 will continue to switch switches 10, 20, 30 and 40 according to the resonant frequency to repeat the waveform for time t2 to t6, thereby outputting the output voltage Vo to the load.

[0089] In step S204, power converter 1 operates in regulation mode. During two-stage operation, the switching signals S1 to S4 can be different, and power converter 1 can alternately operate in the first stage Ph1 and the second stage Ph2, such as... Figure 4 As shown, Figure 4 Details will be explained in later paragraphs. During single-stage operation, switch signals S1 and S2 can be identical, allowing switches 10 and 20 to switch synchronously, and switch signals S3 and S4 can be identical, allowing switches 30 and 40 to switch synchronously. Power converter 1 can repeat operation in the first stage, Ph1, as follows: Figure 5 As shown, Figure 5 The details will be explained in later paragraphs.

[0090] Figure 4 This is a waveform diagram of power converter 1 during two-stage operation, where the horizontal axis represents time and the vertical axis represents voltage or current. See also the following: Figure 1 and Figure 4 The following explains the operation of power converter 1 in two-stage operation. Control circuit 800 generates switching signal S1 based on phase signal P1, switching signal S2 based on phase signal P2, switching signal S3 based on phase signals P1, PA, and PB, and switching signal S4 based on phase signals P1, PA, and PB, thereby adjusting the output voltage Vo to be less than or equal to the upper limit of the output voltage. In the first stage Ph1, phase signal P2 is maintained at a low voltage VL; and in the second stage Ph2, phase signal P1 is maintained at a low voltage VL. Switching signal S1 can be equal to phase signal P1, switching signal S2 can be equal to phase signal P2, switching signal S3 can be equal to the OR operation result of phase signals P1, PA, and PB, and switching signal S4 can be equal to the OR operation result of phase signals P2, PA, and PB. The generation methods of phase signals P1, P2, PA, and PB will be explained in later paragraphs.

[0091] At time t1, the inductor current IL reaches 0A, triggering the phase signal PB to switch from high voltage VH to low voltage VL and triggering the phase signal P1 to switch from low voltage VL to high voltage VH. The phase signals PA and P2 remain at low voltage VL, causing the switching signal S1 to switch from low voltage VL to high voltage VH, the switching signal S2 to remain at low voltage VL, the switching signal S3 to remain at high voltage VH, and the switching signal S4 to switch from high voltage VH to low voltage VL. Therefore, when the inductor current IL reaches 0A, the switch 40 will be turned off, achieving ZCS and reducing switching losses.

[0092] Between time t1 and time t2, switch signals S1 and S3 are maintained at a high voltage VH, and switch signals S2 and S4 are maintained at a low voltage VL, causing switches 10 and 30 to conduct and switches 20 and 40 to be turned off. The first terminal of the flying capacitor 50 receives the input voltage Vin through switch 10, and the second terminal of the flying capacitor 50 is coupled to the first terminal of the inductor 60 through switch 30. Therefore, the input voltage Vin charges the flying capacitor 50 and the output capacitor 70 and excites the inductor L. At this time, the flying capacitor 50 and the inductor 60 can form a resonant circuit, causing the inductor current IL to start to rise.

[0093] At time t2, the input voltage Vin exceeds the input voltage threshold, triggering phase signal P1 to switch from high voltage VH to low voltage VL and triggering phase signal PA to switch from low voltage VL to high voltage VH. Phase signals P2 and PB remain at low voltage VL, causing switch signal S1 to switch from high voltage VH to low voltage VL, switch signal S2 to remain at low voltage VL, switch signal S3 to remain at high voltage VH, and switch signal S4 to switch from low voltage VL to high voltage VH. Therefore, when the inductor 60 is energized, the control circuit 800 can turn off switch 10 before the inductor current IL of inductor 60 reaches 0, thereby reducing the conduction time of switch 10.

[0094] Between time t2 and time t3, switch signals S1 and S2 are maintained at a low voltage VL, and switch signals S3 and S4 are maintained at a high voltage VH, causing switches 10 and 20 to be off and switches 30 and 40 to be on. The first terminal of inductor 60 is coupled to ground via switches 30 and 40, therefore inductor 60 will be demagnetized and pulled down to 0A before the inductor current IL reaches its peak value. Because inductor 60 is coupled to ground, the rate of decrease of the inductor current IL will significantly exceed that of the grounding process. Figure 3 The rate of decrease of the inductor current IL due to resonance, and Figure 4 The time for one excitation and demagnetization of inductor 60 (=t3-t1) will be less than Figure 3 The time for one excitation and demagnetization of inductor 60 is (t3-t1). Therefore, control circuit 800 will switch switches 10, 20, 30 and 40 according to the adjustment frequency exceeding the resonant frequency. The time period between t1 and t3 is called the first stage Ph1.

[0095] At time t3, the inductor current IL reaches 0A, triggering phase signal PA to switch from high voltage VH to low voltage VL and triggering phase signal P2 to switch from low voltage VL to high voltage VH. Phase signals PB and P1 remain at low voltage VL, causing switching signal S1 to remain at low voltage VL, switching signal S2 to switch from low voltage VL to high voltage VH, switching signal S3 to switch from high voltage VH to low voltage VL, and switching signal S4 to remain at high voltage VH. Therefore, when the inductor current IL reaches 0A, switch 30 will be turned off, achieving ZCS and reducing switching losses.

[0096] Between time t3 and time t4, switch signals S2 and S4 are maintained at a high voltage VH, and switch signals S1 and S3 are maintained at a low voltage VL, causing switches 20 and 40 to conduct and switches 10 and 30 to be turned off. The first terminal of the flying capacitor 50 is coupled to the first terminal of the inductor 60 via switch 20, and the second terminal of the flying capacitor 50 is coupled to the ground terminal via switch 40. The flying capacitor 50 can act as a voltage source to charge the output capacitor 70 and excite the inductor L. The flying capacitor 50 and the inductor 60 can form a resonant circuit to cause the inductor current IL to start rising.

[0097] At time t4, the input voltage Vin exceeds the input voltage threshold, triggering phase signal P2 to switch from high voltage VH to low voltage VL and triggering phase signal PB to switch from low voltage VL to high voltage VH. Phase signals P1 and PA remain at low voltage VL, causing switch signal S1 to remain at low voltage VL, switch signal S2 to switch from high voltage VH to low voltage VL, switch signal S3 to switch from low voltage VL to high voltage VH, and switch signal S4 to remain at high voltage VH. Therefore, when the inductor 60 is energized, the control circuit 800 can turn off switch 20 before the inductor current IL of inductor 60 reaches 0, thereby reducing the conduction time of switch 20 and switching switch 20 at an adjustment frequency exceeding the resonant frequency.

[0098] Between time t4 and time t5, switching signals S1 and S2 are maintained at a low voltage VL, and switching signals S3 and S4 are maintained at a high voltage VH, causing switches 10 and 20 to be off and switches 30 and 40 to be on. The first terminal of inductor 60 is coupled to ground via switches 30 and 40, thus inductor 60 will be demagnetized and pulled down to 0A before the inductor current IL reaches its peak value. The period between time t3 and t5 is called the second stage Ph2. Because inductor 60 is coupled to ground, the rate of decrease of the inductor current IL will significantly exceed that of the second stage Ph2. Figure 3 The rate of decrease of the inductor current IL due to resonance, and Figure 4 The time for one excitation and demagnetization of inductor 60 (=t5-t3) will be less than Figure 3 The time for one excitation and demagnetization of inductor 60 is (t5-t3). Therefore, the control circuit 800 will switch switches 10, 20, 30 and 40 according to the adjustment frequency exceeding the resonant frequency.

[0099] Subsequently, if the control circuit 800 continues to determine that the power converter 1 can operate in two stages, the power converter 1 will continue to operate alternately in the first stage Ph1 and the second stage Ph2. The operation mode of the power converter 1 from time t5 to time t9 is similar to that from time t1 to time t5, and the explanation can be found in the preceding paragraphs, so it will not be repeated here.

[0100] and Figure 2Compared to the previous embodiment, Figure 3 In some embodiments, the control circuit 80 can reduce the ON time of switch 10 or switch 20 and increase the simultaneous ON time of switch 30 and switch 40, thereby switching switches 10, 20, 30 and 40 according to an adjustment frequency exceeding the resonant frequency, thereby adjusting the output voltage Vo to be equal to or less than the output voltage threshold value. In some embodiments, when the output voltage Vo exceeds the output voltage threshold value, the control circuit 800 can turn off switch 10 or switch 20 before the inductor current IL of inductor 60 reaches 0 when magnetizing inductor 60. Then, after turning off switch 10 or switch 20, the control circuit 800 can turn on switch 30 and switch 40 to demagnetize inductor 60, and when demagnetizing inductor 60, the control circuit 800 can turn off switch 30 or switch 40 when the inductor current IL of inductor 60 reaches 0. In some embodiments, when the power converter 1 is in a light load state, the control circuit 800 may additionally add the off time of switches 10, 20, 30 and 40.

[0101] In some embodiments, when the power converter 1 is under light load, the control circuit 800 can increase the dead-time delay between phase signals P1 and PA, PA and P2, P2 and PB, and PB and P1, thereby increasing the OFF time of switches 10 and 20, 30 and 40, and thus achieving power saving. When there is a dead-time delay between phase signals P1 and PA, PA and P2, P2 and PB, and PB and P1, Figure 4 Each pulse of switching signals S3 and S4 can be replaced by three sub-pulse waves. For example, the start time of the first sub-pulse wave of switching signal S3 can be later than... Figure 4 The start time of the original pulse wave of the switching signal S3, and the end time of the third sub-pulse wave of the switching signal S3 can be later than... Figure 4 The end time of the original pulse wave of the switching signal S3, and the pulse width of each sub-pulse wave is less than 1 / 3. Figure 4 The pulse width of the original pulse wave of the switching signal S3 is specified, and there may be a time interval between two adjacent sub-pulse waves. Similarly, the start time of the first sub-pulse wave of the switching signal S4 may be later than [the specified time]. Figure 4 The start time of the original pulse wave of the switching signal S4, and the end time of the third sub-pulse wave of the switching signal S4 can be later than... Figure 4 The end time of the original pulse wave of the switching signal S4, and the pulse width of each sub-pulse wave is less than 1 / 3. Figure 4 The pulse width of the original pulse wave of the switching signal S4, and there may be a time interval between two adjacent sub-pulse waves.

[0102] Figure 5This is a waveform diagram of power converter 1 in single-stage operation, where the horizontal axis represents time and the vertical axis represents voltage or current. Figure 6A , Figure 6B , Figure 6C , Figure 6D This is a schematic diagram of the current during periods T1 to T4 of power converter 1 in single-stage operation. The following also refers to... Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D To illustrate the operation of power converter 1 in a single-stage operation, control circuit 800 generates switching signals S1 and S2 based on phase signal P1, and switching signals S3 and S4 based on phase signal PA, thereby adjusting the output voltage Vo to be less than or equal to the input voltage Vin. Control circuit 800 can switch switches 10, 20, 30, and / or 40 when inductor current IL flows from the second terminal to the first terminal of inductor 60. Switching signals S1 and S2 can be equal to phase signal P1, and switching signals S3 and S4 can be equal to phase signal PA. The generation methods of phase signals P1 and PA will be explained in later paragraphs.

[0103] At time t1, the inductor current IL is between its minimum value Imin and 0A, and the switching voltage Vx is equal to the input voltage Vin. Phase signal P1 switches from low voltage VL to high voltage VH, while phase signal PA remains at low voltage VL. The minimum value Imin is a negative current approaching 0A, for example, Imin = -0.1A. Therefore, switching signals S1 and S2 switch from low voltage VL to high voltage VH, while switching signals S3 and S4 remain at low voltage VL, causing switches 10 and 20 to conduct and switches 30 and 40 to turn off. Since the inductor current IL is between its minimum value Imin and 0A and the switching voltage Vx is equal to the input voltage Vin, switches 10 and 20 achieve ZCS (zero-voltage switching) and ZVS (zero-voltage switching), reducing switching losses. Between times t1 and t2, switching signals S1 and S2 remain at a high voltage VH, switching signals S3 and S4 remain at a low voltage VL, the switching voltage Vx remains at the input voltage Vin, and the inductor current IL continues to rise. Figure 6A As shown. The time interval from t1 to t2 can be referred to as time period T1. (Reference) Figure 6A During time period T1, the switching voltage Vx is equal to the input voltage Vin, and the inductor current IL flows sequentially from the first terminal of switch 10 through switch 10, switch 20 and inductor 60 to charge the output capacitor 70.

[0104] At time t2, the output voltage Vo reaches its preset value. Phase signal P1 switches from high voltage VH to low voltage VL, and phase signal PA switches from low voltage VL to high voltage VH. The inductor current IL reaches its maximum value Imax, and the switching voltage Vx switches to a negative voltage V-. The maximum value Imax is a positive current far exceeding 0A, for example, Imax = 3A. The negative voltage V- is a negative voltage close to 0V, for example, V- = -10mV. Therefore, switching signals S1 and S2 switch from high voltage VH to low voltage VL, and switching signals S3 and S4 switch from low voltage VL to high voltage VH, causing switches 10 and 20 to turn off, and switches 30 and 40 to turn on. Between times t2 and t3, switching signals S1 and S2 remain at low voltage VL, switching signals S3 and S4 remain at high voltage VH, the switching voltage Vx remains at a negative voltage V-, and the inductor current IL decreases from its maximum value Imax. The time period from t2 to t3 can be called time period T2. (Reference) Figure 6B During time period T2, the switching voltage Vx is a negative voltage V-, and the inductor current IL flows sequentially from the ground terminal through switch 40, switch 30 and inductor 60 to demagnetize inductor 60, while the switching voltage Vx remains at the negative voltage V-.

[0105] At time t3, the inductor current IL reaches 0A, the switching voltage Vx switches to 0V, phase signal P1 remains at a low voltage VL, and phase signal PA remains at a high voltage VH. Therefore, switching signals S1 and S2 remain at a low voltage VL, and switching signals S3 and S4 remain at a high voltage VH. Between times t3 and t4, switching signals S1 and S2 remain at a low voltage VL, and switching signals S3 and S4 remain at a high voltage VH, causing switches 10 and 20 to remain off, and switches 30 and 40 to remain on. The inductor current IL decreases from 0A, and the switching voltage Vx remains at 0V. Figure 6C As shown. The time interval from t3 to t4 can be referred to as time period T3. (Reference) Figure 6C During time period T3, the switching voltage V is 0V, inductor 60 is completely demagnetized, and the inductor current IL flows sequentially through inductor 60, switch 30, and switch 40 to reduce the inductor current IL to a negative value. The length of time period T3 is positively correlated with the magnitude of the inductor current IL. The longer the time period T3, the larger the magnitude of the inductor current IL.

[0106] At time t4, phase signal P1 remains at a low voltage VL, while phase signal PA switches from a high voltage VH to a low voltage VL. The inductor current IL reaches its minimum value Imin, and the switching voltage Vx switches to the input voltage Vin. Therefore, switching signals S1 and S2 remain at a low voltage VL, and switching signals S3 and S4 switch from a high voltage VH to a low voltage VL, causing switches 10 and 20 to turn off, and switches 30 and 40 to turn off. Between times t4 and t5, switching signals S1 and S2 remain at a low voltage VL, and switching signals S3 and S4 remain at a low voltage VL. The inductor current IL rises from its minimum value Imin, and the switching voltage Vx remains at the input voltage Vin. The time period from t4 to t5 can be referred to as time period T4. (Reference) Figure 6D During time period T4, the switching voltage Vx equals the input voltage Vin. Since switches 30 and 40 are off, the inductor current IL flows sequentially through inductor 60, the body diode of switch 20, and the body diode of switch 10 to the first terminal of switch 10. The time period between t1 and t4 is called the first stage Ph1.

[0107] Subsequently, if the control circuit 800 continues to determine that the power converter 1 can operate in a single-stage operation, the power converter 1 will continue to repeat the first stage Ph1.

[0108] exist Figure 4 In one embodiment, the control circuit 800 turns off switches 30 and 40 only after the inductor current IL reaches 0A, thereby achieving both ZCS and ZVS simultaneously. In other embodiments, the control circuit 800 may also turn off switches 30 and 40 when the inductor current IL reaches 0 during single-stage operation, thereby achieving ZCS. In still other embodiments, the control circuit 800 may also turn off switches 10, 20, 30, and 40 before the inductor current IL reaches 0 during single-stage operation, thereby increasing the average inductor current IL, shortening the period of the first stage Ph1, increasing the adjustment frequency, and increasing circuit efficiency.

[0109] Although Figure 2 and Figure 3 The embodiments described only illustrate the implementation of the cut-off switches 10, 20, 30 and / or 40 when the inductor current IL reaches 0 in non-regulation mode and two-stage operation, respectively. Those skilled in the art can also refer to them. Figure 4In the embodiments, the principle of generating a negative inductor current IL is that the control circuit 800 only cuts off switches 10, 20, 30, and / or 40 after the inductor current IL reaches 0A, thereby achieving ZCS and ZVS simultaneously in non-regulation mode and two-stage operation, reducing switching losses. Furthermore, in some embodiments, the control circuit 800 may also cut off switches 10, 20, 30, and / or 40 before the inductor current IL reaches 0 in non-regulation mode and / or two-stage operation, thereby increasing the average inductor current IL, shortening the period of the first stage Ph1, increasing the regulation frequency, and increasing circuit efficiency.

[0110] Furthermore, the control circuit 80 can reduce the ON time of switch 10 or switch 20 and increase the simultaneous ON time of switch 30 and switch 40, thereby switching switches 10, 20, 30 and 40 according to an adjustment frequency exceeding the resonant frequency, thereby adjusting the output voltage Vo to be equal to or less than the output voltage threshold value. In some embodiments, when the output voltage Vo exceeds the output voltage threshold value, the control circuit 800 can turn off switch 10 or switch 20 before the inductor current IL of inductor 60 reaches 0 when magnetizing inductor 60. Then, after turning off switch 10 or switch 20, the control circuit 800 can turn on switch 30 and switch 40 to demagnetize inductor 60, and when demagnetizing inductor 60, the control circuit 800 can turn off switch 30 or switch 40 when the inductor current IL of inductor 60 reaches 0. In some embodiments, when the power converter 1 is in a light load state, the control circuit 800 may additionally add the off time of switches 10, 20, 30 and 40.

[0111] Figure 7 This is a schematic diagram of a portion of the control circuit 800. The control circuit 800 may include a signal generation circuit 801. The signal generation circuit 801 generates switching signals S1 to S4 based on phase signals P1, P2, PA, and PB and a mode signal MODE. The signal generation circuit 801 may include buffers 80 to 83, OR gates 84, 85, 86, 88, and 89, AND gates 90 to 95, and inverters 96 to 98. The mode signal MODE can be enabled during single-stage operation and disabled during non-adjustment mode and two-stage operation. The mode signal MODE can be used to disable switching signals S2 and S4.

[0112] The buffer 80 includes an input terminal for receiving the phase signal P1 and an output terminal for outputting the switching signal S1. The phase signal P1 can generate the switching signal S1 after passing through the buffer 80. Therefore, the switching signal S1 can be the signal of the phase signal P1 after a gate delay.

[0113] Inverter 96 includes an input terminal for receiving the mode signal MODE and an output terminal. AND gate 90 includes a first input terminal for receiving the phase signal P2, a second input terminal coupled to the output terminal and the output terminal of inverter 96. AND gate 91 includes a first input terminal for receiving the mode signal MODE, a second input terminal for receiving the phase signal P1, and an output terminal. OR gate 84 includes a first input terminal coupled to the output terminal of AND gate 90, a second input terminal coupled to the output terminal and the output terminal of AND gate 91. Buffer 81 includes an input terminal coupled to the output terminal and the output terminal of OR gate 84, and is used to output a switch signal S2. When the mode signal MODE is enabled, the switch signal S2 can be the phase signal P1 after a delay. When the mode signal MODE is disabled, the switch signal S2 can be the phase signal P2 after a gate delay.

[0114] OR gate 88 includes a first input terminal for receiving phase signal P1, a second input terminal for receiving phase signal PA, a third input terminal for receiving phase signal PB, and an output terminal. Inverter 97 includes an input terminal for receiving mode signal MODE and an output terminal. AND gate 92 includes a first input terminal coupled to the output terminal of OR gate 88, a second input terminal coupled to the output terminal of inverter 97, and an output terminal. AND gate 93 includes a first input terminal for receiving mode signal MODE, a second input terminal for receiving phase signal PA, and an output terminal. OR gate 85 includes a first input terminal coupled to the output terminal of AND gate 92, a second input terminal coupled to the output terminal of AND gate 93, and an output terminal. Buffer 82 includes an input terminal coupled to the output terminal of OR gate 85 and an output terminal for outputting switch signal S3. When mode signal MODE is enabled, switch signal S3 can be the phase signal PA after a delay. When the mode signal MODE is disabled, the switch signal S3 can be the result of the OR operation of phase signals P1, PA and PB, after a gate delay.

[0115] OR gate 89 includes a first input terminal for receiving phase signal P2, a second input terminal for receiving phase signal PA, a third input terminal for receiving phase signal PB, and an output terminal. Inverter 98 includes an input terminal for receiving mode signal MODE and an output terminal. AND gate 94 includes a first input terminal coupled to the output terminal of OR gate 89, a second input terminal coupled to the output terminal of inverter 98, and an output terminal. AND gate 95 includes a first input terminal for receiving mode signal MODE, a second input terminal for receiving phase signal PA, and an output terminal. OR gate 86 includes a first input terminal coupled to the output terminal of AND gate 94, a second input terminal coupled to the output terminal of AND gate 95, and an output terminal. Buffer 83 includes an input terminal coupled to the output terminal of OR gate 86 and an output terminal for outputting switch signal S4. Switch signal S4 can be the phase signal PA after a certain delay. When the mode signal MODE is disabled, the switch signal S4 can be the result of the OR operation of phase signals P2, PA and PB, after a gate delay.

[0116] Figure 8 This is a schematic diagram of other parts of the control circuit 800. The control circuit 800 may also include a feedback circuit 802. The feedback circuit 802 can generate a feedback signal SFB to regulate the output voltage Vo. The feedback signal SFB can indicate that the input voltage Vin exceeds the input voltage threshold or the output voltage Vo exceeds the output voltage upper limit, and can be used to reset the phase signals P1 and / or P2 to a low voltage VL earlier, thereby reducing the on-time of switches 10 and / or 20 and increasing the regulation frequency. The feedback circuit 802 may include a NOR gate 110, a current source 112, a transistor 111, capacitors 113 and 152, resistors 114, 115, 116, 117 and 151, a switch 120, an error amplifier 150, and a comparator 155.

[0117] NOR gate 110 includes a first input terminal for receiving phase signal P1, a second input terminal for receiving phase signal P2, and an output terminal for outputting the result of the OR operation of phase signals P1 and P2. Current source 112 includes a first terminal coupled to a power supply terminal for receiving the power supply voltage Vcc, and a second terminal. Transistor 111 includes a control terminal coupled to the output terminal of NOR gate 110 for receiving the operation result of NOR gate 110, a first terminal coupled to the second terminal of current source 112, and a second terminal coupled to ground. Capacitor 113 includes a first terminal coupled to the first terminal and the second terminal of transistor 111, and a second terminal coupled to ground. NOR gate 110, current source 112, transistor 111, and capacitor 113 can form a ramp circuit. When phase signal P1 or phase signal P2 is a high voltage VH, the ramp circuit can generate a gradually rising ramp signal RAMP. When both phase signal P1 and / or phase signal P2 are at low voltage VL, the ramp circuit can reset the ramp signal RAMP to ground voltage GND.

[0118] Resistor 114 includes a first terminal for receiving the output voltage Vo and a second terminal. Resistor 115 includes a first terminal, coupled to the second terminal of resistor 114, and the second terminal is coupled to ground. Resistor 116 includes a first terminal for receiving a reference voltage VR and a second terminal. The reference voltage VR can be set to 2V or other suitable values. In some embodiments, the power converter 1 can use the same reference voltage VR, such as 2V, for both single-stage and two-stage operation. In some embodiments, the power converter 1 can use different reference voltages VR for single-stage and two-stage operation; for example, the reference voltage VR for single-stage operation can be 1.6V, and the reference voltage VR for two-stage operation can be 2V. Resistor 117 includes a first terminal, coupled to the second terminal of resistor 116. Switch 120 includes a control terminal for receiving a closed-loop signal CLP, a first terminal coupled to the second terminal of resistor 116, and the second terminal is coupled to ground. Resistors 114 and 115 can form a voltage divider to generate a voltage division based on the output voltage Vo. For example, resistor 114 can have a resistance of 9k ohms, and resistor 115 can have a resistance of 1k ohms, used to enable the voltage divider to produce a 10:1 voltage division ratio. If the output voltage Vo is 20V, then the first terminal of resistor 115 can generate 2V as a voltage divider for the output voltage Vo. Error amplifier 150 includes an inverting input terminal coupled to the second terminal of resistor 114, a non-inverting input terminal coupled to the second terminal of resistor 116, and an output terminal. Resistor 151 includes a first terminal coupled to the output terminal and a second terminal of error amplifier 150. Capacitor 152 includes a first terminal coupled to the second terminal of resistor 114, and a second terminal coupled to ground. When the closed-loop signal CLP is a low voltage VL, switch 120 can be turned off, and error amplifier 150 can compare the voltage divider of the output voltage Vo with the reference voltage VR to generate an error amplification signal COMP. The error amplification signal COMP can be a stable voltage level and is related to the output voltage Vo. If the voltage division of the output voltage Vo exceeds the reference voltage VR, the error amplification signal COMP will decrease; if the voltage division of the output voltage Vo is less than the reference voltage VR, the error amplification signal COMP will increase. For example, if the reference voltage VR is 2V and the voltage division of the output voltage Vo is 2V, the error amplifier 150 can set the error amplification signal COMP to 3V; if the reference voltage VR is 2V and the voltage division of the output voltage Vo is 2.2V, the error amplifier 150 can set the error amplification signal COMP to 2.8V; if the reference voltage VR is 2V and the voltage division of the output voltage Vo is 1.8V, the error amplifier 150 can set the error amplification signal COMP to 3.2V.

[0119] The closed-loop signal CLP indicates the operating mode of power converter 1. If the closed-loop signal CLP is a low voltage VL, power converter 1 operates in non-regulated mode; if the closed-loop signal CLP is a high voltage VH, power converter 1 operates in regulated mode. When the closed-loop signal CLP is a high voltage VH, switch 120 can be turned on, and resistors 116 and 117 can form a voltage divider to generate a voltage division based on the reference voltage VR. Error amplifier 150 compares the voltage division of output voltage Vo with the voltage division of reference voltage VR to generate an amplified error signal COMP. For example, resistor 116 can have a resistance of 1k ohms, and resistor 117 can have a resistance of 9k ohms, to enable the voltage divider to produce a 10:9 voltage division ratio. If the reference voltage VR is 2V, then a 1.8V voltage can be generated at the first terminal of resistor 117 as the reference voltage VR. Error amplifier 150 can decrease the level of error amplification signal COMP when the voltage division of output voltage Vo exceeds 1.8V, and increase the level of error amplification signal COMP when the voltage division of output voltage Vo is less than 1.8V. The closed-loop signal CLP can provide hysteresis control for the reference voltage VR. Resistor 151 and capacitor 152 can form a low-pass filter to filter the error amplification signal COMP. In some embodiments, resistor 151 and capacitor 152 can be omitted, and the error amplification signal COMP can be directly input to comparator 155.

[0120] Comparator 155 includes a positive input terminal coupled to the first terminal of capacitor 113, an inverting input terminal coupled to the first terminal of resistor 151, and an output terminal for outputting a feedback signal SFB. Comparator 155 can compare the ramp signal RAMP and the error amplification signal COMP. When the ramp signal RAMP is less than the error amplification signal COMP, comparator 155 can set the feedback signal SFB to a low voltage VL. Once the ramp signal RAMP reaches the error amplification signal COMP, comparator 155 can insert a positive pulse with a preset width into the feedback signal SFB.

[0121] As described in the preceding paragraphs, if the voltage division of the output voltage Vo exceeds the reference voltage VR, the error amplification signal COMP will decrease, causing the ramp signal RAMP to reach the error amplification signal COMP more quickly, thereby generating the feedback signal SFB faster. Furthermore, when the closed-loop signal CLP is a high voltage VH, the error amplification signal COMP will decrease further, causing the ramp signal RAMP to reach the error amplification signal COMP even faster, thus generating the feedback signal SFB more quickly and stably, thereby increasing the reliability of the feedback signal SFB.

[0122] Figure 9 This is a waveform diagram of the 802 feedback circuit, where the horizontal axis represents time and the vertical axis represents voltage. The following is a combination of... Figure 8Explain how the feedback circuit 802 operates.

[0123] Between times t1 and t2, phase signal P1 is at a high voltage VH, triggering the ramp signal RAMP to rise. Simultaneously, phase signal P2 and feedback signal SFB remain at a low voltage VL. At time t2, the ramp signal RAMP and the error amplifier signal COMP are equal, triggering pulse Pfb1 on the feedback signal SFB. Pulse Pfb1 switches phase signal P1 to a low voltage VL, and since both phase signals P1 and P2 are at a low voltage VL, the ramp signal RAMP is reset to a low voltage VL. At time t3, pulse Pfb1 ends, and phase signals P1 and P2, as well as the ramp signal RAMP, remain at a low voltage VL. Between times t3 and t4, phase signals P1 and P2, the ramp signal RAMP, and the feedback signal SFB all remain at a low voltage VL. In single-stage operation, if the input voltage Vin is too low, for example, if the reference voltage VR is 2V and the input voltage Vin is 10V, the ramp signal RAMP will remain less than the error amplification signal COMP, so the comparator 155 will not generate the pulse in the feedback signal SFB.

[0124] Between times t4 and t5, phase signal P2 is at a high voltage VH, triggering the ramp signal RAMP to rise. Simultaneously, phase signal P1 and feedback signal SFB remain at a low voltage VL. At time t5, the ramp signal RAMP and the error amplifier signal COMP are equal, triggering pulse Pfb2 on the feedback signal SFB. Pulse Pfb2 triggers phase signal P2 to switch to a low voltage VL. Since both phase signals P1 and P2 are at a low voltage VL, the ramp signal RAMP is reset to a low voltage VL. At time t6, pulse Pfb2 ends, and phase signals P1 and P2, as well as the ramp signal RAMP, all remain at a low voltage VL.

[0125] The feedback circuit 802 can repeat the waveform from time t1 to t2 to generate a feedback signal SFB.

[0126] Figure 10 This is a schematic diagram of other parts of the control circuit 800. The control circuit 800 may also include a state detection circuit 803 and a closed-loop circuit 804. The state detection circuit 803 can generate a zero-crossing signal SZ and a cutoff signal SP. The zero-crossing signal SZ indicates that the voltage across inductor 60 is 0V, and the cutoff signal SP can be used to cut off switches 30 and 40. The closed-loop circuit 804 can generate a closed-loop signal CLP, which indicates the operating mode of the power converter 1. When the closed-loop signal CLP is a high voltage VH, it indicates that the power converter 1 is operating in regulation mode, and when the closed-loop signal CLP is a low voltage VL, it indicates that the power converter 1 is operating in non-regulation mode.

[0127] The state detection circuit 803 may include comparators 210 and 220, a zero-crossing detector (ZCD) 250, a pulse generator 223, and an AND gate 225. Comparator 210 includes a positive input for receiving the switching voltage Vx, an inverting input for receiving the output voltage Vo, and an output for outputting the comparison result of the switching voltage Vx and the output voltage Vo. The switching voltage Vx is the voltage at the first terminal of inductor 60, and the output voltage Vo is the voltage at the second terminal of inductor 60. When the switching voltage Vx is detected to exceed the output voltage Vo, comparator 210 outputs a high voltage VH as the comparison result; when the switching voltage Vx is detected to be less than the output voltage Vo, comparator 210 outputs a low voltage VL as the comparison result. The zero-crossing detector 250 includes an input coupled to the output of comparator 210 for receiving the comparison result of the switching voltage Vx and the output voltage Vo, and an output for outputting a zero-crossing signal SZ. When the comparator 210 detects that the two consecutive comparison results switch from high voltage VH to low voltage VL or from low voltage VL to high voltage VH, the zero-crossing detector 250 can generate a pulse with a predetermined width on the zero-crossing signal SZ; when the comparator 210 detects that the two consecutive comparison results are both high voltage VH or both are low voltage VH, the zero-crossing detector 250 can set the zero-crossing signal SZ to low voltage VL.

[0128] Comparator 220 includes a positive input terminal for receiving the switching voltage Vx, an inverting input terminal for receiving the demagnetizing reference voltage VT, and an output terminal for outputting the comparison result of the switching voltage Vx and the demagnetizing reference voltage VT as the demagnetizing signal SDM. The demagnetizing reference voltage VT can be set to 0V. The switching voltage Vx can be equal to the voltage across switches 30 and 40. If inductor 60 is completely demagnetized, the switching voltage Vx will reach its peak value. When the switching voltage Vx exceeds the demagnetizing reference voltage VT, comparator 220 can set the demagnetizing signal SDM to a high voltage VH; when the switching voltage Vx is less than the demagnetizing reference voltage VT, comparator 220 can set the demagnetizing signal SDM to a low voltage VL. Pulse generator 223 includes an enable terminal for receiving the control signal ZM, an input terminal for receiving the demagnetizing signal SDM, and an output terminal. AND gate 225 includes a first input terminal for receiving the demagnetizing signal SDM, a second input terminal coupled to the output terminal of pulse generator 223, and an output terminal for outputting a cutoff signal SP. Control signal ZM can be used to control the ZVS operation of power converter 1. Control signal ZM can be enabled in single-stage operation and disabled in non-regulation mode and two-stage operation.

[0129] When the control signal ZM is disabled, the cutoff signal SP can be the signal after the demagnetizing signal SDM has undergone a gate delay. When the control signal ZM is enabled, the pulse generator 223 can generate a negative pulse on the cutoff signal SP after receiving the demagnetizing signal SDM and after a first predetermined delay. The cutoff signal SP can be the signal after a first predetermined delay. The length of the first predetermined delay is equal to... Figure 5 The length of the mid-term T3.

[0130] The closed-loop circuit 804 may include inverters 261 and 267, a flip-flop 260, a pulse generator 265, and an OR gate 263. Inverter 261 includes an input terminal for receiving a zero-crossing signal SZ and an output terminal for outputting the inverted signal of the zero-crossing signal SZ. OR gate 263 includes a first input terminal for receiving a phase signal P1, a second input terminal for receiving a phase signal P2, and an output terminal for outputting the result of the OR operation of phase signals P1 and P2. Pulse generator 265 includes an input terminal for receiving the result of the OR operation of output phase signals P1 and P2 and an output terminal for outputting a first pulse signal. Inverter 267 includes an input terminal for receiving the first pulse signal and an output terminal for outputting a first reset signal. The trigger 260 includes a data input terminal for receiving the inverted zero-crossing signal SZ, a clock terminal for receiving the feedback signal SFB, a reset terminal for receiving the first reset signal, and an output terminal for outputting the closed-loop signal CLP. The closed-loop signal CLP can be generated by the feedback signal SFB and reset by the rising edge of the phase signal P1 or P2.

[0131] Figure 11 and Figure 12 This is a schematic diagram of the other parts of the control circuit 800. Figure 11 The display control circuit 800 may further include a starting circuit 300, and phase circuits 805 and 806. Figure 12 The display control circuit 800 may further include phase circuits 807 and 808. The start circuit 300 generates a start signal Son, phase circuit 805 generates a phase signal P1 and a trigger signal TG1, phase circuit 806 generates a phase signal PA and a trigger signal TGA, phase circuit 807 generates a phase signal P2 and a trigger signal TG2, and phase circuit 808 generates a phase signal PB and a trigger signal TGB. When the closed-loop signal CLP is a low voltage VL (non-regulation mode), phase circuits 805 and 807 are enabled, and phase circuits 806 and 808 are disabled. When the closed-loop signal CLP is a high voltage VH (regulation mode), all phase circuits 805 to 808 are enabled.

[0132] The phase circuit 805 may include AND gates 321 and 322, NOR gate 325, flip-flop 320, and pulse generator 330. AND gate 321 includes a first input for receiving the phase signal P1, a second input for receiving the zero-crossing signal SZ, and an output for outputting the result of the AND operation of the phase signal P1 and the zero-crossing signal SZ. AND gate 322 includes a first input for receiving the phase signal P1, a second input for receiving the feedback signal SFB, and an output for outputting the result of the AND operation of the phase signal P1 and the feedback signal SFB. NOR gate 325 includes a first input coupled to the output of AND gate 321 for receiving the result of the AND operation, a second input coupled to the output of AND gate 322 for receiving the result of the AND operation, and an output for outputting the result of the NOT operation. The trigger 320 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal for receiving the start signal Son, a reset terminal, an output terminal coupled to the NOR gate 325 for receiving the operation result of the NOR gate 325, an output terminal for outputting the phase signal P1, and an inverting output terminal for outputting the inverted signal of the phase signal P1. The pulse generator 330 includes an input terminal for receiving the inverted signal of the phase signal P1, and an output terminal for outputting the trigger signal TG1.

[0133] The phase circuit 806 may include an AND gate 341, a NAND gate 342, a flip-flop 343, and a pulse generator 345. The AND gate 341 includes a first input terminal for receiving a closed-loop signal CLP, a second input terminal for receiving a trigger signal TG1, and an output terminal for outputting the result of the AND operation of the closed-loop signal CLP and the trigger signal TG1. The NAND gate 342 includes a first input terminal for receiving a cutoff signal SP, a second input terminal for receiving a phase signal PA, and an output terminal for outputting the result of the NAND operation of the cutoff signal SP and the phase signal PA. The flip-flop 343 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal coupled to the output terminal of the AND gate 341 for receiving the result of the AND gate 341 operation, a reset terminal coupled to the output terminal of the NAND gate 342 for receiving the result of the NAND gate 342 operation, an output terminal for outputting the phase signal PA, and an inverting output terminal for outputting the inverted signal of the phase signal PA. The pulse generator 345 includes an input terminal for receiving the inverted phase signal PA and an output terminal for outputting the trigger signal TGA.

[0134] Trigger 320 can be triggered by start signal Son to set phase signal P1 to a high voltage VH, and can be reset by zero-crossing signal SZ and / or feedback signal SFB. Pulse generator 330 can generate a time delay for trigger signal TG1. The longer the time delay of trigger signal TG1, the later the start time of phase signal P2 / PA is, increasing the time delay between the end of phase signal P1 and the start of phase signal P2 / PA.

[0135] When the closed-loop signal CLP is a low voltage VL, the phase circuit 806 is disabled. When the closed-loop signal CLP is a high voltage VH, the phase circuit 806 is enabled, and the trigger 343 can be triggered by the trigger signal TG1 to generate the phase signal PA, and can be reset by the cutoff signal SP. The pulse generator 345 can be used to generate the space-time delay (second predetermined delay) of the trigger signal TGA. The longer the space-time delay of the trigger signal TGA, the later the start time of the phase signal P2 is, increasing the space-time delay between the end of the phase signal PA and the start of the phase signal P2. The length of the second predetermined delay is equal to... Figure 5 The length of the mid-term T4.

[0136] The starting circuit 300 may include inverters 311 and 313, AND gates 310, 312, 316 and 317, and OR gates 315 and 318. Inverter 311 includes an input for receiving a closed-loop signal CLP and an output for outputting an inverted signal of the closed-loop signal CLP. AND gate 310 includes a first input for receiving a trigger signal TGB, a second input for receiving the closed-loop signal CLP, and an output. AND gate 312 includes a first input for receiving the inverted signal of the closed-loop signal CLP, a second input for receiving a trigger signal TG2, and an output. OR gate 315 includes a first input coupled to the output of AND gate 310, a second input coupled to the output of AND gate 312, and an output. Inverter 313 includes an input for receiving a mode signal MODE and an output for outputting an inverted signal of the mode signal MODE. AND gate 316 includes a first input terminal coupled to the output terminal of OR gate 315, a second input terminal for receiving the inverted signal of the mode signal MODE, and an output terminal. AND gate 317 includes a first input terminal for receiving the mode signal MODE, a second input terminal for receiving the trigger signal TGA, and an output terminal. OR gate 318 includes a first input terminal coupled to the output terminal of AND gate 316, a second input terminal coupled to the output terminal of AND gate 317, and an output terminal for outputting the start signal Son.

[0137] When the mode signal MODE is enabled, power converter 1 can perform single-stage operation, and the start signal Son can be the trigger signal TGA after a gate delay. When the mode signal MODE is disabled and the loop signal CLP is enabled, power converter 1 can perform two-stage operation, and the start signal Son can be the trigger signal TGB after a gate delay. When the mode signal MODE is disabled and the loop signal CLP is disabled, power converter 1 can operate in non-regulation mode, and the start signal Son can be the trigger signal TG2 after a gate delay.

[0138] The phase circuit 807 may include AND gates 410, 412, 421, and 422, OR gate 415, NOR gate 425, flip-flop 420, pulse generator 430, and inverter 411. AND gate 410 includes a first input for receiving a trigger signal TGA, a second input for receiving a closed-loop signal CLP, and an output for outputting the result of the AND operation of the trigger signal TGA and the closed-loop signal CLP. Inverter 411 includes an input for receiving the closed-loop signal CLP and an output for outputting the inverted signal of the closed-loop signal CLP. AND gate 412 includes a first input coupled to the output of inverter 411 for receiving the inverted signal of the closed-loop signal CLP, a second input for receiving a trigger signal TG1, and an output for outputting the result of the AND operation of the inverted signal of the closed-loop signal CLP and the trigger signal TG1.

[0139] OR gate 415 includes a first input terminal coupled to the output terminal of AND gate 410 for receiving the operation result of AND gate 410, a second input terminal coupled to the output terminal of AND gate 412 for receiving the operation result of AND gate 412, and an output terminal for outputting the result of the OR operation. AND gate 421 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the zero-crossing signal SZ, and an output terminal for outputting the result of the AND operation of the phase signal P2 and the zero-crossing signal SZ. AND gate 422 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the feedback signal SFB, and an output terminal for outputting the result of the AND operation of the phase signal P2 and the feedback signal SFB. NOR gate 425 includes a first input terminal for receiving the operation result of AND gate 421, a second input terminal for receiving the operation result of AND gate 422, and an output terminal for outputting the result of the NOT OR operation.

[0140] Flip-flop 420 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal, an output terminal coupled to OR gate 415 for receiving the operation result of OR gate 415, a reset terminal for receiving the operation result of NOR gate 425, an output terminal for outputting the phase signal P2, and an inverting output terminal for outputting the inverted signal of phase signal P2. Pulse generator 430 includes an input terminal for receiving the inverted signal of phase signal P2, and an output terminal for outputting the trigger signal TG2.

[0141] The phase circuit 808 may include an AND gate 441, a NAND gate 442, a flip-flop 443, and a pulse generator 445. The AND gate 441 includes a first input terminal for receiving a closed-loop signal CLP, a second input terminal for receiving a trigger signal TG2, and an output terminal for outputting the result of the AND operation of the closed-loop signal CLP and the trigger signal TG2. The NAND gate 442 includes a first input terminal for receiving a cutoff signal SP, a second input terminal for receiving a phase signal PB, and an output terminal for outputting the result of the NAND operation of the cutoff signal SP and the phase signal PB. The flip-flop 443 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal for receiving the result of the AND gate 441 operation, a reset terminal for receiving the result of the NAND gate 442 operation, an output terminal for outputting the phase signal PB, and an inverting output terminal for outputting the inverted signal of the phase signal PB. The pulse generator 445 includes an input terminal for receiving the inverted phase signal PB and an output terminal for outputting the trigger signal TGB.

[0142] When the closed-loop signal CLP is at a low voltage VL, AND gate 410 is disabled, and trigger 420 can be triggered by trigger signal TG1 to generate phase signal P2, and can be reset by zero-crossing signal SZ. When the closed-loop signal CLP is at a high voltage VH, AND gate 412 is disabled, and trigger 420 can be triggered by trigger signal TGA to generate phase signal P2, and can be reset by zero-crossing signal SZ and / or feedback signal SFB. Pulse generator 430 can be used to generate a time delay for trigger signal TG2. The longer the time delay of trigger signal TG2, the later the start time of phase signal P1 / PB is, increasing the time between the end of phase signal P2 and the start of phase signal P1 / PB.

[0143] When the closed-loop signal CLP is a low voltage VL, the phase circuit 808 is disabled. When the closed-loop signal CLP is a high voltage VH, the phase circuit 808 is enabled, and the trigger 443 can be triggered by the trigger signal TG2 to generate the phase signal PB, and can be reset by the cutoff signal SP. The pulse generator 445 can be used to generate the space-time delay of the trigger signal TGB. The longer the space-time delay of the trigger signal TGB, the later the start time of the phase signal PB is, increasing the space-time between the end of the phase signal PB and the start of the phase signal P1.

[0144] When the power converter 1 is under light load, the control circuit 800 can additionally set pulse generators 330, 345, 440 and 445 to increase the time delay of trigger signals TG1, TGA, TG2 and TGB, thereby increasing the off time of switches 10 and 20, 30 and 40, and thus achieving the purpose of saving power.

[0145] The embodiments of the present invention are used to control the power converter 1 to operate in non-regulation mode or regulation mode to achieve ZVS and ZCS, avoid damage to the load, and at the same time reduce switching losses and enhance system efficiency.

[0146] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A power converter, comprising: The first switch includes: a control terminal; a first terminal for receiving input voltage; and a second terminal; The second switch includes: a control terminal; a first terminal coupled to the second terminal of the first switch; and a second terminal. A third switch includes a control terminal; a first terminal coupled to the second terminal of the second switch; and a second terminal. The fourth switch includes: a control terminal; a first terminal coupled to the second terminal of the third switch; and a second terminal coupled to a ground terminal. A flying capacitor includes: a first terminal coupled to the second terminal of the first switch; and a second terminal coupled to the second terminal of the third switch; An inductor includes: a first terminal coupled to the second terminal of the second switch; and a second terminal; The output capacitor includes: a first terminal coupled to the second terminal of the inductor for outputting an output voltage; and a second terminal coupled to the ground terminal; as well as A control circuit, coupled to the first terminal of the first switch, the control terminal of the first switch, the control terminal of the second switch, the control terminal of the third switch, and the control terminal of the fourth switch, is used to switch the first switch, the second switch, the third switch, and the fourth switch according to the resonant frequency in non-adjustment mode, and to switch the first switch, the second switch, the third switch, and the fourth switch according to an adjustment frequency exceeding the resonant frequency in adjustment mode. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor will form a resonant circuit with the resonant frequency.

2. The power converter of claim 1, wherein when the input voltage is between a high voltage threshold and a low voltage threshold, the control circuit is configured to execute the non-adjustment mode, switching the first switch, the second switch, the third switch and the fourth switch when the inductor current is 0, so as to generate a voltage divider of the input voltage as the output voltage.

3. The power converter of claim 1, wherein the control circuit is configured to switch the first switch, the second switch, the third switch and / or the fourth switch when the inductor current flows from the second terminal of the inductor to the first terminal of the inductor.

4. The power converter of claim 1, wherein when the input voltage is less than a low voltage threshold, the power converter performs a single-stage operation of the regulation mode to regulate the output voltage to be less than or equal to the input voltage.

5. The power converter of claim 4, wherein the control circuit is configured to, in the single-stage operation mode, shut off the third switch and the fourth switch after the inductor current reaches 0 and after a first predetermined delay.

6. The power converter of claim 5, wherein the control circuit is configured to, in the single-stage operation mode, turn on the first switch and the second switch after turning off the third switch and the fourth switch and after a second predetermined delay.

7. The power converter of claim 1, wherein when the input voltage exceeds a high voltage threshold, the power converter performs a two-stage operation of the regulation mode to adjust the output voltage to be less than or equal to half of the input voltage, wherein the high voltage threshold is greater than a low voltage threshold.

8. The power converter of claim 7, wherein in the two-stage operation mode: When the first switch and the third switch are turned on, the input voltage charges the flying capacitor and the output capacitor through the inductor; and When the second switch and the fourth switch are turned on, the flying capacitor charges the output capacitor through the inductor.

9. The power converter of claim 1, wherein in the adjustment mode, the control circuit is used to reduce the on-time of the first switch and the second switch.

10. The power converter of claim 1, wherein the control circuit is configured to, in the adjustment mode, turn off the first switch, the second switch, the third switch and / or the fourth switch before the inductor current reaches 0.

11. The power converter of claim 1, wherein the control circuit is configured to, in the adjustment mode, turn off the first switch, the second switch, the third switch and / or the fourth switch when the inductor current reaches 0.

12. The power converter of claim 1, wherein the control circuit is configured to, in the adjustment mode, turn off the first switch, the second switch, the third switch and / or the fourth switch after the inductor current reaches 0.

13. The power converter of claim 1, wherein the power converter operates in a discontinuous conduction mode.

14. The power converter of claim 1, wherein the control circuit comprises: The first phase circuit is used to generate a first phase signal and a first trigger signal based on a start signal, a zero-crossing signal and a feedback signal; The second phase circuit is coupled to the first phase circuit and is used to generate a second phase signal and a second trigger signal based on the first trigger signal, the closed loop signal and the cutoff signal. The third phase circuit is coupled to the second phase circuit and is used to generate a third phase signal and a third trigger signal based on the first trigger signal, the second trigger signal, the closed loop signal, the zero crossover signal and the feedback signal. The fourth phase circuit is coupled to the third phase circuit and the first phase circuit, and is used to generate a fourth phase signal and a fourth trigger signal based on the third trigger signal, the closed loop signal and the cut-off signal. A start circuit, coupled to the first phase circuit, the second phase circuit, the third phase circuit, and the fourth phase circuit, is used to generate the start signal based on the mode signal, the closed-loop signal, the second trigger signal, the third trigger signal, and the fourth trigger signal; A signal generation circuit, coupled to the first phase circuit, the second phase circuit, the third phase circuit, and the fourth phase circuit, is used to generate a first switch signal, a second switch signal, a third switch signal, and a fourth switch signal based on the first phase signal, the second phase signal, the third phase signal, the fourth phase signal, and the mode signal. The first switch signal, the second switch signal, the third switch signal, and the fourth switch signal respectively switch the first switch, the second switch, the third switch, and the fourth switch. A feedback circuit, coupled to the first phase circuit, the third phase circuit, and the first terminal of the output capacitor, is used to generate the feedback signal based on the first phase signal, the third phase signal, the output voltage, and the reference voltage. A state detection circuit, coupled to the first terminal of the output capacitor and the first terminal of the inductor, is used to generate the zero-crossing signal and the cut-off signal based on the output voltage, the demagnetization reference voltage and the switching voltage of the first terminal of the inductor. as well as A closed-loop circuit, coupled to the state detection circuit, the feedback circuit, the first phase circuit, and the third phase circuit, is used to generate the closed-loop signal based on the zero-crossing signal, the feedback signal, the first phase signal, and the third phase signal.

15. The power converter of claim 14, wherein, The first phase circuit includes a first AND gate, a second AND gate, a first NOR gate, a first flip-flop, and a first pulse generator. The first AND gate contains: The first input terminal is used to receive the first phase signal; The second input terminal is used to receive the zero-crossing signal; and Output end, The second AND gate contains: The first input terminal is used to receive the first phase signal; The second input terminal is used to receive the feedback signal; as well as Output end, The first NOR gate includes: The first input terminal is coupled to the output terminal of the first AND gate; The second input terminal is coupled to the output terminal of the second AND gate; as well as Output end, The first trigger includes: The data input terminal is used to receive the power supply voltage; The clock input is used to receive the start signal; The reset terminal is coupled to the output terminal of the first NOR gate; The output terminal is used to output the first phase signal; as well as The inverting output terminal is used to output the inverted signal of the first phase signal. The first pulse generator includes: The input terminal is used to receive the inverted signal of the first phase signal; as well as The output terminal is used to output the first trigger signal. The second phase circuit includes a third AND gate, a first NAND gate, a second flip-flop, and a second pulse generator. The third AND gate contains: The first input terminal is used to receive the closed-loop signal; The second input terminal is used to receive the first trigger signal; as well as Output end, The first NAND gate includes: The first input terminal is used to receive the cutoff signal; The second input terminal is used to receive the second phase signal; as well as Output end, The second trigger contains: The data input terminal is used to receive the power supply voltage; The clock input is coupled to the output of the third AND gate; The reset terminal is coupled to the output terminal of the first NAND gate; The output terminal is used to output the second phase signal; as well as The inverting output terminal is used to output the inverted signal of the second phase signal. The second pulse generator includes: The input terminal is used to receive the inverted signal of the second phase signal; as well as The output terminal is used to output the second trigger signal. The starting circuit includes a first inverter, a fourth AND gate, a fifth AND gate, a first OR gate, a second inverter, a sixth AND gate, a seventh AND gate, and a second OR gate. The first inverter includes: The input terminal is used to receive the closed-loop signal; and Output end, The fourth AND gate contains: The first input terminal is used to receive the fourth trigger signal; The second input terminal is used to receive the closed-loop signal; and Output end, The fifth AND gate contains: The first input terminal is used to receive one of the inverted signals of the closed loop signal; The second input terminal is used to receive the third trigger signal; and Output end, The first OR gate contains: The first input terminal is coupled to the output terminal of the fourth AND gate; The second input terminal is coupled to the output terminal of the fifth AND gate; and Output end, The second inverter includes: The input terminal is used to receive the mode signal; and The output terminal is used to output the inverted signal of one of the signals of this mode. The sixth AND gate contains: The first input terminal is coupled to the output terminal of the first OR gate; The second input terminal is used to receive the inverted signal of the mode signal; as well as Output end, The seventh AND gate contains: The first input terminal is used to receive the mode signal; The second input terminal is used to receive the second trigger signal; as well as Output end, The second OR gate contains: The first input terminal is coupled to the output terminal of the sixth AND gate; The second input terminal is coupled to the output terminal of the seventh AND gate; and The output terminal is used to output the start signal.

16. The power converter of claim 14, wherein, The third phase circuit includes a first AND gate, a second AND gate, a first NOR gate, a first inverter, a fourth AND gate, a fifth AND gate, a first OR gate, a first flip-flop, and a first pulse generator. The first AND gate contains: The first input terminal is used to receive the third phase signal; The second input terminal is used to receive the zero-crossing signal; and Output end, The second AND gate contains: The first input terminal is used to receive the third phase signal; a second input to receive the feedback signal; as well as Output end, The first NOR gate includes: The first input terminal is coupled to the output terminal of the first AND gate; The second input terminal is coupled to the output terminal of the second AND gate; and Output end, The first inverter includes: The input terminal is used to receive the closed-loop signal; and Output end, The fourth AND gate contains: The first input terminal is used to receive the second trigger signal; The second input terminal is used to receive the closed-loop signal; and Output end, The fifth AND gate contains: The first input terminal is coupled to the output terminal of the first inverter; The second input terminal is used to receive the first trigger signal; as well as Output end, The first OR gate contains: The first input terminal is coupled to the output terminal of the fourth AND gate; The second input terminal is coupled to the output terminal of the fifth AND gate; and Output end, The first trigger includes: The data input terminal is used to receive the power supply voltage; The clock input is coupled to the output of the fourth AND gate; The reset terminal is coupled to the output terminal of the first NOR gate; The output terminal is used to output the third phase signal; as well as The inverting output terminal is used to output the inverted signal of the third phase signal. The first pulse generator includes: The input terminal is used to receive the inverted signal of the third phase signal; as well as The output terminal is used to output the third trigger signal. The fourth phase circuit includes a third AND gate, a first NAND gate, a second flip-flop, and a second pulse generator. The third AND gate contains: The first input terminal is used to receive the closed-loop signal; The second input terminal is used to receive the third trigger signal; and Output end, The first NAND gate includes: The first input terminal is used to receive the cutoff signal; The second input terminal is used to receive the fourth phase signal; as well as Output end, The second trigger contains: The data input terminal is used to receive the supply voltage; The clock input is coupled to the output of the third AND gate; The reset terminal is coupled to the output terminal of the first NAND gate; The output terminal is used to output the fourth phase signal; as well as The inverting output terminal is used to output the inverted signal of the fourth phase signal. The second pulse generator includes: The input terminal is used to receive the inverted signal of the fourth phase signal; as well as The output terminal is used to output the third trigger signal.

17. The power converter of claim 14, wherein, The signal generation circuit includes a first buffer, a first inverter, a first AND gate, a second AND gate, a first OR gate, a second buffer, a second OR gate, a second inverter, a third AND gate, a fourth AND gate, a third OR gate, a third buffer, a fourth OR gate, a third inverter, a fifth AND gate, a sixth AND gate, a fifth OR gate, and a fourth buffer. The first buffer contains: The input terminal is used to receive the first phase signal; and The output terminal is used to output the first switch signal. The first inverter includes: an input to receive the mode signal; as well as Output end, The first AND gate contains: The first input terminal is used to receive the third phase signal; The second input terminal is coupled to the output terminal of the first inverter; as well as Output end, The second AND gate contains: The first input terminal is used to receive the mode signal; The second input terminal is used to receive the first phase signal; as well as Output end, The first OR gate contains: The first input terminal is coupled to the output terminal of the first AND gate; The second input terminal is coupled to the output terminal of the second AND gate; and Output end, The second buffer contains: The input terminal is coupled to the output terminal of the first OR gate; and The output terminal is used to output the second switch signal. The second OR gate contains: The first input terminal is used to receive the first phase signal; The second input terminal is used to receive the second phase signal; The third input terminal is used to receive the fourth phase signal; and Output end, The second inverter includes: The input terminal is used to receive the mode signal; as well as Output end, The third AND gate contains: The first input terminal is coupled to the output terminal of the second OR gate; The second input terminal is coupled to the output terminal of the second inverter; as well as Output end, The fourth AND gate contains: The first input terminal is used to receive the mode signal; The second input terminal is used to receive the second phase signal; as well as Output end, The third OR gate contains: The first input terminal is coupled to the output terminal of the third AND gate; The second input terminal is coupled to the output terminal of the fourth AND gate; and Output end, The third buffer contains: The input terminal is coupled to the output terminal of the third OR gate; and The output terminal is used to output the third switch signal. The fourth OR gate contains: The first input terminal is used to receive the third phase signal; The second input terminal is used to receive the second phase signal; The third input terminal is used to receive the fourth phase signal; as well as Output end, The third inverter includes: The input terminal is used to receive the mode signal; as well as Output end, The fifth AND gate contains: The first input terminal is coupled to the output terminal of the fourth OR gate; The second input terminal is coupled to the output terminal of the third inverter; as well as Output end, The sixth AND gate contains: The first input terminal is used to receive the mode signal; The second input terminal is used to receive the second phase signal; as well as Output end, The fifth OR gate contains: The first input terminal is coupled to the output terminal of the fifth AND gate; The second input terminal is coupled to the output terminal of the sixth AND gate; as well as Output end, The fourth buffer contains: The input terminal is coupled to the output terminal of the fifth OR gate; and The output terminal is used to output the fourth switch signal.

18. The power converter of claim 14, wherein: The feedback circuit includes a first NOR gate, a current source, a transistor, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a switch, an error amplifier, a fifth resistor, a second capacitor, and a comparator. The first NOR gate includes: The first input terminal is used to receive the first phase signal; The second input terminal is used to receive the third phase signal; and Output end, The current source includes: The first terminal is coupled to the power supply terminal and is used to receive the power supply voltage; as well as The second end, The transistor contains: The control terminal is coupled to the output terminal of the first NOR gate; The first terminal is coupled to the second terminal of the current source; and The second terminal is coupled to the ground terminal. The first capacitor includes: The first terminal is coupled to the first terminal of the transistor; and The second terminal is coupled to the grounding terminal. The first resistor includes: The first terminal is used to receive the output voltage; and The second end, The second resistor includes: The first terminal is coupled to the second terminal of the first resistor; and The second terminal is coupled to the grounding terminal. The third resistor includes: The first terminal is used to receive the reference voltage; and The second end, The fourth resistor includes: The first terminal is coupled to the second terminal of the third resistor; and The second end, The switch contains: The control terminal is used to receive the closed-loop signal; The first terminal is coupled to the second terminal of the third resistor; and The second terminal is coupled to the grounding terminal. The error amplifier includes: The inverting input terminal is coupled to the second terminal of the first resistor; The positive input terminal is coupled to the second terminal of the third resistor; and Output end, The fifth resistor includes: The first terminal is coupled to the output terminal of the error amplifier; and The second end, The second capacitor includes: The first terminal is coupled to the second terminal of the first resistor; and The second terminal is coupled to the grounding terminal. The comparator includes: The positive input terminal is coupled to the first terminal of the first capacitor; The inverting input terminal is coupled to the first terminal of the fifth resistor; as well as The output terminal is used to output the feedback signal.

19. The power converter of claim 14, wherein, The state detection circuit includes a first comparator, a zero-crossing detector, a second comparator, a first pulse generator, and a first AND gate. The first comparator includes: The positive input terminal is used to receive the switching voltage; The inverting input terminal is used to receive the output voltage; and Output end, This zero-crossing detector includes: The input terminal is coupled to the output terminal of the first comparator; and The output terminal is used to output the zero-crossing signal. The second comparator includes: The positive input terminal is used to receive the switching voltage; The inverting input terminal is used to receive the demagnetization reference voltage; as well as The output terminal is used to output the demagnetization signal. The first pulse generator includes: Enable terminal, used to receive control signals; The input terminal is used to receive the demagnetization signal; as well as Output end, The first AND gate contains: The first input terminal is used to receive the demagnetization signal; The second input terminal is coupled to the output terminal of the first pulse generator; and The output terminal is used to output the cutoff signal. The closed-loop circuit includes a first inverter, a first OR gate, a second pulse generator, a second inverter, and a flip-flop. The first inverter includes: The input terminal is used to receive the zero-crossing signal; and The output terminal is used to output the inverted signal of one of the zero-crossing signals. The first OR gate includes: a first input terminal for receiving the first phase signal; a second input terminal for receiving the third phase signal; and Output end, The second pulse generator includes: The input terminal is coupled to the output terminal of the first OR gate; and The output terminal is used to output the first pulse signal. The second inverter includes: The input terminal is used to receive the first pulse signal; as well as The output terminal is used to output a reset signal. The trigger contains: The data input terminal is used to receive the inverted signal of the zero-crossing signal; The clock input is used to receive the feedback signal; The reset terminal is used to receive the reset signal; as well as The output terminal is used to output the closed-loop signal.

20. A control method for a power converter, the power converter comprising a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor, and a control circuit, wherein the first switch comprises: a control terminal; a first terminal for receiving an input voltage; and a second terminal; the second switch comprises: a control terminal; a first terminal coupled to the second terminal of the first switch; and a second terminal; the third switch comprises: a control terminal; a first terminal coupled to the second terminal of the second switch; and a second terminal; the fourth switch comprises: a control terminal; a first terminal coupled to the second terminal of the third switch; and a second terminal. The flying capacitor includes: a first terminal coupled to the second terminal of the first switch; and a second terminal coupled to the second terminal of the third switch. The inductor includes: a first terminal coupled to the second terminal of the second switch; and a second terminal. The output capacitor includes: a first terminal coupled to the second terminal of the inductor for outputting an output voltage; and a second terminal coupled to the ground terminal. The control circuit is coupled to the first terminal of the first switch, the control terminal of the first switch, the control terminal of the second switch, the control terminal of the third switch, and the control terminal of the fourth switch. The control method includes: In non-adjustment mode, the control circuit switches the first switch, the second switch, the third switch, and the fourth switch according to the resonant frequency; and In adjustment mode, the control circuit switches the first switch, the second switch, the third switch, and the fourth switch according to an adjustment frequency exceeding the resonant frequency. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor will form a resonant circuit with the resonant frequency.

21. The method of claim 20, wherein the control circuit is configured to switch the first switch, the second switch, the third switch and / or the fourth switch when the inductor current flows from the second terminal of the inductor to the first terminal of the inductor.

22. The method of claim 20, wherein when the input voltage is less than a low voltage threshold, the power converter performs a single-stage operation of the regulation mode to regulate the output voltage to be less than or equal to the input voltage. The control circuit switches the first switch, the second switch, the third switch, and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: After the inductor current reaches 0 and a first predetermined time has elapsed, the control circuit shuts off the third switch and the fourth switch; and After the third and fourth switches are turned off and a second predetermined time has elapsed, the control circuit turns on the first and second switches.

23. The method of claim 20, wherein when the input voltage exceeds a high voltage threshold, the power converter performs a two-stage operation of the regulation mode to adjust the output voltage to be less than or equal to half of the input voltage, wherein the high voltage threshold is greater than a low voltage threshold. The control circuit switches the first switch, the second switch, the third switch, and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: When the first switch and the third switch are turned on, the input voltage charges the flying capacitor and the output capacitor through the inductor; and When the second switch and the fourth switch are turned on, the flying capacitor charges the output capacitor through the inductor.

24. The method of claim 20, wherein the control circuit switches the first switch, the second switch, the third switch, and the fourth switch according to the adjustment frequency exceeding the resonant frequency, comprising: The control circuit shuts off the first switch, the second switch, the third switch, and / or the fourth switch before the inductor current reaches 0.

25. The method of claim 20, wherein the control circuit switches the first switch, the second switch, the third switch, and the fourth switch according to the adjustment frequency exceeding the resonant frequency, comprising: The control circuit shuts off the first switch, the second switch, the third switch, and / or the fourth switch when the inductor current reaches 0.

26. The method of claim 20, wherein the control circuit switches the first switch, the second switch, the third switch, and the fourth switch according to the adjustment frequency exceeding the resonant frequency, comprising: The control circuit shuts off the first switch, the second switch, the third switch, and / or the fourth switch after the inductor current reaches 0.

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