Synchronous buck dc-dc architecture automatically preventing duty cycle jump during low buck ratio operation

Abstract

The application discloses a synchronous step-down DCDC architecture for automatically preventing duty cycle mutation during low step-down ratio operation, comprising an error amplifier, a voltage comparator, a PWM generating circuit, a PWM signal control module, a low-side switch tube control module, a high-side switch tube and a low-side switch tube, the error amplifier compares an input voltage reference signal Vref and a voltage feedback signal FB to output an error comparison result, and the voltage comparator compares the input error comparison result and a switch tube current detection signal to output a voltage comparison result.The synchronous step-down DCDC architecture for automatically preventing duty cycle mutation during low step-down ratio operation can overcome the large fluctuation of VOUT voltage caused by the mutation of duty cycle when the VIN and VOUT voltages of the current device are close to each other, and can keep the output voltage VOUT at a lower ripple under the condition of any input VIN.

Description

Technical Field

[0001] This invention relates to a synchronous buck DC-DC architecture that automatically prevents sudden changes in duty cycle when operating at a low buck ratio. Background Technology

[0002] Synchronous buck DC-DC converters with fixed frequency and peak current control mode are widely used in the industry, for example, to step down a 24V or 48V voltage bus to 3.3V / 5V to power other low-voltage modules.

[0003] like Figure 3 The diagram shows the waveforms of a synchronous buck DC-DC converter in fixed-frequency peak current control mode operating at a low buck ratio (VIN and VOUT voltages are close). Here, clk_pwm is the falling edge synchronization clock, SW is the switching node, Ic is the inductor peak current control signal, and IL is the inductor current. As shown, the switch opens synchronously with the falling edge of the clk_pwm clock, and closes when the inductor current reaches IL. When VIN and VOUT voltages are very close, the inductor current rises slowly, potentially resulting in the inductor current not reaching the control current Ic before the falling edge of the second synchronization clock clk2 arrives. In this case, the switch will remain open until IL reaches Ic. If the inductor current IL reaches the control current Ic immediately after the falling edge of clk2, the switch will be turned off, and the inductor current IL will decrease at a rate of VOUT / L until the falling edge of the third synchronization clock clk3, at which point the switch will turn back on, and the inductor current IL will rise again. Figure 3 It can be seen that when VIN and VOUT are close to a certain level, frequency hopping will occur, the duty cycle will change abruptly, and the output VOUT voltage will fluctuate greatly.

[0004] Therefore, further improvements should be made to address the aforementioned issues. Summary of the Invention

[0005] The main objective of this invention is to provide a synchronous buck DC-DC architecture that automatically prevents sudden changes in duty cycle when operating at a low buck ratio. This architecture overcomes the large fluctuations in VOUT voltage caused by sudden changes in duty cycle when VIN and VOUT voltages are close on current devices, and allows the output voltage VOUT to maintain low ripple under any input VIN condition.

[0006] To achieve the above objectives, this invention provides a synchronous buck DC-DC architecture that automatically prevents sudden changes in duty cycle during low buck ratio operation, comprising an error amplifier, a voltage comparator, a PWM generation circuit, a PWM signal control module, a low-side switch control module, a high-side switch, and a low-side switch, wherein:

[0007] The error amplifier compares the input voltage reference signal Vref and the voltage feedback signal FB to output the error comparison result;

[0008] The voltage comparator compares the input error comparison result with the switching transistor current detection signal (detection of the input power supply VIN) to output the voltage comparison result.

[0009] The PWM generation circuit takes into account the voltage comparison result, the system clock, and the gate control signal HG output by the PWM signal control module. After processing, it outputs the PWM signal Data and the flag signal Flag, whose rising edge is synchronized with the falling edge of the system clock, respectively, so as to control the working state of the high-side switch and the low-side switch.

[0010] The PWM signal control module receives the PWM signal Data, the flag signal Flag, and the gate control signal LG output by the low-side switch control module, respectively. After processing, the output gate control signal HG is output to the gate of the high-side switch and an input terminal of the PWM generation circuit, thereby controlling the high-side switch to turn on and off.

[0011] The low-side switch control module receives the PWM signal Data and the flag signal Flag respectively. After processing, the output gate control signal HG is output to the gate of the low-side switch and an input terminal of the PWM signal control module, thereby controlling the low-side switch to turn on and off.

[0012] The drain of the high-side switching transistor is connected to the input power supply VIN, and the source of the high-side switching transistor is electrically connected to the drain of the low-side open-ended transistor and together they are connected to the output power supply OUT through an inductor.

[0013] As a further preferred technical solution to the above technical solution, for the PWM generation circuit:

[0014] When the current IL of the high-side switch exceeds the control current Ic, the voltage comparator outputs the voltage comparison result of the overcurrent signal to reset the PWM signal Data, and the flag signal Flag is generated by the gate control signal HG of the high-side switch when the system clock falls:

[0015] When the system clock falls, if the gate control signal HG is low, the flag signal Flag is reset; if the gate control signal HG is high, the flag signal Flag is set. Thus, if the PWM signal Data remains high for more than one clock cycle, the flag signal Flag will be set.

[0016] As a further preferred technical solution to the above technical solution, for the PWM signal control module:

[0017] Under normal conditions, the gate control signal HG is in phase with the PWM signal Data, and its rising edge is synchronized with the falling edge of the system clock. When the flag signal Flag is set, the output gate control signal HG is not synchronized with the falling edge of the system clock. Therefore, as long as the gate control signal LG of the low-side switch is reset, the gate control signal HG will be set.

[0018] As a further preferred technical solution to the above technical solution, for the low-side switching transistor control module:

[0019] Under normal conditions, the gate control signal LG is inverted with the PWM signal Data and is synchronously reset on the falling edge of the system clock. When the flag signal Flag is set, the output gate control signal LG is not synchronized by the falling edge of the system clock and will be limited by the built-in timer for the setting time. When the setting time of the gate control signal LG reaches the timer's countdown time, the gate control signal LG will be reset.

[0020] As a further preferred technical solution to the above technical solution, when the voltages of the input power supply VIN and the output power supply VOUT are close:

[0021] When the first clock clk1 falls, the PWM signal Data is set, the gate control signal HG is set at the same time, the high-side switch is turned on, the gate control signal LG is reset at the same time, and the low-side switch is turned off.

[0022] When the second clock clk2 falls, the gate control signal HG is high, the high-side switch is on for more than one clock cycle, the flag signal Flag is set, and then at time T1 the inductor current IL reaches the control current Ic, the gate control signal HG is reset, the high-side switch is turned off, the gate control signal LG is set, and the low-side rectifier is turned on.

[0023] The maximum on-time of the gate control signal LG, Max Toff, is controlled by an internal timer. When the on-time reaches Max Toff, the gate control signal LG is forcibly reset, the low-side rectifier is turned off, and the gate control signal HG is set, turning on the high-side switch until the inductor current IL reaches the control current Ic.

[0024] As a further preferred technical solution of the above technical solution, a resistor RT and a resistor RB are connected in series between the output power supply VOUT and ground. The tap signal between resistor RT and resistor RB is a voltage feedback signal FB and is connected to the negative input terminal of the error amplifier. Attached Figure Description

[0025] Figure 1This is a circuit diagram of the synchronous buck DC-DC architecture of the present invention, which automatically prevents sudden changes in duty cycle when operating at a low buck ratio.

[0026] Figure 2 This is a timing control diagram of the VIN and VOUT signals when they approach each other in the synchronous buck DC-DC architecture of the present invention, which automatically prevents sudden changes in duty cycle when operating at a low buck ratio.

[0027] Figure 3 This is a waveform diagram of an existing synchronous buck DC-DC converter with fixed frequency peak current control mode operating at a low buck ratio.

[0028] The reference numerals in the attached figures include: 01, error amplifier; 02, voltage comparator; 03, PWM generation circuit; 04, PWM signal control module; 05, low-side switching transistor control module; 06, high-side switching transistor; 07, low-side switching transistor; 08, inductor; 09, resistor RT; 10, resistor RB. Detailed Implementation

[0029] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0030] In the preferred embodiments of the present invention, those skilled in the art should note that the resistors and the like involved in the present invention can be considered as prior art.

[0031] Preferred embodiment.

[0032] This invention discloses a synchronous buck DC-DC architecture that automatically prevents sudden changes in duty cycle when operating at a low buck ratio, including an error amplifier 01, a voltage comparator 02, a PWM generation circuit 03, a PWM signal control module 04, a low-side switch control module 05, a high-side switch 06, and a low-side switch 07, wherein:

[0033] The error amplifier 01 compares the input voltage reference signal Vref and the voltage feedback signal FB to output the error comparison result;

[0034] The voltage comparator 02 compares the input error comparison result with the switching transistor current detection signal (detection of the input power supply VIN) to output the voltage comparison result;

[0035] The PWM generation circuit 03 takes into account the voltage comparison result, the system clock, and the gate control signal HG output by the PWM signal control module. After processing, it outputs the PWM signal Data and the flag signal Flag, whose rising edge is synchronized with the falling edge of the system clock, respectively, so as to control the working state of the high-side switch 06 and the low-side switch 07.

[0036] The PWM signal control module 04 receives the PWM signal Data, the flag signal Flag, and the gate control signal LG output by the low-side switch control module 05, respectively. After processing, the output gate control signal HG is output to the gate of the high-side switch 06 and an input terminal of the PWM generation circuit 03, respectively, so as to control the turning on and off of the high-side switch 06.

[0037] The low-side switch control module 05 receives the PWM signal Data and the flag signal Flag respectively. After processing, it outputs the gate control signal HG to the gate of the low-side switch 07 and an input terminal of the PWM signal control module 04, thereby controlling the low-side switch 07 to turn on and off.

[0038] The drain of the high-side switching transistor 06 is connected to the input power supply VIN. The source of the high-side switching transistor 07 is electrically connected to the drain of the low-side open-ended transistor 07 and together they are connected to the output power supply OUT through the inductor 08.

[0039] Specifically, for PWM generation circuit 03:

[0040] When the current IL of the high-side switch 06 exceeds the control current Ic, the voltage comparator 02 outputs the voltage comparison result of the overcurrent signal to reset the PWM signal Data, and the flag signal Flag is generated by the gate control signal HG of the high-side switch when the system clock falls:

[0041] When the system clock falls, if the gate control signal HG is low, the flag signal Flag is reset; if the gate control signal HG is high, the flag signal Flag is set. Thus, if the PWM signal Data remains high for more than one clock cycle, the flag signal Flag will be set.

[0042] More specifically, for PWM signal control module 04:

[0043] Under normal conditions, the gate control signal HG is in phase with the PWM signal Data, and its rising edge is synchronized with the falling edge of the system clock. When the flag signal Flag is set, the output gate control signal HG is not synchronized with the falling edge of the system clock. Therefore, as long as the gate control signal LG of the low-side switch 07 is reset, the gate control signal HG will be set.

[0044] Furthermore, regarding the low-side switching transistor control module 05:

[0045] Under normal conditions, the gate control signal LG is inverted with the PWM signal Data and is synchronously reset on the falling edge of the system clock. When the flag signal Flag is set, the output gate control signal LG is not synchronized by the falling edge of the system clock and will be limited by the built-in timer for the setting time. When the setting time of the gate control signal LG reaches the timer's countdown time, the gate control signal LG will be reset.

[0046] Furthermore, when the voltages of the input power supply VIN and the output power supply VOUT are close:

[0047] When the first clock clk1 falls, the PWM signal Data is set, the gate control signal HG is set at the same time, the high-side switch is turned on, the gate control signal LG is reset at the same time, and the low-side switch is turned off.

[0048] When the second clock clk2 falls, the gate control signal HG is high, the high-side switch is on for more than one clock cycle, the flag signal Flag is set, and then at time T1 the inductor current IL reaches the control current Ic, the gate control signal HG is reset, the high-side switch is turned off, the gate control signal LG is set, and the low-side rectifier is turned on.

[0049] The maximum on-time of the gate control signal LG, Max Toff, is controlled by an internal timer. When the on-time reaches Max Toff, the gate control signal LG is forcibly reset, the low-side rectifier is turned off, and the gate control signal HG is set, turning on the high-side switch until the inductor current IL reaches the control current Ic.

[0050] Preferably, a resistor RT (09) and a resistor RB (10) are connected in series between the output power supply VOUT and ground. The tap signal between the resistor RT (09) and the resistor RB (10) is a voltage feedback signal FB and is connected to the negative input terminal of the error amplifier.

[0051] Preferably, the present invention is applicable to all situations where synchronous buck DC-DC converters require similar VIN and VOUT voltages and employ a fixed frequency and peak current control mode.

[0052] Preferably, such as Figure 1 As shown:

[0053] Component 01 is an error amplifier. Its positive input is connected to the voltage reference signal Vref, and its negative input is connected to the output voltage feedback signal FB. The output is the error comparison result.

[0054] Component 02 is a voltage comparator. The negative input of comparator 02 is connected to the output error comparison result of component 01, and the positive input is connected to the current detection signal of the switching transistor.

[0055] Component 03 is a PWM generator circuit. Its input is connected to the voltage comparator output of component 02 and the system clock, while the other input is connected to the gate control signal "HG" of component 06. It outputs a PWM signal "Data" and a flag signal "Flag," whose rising edge is synchronized with the falling edge of the system clock. These are used to control the operation of the high-side switch in component 06 and the rectifier in component 07. When the high-side switch current IL of component 06 exceeds the control current Ic, component 02 outputs an overcurrent signal, resetting the "Data" signal. The flag signal "Flag" is generated by detecting the falling edge of the system clock on the gate control signal "HG" of component 06: if "HG" is low on the falling edge of the system clock, the flag signal "Flag" is reset; if "HG" is high on the falling edge of the system clock, the flag signal "Flag" is set. In other words, if the PWM signal "Data" remains high for more than one clock cycle, the flag bit "Flag" will be set.

[0056] Component 04, the HS latch, is a PWM signal latch. The input signals to Component 04 are the output signals "Data" and "Flag" from Component 03, and the output signal "LG" from Component 05. The output signal of Component 04 is the "HG" signal, connected to the gate of the high-side switch in Component 06, used to control the switching on and off of the high-side switch in Component 06. Under normal conditions, the "HG" signal is in phase with the PWM signal "Data," and its rising edge is synchronized with the falling edge of the system clock. When the flag signal "Flag" is set, the output gate control signal "HG" is not synchronized with the falling edge of the system clock; in this case, as long as the gate control signal "LG" of Component 07 is reset, the "HG" signal will be set.

[0057] Component 05, LS control, is the low-side rectifier control module. Its input signals are the "Date" and "Flag" signals from component 03, and its output signal is "LG," connected to the gate of the low-side rectifier (i.e., the low-side switch) in component 07. In normal mode, the "LG" signal is inverted compared to the PWM signal "Data," and is synchronously reset on the falling edge of the system clock. When the "Flag" signal is set, the output gate control signal "LG" is not synchronized with the falling edge of the system clock and is limited by a built-in timer. When the "LG" signal is set for the specified duration, the "LG" signal will be reset.

[0058] Component 06 is the high-side switching transistor. Its source is connected to the drain of the low-side rectifier diode in component 07, and then connected to the inductor in component 08. The drain is connected to the power supply VIN. The gate is connected to the output "HG" of component 04. It is turned on when the "HG" signal is high and turned off when the "HG" signal is low.

[0059] Component 07 is the low-side switch, its drain is connected to the source of the high-side switch in component 06, and it is connected to the inductor in component 08. The source is grounded. Its gate is connected to the output "LG" of component 05; it is turned on when the "LG" signal is high and turned off when the "LG" signal is low.

[0060] Component 08 is an inductor, with one end connected to the source terminal of component 06 and the drain terminal of component 07, and the other end connected to the output "VOUT".

[0061] Components 09 and 10 are resistors RT and RB, which are connected in series between VOUT and ground. The middle tap signal FB of the resistor is a voltage feedback signal, which is input to the negative input terminal of component 01.

[0062] like Figure 2 The diagram shows the timing when VIN and VOUT voltages are close. At the falling edge of the first clock cycle clk1, "Data" is set, "HG" is simultaneously set, the high-side switch of component 06 is turned on, "LG" is simultaneously reset, and the rectifier of component 07 is turned off. At the falling edge of the second clock cycle clk2, "HG" is high, the high-side switch of component 06 is on for more than one clock cycle, and "Flag" is set. Subsequently, at time T1, the inductor current IL reaches the control current Ic, the "HG" signal is reset, the high-side switch of component 06 is turned off, the "LG" signal is set, and the low-side rectifier of component 07 is turned on. The maximum on-time of "LG," Max Toff, is controlled by an internal timer. When the on-time reaches Max Toff, "LG" is forcibly reset, the low-side rectifier is turned off, the "HG" signal is set, and the high-side switch is turned on, until the inductor current IL reaches the control current Ic.

[0063] It is worth mentioning that the technical features such as resistors involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.

[0064] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A synchronous buck DC-DC architecture that automatically prevents sudden changes in duty cycle when operating at a low buck ratio, characterized in that, It includes an error amplifier, a voltage comparator, a PWM generation circuit, a PWM signal control module, a low-side switch control module, a high-side switch, and a low-side switch, wherein: The error amplifier compares the input voltage reference signal Vref and the voltage feedback signal FB to output the error comparison result; The voltage comparator compares the input error comparison result with the switching transistor current detection signal to output the voltage comparison result; The PWM generation circuit takes into account the voltage comparison result, the system clock, and the gate control signal HG output by the PWM signal control module. After processing, it outputs the PWM signal Data and the flag signal Flag, whose rising edge is synchronized with the falling edge of the system clock, respectively, so as to control the working state of the high-side switch and the low-side switch. The PWM signal control module receives the PWM signal Data, the flag signal Flag, and the gate control signal LG output by the low-side switch control module, respectively. After processing, the output gate control signal HG is output to the gate of the high-side switch and an input terminal of the PWM generation circuit, thereby controlling the high-side switch to turn on and off. The low-side switch control module receives the PWM signal Data and the flag signal Flag respectively. After processing, it outputs the gate control signal LG to the gate of the low-side switch, thereby controlling the turn-on and turn-off of the low-side switch. The drain of the high-side switch is connected to the input power supply VIN, and the source of the high-side switch is electrically connected to the drain of the low-side switch and together they are connected to the output power supply OUT through an inductor.

2. The synchronous buck DC-DC architecture for automatically preventing sudden changes in duty cycle during low buck ratio operation as described in claim 1, characterized in that, For PWM generation circuits: When the current IL of the high-side switch exceeds the control current Ic, the voltage comparator outputs the voltage comparison result of the overcurrent signal to reset the PWM signal Data, and the flag signal Flag is generated by the gate control signal HG of the high-side switch when the system clock falls: When the system clock falls, if the gate control signal HG is low, the flag signal Flag is reset; if the gate control signal HG is high, the flag signal Flag is set. Thus, if the PWM signal Data remains high for more than one clock cycle, the flag signal Flag will be set.

3. The synchronous buck DC-DC architecture for automatically preventing sudden changes in duty cycle during low buck ratio operation as described in claim 2, characterized in that, For the PWM signal control module: Under normal conditions, the gate control signal HG is in phase with the PWM signal Data, and its rising edge is synchronized with the falling edge of the system clock. When the flag signal Flag is set, the output gate control signal HG is not synchronized with the falling edge of the system clock. Therefore, as long as the gate control signal LG of the low-side switch is reset, the gate control signal HG will be set.

4. The synchronous buck DC-DC architecture for automatically preventing sudden changes in duty cycle during low buck ratio operation as described in claim 3, characterized in that, For the low-side switching transistor control module: Under normal conditions, the gate control signal LG is inverted with the PWM signal Data and is synchronously reset on the falling edge of the system clock. When the flag signal Flag is set, the output gate control signal LG is not synchronized by the falling edge of the system clock and will be limited by the built-in timer for the setting time. When the setting time of the gate control signal LG reaches the timer's countdown time, the gate control signal LG will be reset.

5. The synchronous buck DC-DC architecture for automatically preventing sudden changes in duty cycle during low buck ratio operation as described in claim 4, characterized in that, When the voltages of the input power supply VIN and the output power supply VOUT are close: When the first clock clk1 falls, the PWM signal Data is set, the gate control signal HG is set at the same time, the high-side switch is turned on, the gate control signal LG is reset at the same time, and the low-side switch is turned off. When the second clock clk2 falls, the gate control signal HG is high, the high-side switch is on for more than one clock cycle, the flag signal Flag is set, and then at time T1 the inductor current IL reaches the control current Ic, the gate control signal HG is reset, the high-side switch is turned off, the gate control signal LG is set, and the low-side rectifier is turned on. Maximum on-time of gate control signal LG Controlled by an internal timer, when the opening time arrives... When the gate control signal LG is forcibly reset, the low-side rectifier is turned off, and at the same time the gate control signal HG is set, the high-side switch is turned on, until the inductor current IL reaches the control current Ic.

6. The synchronous buck DC-DC architecture for automatically preventing sudden changes in duty cycle during low buck ratio operation as described in claim 1, characterized in that, A series resistor RT and a resistor RB are connected between the output power supply VOUT and ground. The tap signal between resistor RT and resistor RB is a voltage feedback signal FB and is connected to the negative input terminal of the error amplifier.

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