Transistor structure and method of manufacturing the same

Abstract

The present disclosure provides a transistor structure and a method of fabricating the same. The transistor structure includes a substrate, a gate structure, a plurality of first pocket-doped regions, a plurality of second pocket-doped regions, a plurality of source / drain extension regions, and a plurality of source / drain regions. The gate structure is on the substrate. The plurality of first pocket-doped regions is in the substrate beside the gate structure. The first pocket-doped regions comprise a group IVA element. The plurality of second pocket-doped regions is in the substrate beside the gate structure. The second pocket-doped regions have a depth greater than a depth of the first pocket-doped regions. The plurality of source / drain extension regions is in the plurality of first pocket-doped regions. The plurality of source / drain regions is in the substrate beside the gate structure. The source / drain extension regions are between the source / drain regions and the gate structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a transistor structure and a method for manufacturing the same. Background Technology

[0002] With advancements in semiconductor technology, the size of transistor devices continues to shrink. However, doping in the doped regions of transistor devices is prone to diffusion due to thermal processes. This results in a reduction in the effective channel length of the transistor device, leading to a short-channel effect, which in turn degrades the electrical characteristics of the transistor device. Summary of the Invention

[0003] This disclosure provides a transistor structure and a method for manufacturing the same, which can effectively suppress short-channel effects.

[0004] This disclosure discloses a transistor structure including: a substrate, a gate structure, a plurality of first pocket-doped regions, a plurality of second pocket-doped regions, a plurality of source / drain extension (SDE) regions, and a plurality of source / drain regions. The gate structure is located on the substrate. The plurality of first pocket-doped regions are located in the substrate adjacent to the gate structure. The first pocket-doped regions are doped with group IVA elements. The plurality of second pocket-doped regions are located in the substrate adjacent to the gate structure. The depth of the second pocket-doped regions is greater than the depth of the first pocket-doped regions. The plurality of source / drain extension regions are located in the plurality of first pocket-doped regions. The plurality of source / drain regions are located in the substrate adjacent to the gate structure. The source / drain extension regions are located between the source / drain regions and the gate structure.

[0005] According to one embodiment of the present disclosure, in the above-described transistor structure, the doping of the first pocket doped region may include carbon (C) or germanium (Ge).

[0006] According to one embodiment of this disclosure, in the transistor structure described above, the source / drain region may be connected to the source / drain extension region. The transistor structure also includes a plurality of spacer walls. The plurality of spacer walls are located on the sidewalls of the gate structure. The source / drain extension region may be located below the spacer walls.

[0007] According to one embodiment of this disclosure, the transistor structure further includes a plurality of first contact-doped regions and a plurality of second contact-doped regions. The plurality of first contact-doped regions are located in the substrate adjacent to the gate structure. The source / drain regions may be located within the first contact-doped regions. The doping of the first contact-doped regions includes group IVA elements. Second contact-doped regions are located within the plurality of first contact-doped regions. The depth of the second contact-doped regions may be greater than the depth of the source / drain regions.

[0008] This disclosure proposes another transistor structure, including: a substrate, a gate structure, multiple source / drain regions, and multiple contact window doped regions. The gate structure is located on the substrate. The multiple source / drain regions are located in the substrate adjacent to the gate structure. The multiple contact window doped regions are located in the substrate adjacent to the gate structure. The source / drain regions are located in the contact window doped regions. The doping of the contact window doped regions includes group IVA elements.

[0009] This disclosure discloses a method for manufacturing a transistor structure, the method comprising the following steps: providing a substrate; forming a gate structure on the substrate; forming a plurality of first pocket doped regions in the substrate adjacent to the gate structure; the first pocket doped regions being doped with group IVA elements; forming a plurality of second pocket doped regions in the substrate adjacent to the gate structure; the depth of the second pocket doped regions being greater than the depth of the first pocket doped regions; forming a plurality of source / drain extension regions in the plurality of first pocket doped regions; forming a plurality of source / drain regions in the substrate adjacent to the gate structure; the source / drain extension regions being located between the source / drain regions and the gate structure.

[0010] According to an embodiment of this disclosure, in the manufacturing method of the above-described transistor structure, the method for forming the first pocket doped region can be cold implantation. The temperature of cold implantation can be from -20°C to -100°C.

[0011] According to an embodiment of this disclosure, the method for manufacturing the transistor structure described above further includes the following step: forming a plurality of first contact window doped regions in a substrate adjacent to the gate structure. Source / drain regions are located within the first contact window doped regions. The doping of the first contact window doped regions may include group IVA elements.

[0012] According to an embodiment of this disclosure, in the manufacturing method of the above-described transistor structure, the method for forming the first contact window doped region can be cold implantation. The cold implantation temperature can be from -20°C to -100°C.

[0013] According to an embodiment of this disclosure, the manufacturing method of the above-described transistor structure further includes the following step: forming a plurality of second contact window doped regions within a plurality of first contact window doped regions. The depth of the second contact window doped regions may be greater than the depth of the source / drain regions.

[0014] Based on the above, in the transistor structures of some embodiments of this disclosure, multiple source / drain extension regions are located in multiple first pocket doped regions, and the dopants in the first pocket doped regions include group IVA elements. Therefore, the diffusion of dopants from the source / drain extension regions can be suppressed by the first pocket doped regions, thereby effectively suppressing short-channel effects and punch-through effects, and reducing leakage current. In the transistor structures of some embodiments of this disclosure, the source / drain regions are located in contact window doped regions, and the dopants in the contact window doped regions include group IVA elements. Therefore, the diffusion of dopants from the source / drain regions can be suppressed by the contact window doped regions, thereby effectively suppressing short-channel effects and breakdown effects, and reducing resistance. In the manufacturing method of the transistor structure of some embodiments of this disclosure, multiple source / drain extension regions are formed in multiple first pocket doped regions, and the dopants in the first pocket doped regions include group IVA elements. Therefore, the diffusion of dopants from the source / drain extension regions can be suppressed by the first pocket doped regions, thereby effectively suppressing short-channel effects and breakdown effects, and reducing leakage current.

[0015] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0016] Figures 1A to 1F This is a cross-sectional view showing the manufacturing process of a transistor structure according to some embodiments of the present disclosure;

[0017] Explanation of reference numerals in the attached figures:

[0018] 10: Transistor structure;

[0019] 100: Substrate;

[0020] 102: Isolation structure;

[0021] 104: Gate structure;

[0022] 106, 124: Dielectric layer;

[0023] 108: Conductive layer;

[0024] 110: Metal silicide layer;

[0025] 112: Hard mask layer;

[0026] 114, 116: Pocket doping regions;

[0027] 118: Source / drain extension region;

[0028] 120: Spacer wall;

[0029] 122: Source / Drain region;

[0030] 126, 128: Doped regions of the contact window;

[0031] OP: rising mouth. Detailed Implementation

[0032] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of this disclosure. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of discussion.

[0033] Figures 1A to 1F This is a cross-sectional view showing the manufacturing process of a transistor structure according to some embodiments of the present disclosure.

[0034] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, an isolation structure 102 may be formed in the substrate 100. The isolation structure 102 is, for example, a shallow trench isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide.

[0035] Next, a gate structure 104 is formed on the substrate 100. The gate structure 104 may include a dielectric layer 106 and a conductive layer 108. The dielectric layer 106 is located on the substrate 100. The dielectric layer 106 can be used as a gate dielectric layer. The material of the dielectric layer 106 is, for example, silicon oxide. The conductive layer 108 is located on the dielectric layer 106. The conductive layer 108 can be used as a gate. The material of the conductive layer 108 is, for example, doped polysilicon. In some embodiments, the gate structure 104 further includes at least one of a metal silicide layer 110 and a hard mask layer 112. The metal silicide layer 110 is located on the conductive layer 108. The material of the metal silicide layer 110 is, for example, tungsten silicide (WSi). The hard mask layer 112 is located on the metal silicide layer 110. The material of the hard mask layer 112 is, for example, silicon oxide.

[0036] In some embodiments, the method for forming the dielectric layer 106, the conductive layer 108, the metal silicide layer 110, and the hard mask layer 112 may include the following steps. First, a dielectric material layer (not shown), a conductive material layer (not shown), a metal silicide material layer (not shown), and a hard mask material layer (not shown) may be sequentially formed on a substrate 100. Next, the hard mask material layer, the metal silicide material layer, the conductive material layer, and the dielectric material layer may be patterned by photolithography and etching processes to form the hard mask layer 112, the metal silicide layer 110, the conductive layer 108, and the dielectric layer 106.

[0037] Please refer to Figure 1B A plurality of pocket doped regions 114 are formed in the substrate 100 adjacent to the gate structure 104. In some embodiments, the depth of the pocket doped regions 114 is, for example, 170 angstroms. The doping depth of the pocket doped region 114 is up to 300 angstroms. The doping of the pocket doped region 114 includes Group IVA elements. The doping of the pocket doped region 114 may include carbon, silicon, germanium, tin, or lead. In some embodiments, the doping of the pocket doped region 114 may be carbon or germanium. In this embodiment, the doping of the pocket doped region 114 is exemplified by carbon, but this disclosure is not limited thereto. The method of forming the pocket doped region 114 may be cold implantation. In embodiments of this disclosure, the term "cold implantation" refers to an ion implantation process performed at low temperatures. In some embodiments, the temperature for cold implantation to form the pocket doped region 114 may be -20°C to -100°C. In some embodiments, the implantation energy for cold implantation to form the pocket doped region 114 may be 5 kEV to 15 kEV. In some embodiments, the implantation dose for cold implantation to form the pocket doped region 114 may be 5 × 10⁻⁶. 13 Atoms / square centimeters to 5×10 15 Atoms per square centimeter. In some embodiments, the tilt angle for cold implantation to form the pocket doped region 114 may be 3 to 15 degrees. In some embodiments, when the doping of the pocket doped region 114 is carbon, the gas source for cold implantation may be carbon dioxide gas (CO2 gas).

[0038] Next, a plurality of pocket doped regions 116 are formed in the substrate 100 adjacent to the gate structure 104. The depth of the pocket doped regions 116 is greater than the depth of the pocket doped regions 114. The pocket doped regions 116 may have a first conductivity type (e.g., N-type conductivity). Hereinafter, the first conductivity type and the second conductivity type may be one of N-type conductivity and the other of P-type conductivity. In this embodiment, the first conductivity type is exemplified by N-type conductivity, and the second conductivity type is exemplified by P-type conductivity, but this disclosure is not limited thereto. In other embodiments, the first conductivity type may be P-type conductivity, and the second conductivity type may be N-type conductivity. In this embodiment, the pocket doped regions 116 may have N-type conductivity, and the dopant of the pocket doped regions 116 is, for example, arsenic (As). The method for forming the pocket doped regions 116 is, for example, ion implantation.

[0039] Then, a plurality of source / drain extension regions 118 are formed in the plurality of pocket doped regions 114. In some embodiments, the source / drain extension regions may also be referred to as "lightly doped drain (LDD) regions". The source / drain extension regions 118 may have a second conductivity type (e.g., P-type conductivity). In this embodiment, the source / drain extension regions 118 may have a P-type conductivity, and the doping of the source / drain extension regions 118 is, for example, boron (B) or boron difluoride (BF2). The method for forming the source / drain extension regions 118 is, for example, ion implantation.

[0040] Please refer to Figure 1C Multiple spacer walls 120 can be formed on the sidewalls of the gate structure 104. The spacer walls 120 can be a single-layer or multi-layer structure. The material of the spacer walls 120 is, for example, silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the method of forming the spacer walls 120 may include the following steps: First, a spacer wall material layer (not shown) can be conformally formed on the substrate 100, the isolation structure 102, and the gate structure 104. Next, the spacer wall material layer is subjected to a back-etching process (e.g., a dry etching process) to form the spacer walls 120.

[0041] Then, a plurality of source / drain regions 122 are formed in the substrate 100 adjacent to the gate structure 104. A source / drain extension region 118 is located between the source / drain regions 122 and the gate structure 104. The source / drain regions 122 may be connected to the source / drain extension region 118. The depth of the source / drain regions 122 may be greater than the depth of the source / drain extension region 118. The source / drain regions 122 may have a second conductivity type (e.g., P-type conductivity). In this embodiment, the source / drain regions 122 may have a P-type conductivity, and the doping of the source / drain regions 122 may be, for example, boron (B) or boron difluoride (BF2). The method for forming the source / drain regions 122 is, for example, ion implantation.

[0042] Please refer to Figure 1D A dielectric layer 124 can be formed on the substrate 100, the isolation structure 102, the gate structure 104, and the spacer 120. The dielectric layer 124 can be a single-layer structure or a multi-layer structure. The material of the dielectric layer 124 is, for example, silicon oxide, silicon nitride, or a combination thereof. The method for forming the dielectric layer 124 is, for example, chemical vapor deposition.

[0043] Please refer to Figure 1E Multiple openings (OPs) can be formed in the dielectric layer 124. The openings (OPs) can expose the source / drain regions 122. In some embodiments, the openings (OPs) can be formed by removing a portion of the dielectric layer 124 through photolithography and etching processes. In some embodiments, a portion of the source / drain regions 122 may be removed during the process of forming the openings (OPs).

[0044] Please refer to Figure 1F A plurality of contact window doped regions 126 may be formed in the substrate 100 adjacent to the gate structure 104. Source / drain regions 122 are located within the contact window doped regions 126. In some embodiments, the depth of the contact window doped regions 126 is, for example, 250 angstroms to 400 angstroms. The doping of the contact window doped regions 126 may include group IVA elements. The doping of the contact window doped regions 126 may include carbon, silicon, germanium, tin, or lead.

[0045] In some embodiments, the doping of the contact window doped region 126 may be carbon or germanium. In this embodiment, carbon is used as an example for the doping of the contact window doped region 126, but this disclosure is not limited thereto. The contact window doped region 126 may be formed by cold implantation. In some embodiments, the temperature for cold implantation to form the contact window doped region 126 may be -20°C to -100°C. In some embodiments, the implantation energy for cold implantation to form the contact window doped region 126 may be 10 kEV to 20 kEV. In some embodiments, the implantation dose for cold implantation to form the contact window doped region 126 may be 1 × 10⁻⁶. 14 Atoms / square centimeters to 1×10 16 Atoms per square centimeter. In some embodiments, the tilt angle of the cold injection for forming the contact window doped region 126 may be 0 degrees. In some embodiments, when the contact window doped region 126 is doped with carbon, the gas source for cold injection may be carbon dioxide gas.

[0046] Next, a plurality of contact window doped regions 128 can be formed in the plurality of contact window doped regions 126. The depth of the contact window doped region 128 can be greater than the depth of the source / drain region 122. In some embodiments, the depth of the contact window doped region 128 is, for example, 100 angstroms to 200 angstroms. The contact window doped region 128 may have a second conductivity type (e.g., P-type conductivity). In this embodiment, the contact window doped region 128 may have a P-type conductivity, and the doping of the contact window doped region 128 is, for example, boron (B) or boron difluoride (BF2). The contact window doped region 128 is formed by, for example, ion implantation.

[0047] Based on the above, in some embodiments of the transistor structure 10 manufacturing method, a plurality of source / drain extension regions 118 are formed in a plurality of pocket doped regions 114, and the doping of the pocket doped regions 114 includes group IVA elements. Therefore, the diffusion of dopants in the source / drain extension regions 118 can be suppressed by the pocket doped regions 114, thereby effectively suppressing short-channel effects and breakdown effects, and reducing leakage current. Furthermore, in some embodiments of the transistor structure 10 manufacturing method, a plurality of contact window doped regions 126 are formed in the substrate 100 adjacent to the gate structure 104, and the source / drain regions 122 are located in the contact window doped regions 126, and the doping of the contact window doped regions 126 can include group IVA elements. Therefore, the diffusion of dopants in the source / drain regions 122 can be suppressed by the contact window doped regions 126, thereby effectively suppressing short-channel effects and breakdown effects, and reducing resistance. In some embodiments, the transistor structure 10 manufacturing method further includes forming a plurality of contact window doped regions 128 in the plurality of contact window doped regions 126. Since the doped region 126 of the contact window can suppress the diffusion of dopants from the doped region 128 of the contact window, it can effectively suppress the short-channel effect and the breakdown effect, and reduce the resistance.

[0048] The following is through Figure 1F The transistor structure 10 of the above embodiment will be explained here. Furthermore, although the method for forming the transistor structure 10 is described using the above method as an example, this disclosure is not limited thereto.

[0049] Please refer to Figure 1F The transistor structure 10 includes a substrate 100, a gate structure 104, multiple pocket doped regions 114, multiple pocket doped regions 116, multiple source / drain extension regions 118, and multiple source / drain regions 122. The transistor structure 10 can be a P-type metal-oxide-semiconductor (PMOS) transistor structure or an N-type metal-oxide-semiconductor (NMOS) transistor structure. In this embodiment, the transistor structure 10 is an example of a P-type metal-oxide-semiconductor transistor structure, but this disclosure is not limited thereto. The gate structure 104 is located on the substrate 100. The multiple pocket doped regions 114 are located in the substrate 100 adjacent to the gate structure 104. The doping of the pocket doped regions 114 includes group IVA elements. The multiple pocket doped regions 116 are located in the substrate 100 adjacent to the gate structure 104. The depth of the pocket doped regions 116 is greater than the depth of the pocket doped regions 114. The multiple source / drain extension regions 118 are located in the multiple pocket doped regions 114. Multiple source / drain regions 122 are located in the substrate 100 adjacent to the gate structure 104. Source / drain extension regions 118 are located between the source / drain regions 122 and the gate structure 104.

[0050] In some embodiments, the transistor structure 10 further includes a plurality of contact window doped regions 126. The plurality of contact window doped regions 126 are located in the substrate 100 adjacent to the gate structure 104. Source / drain regions 122 may be located within the contact window doped regions 126. The doping of the contact window doped regions 126 may include group IVA elements. In some embodiments, the transistor structure 10 further includes a plurality of contact window doped regions 128. The plurality of contact window doped regions 128 are located within the plurality of contact window doped regions 126. The depth of the contact window doped regions 128 may be greater than the depth of the source / drain regions 122. In some embodiments, the transistor structure 10 further includes a plurality of spacer walls 120. The plurality of spacer walls 120 are located on the sidewalls of the gate structure 104. Source / drain extension regions 118 may be located below the spacer walls 120.

[0051] In the above embodiments, although the transistor structure 10 includes both the pocket doped region 114 and the contact window doped region 126, this disclosure is not limited thereto. In some other embodiments, the transistor structure 10 includes the pocket doped region 114 but does not include the contact window doped region 126. In some other embodiments, the transistor structure 10 includes the contact window doped region 126 but does not include the pocket doped region 114.

[0052] In some embodiments, the transistor structure 10 may be applied to a complementary metal oxide semiconductor (CMOS) under array (CuA) architecture or a complementary metal oxide semiconductor (CMOS near array (CnA) architecture.

[0053] Furthermore, the remaining components in the transistor structure 10 can be described with reference to the above embodiments. Additionally, the details of each component in the transistor structure 10 (e.g., materials and formation methods) have been described in detail in the above embodiments and will not be repeated here.

[0054] As described above, in some embodiments of the transistor structure 10, multiple source / drain extension regions 118 are located within multiple pocket doped regions 114, and the doping of the pocket doped regions 114 includes group IVA elements. Therefore, the diffusion of dopants from the source / drain extension regions 118 can be suppressed by the pocket doped regions 114, thereby effectively suppressing short-channel effects and breakdown effects, and reducing leakage current. In some embodiments of the transistor structure 10, source / drain regions 122 are located within contact window doped regions 126, and the doping of the contact window doped regions 126 includes group IVA elements. Therefore, the diffusion of dopants from the source / drain regions 122 can be suppressed by the contact window doped regions 126, thereby effectively suppressing short-channel effects and breakdown effects, and reducing resistance. In some embodiments, the transistor structure 10 further includes multiple contact window doped regions 128, and the multiple contact window doped regions 128 are located within the multiple contact window doped regions 126. Since the doped region 126 of the contact window can suppress the diffusion of dopants from the doped region 128 of the contact window, it can effectively suppress the short-channel effect and the breakdown effect, and reduce the resistance.

[0055] In summary, in the transistor structure and manufacturing method of the above embodiments, since the doped region including group IVA elements can suppress the diffusion of dopants from the source / drain extension region and / or the source / drain region, the short-channel effect can be effectively suppressed.

[0056] Although this disclosure has been presented above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the appended claims.

Claims

1. A transistor structure, characterized in that, include: Substrate; A gate structure is located on the substrate; Multiple first pocket doped regions are located in the substrate adjacent to the gate structure, wherein the doping of the first pocket doped regions includes group IVA elements; Multiple source / drain extension regions are located within multiple first pocket doped regions; Multiple source / drain regions are located in the substrate adjacent to the gate structure, wherein the source / drain extension regions are located between the source / drain regions and the gate structure; Multiple first contact window doped regions are located in the substrate adjacent to the gate structure, wherein the source / drain regions are located in the first contact window doped regions; as well as Multiple second contact window doped regions are located within multiple first contact window doped regions, wherein the depth of the second contact window doped regions is greater than the depth of the source / drain regions, and the doping of the first contact window doped regions includes group IVA elements; The conductivity type of the doped region of the second contact window is the same as that of the source / drain region.

2. The transistor structure according to claim 1, wherein the doping of the first pocket doped region comprises carbon or germanium.

3. The transistor structure according to claim 1, wherein the source / drain region is connected to the source / drain extension region, and the transistor structure further comprises: Multiple spacer walls are located on the sidewalls of the gate structure, wherein the source / drain extension regions are located below the spacer walls.

4. The transistor structure according to claim 1, further comprising: Multiple second pocket doped regions are located in the substrate adjacent to the gate structure, wherein the depth of the second pocket doped region is greater than the depth of the first pocket doped region; The conductivity type of the second pocket doped region is different from that of the source / drain extension region.

5. A transistor structure, characterized in that, include: Substrate; A gate structure is located on the substrate; Multiple source / drain regions are located in the substrate adjacent to the gate structure; as well as Multiple first contact window doped regions are located in the substrate adjacent to the gate structure, wherein the source / drain regions are located in the first contact window doped regions; as well as Multiple second contact window doped regions are located within multiple first contact window doped regions, wherein the depth of the second contact window doped regions is greater than the depth of the source / drain regions, and the doping of the first contact window doped regions includes group IVA elements; The conductivity type of the doped region of the second contact window is the same as that of the source / drain region.

6. The transistor structure according to claim 5, further comprising: Multiple first pocket doped regions are located in the substrate adjacent to the gate structure, wherein the doping of the first pocket doped regions includes group IVA elements.

7. The transistor structure according to claim 6, further comprising: Multiple second pocket doped regions are located in the substrate adjacent to the gate structure, wherein the depth of the second pocket doped region is greater than the depth of the first pocket doped region; The conductivity type of the second pocket doped region is different from that of the source / drain extension regions formed in the plurality of first pocket doped regions.

8. A method for manufacturing a transistor structure, characterized in that, include: Provide substrate; A gate structure is formed on the substrate; A plurality of first pocket doped regions are formed in the substrate adjacent to the gate structure, wherein the doping of the first pocket doped regions includes group IVA elements; Multiple source / drain extension regions are formed in multiple first pocket doped regions; A plurality of source / drain regions are formed in a substrate adjacent to the gate structure, wherein the source / drain extension regions are located between the source / drain regions and the gate structure; A plurality of first contact window doped regions are formed in the substrate adjacent to the gate structure, wherein the source / drain regions are located in the first contact window doped regions, and the doping of the first contact window doped regions includes the group IVA elements; as well as A plurality of second contact window doped regions are formed in a plurality of first contact window doped regions, wherein the depth of the second contact window doped regions is greater than the depth of the source / drain regions; The conductivity type of the doped region of the second contact window is the same as that of the source / drain region.

9. The method for manufacturing a transistor structure according to claim 8, further comprising: A plurality of second pocket doped regions are formed in the substrate adjacent to the gate structure, wherein the depth of the second pocket doped regions is greater than the depth of the first pocket doped regions; The conductivity type of the second pocket doped region is different from that of the source / drain extension region.

Images