Gate-level netlist processing method, device, equipment and storage medium

Abstract

This invention provides a method, apparatus, device, and storage medium for processing gate-level netlists. The method includes: acquiring an original gate-level netlist and a corresponding timing constraint file; determining the timing path group included in the original gate-level netlist based on the original gate-level netlist and the timing constraint file; reconstructing the timing paths in the timing path group while keeping their logical functions unchanged to obtain a target gate-level netlist. In the reconstructed timing path group, each level of logical unit included in the timing path can find the same type of logical unit in any other timing path in the timing path group. This ensures that when data signals propagate in different timing paths, the number and type of logical units they pass through are the same, thereby making the delay times of multiple timing paths the same or similar, and enabling more accurate control of the delay offset between timing paths.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a method, apparatus, device, and storage medium for processing gate-level netlists. Background Technology

[0002] In chip design, all timing paths within the chip must meet timing constraints for the chip to function correctly. The chip design process involves first describing the circuit using a Hardware Description Language (HDL) to obtain HDL code. Then, the HDL code is synthesized into a gate-level netlist. Placement and routing are performed using the gate-level netlist, parasitic parameters are extracted after routing, and these parameters are back-annotated back into the gate-level netlist. Static timing analysis is then performed on the timing paths in the gate-level netlist. If the timing paths in the gate-level netlist meet the timing constraints, a layout is generated. Finally, the chip is manufactured based on the layout.

[0003] As chip structures become increasingly complex, chips typically include numerous timing paths. To address the constraints of some timing paths, it's necessary to control the delay offset between them, ensuring that the delay times of multiple timing paths are equal or similar to meet the chip's timing constraints. In prior art, for multiple timing paths requiring delay offset control, buffers are inserted into timing paths with shorter delay times to make the delay times of multiple paths the same or similar. However, controlling delay time by inserting buffers cannot accurately reduce the delay offset between timing paths. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a gate-level netlist processing method to overcome or at least partially solve the above problems, so as to solve the problem of being unable to accurately reduce the delay offset between timing paths.

[0005] Accordingly, embodiments of the present invention also provide a gate-level netlist processing device, an electronic device, and a storage medium to ensure the implementation and application of the above method.

[0006] To address the aforementioned problems, embodiments of the present invention disclose a method for processing gate-level netlists, comprising:

[0007] Obtain the original gate-level netlist and the corresponding timing constraint file;

[0008] Based on the original gate-level netlist and the timing constraint file, determine the timing path group included in the original gate-level netlist, wherein the timing path group includes multiple timing paths for which delay offset needs to be controlled;

[0009] While keeping the logical function of the timing path unchanged, the timing paths in the timing path group are reconstructed to obtain a target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logical unit included in the timing path group, a logical unit of the same type can be found in any other timing path in the timing path group.

[0010] Optionally, the step of keeping the logical function of the timing path unchanged and reconstructing the timing paths in the timing path group to obtain the target gate-level netlist includes: controlling that the logical units at the same level in multiple timing paths are of the same type.

[0011] Optionally, the step of keeping the logical function of the timing path unchanged, reconstructing the timing paths in the timing path group to obtain the target gate-level netlist further includes: controlling the driving capability of logical units at the same level in multiple timing paths to be the same.

[0012] Optionally, the step of maintaining the logical function of the timing path unchanged and reconstructing the timing paths in the timing path group to obtain the target gate-level netlist includes:

[0013] A reference logic unit set is determined, wherein the reference logic unit set consists of all types of logic units in the timing path group, and the number of logic units of each type reaches a target number, wherein the target number is the maximum number of logic units of the corresponding type in the timing path group in the same timing path;

[0014] Determine a first timing path and a corresponding first set of logic units, wherein the first timing path is the timing path with the largest number of levels in the timing path group, and the first set of logic units is composed of the logic units in the first timing path;

[0015] A second timing path and a corresponding set of second logic units are determined; the second timing path is any timing path in the timing path group other than the first timing path, and the set of second logic units is composed of logic units in the corresponding second timing path;

[0016] Insert a first target logic unit into the first timing path and keep the logic function of the first timing path unchanged, thereby reconstructing the first timing path. The first target logic unit is the logic unit included in the difference set between the first logic unit set and the reference logic unit set.

[0017] A second target logic unit is inserted into the second timing path, and the logic function of the second timing path is kept unchanged, thereby reconstructing the second timing path. The second target logic unit is the logic unit included in the difference set between the second logic unit set and the third logic unit set. The third logic unit set is composed of the logic units in the reconstructed first timing path.

[0018] Optionally, after reconstructing the timing paths in the timing path group while maintaining the logical function of the timing paths unchanged to obtain the target gate-level netlist, the method further includes:

[0019] Following the same layout rules, the logic units included in each of the timing paths are laid out to obtain a primary layout corresponding to the target gate-level netlist.

[0020] Optionally, after laying out the logic units included in each timing path according to the same layout rules to obtain the primary layout corresponding to the target gate-level netlist, the gate-level netlist processing method further includes:

[0021] In the primary layout, the routing of each timing path is set according to the same routing rules to obtain the target layout corresponding to the target gate-level netlist.

[0022] Optionally, before reconstructing the timing paths in the timing path group while maintaining the logical function of the timing paths to obtain the target gate-level netlist, the gate-level netlist processing method further includes:

[0023] While keeping the logical function of the timing path unchanged, logical units with the same function in the timing path are replaced by logical units from a preset set of logical units. The preset set of logical units includes pre-set logical units used to simplify the structure of the timing path.

[0024] This invention also discloses a gate-level netlist processing apparatus, comprising:

[0025] The acquisition module is used to acquire the original gate-level netlist and the corresponding timing constraint file;

[0026] The determination module is used to determine the timing path group included in the original gate-level netlist based on the original gate-level netlist and the timing constraint file, wherein the timing path group includes multiple timing paths for which delay offset needs to be controlled;

[0027] The refactoring module is used to refactor the timing paths in the timing path group while keeping the logical function of the timing path unchanged, to obtain a target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logical unit included in the timing path group, a logical unit of the same type can be found in any other timing path in the timing path group.

[0028] This invention also discloses an electronic device, including a memory and one or more processors, wherein the memory stores one or more programs and is configured to be executed by the one or more processors, the one or more programs containing instructions for performing the following operations:

[0029] Obtain the original gate-level netlist and the corresponding timing constraint file;

[0030] Based on the original gate-level netlist and the timing constraint file, determine the timing path group included in the original gate-level netlist, wherein the timing path group includes multiple timing paths for which delay offset needs to be controlled;

[0031] While keeping the logical function of the timing path unchanged, the timing paths in the timing path group are reconstructed to obtain a target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logical unit included in the timing path group, a logical unit of the same type can be found in any other timing path in the timing path group.

[0032] This invention also discloses a readable storage medium, which, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to perform the gate-level netlist processing method described above.

[0033] The embodiments of this invention include the following advantages: Obtaining the original gate-level netlist and the corresponding timing constraint file; determining the timing path groups included in the original gate-level netlist based on the original gate-level netlist and the timing constraint file; maintaining the logical function of the timing paths in the timing path groups unchanged; reconstructing some or all of the timing paths to obtain the target gate-level netlist. Specifically, each level of logic unit included in the timing path group after reconstruction can find the same type of logic unit in any other timing path in the group. This ensures that when data signals propagate in different timing paths, the number and type of logic units they pass through are the same, thereby making the delay times of multiple timing paths the same or similar, and enabling more accurate control of the delay offset between timing paths. Attached Figure Description

[0034] Figure 1A flowchart illustrating the steps of an embodiment of a gate-level netlist processing method according to the present invention is shown.

[0035] Figure 2 This invention illustrates a temporal path group in a primitive gate-level netlist;

[0036] Figure 3 This invention illustrates a temporal path group in a target gate-level netlist;

[0037] Figure 4 A flowchart illustrating the steps of another embodiment of the gate-level netlist processing method of the present invention is shown;

[0038] Figure 5 Another time-series path group in a target gate-level netlist is shown as an example of the present invention;

[0039] Figure 6 A structural block diagram of an embodiment of a gate-level netlist processing apparatus according to the present invention is shown;

[0040] Figure 7 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0041] This embodiment provides a method for processing gate-level netlists. The invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] One of the core concepts of this invention is to reconstruct multiple timing paths for a set of timing paths that require control of delay offset between paths, so that the number of stages of the multiple timing paths is the same and the type of logic units included in the multiple timing paths is the same, so that when the data signal propagates in different timing paths, the number and type of logic units it passes through are the same, thereby making the delay time of the multiple timing paths the same or similar, and enabling more accurate control of delay offset between timing paths.

[0043] Figure 1 A flowchart illustrating the steps of an embodiment of a gate-level netlist processing method according to the present invention is shown. (Refer to...) Figure 1 The gate-level netlist processing method provided in this embodiment, applied to electronic devices, may include the following steps:

[0044] Step 101: Obtain the original gate-level netlist and the corresponding timing constraint file.

[0045] The original gate-level netlist can be a logic circuit generated by converting hardware description language code using an electronic design automation (EDA) tool, or it can be a logic circuit drawn by the user using circuit drawing software. The original gate-level netlist can include logic units such as multiplexers (MUX), flip-flops, NAND gates, OR gates, NOR gates, XNOR gates, OR gates, inverters, and / or buffers. These logic units are connected according to the logical relationships described in the hardware description language code. A timing path is the logical path that data signals traverse during propagation in the logic circuit. A timing path consists of one or more logic units, and each timing path has a start point and an end point. The timing constraint file describes the start and end points of the timing paths, as well as the timing constraint relationships between the timing paths.

[0046] For example, Figure 2 This invention illustrates a temporal path group in a primitive gate-level netlist, such as... Figure 2 As shown, the original gate-level netlist includes timing paths A, B, and C. Timing path A consists of a data selector MUX2, an AND gate AND2, and an OR gate OR2 connected in series. Timing path B consists of a data selector MUX2 and an AND gate AND2 connected in series. Timing path C consists of a NAND gate NAND2. Timing paths A, B, and C can be timing paths within the same circuit module in the chip. The timing constraint file describes the start point IN and end point OUT of timing paths A, B, and C, respectively. The start point IN can be the input terminal of the circuit module, and the end point can be the output terminal of the circuit module.

[0047] In practical applications, when timing paths A, B, and C originate from the input terminal of the same circuit module and terminate at the output terminal of the same circuit module, according to the constraints of the circuitry within the chip, there may be a requirement that the delay times of the data signal in timing paths A, B, and C be equal or close. This ensures that the data signal, after being input from the circuit module's input terminal, can be output from the circuit module's output terminal at the same or similar time points. Therefore, the difference between the delay times of the data signal in timing path A, timing path B, and timing path C should not exceed the maximum delay offset time, which is, for example, 1 nanosecond. The timing constraint file describes the maximum delay offset time between timing paths A, B, and C. During chip operation, if the difference between the delay times of the data signal in timing path A, timing path B, and timing path C is not higher than the maximum delay offset time, the delay offset between timing path A, timing path B, and timing path C conforms to the timing constraint relationship described in the timing constraint file, and the chip can work normally.

[0048] In this embodiment, the electronic device can obtain the original gate-level netlist and the corresponding timing constraint file from a preset storage location, or receive the original gate-level netlist and the corresponding timing constraint file sent by other electronic devices. The process by which the electronic device obtains the original gate-level netlist and the corresponding timing constraint file can be set according to requirements, and this embodiment does not impose any restrictions on this.

[0049] It should be noted that, for ease of understanding, Figure 2 This only shows a simple set of timing paths in the original gate-level netlist that require control of the delay offset between paths. Figure 2 The original gate-level netlist shown does not represent the actual logic circuit. The actual logic circuit may include one or more timing paths that require control over the delay offset between paths.

[0050] Step 102: Based on the original gate-level netlist and timing constraint file, determine the timing path groups included in the original gate-level netlist.

[0051] The timing path group includes multiple timing paths for which delay offsets need to be controlled.

[0052] In this embodiment, the electronic device can determine the timing path group requiring delay offset control from the original gate-level netlist based on the connection relationships between logic units in the original gate-level netlist and the timing constraint relationships between timing paths described in the timing constraint file. Referring to the above example, the electronic device can determine, through the timing constraint file, that the starting point of timing paths A, B, and C is the input terminal of the circuit module, and the ending point is the output terminal of the circuit module. Since timing paths A, B, and C have the same starting point and the same ending point, they can be determined as a group of timing paths requiring delay offset control, forming a timing path group. Simultaneously, the electronic device can determine, based on the maximum delay offset time described in the timing constraint file, that the difference in delay time between timing paths A, B, and C is not higher than the maximum delay offset time, for example, 1 nanosecond. Further, the electronic device can determine the logic units included in each timing path based on the connection relationships between logic elements in the original gate-level netlist. The specific process by which the electronic device determines the timing path group based on the original gate-level netlist and timing constraint file can be set according to requirements, and this embodiment does not impose any restrictions on it.

[0053] Step 103: Keep the logical function of the timing path unchanged, reconstruct the timing path in the timing path group to obtain the target gate-level netlist.

[0054] In the target gate-level netlist, all timing paths in the timing path group have the same level, and for each level of logic unit included in a timing path group, a logic unit of the same type can be found in any other timing path in the group. The type of logic unit corresponds to its function; logic units of the same type have the same function. The level of a timing path is the number of logic units connected in series in the timing path. In a timing path, each logic unit constitutes one level of the timing path. The level of a logic unit is its position in the timing path. For example... Figure 2 As shown, in timing path A, the data selector has one stage, which is the first-level logic unit of timing path A; in timing path B, the AND gate has two stages, which is the second-level logic unit of timing path B. The second-level logic units in timing path A and timing path B are of the same type, both being AND gates.

[0055] In this embodiment, after determining the timing path group that requires delay offset control, the electronic device can keep the logic function of each timing path in the timing path group unchanged, reconstruct some or all of the timing paths in the timing path group so that the number of stages of each timing path in the timing path group is the same, and the corresponding stages of multiple timing paths have the same type of logic units, thereby making the delay time of the data signal in each timing path equal or close.

[0056] Alternatively, step 103 can be implemented in the following way:

[0057] Step 1031: Determine the reference logic unit set, which consists of all types of logic units in the timing path group, and the number of logic units of each type reaches a target number, where the target number is the maximum number of logic units of the corresponding type in the same timing path within the timing path group. This target number is also the minimum required number of logic units of the corresponding type.

[0058] Step 1032: Determine the first timing path and the corresponding first logic unit set. The first timing path is the timing path with the largest number of levels in the timing path group, and the first logic unit set is composed of the logic units in the first timing path.

[0059] Step 1033: Determine the second timing path and the corresponding second logic unit set. The second timing path is any timing path in the timing path group other than the first timing path. The second logic unit set is composed of the logic units in the corresponding second timing path.

[0060] Step 1034: Insert a first target logic unit into the first timing path while maintaining the original logic function of the first timing path, thereby reconstructing the first timing path. The first target logic unit is the logic unit included in the difference set between the first logic unit set and the reference logic unit set. If the difference set between the first logic unit set and the reference logic unit set is empty, no new logic unit needs to be added to the first timing path; if the difference set between the first logic unit set and the reference logic unit set is not empty, new logic units need to be added to the first timing path.

[0061] Step 1035: Insert a second target logic unit into the second timing path and keep the logic function of the second timing path unchanged, thereby reconstructing the second timing path. The second target logic unit is the logic unit included in the difference set between the second logic unit set and the third logic unit set. The third logic unit set is composed of the logic units in the reconstructed first timing path.

[0062] In this embodiment, during the reconstruction of the timing path, the first step is to count all types of logic units included in the timing path group, determine the target number of logic units of each type, and combine them to obtain a reference logic unit set. For example... Figure 2 As shown, the logic unit types included in timing paths A, B, and C are data selectors (MUX2), AND gates (AND2), OR gates (OR2), and NAND gates (NAND2). Since the number of data selectors in timing path A is 1 and the number of data selectors in timing path B is 1, the maximum number of data selectors is determined to be 1, i.e., the target number of data selectors is 1. The number of AND gates in both timing paths A and B is 1, which determines that the target number of AND gates, OR gates, and NAND gates is 1. Therefore, the reference logic unit set includes one data selector, one AND gate, one OR gate, and one NAND gate.

[0063] In the process of reconstructing multiple timing paths, the timing path with the highest order in the timing path group can be identified as the first timing path, and the other timing paths in the timing path group besides the first timing path can be identified as the second timing paths. For example... Figure 2 As shown, timing path A consists of three logic units connected in series, and its level is 3; timing path B consists of two logic units connected in series, and its level is 2; timing path C has a level of 1. In this case, timing path A can be designated as the first timing path, and timing paths B and C can be designated as the second timing paths. It should be noted that when the level of multiple timing paths is the maximum value, one timing path can be randomly designated as the first timing path, and the others as the second timing paths.

[0064] At the same time, the set of all logical units included in the first timing path can be defined as the first logical unit set. For example... Figure 2 As shown, the first set of logic units includes a data selector, an AND gate, and an OR gate. Similarly, the set of all logic units included in the second timing path is determined as the second set of logic units corresponding to the second timing path. Figure 2 As shown, the second logic unit set corresponding to timing path B includes a data selector and an AND gate. The second logic unit set corresponding to timing path C includes a NAND gate.

[0065] In this embodiment, the electronic device first calculates the difference between the reference logic unit set and the first logic unit set, then inserts the first target logic unit included in the difference set into the first timing path, and controls the logic function of the first timing path to remain unchanged, thereby reconstructing the first timing path. Combined with... Figure 2As shown, the first target logic unit included in the difference set between the first logic unit set and the reference logic unit set is a NAND gate, and a NAND gate NAND2 can be inserted in the timing path A. Figure 3 This invention illustrates a temporal path group in a target gate-level netlist, such as... Figure 3 As shown, a NAND gate can be inserted at the end of timing path A. To maintain the logical function of timing path A, an XOR gate (XOR2) can be inserted after the NAND gate. One input of the NAND gate is connected to the output of the OR gate, and the other input is connected to a high-level signal (a high-level signal is a constant value of 1, and a low-level signal is a constant value of 0). The output of the NAND gate is connected to one input of the XOR gate, and the other input of the XOR gate is connected to a high-level signal. The output of the XOR gate serves as the output of the reconstructed timing path A. A NAND operation with 1 and data is equivalent to an inversion operation; an XOR operation with 1 and data is equivalent to an inversion operation. Therefore, in the reconstructed timing path A, the NAND gate and the XOR gate are equivalent to inverters. Two inverters connected in series do not change the logical function of timing path A. The XOR gate is equivalent to an inverter, so an inverter can also be used instead. The specific insertion positions of the NAND gate and the XOR gate can be set according to requirements, as long as the logical function of timing path A remains unchanged. It should be noted that when the number of targets for the first target logic unit is greater than 1, for example, if the number of targets is 2, two corresponding first target logic units can be inserted into the first timing path. Furthermore, if the logical function of the first timing path can be maintained after inserting the first target logic unit into the first timing path, no other logic units need to be inserted into the first timing path.

[0066] After reconstructing the first timing path, all logic units in the reconstructed first timing path can be combined into a third logic unit set to reconstruct the second timing path. Referring to the example above, the third logic unit set includes a data selector, an AND gate, an OR gate, a NAND gate, and an XOR gate. The second logic unit set corresponding to timing path B includes a data selector and an AND gate. It can be determined that the second target logic unit included in the difference set between the third and second logic unit sets is an OR gate, a NAND gate, and an XOR gate. Therefore, an OR gate, a NAND gate, and an XOR gate can be inserted into timing path B. To maintain the logic function of timing path B, one input of the OR gate can be used as the input of timing path B, and the other input can be connected to a low level. A NAND gate and an XOR gate are then connected in series after the output of the OR gate. One input of the NAND gate is connected to a high-level signal, and one input of the XOR gate is also connected to a high-level signal. The output of the XOR gate is connected to the input of the data selector. Since one input of the OR gate is connected to a low level, the OR gate does not change the data of the input timing path B. The OR gate is equivalent to a buffer. The NAND gate and the XOR gate are equivalent to two inverters connected in series, which can keep the logic function of timing path B unchanged.

[0067] Similarly, combining Figure 2 and Figure 3 The second set of logic units corresponding to timing path C includes a NAND gate. It can be determined that the second target logic unit in the difference set between the third and second sets of logic units is a data selector, an AND gate, an OR gate, and an XOR gate. Therefore, a data selector, an AND gate, an OR gate, and an XOR gate can be inserted into timing path C. One input of the data selector can be used as an input of timing path C, and the other input can be connected to a constant 0, so that the data selector does not change the input of timing path C. An AND gate is connected in series after the data selector, with one input connected to a high-level signal. The AND gate does not change the output data of the data selector. The data selector and the AND gate act as a buffer. The output of the AND gate is connected to the input of the NAND gate. After the NAND gate, an OR gate and an XOR gate are connected in series. One input of the OR gate is connected to the output of the NAND gate, and the other input is connected to a low-level signal. One input of the XOR gate is connected to the output of the OR gate, and the other input is connected to a high-level signal. The OR gate and the XOR gate are like buffers, which do not change the output data of the NAND gate, that is, do not change the output of timing path C, and can keep the logic function of timing path C unchanged.

[0068] Combination Figure 2 and Figure 3It is known that before the reconfiguration, timing paths A, B, and C have different levels and include different logic units. When data signals propagate through these paths, the number and type of logic units they pass through differ, resulting in significant differences in the latency of the data signals. Inserting buffers makes it difficult to accurately control the latency of data signals in these paths, thus failing to accurately reduce the latency offset between them, especially at different process corners. After the reconfiguration, the logical functions of timing paths A, B, and C remain unchanged. Furthermore, all three paths become 5-level timing paths, and each logic unit in each level of the timing path group can be found in every other timing path in the group of the same type. For example, in the reconstructed timing paths A and B, the first-level logic unit of timing path A is of the same type as the fourth-level logic unit of timing path B. Similarly, in the reconstructed timing paths B and C, the fourth-level logic unit of timing path B is of the same type as the first-level logic unit of timing path C. In this case, as the data signal is transmitted from the input to the output of timing paths A, B, and C, it passes through the same number and type of logic units. This ensures that the delay times of timing paths A, B, and C are the same or similar, allowing for more precise control of the delay offset between them.

[0069] It should be noted that during the timing path reconstruction process, some or all timing paths in the timing path group can be reconstructed, so that each logic unit at each level in each timing path in the timing path group has a corresponding logic unit of the same type in other timing paths in the timing path group. In practical applications, other methods can also be used to reconstruct timing paths. The specific reconstruction process of timing paths can be set according to requirements, and this embodiment does not impose any restrictions on it.

[0070] In summary, this embodiment obtains the original gate-level netlist and the corresponding timing constraint file. Based on the original gate-level netlist and the timing constraint file, the timing path groups included in the original gate-level netlist are determined. The logical functions of the timing paths in the timing path groups remain unchanged, and the timing paths in the timing path groups are reconstructed to obtain the target gate-level netlist. In the reconstructed timing path groups, each level of logic unit included in the timing path can find the same type of logic unit in any other timing path in the group. This ensures that when the data signal propagates in different timing paths, the number and type of logic units it passes through are the same, thereby making the delay times of multiple timing paths the same or similar, and allowing for more accurate control of the delay offset between timing paths.

[0071] Reference Figure 4 The diagram illustrates a step flowchart of another embodiment of the gate-level netlist processing method of the present invention, which may specifically include the following steps:

[0072] Step 401: Obtain the original gate-level netlist and the corresponding timing constraint file.

[0073] Step 402: Based on the original gate-level netlist and timing constraint file, determine the timing path groups included in the original gate-level netlist.

[0074] Step 403: Keep the logical function of the timing path unchanged, reconstruct the timing path in the timing path group to obtain the target gate-level netlist.

[0075] Optionally, the method may further include: controlling that logical units of the same type are at the same level in multiple timing paths.

[0076] In this embodiment, during the reconstruction of timing paths, logic units of the same type can be set at the same level in multiple timing paths, making the logical structures of multiple timing paths identical. For example, Figure 5 Another example of the present invention is shown in a target gate-level netlist, such as a time-series path group. Figure 5 As shown, and in conjunction with the above example, after obtaining the reconstructed timing path A, timing paths B and C can be reconstructed according to the logical structure of the reconstructed timing path A. Combined with... Figure 2 and Figure 5In the process of reconstructing timing path C, it can first be determined that the second target logic unit included in the difference set between the third logic unit set corresponding to the reconstructed timing path A and the second logic unit set corresponding to timing path C is a data selector, an AND gate, an OR gate, and an XOR gate. Then, it can be determined that the types of the first-level logic units in timing path C are different from those in the first-level logic units of the reconstructed timing path A. At this point, the data selector in the first level of the reconstructed timing path A can be inserted into the first level of timing path C. Then, the second and third level logic units of timing path C and the reconstructed timing path A are compared sequentially. An AND gate is inserted in the second level of timing path C, and an OR gate is inserted in the third level of timing path C. The types of the fourth-level logic units in timing path C and the reconstructed timing path A are the same. The types of the fifth-level logic units in timing path C and the reconstructed timing path A are different. An XOR gate is inserted in the fifth level of timing path C, making the logic structure of timing path C the same as that of timing path A. Similarly, timing path B is reconstructed according to the logic structure of the reconstructed timing path A. At the same level in timing paths A, B, and C, the logic units are of the same type, compared to... Figure 3 The timing path shown, Figure 5 The logical structures of timing paths A, B, and C are completely identical, and the delay times of the data signals in timing paths A, B, and C are much closer.

[0077] In practical applications, during the reconstruction of timing paths, controlling different timing paths to have the same number of levels and the same type of logic units at the same level can make the timing paths have the same logical structure. Timing paths with the same logical structure have closer delay times.

[0078] Optionally, the method may further include: controlling the driving capability of logic units at the same level in multiple timing paths to be the same.

[0079] In this embodiment, during the reconstruction of the timing path, the logic units at the same level of the timing path can be controlled to have the same type and the same driving capability. Referring to the example above, during the reconstruction of timing path A, the driving capability of each logic unit in timing path A can be recorded. During the reconstruction of timing paths B and C, the driving capabilities of logic units at the same level can be set to be the same. For example, in the reconstructed timing path A, the driving capability of the NAND gate at the fourth level is "X2". During the reconstruction of timing paths B and C, NAND gates with a driving capability of "X2" can be inserted at the fourth level of timing paths B and C, respectively.

[0080] In practical applications, the delay time of data signals in logic units is negatively correlated with the driving capability of logic units. For timing paths with the same logic structure, setting logic units with the same driving capability at the same level can make different timing paths have the same driving capability, and can further make the delay time of different timing paths closer.

[0081] In one embodiment, for the driving capabilities of logic units at the same level in different timing paths within a timing path group, the highest driving capability can be selected as the unified driving capability for all logic units at the same level. For example, in determining the reference logic unit set, the electronic device can statistically analyze the driving capabilities of each logic unit included in timing paths A, B, and C, and for each type of logic unit, select the highest driving capability as the driving capability for logic units of the same type. Combined with... Figure 2 and Figure 5 As shown, before refactoring the timing paths, the drive capability of the data selectors in timing path A is "X2", and the drive capability of the data selectors in timing path B is "X3". The larger drive capability "X3" can be used as the drive capability of the data selectors during timing path refactoring. During the timing path refactoring process, the drive capability of the data selectors in timing paths A, B, and C is set to "X3". In practical applications, setting a larger drive capability for logic units can shorten the latency of the timing paths.

[0082] In one embodiment, after the timing path is reconstructed, it can be verified to confirm that its logical function remains unchanged before and after reconstruction. Specifically, formal verification tools can be used to verify the logical function of the timing path. If it is determined that the logical function of the reconstructed timing path has changed, the timing path can be reconstructed again to ensure that its logical function remains unchanged.

[0083] Step 404: Following the same layout rules, lay out the logic units included in each timing path to obtain the primary layout corresponding to the target gate-level netlist.

[0084] In this embodiment, after obtaining the target gate-level netlist, layout design can be performed based on the target gate-level netlist to generate a primary layout of the circuit module. For example, a placement and routing tool (such as an IC Compiler) can be used for placement planning to determine the size of the circuit module corresponding to the target gate-level netlist and to place the position of each logic unit in the target gate-level netlist. Referring to the above example, during the placement of logic units in timing path A, the Manhattan distance between two adjacent logic units can be controlled to be X. During the placement of logic units in timing path B, the Manhattan distance between two adjacent logic units can also be controlled to be X. Similarly, during the placement of logic units in timing path C, the Manhattan distance between two adjacent logic units can also be controlled to be X. By sequentially placing timing paths A, B, and C, a primary layout corresponding to the target gate-level netlist is obtained. Specific placement rules can be set according to requirements; this embodiment does not impose any restrictions on this.

[0085] In practical applications, when using the same layout rules to lay out different timing paths, it is possible to give different timing paths the same physical structure. Since the physical structure of a timing path affects its latency, when the physical structures of timing paths are the same, the latency of different timing paths will be closer.

[0086] Step 405: In the primary layout, set the routing of each timing path according to the same routing rules to obtain the target layout corresponding to the target gate-level netlist.

[0087] In this embodiment, after the timing paths are laid out, the same routing rules can be used to set the traces for each timing path. The routing rules can include at least one of the following routing parameters: trace width, trace spacing, and trace metal layer. For example, when setting the traces for timing path A in the primary layout, the trace width and trace spacing of timing path A, as well as the corresponding trace metal layer, can be recorded. When setting up timing paths B and C, the same metal layer as timing path A can be used for routing, and the same trace spacing and trace width can be used for setting the traces for timing paths B and C, making the routing rules for timing paths A, B, and C identical. Specific routing rules can be set according to requirements; this embodiment does not impose any limitations on this.

[0088] During the actual operation of a chip, the routing width, routing spacing, and routing metal layers of a timing path can affect the timing path's delay time. When the routing rules of different timing paths are the same, the delay times of multiple timing paths can be made closer.

[0089] Optionally, prior to step 401, the method may further include:

[0090] While keeping the logical function of the timing path unchanged, the logical units with the same function in the timing path are replaced by logical units from a preset set of logical units. The preset set of logical units includes pre-set logical units used to simplify the structure of the timing path.

[0091] In this embodiment, before reconstructing the timing path, simple logic units can be used to simplify it. For example, logic units from a preset logic unit set can replace functionally identical logic units in the timing path. Users can pre-add simple logic units such as AND gates, NAND gates, OR gates, NOR gates, XNOR gates, XOR gates, inverters, and buffers to the preset logic unit set. After determining the timing path, the electronic device can first scan the timing path and replace functionally identical combinational logic units in the timing path with logic units from the preset logic unit set to simplify the timing path structure. After simplifying the timing path with simple logic units, simple logic units can be inserted into the timing path during the timing path reconstruction stage, so that the reconstructed logic units have a simple structure, further simplifying the chip structure. The specific types and structures of the logic units included in the preset logic unit set can be set according to requirements, and this embodiment does not impose any restrictions on this.

[0092] In summary, this embodiment obtains the original gate-level netlist and the corresponding timing constraint file. Based on the original gate-level netlist and the timing constraint file, the timing path groups included in the original gate-level netlist are determined. The logical functions of the timing paths in the timing path groups remain unchanged, and some or all of the timing paths are reconstructed to obtain the target gate-level netlist. In the reconstructed timing path groups, each level of logic unit included in the timing path can find the same type of logic unit in any other timing path within the timing path group. This ensures that when data signals propagate through different timing paths, the number and type of logic units they pass through are the same, thereby making the delay times of multiple timing paths the same or similar, and allowing for more accurate control of the delay offset between timing paths.

[0093] Figure 6 A structural block diagram of an embodiment of a gate-level netlist processing apparatus according to the present invention is shown. (Refer to...) Figure 6 The gate-level netlist processing device 600 provided in this embodiment is disposed in an electronic device and may include the following modules:

[0094] Module 601 is used to acquire the original gate-level netlist and the corresponding timing constraint file;

[0095] The determination module 602 is used to determine the timing path group included in the original gate-level netlist and timing constraint file, wherein the timing path group includes multiple timing paths for which delay offset needs to be controlled;

[0096] The refactoring module 603 is used to refactor the timing paths in the timing path group while keeping the logical function of the timing path unchanged, to obtain the target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logic unit included in the timing path group, a logic unit of the same type can be found in any other timing path in the timing path group.

[0097] Optionally, the reconfiguration module 603 is also used to control that the logical units at the same level in multiple timing paths are of the same type.

[0098] Optionally, the reconfiguration module 603 is also used to control the driving capability of logic units at the same level in multiple timing paths to be the same.

[0099] Optionally, the refactoring module 603 is specifically used to determine a reference logic unit set, wherein the reference logic unit set consists of logic units of all types in the timing path group, and the number of logic units of each type reaches a target number, wherein the target number is the maximum number of logic units of the corresponding type in the same timing path in the timing path group; determine a first timing path and a corresponding first logic unit set, wherein the first timing path is the timing path with the largest level in the timing path group, and the first logic unit set consists of logic units in the first timing path; determine a second timing path and a corresponding second logic unit set; wherein the second timing path is any timing path in the timing path group other than the first timing path. The second set of logic units consists of logic units in the corresponding second timing path; a first target logic unit is inserted into the first timing path, and the logic function of the first timing path is kept unchanged, thereby reconstructing the first timing path, wherein the first target logic unit is the logic unit included in the difference set between the first set of logic units and the reference set of logic units; a second target logic unit is inserted into the second timing path, and the logic function of the second timing path is kept unchanged, thereby reconstructing the second timing path, wherein the second target logic unit is the logic unit included in the difference set between the second set of logic units and the third set of logic units, and the third set of logic units consists of logic units in the reconstructed first timing path.

[0100] Optionally, the device further includes a layout module for laying out the logic units included in each timing path according to the same layout rules, so as to obtain a primary layout corresponding to the target gate-level netlist.

[0101] Optionally, the device further includes a routing module for setting the routing of each timing path in the primary layout according to the same routing rules to obtain a target layout corresponding to the target gate-level netlist.

[0102] Optionally, the device further includes: a replacement module, used to keep the logical function of the timing path unchanged, and to replace the logical units with the same function in the timing path with logical units from a preset set of logical units, wherein the preset set of logical units includes pre-set logical units for simplifying the structure of the timing path.

[0103] In summary, this embodiment obtains the original gate-level netlist and the corresponding timing constraint file. Based on the original gate-level netlist and the timing constraint file, the timing path groups included in the original gate-level netlist are determined. The logical functions of the timing paths in the timing path groups remain unchanged, and some or all of the timing paths are reconstructed to obtain the target gate-level netlist. In the reconstructed timing path groups, each level of logic unit included in the timing path can find the same type of logic unit in any other timing path within the timing path group. This ensures that when data signals propagate through different timing paths, the number and type of logic units they pass through are the same, thereby making the delay times of multiple timing paths the same or similar, and allowing for more accurate control of the delay offset between timing paths.

[0104] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0105] Figure 7 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention is shown, with reference to... Figure 7 The electronic device 700 may include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.

[0106] Processing component 702 typically controls the overall operation of electronic device 700, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 702 may include one or more modules to facilitate interaction between processing component 702 and other components. For example, processing component 702 may include a multimedia module to facilitate interaction between multimedia component 708 and processing component 702.

[0107] Memory 704 is configured to store various types of data to support the operation of device 700. Examples of this data include instructions for any application or method operating on electronic device 700, contact data, phonebook data, messages, pictures, videos, etc. Memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0108] Power supply component 706 provides power to various components of electronic device 700. Power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 700.

[0109] Multimedia component 708 includes a screen that provides an output interface between the electronic device 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 708 includes a front-facing camera and / or a rear-facing camera. When the electronic device 700 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0110] Audio component 710 is configured to output and / or input audio signals. For example, audio component 710 includes a microphone (MIC) configured to receive external audio signals when electronic device 700 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 704 or transmitted via communication component 716. In some embodiments, audio component 710 also includes a speaker for outputting audio signals.

[0111] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.

[0112] Sensor assembly 714 includes one or more sensors for providing state assessments of various aspects of electronic device 700. For example, sensor assembly 714 may detect the on / off state of device 700, the relative positioning of components such as the display and keypad of electronic device 700, changes in position of electronic device 700 or a component of electronic device 700, the presence or absence of user contact with electronic device 700, orientation or acceleration / deceleration of electronic device 700, and temperature changes of electronic device 700. Sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 714 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0113] Communication component 716 is configured to facilitate wired or wireless communication between electronic device 700 and other devices. Electronic device 700 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 714 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 714 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0114] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0115] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, which can be executed by a processor 720 of an electronic device 700 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0116] A computer-readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the gate-level netlist processing method described in one or more of the above embodiments, the method comprising:

[0117] Obtain the original gate-level netlist and the corresponding timing constraint file;

[0118] Based on the original gate-level netlist and timing constraint file, determine the timing path groups included in the original gate-level netlist, where each timing path group includes multiple timing paths for which delay offset needs to be controlled.

[0119] While keeping the logical function of the timing path unchanged, the timing paths in the timing path group are reconstructed to obtain the target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logic unit included in the timing path group, a logic unit of the same type can be found in any other timing path in the timing path group.

[0120] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0121] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0122] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0123] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0124] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0125] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0126] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0127] The present invention has provided a detailed description of a gate-level netlist processing method and apparatus, an electronic device, and a storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for processing gate-level netlists, characterized in that, include: Obtain the original gate-level netlist and the corresponding timing constraint file; Based on the original gate-level netlist and the timing constraint file, determine the timing path group included in the original gate-level netlist, wherein the timing path group includes multiple timing paths for which delay offset needs to be controlled; While keeping the logical function of the timing path unchanged, the timing paths in the timing path group are reconstructed to obtain a target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logical unit included in the timing path group, a logical unit of the same type can be found in any other timing path in the timing path group.

2. The method according to claim 1, characterized in that, The step of maintaining the logical function of the timing path unchanged and reconstructing the timing paths in the timing path group to obtain the target gate-level netlist includes: Control that the logic units at the same level in multiple timing paths are of the same type.

3. The method according to claim 2, characterized in that, Also includes: The driving capability of logic units at the same level in multiple timing paths is the same.

4. The method according to any one of claims 1-3, characterized in that, The step of maintaining the logical function of the timing path unchanged and reconstructing the timing paths in the timing path group to obtain the target gate-level netlist includes: A reference logic unit set is determined, wherein the reference logic unit set consists of all types of logic units in the timing path group, and the number of logic units of each type reaches a target number, wherein the target number is the maximum number of logic units of the corresponding type in the timing path group in the same timing path; Determine a first timing path and a corresponding first set of logic units, wherein the first timing path is the timing path with the largest number of levels in the timing path group, and the first set of logic units is composed of the logic units in the first timing path; A second timing path and a corresponding set of second logic units are determined; the second timing path is any timing path in the timing path group other than the first timing path, and the set of second logic units is composed of logic units in the corresponding second timing path; Insert a first target logic unit into the first timing path and keep the logic function of the first timing path unchanged, thereby reconstructing the first timing path. The first target logic unit is the logic unit included in the difference set between the first logic unit set and the reference logic unit set. A second target logic unit is inserted into the second timing path, and the logic function of the second timing path is kept unchanged, thereby reconstructing the second timing path. The second target logic unit is the logic unit included in the difference set between the second logic unit set and the third logic unit set. The third logic unit set is composed of the logic units in the reconstructed first timing path.

5. The method according to claim 1, characterized in that, After reconstructing the timing paths in the timing path group while maintaining the logical function of the timing paths unchanged to obtain the target gate-level netlist, the method further includes: Following the same layout rules, the logic units included in each of the timing paths are laid out to obtain a primary layout corresponding to the target gate-level netlist.

6. The method according to claim 5, characterized in that, After laying out the logic units included in each of the timing paths according to the same layout rules to obtain the primary layout corresponding to the target gate-level netlist, the process further includes: In the primary layout, the routing of each timing path is set according to the same routing rules to obtain the target layout corresponding to the target gate-level netlist.

7. The method according to claim 1, characterized in that, Before reconstructing the timing paths in the timing path group while maintaining the logical function of the timing paths unchanged to obtain the target gate-level netlist, the method further includes: While keeping the logical function of the timing path unchanged, logical units with the same function in the timing path are replaced by logical units from a preset set of logical units. The preset set of logical units includes pre-set logical units used to simplify the structure of the timing path.

8. A gate-level netlist processing apparatus, characterized in that, include: The acquisition module is used to acquire the original gate-level netlist and the corresponding timing constraint file; The determination module is used to determine the timing path group included in the original gate-level netlist based on the original gate-level netlist and the timing constraint file, wherein the timing path group includes multiple timing paths for which delay offset needs to be controlled; The refactoring module is used to refactor the timing paths in the timing path group while keeping the logical function of the timing path unchanged, to obtain a target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logical unit included in the timing path group, a logical unit of the same type can be found in any other timing path in the timing path group.

9. An electronic device, characterized in that, It includes a memory and one or more processors, wherein the memory stores one or more programs and is configured to be executed by the one or more processors, the one or more programs containing instructions for performing the following operations: Obtain the original gate-level netlist and the corresponding timing constraint file; Based on the original gate-level netlist and the timing constraint file, determine the timing path group included in the original gate-level netlist, wherein the timing path group includes multiple timing paths for which delay offset needs to be controlled; While keeping the logical function of the timing path unchanged, the timing paths in the timing path group are reconstructed to obtain a target gate-level netlist. In the target gate-level netlist, the number of levels of each timing path in the timing path group is the same, and for each level of logical unit included in the timing path group, a logical unit of the same type can be found in any other timing path in the timing path group.

10. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the gate-level netlist processing method as described in any one of claims 1-7.

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