Error measurement method and device for two-bit quantum logic gate and quantum computer

Abstract

The application discloses an error measurement method and device of a two-bit quantum logic gate and a quantum computer, specifically, quantum states of two coupled quantum bits are prepared to a |11> state, the two quantum bits are in an excited state, a plurality of two-bit quantum logic gate operations are continuously applied to the two quantum bits to continuously accumulate high excited state leakage of the quantum bits, thereby amplifying errors of the two-bit quantum logic gate caused by high excited state leakage of the quantum bits, then, final state information of one of the quantum bits is measured, and errors of the two-bit quantum logic gate are obtained based on the final state information, so as to provide a basis for studying control waveforms of high-precision two-bit quantum logic gates.

Description

Technical Field

[0001] The present application relates to the field of quantum information, and in particular to a method and device for measuring the error of a two-bit quantum logic gate and a quantum computer. Background Art

[0002] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. The core of a quantum computer is the multi-bit qubit integrated on a quantum chip. The performance of a quantum computer is primarily determined by the number of qubits integrated on the quantum chip and the performance of the qubits. Qubit performance metrics include the fidelity of single-bit quantum logic gates and the fidelity of two-bit quantum logic gates.

[0003] In related technologies, the fidelity of single-bit quantum logic gates can generally reach 99.9%, meeting the requirements of many quantum algorithms. Currently, the low manipulation precision of two-bit quantum logic gates causes leakage of highly excited states of the qubit, resulting in errors in the two-bit quantum logic gates. This error also affects the fidelity of the two-bit quantum logic gates, further reducing qubit performance. Therefore, to achieve optimal qubit performance, obtaining high-fidelity two-bit quantum logic gates is a core issue in current quantum computing.

[0004] The control waveform of a high-precision two-bit quantum logic gate is crucial for achieving high-fidelity two-bit quantum logic gates. The error in a two-bit quantum logic gate is primarily related to the accuracy of the control waveform. Therefore, measuring this error provides a basis for studying the control waveform of high-precision two-bit quantum logic gates. Summary of the Invention

[0005] The inventors have found in actual applications that the error caused by a single two-bit quantum logic gate is easily submerged in the quantum state reading error of the quantum bit and cannot be measured. Therefore, the purpose of this application is to provide an error measurement method, device and quantum computer for a two-bit quantum logic gate, which can amplify the error of the two-bit quantum logic gate and thus measure the error of the two-bit quantum logic gate.

[0006] To achieve the above objectives, the first embodiment of the present application proposes a method for measuring the error of a two-bit quantum logic gate, comprising:

[0007] preparing the quantum states of the two coupled qubits to a |11> state, wherein the |11> state is used to indicate that the quantum states of the two qubits are both excited states;

[0008] Continuously applying a plurality of two-bit quantum logic gate operations to the two quantum bits;

[0009] measuring final state information of one of the quantum bits;

[0010] An error of a two-bit quantum logic gate is obtained based on the final state information.

[0011] The second embodiment of the present application provides an error measurement device for a two-bit quantum logic gate, comprising:

[0012] A quantum state initialization module, configured to prepare the quantum states of two coupled qubits to a |11> state, wherein the |11> state indicates that the quantum states of the two qubits are both excited states;

[0013] a frequency control module, configured to continuously apply a plurality of two-bit quantum logic gate operations to the two quantum bits;

[0014] A quantum state measurement module, configured to measure the final state information of one of the quantum bits;

[0015] An error observation module is used to obtain the error of the two-bit quantum logic gate based on the final state information.

[0016] The third embodiment of the present application proposes a quantum computer, including the error measurement device of the two-bit quantum logic gate as described above.

[0017] The fourth aspect of the present application provides a readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it can implement the error measurement method steps of the two-bit quantum logic gate as described in any one of the above items.

[0018] Compared with the prior art, this application has the following beneficial effects:

[0019] In the embodiment of the present application, the quantum state of two coupled qubits is prepared to the |11> state, so that both qubits are in an excited state. Multiple two-bit quantum logic gate operations are then continuously applied to the two qubits to continuously accumulate the highly excited state leakage of the qubits, thereby amplifying the error of the two-bit quantum logic gate caused by the highly excited state leakage of the qubits. The final state information of one of the qubits is then measured, and the error of the two-bit quantum logic gate is obtained based on the final state information, providing a basis for studying the control waveform of a high-precision two-bit quantum logic gate.

[0020] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application and should not be regarded as limiting the scope. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a block diagram of the internal structure of a quantum chip in related technologies;

[0023] Figure 2 This is a flowchart of the error measurement method for a two-bit quantum logic gate provided in one embodiment of the present application;

[0024] Figure 3 This is a flowchart of the process of step S2 of the method provided in one embodiment of the present application;

[0025] Figure 4 This is a schematic diagram of the timing of applying relevant signals during a single measurement operation of a two-bit quantum logic gate error provided in an example of the present application;

[0026] Figure 5A This is the measurement data of 5 CZ gate operations provided in an example of this application;

[0027] Figure 5B This is the measurement data of 10 CZ gate operations provided in an example of this application;

[0028] Figure 5C This is the measurement data of 12 CZ gate operations provided in an example of this application;

[0029] Figure 5D This is the measurement data of 15 CZ gate operations provided in an example of this application;

[0030] Figure 5E This is the measurement data of 18 CZ gate operations provided in an example of this application;

[0031] Figure 6 This is a structural block diagram of an error measurement device for a two-bit quantum logic gate provided in one embodiment of the present application. DETAILED DESCRIPTION

[0032] The following is a more detailed description of the specific embodiments of the present application, with reference to schematic diagrams. The advantages and features of the present application will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present application.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referenced. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0034] The method provided in the embodiments of the present application can be applied to a computer terminal, or so-called quantum computer.

[0035] In a quantum computer, a quantum chip is the processor that performs quantum computations, see Figure 1 The quantum chip integrates multiple, one-to-one, and mutually coupled qubits and readout resonant cavities. The section of each readout resonant cavity away from the corresponding qubit is connected to a readout signal transmission line integrated on the quantum chip. Each qubit is coupled to an XY signal transmission line and a Z signal transmission line. The XY signal transmission line is used to receive quantum state control signals, and the Z signal transmission line is used to receive frequency control signals. The frequency control signals include bias voltage signals and / or pulse bias control signals. The bias voltage signal can coarsely adjust the frequency of the qubit, and the pulse bias control signal can finely adjust the frequency of the qubit. The readout signal transmission line is used to receive readout detection signals and transmit readout feedback signals.

[0036] The control and processing process of quantum bits is briefly described as follows:

[0037] The bias voltage signal on the Z signal transmission line adjusts the frequency of the qubit to the operating point frequency. The pulse bias control signal on the Z signal transmission line further fine-tunes the operating point frequency of the qubit to a specific frequency. A quantum state control signal is then applied via the XY signal transmission line to control the quantum state of the qubit in its initial state. Finally, a read resonant cavity is used to read (or measure) the quantum state of the controlled qubit. It should be noted that the operating point frequency and the specific frequency can be set based on actual application requirements and are not specifically limited here.

[0038] Specifically, a loaded pulse signal, commonly referred to as a read probe signal, is applied through a read signal transmission line. The read probe signal is typically a microwave signal with a frequency of 4-8 GHz. The quantum state of the qubit is determined by analyzing the read feedback signal output by the read signal transmission line. The fundamental reason why the read resonant cavity can read the quantum state of the qubit is that different quantum states of the qubit produce different dispersion frequency shifts in the read resonant cavity. As a result, different quantum states of the qubit have different responses to the read probe signal applied to the read resonant cavity. This response signal is called the read feedback signal. Only when the carrier frequency of the qubit's read probe signal is very close to the natural frequency (also called the resonant frequency) of the read resonant cavity will the read resonant cavity show significant differences in the response of the qubit to the read probe signal due to different quantum states of the qubit, thus maximizing the distinguishability of the read feedback signal. Based on this, the quantum state of the qubit is determined by analyzing the read feedback signal of a certain pulse length. For example, each acquired read feedback signal is converted into a coordinate point in an orthogonal plane coordinate system (i.e., the IQ coordinate system). Based on the position of the coordinate point, the corresponding quantum state is determined to be the ground state (|0> state) or the excited state (|1> state). It can be understood that the |0> state and the |1> state are two eigenstates of the quantum bit.

[0039] In related technologies, most quantum algorithms are implemented using quantum gate circuits. The overall concept of quantum computers based on quantum gate circuits is similar to that of classical computers. First, several basic quantum logic gates are implemented. These gates are then combined to complete quantum algorithms and perform calculations. Quantum logic gate operations primarily consist of single-bit quantum logic gates and two-bit quantum logic gates, although multi-bit quantum logic gates also exist. It has been theoretically proven that any combination of a single-bit quantum logic gate operation and any two-bit quantum logic gate (also known as a "two-bit quantum entanglement gate") can realize any quantum logic gate operation in a complex system.

[0040] An ideal qubit is a two-level system, correspondingly consisting of only a ground state and an excited state. However, in practical applications, qubits are implemented using the lowest two energy levels of a multi-level system, and the energy levels of qubits transition stepwise. Therefore, when the control signal applied to a qubit in a two-bit quantum logic gate is not precise, the qubit may be excited to a higher-energy state (|2> state) than the excited state. Consequently, the error of the two-bit quantum logic gate includes errors caused by leakage from the qubit's higher-energy state, i.e., leakage error. This error is primarily related to the operational accuracy of the two-bit quantum logic gate, specifically the parameter accuracy of the control waveform (or "control signal") of the two-bit quantum logic gate. Furthermore, the inventors have discovered in practical applications that leakage errors caused by the operation of a single two-bit quantum logic gate are easily overwhelmed by the quantum state readout error of the qubit, making them unmeasurable.

[0041] Based on this, the present application proposes a two-bit quantum logic gate error measurement method, device and quantum computer. It realizes the accumulation of high-excited state leakage of quantum bits by performing multiple consecutive two-bit quantum logic gate operations on two coupled quantum bits, thereby amplifying the leakage error in the error of the two-bit quantum logic gate and realizing the measurement of the error, providing a basis for studying the control waveform of high-precision two-bit quantum logic gates.

[0042] Please refer to Figure 2 , an embodiment of the present application provides an error measurement method for a two-bit quantum logic gate, comprising:

[0043] S1: preparing the quantum states of two coupled quantum bits to a |11> state, wherein the |11> state indicates that the quantum states of the two quantum bits are both excited states.

[0044] In this step, two mutually coupled qubits are selected to perform a two-bit quantum logic gate operation. A quantum state control signal is applied via the XY signal transmission line connecting the two qubits to control the quantum state of the two qubits to the |11> state.

[0045] S2: Continuously applying a plurality of two-bit quantum logic gate operations to the two quantum bits.

[0046] In this step, multiple two-bit quantum logic gate control waveforms are continuously applied to the two qubits in the |11> state. Specifically, multiple frequency control signals corresponding to the two-bit quantum logic gates are applied to the corresponding qubits via the Z signal transmission line connecting the two qubits, thereby completing the two-bit quantum logic gate operation on the two qubits. The number of two-bit quantum logic gate operations can be set based on actual application requirements and is not specifically limited here.

[0047] S3: Measure the final state information of one of the quantum bits.

[0048] It should be noted that in this step, the final state information of the qubit refers to the quantum state information of the qubit after manipulation. This quantum state information includes all data regarding the qubit's quantum state, including the ground state, excited state, and highly excited state. Obtaining the quantum state of the qubit after manipulation specifically involves applying a read probe signal to the qubit via a read signal transmission line connected to the qubit, receiving a corresponding read feedback signal, and analyzing the read feedback signal to obtain the final state of the qubit. This final state is one of the ground state, excited state, and highly excited state. In other words, a single measurement of the qubit only reveals one of its quantum states. Therefore, a large number of qubit measurements are required to obtain this quantum state information.

[0049] S4: Obtaining an error of a two-bit quantum logic gate based on the final state information.

[0050] In this step, the quantum state of the regulated quantum bit is affected by the operation of the two-bit quantum logic gate. Therefore, the error of the two-bit quantum logic gate can be obtained from the final state information.

[0051] It can be seen that in the embodiment of the present application, the quantum state of two coupled quantum bits is prepared to the |11> state, so that both of the quantum bits are in an excited state, and then a plurality of two-bit quantum logic gate operations are continuously applied to the two quantum bits to continuously accumulate the high excited state leakage of the quantum bits, thereby amplifying the error of the two-bit quantum logic gate caused by the high excited state leakage of the quantum bits, and then measuring the final state information of one of the quantum bits, and obtaining the error of the two-bit quantum logic gate based on the final state information, so as to provide a basis for studying the control waveform of the high-precision two-bit quantum logic gate.

[0052] As a specific implementation of the embodiment of the present application, in step S1, preparing the initial state of the two coupled quantum bits to the |11> state specifically includes:

[0053] Initializing the quantum states of the two quantum bits to a |00> state, wherein the |00> state indicates that the quantum states of the two quantum bits are both ground states.

[0054] A π pulse is applied to each of the two quantum bits simultaneously to prepare the quantum states of the two quantum bits to a |11> state.

[0055] It should be noted that in order to precisely control the quantum states of the two qubits to an excited state, they must first be initialized to the ground state. Those skilled in the art will appreciate that applying a π pulse as the quantum state control signal to a qubit in the ground state can control the quantum state of that qubit to an excited state. Therefore, by simultaneously applying a π pulse to each of the two qubits in the ground state, the quantum states of both qubits can be simultaneously controlled (i.e., prepared) to an excited state, namely the |11> state.

[0056] As a specific implementation of the embodiment of this application, please refer to Figure 3 In step S2, the step of continuously applying a plurality of two-bit quantum logic gate operations to the two quantum bits specifically includes:

[0057] S21: Mark the two quantum bits as a low-frequency quantum bit and a high-frequency quantum bit, respectively.

[0058] It should be noted that in quantum computing, a two-bit quantum logic gate is a type of quantum logic gate operation that can produce an entangled state of two quantum bits. Common two-bit quantum logic gates include SWAP gates, iSWAP gates, and controllable phase gates (Controlled-NOT (CNOT gate), Controlled-Z (CZ gate), and Controlled-U gate). The two-bit quantum logic gate operation applied to two quantum bits specifically regulates the frequency of the two quantum bits, and changes in the frequency affect the quantum state of the quantum bits. In the embodiments of the present application, the two-bit quantum logic gate operation can be any one of a SWAP gate operation, an iSWAP gate operation, and a controllable phase gate operation, and is not specifically limited here.

[0059] Therefore, in order to distinguish the two qubits acting on a two-bit quantum logic gate, in this step, the two qubits are respectively labeled as the low-frequency qubit with a lower frequency and the high-frequency qubit with a higher frequency, wherein the operating point frequency of the low-frequency qubit is lower than the operating point frequency of the high-frequency qubit. In practical applications, the low-frequency qubit can be used as the target bit of a two-bit quantum logic gate, and the high-frequency qubit as the control bit of the two-bit quantum logic gate; the high-frequency qubit can be used as the target bit of a two-bit quantum logic gate, and the low-frequency qubit as the control bit of the two-bit quantum logic gate; the low-frequency qubit and the high-frequency qubit can also be used as the control bits of a two-bit quantum logic gate, and either the low-frequency qubit or the high-frequency qubit can be used as the target bit of a two-bit quantum logic gate, without limitation here.

[0060] S22: Continuously applying a plurality of the two-bit quantum logic gate operations to the low-frequency quantum bit and / or the high-frequency quantum bit.

[0061] Those skilled in the art will understand that applying a two-bit quantum logic gate operation to two qubits simply involves applying the control waveform of the two-bit quantum logic gate to the two qubits. Furthermore, the specific qubit to which the control waveform is applied can be determined based on the set operating point parameters of the two-bit quantum logic gate control waveform. In this step, the sequential application of multiple two-bit quantum logic gate operations to the low-frequency qubit and / or the high-frequency qubit involves sequentially splicing the control waveforms of multiple two-bit quantum logic gates together and applying them sequentially to the low-frequency qubit and / or the high-frequency qubit.

[0062] Preferably, the number of two-bit quantum logic gate operations is no less than three, that is, the number of two-bit quantum logic gate control waveforms continuously applied to the corresponding qubit is no less than three. Furthermore, the operating point parameters of the control waveforms of the multiple two-bit quantum logic gates are the same. When the multiple two-bit quantum logic gate control waveforms are continuously applied to the low-frequency qubit (or the high-frequency qubit), multiple zero waveforms of the same width as the two-bit quantum logic gate control waveform are also continuously applied to the high-frequency qubit (or the low-frequency qubit).

[0063] It should be noted that, relative to the zero waveform, the control waveform of the two-bit quantum logic gate is a non-zero waveform. Both this waveform and the zero waveform are applied to the quantum bit as pulse bias control signals.

[0064] When the control waveform of the two-bit quantum logic gate is applied to the low-frequency quantum bit and the zero waveform is applied to the high-frequency quantum bit, the frequency of the low-frequency quantum bit is specifically adjusted to the specific frequency of the high-frequency quantum bit, so that the low-frequency quantum bit and the high-frequency quantum bit resonate at this frequency, thereby changing the quantum state of the two quantum bits.

[0065] When the control waveform of the two-bit quantum logic gate is applied to the high-frequency quantum bit and the zero waveform is applied to the low-frequency quantum bit, the frequency of the high-frequency quantum bit is specifically adjusted to the specific frequency of the low-frequency quantum bit, so that the low-frequency quantum bit and the high-frequency quantum bit resonate at this frequency, thereby changing the quantum state of the two quantum bits.

[0066] When the control waveform of the two-bit quantum logic gate is applied to the low-frequency quantum bit and the high-frequency quantum bit, the frequencies of the low-frequency quantum bit and the high-frequency quantum bit are specifically adjusted to a predetermined specific frequency, so that the low-frequency quantum bit and the high-frequency quantum bit resonate at the frequency, thereby changing the quantum state of the two quantum bits.

[0067] For example, if the low-frequency qubit is selected as the control bit of a two-bit quantum logic gate, multiple two-bit quantum logic gate control waveforms are continuously applied to the low-frequency qubit. In this case, the high-frequency qubit is the target bit of the two-bit quantum logic gate, and the final state information of the high-frequency qubit is measured.

[0068] If the high-frequency quantum bit is selected as the control bit of the two-bit quantum logic gate, multiple control waveforms of the two-bit quantum logic gate are continuously applied to the high-frequency quantum bit. At this time, the low-frequency quantum bit is used as the target bit of the two-bit quantum logic gate, and the final state information of the low-frequency quantum bit is measured.

[0069] If the low-frequency qubit and the high-frequency qubit are selected as control bits for a two-bit quantum logic gate, multiple two-bit quantum logic gate control waveforms are applied simultaneously and continuously to the low-frequency qubit and the high-frequency qubit. In this case, either the low-frequency qubit or the high-frequency qubit can be selected as the target bit for the two-bit quantum logic gate, and the final state information of the low-frequency qubit or the high-frequency qubit can be measured.

[0070] It should be noted that when different qubits are selected as control bits of the two-bit quantum logic gate, the operating point parameters of the control waveform of the two-bit quantum logic gate applied to the corresponding qubits are different.

[0071] As a specific implementation of the embodiment of the present application, in step S3, measuring the final state information of one of the quantum bits specifically includes:

[0072] Measure the final state information of the low-frequency quantum bit or the high-frequency quantum bit, wherein the final state information includes all data of the quantum state of the low-frequency quantum bit or the high-frequency quantum bit in the ground state, excited state and highly excited state after being controlled.

[0073] In this step, the object of measurement is the qubit used as the target bit of the two-bit quantum logic gate. When the low-frequency qubit is used as the target bit of the two-bit quantum logic gate, all data of the low-frequency qubit in the ground state, excited state, and highly excited state after being manipulated are measured. When the high-frequency qubit is used as the target bit of the two-bit quantum logic gate, all data of the high-frequency qubit in the ground state, excited state, and highly excited state after being manipulated are measured. Furthermore, when either the low-frequency qubit or the high-frequency qubit is selected as the target bit of the two-bit quantum logic gate, the errors of the two-bit quantum logic gate obtained by measurement are substantially the same.

[0074] As a specific implementation of the embodiment of the present application, in step S4, obtaining the error of the two-bit quantum logic gate based on the final state information specifically includes:

[0075] The final state information is processed into quantum state scattered point data in an IQ coordinate system.

[0076] A quantum state reading criterion is used to obtain the highly excited state scatter data contained in the quantum state scatter data, wherein the highly excited state scatter data is the error of a two-bit quantum logic gate, and the quantum state reading criterion is used to distinguish the ground state data, excited state data, and highly excited state data in the quantum state scatter data.

[0077] It should be noted that by applying different read detection signals to the corresponding qubit to be read and repeating this process, the resulting quantum state scatter data is distributed as two state circles in the IQ coordinate system, representing the two different eigenstates of the qubit to be read, specifically the |0> state and the |1> state. Therefore, the quantum state read criterion can be a binary read criterion for the qubit quantum state, namely, a state circle classification criterion for the qubit's |0> state and |1> state. This quantum state read criterion distinguishes ground state data from excited state data from the quantum state scatter data in the IQ coordinate system, and determines that the portion of the quantum state scatter data in the IQ coordinate system that is neither ground state data nor excited state data is highly excited state data, thereby obtaining the error of the two-bit quantum logic gate caused by the leakage of the qubit's highly excited state and amplified.

[0078] The quantum state reading criterion can also be a three-category reading criterion for the qubit quantum state, namely, a state spot classification criterion for the qubit's |0>, |1>, and |2> states. This quantum state reading criterion distinguishes ground state data, excited state data, and highly excited state data from the quantum state scatter data in the IQ coordinate system, thereby obtaining the amplified error of the two-bit quantum logic gate caused by leakage of the qubit's highly excited state.

[0079] The quantum state reading criterion may also be a reading criterion for four or more categories of qubit quantum states. In practical applications, as long as the quantum state reading criterion can distinguish highly excited state data from the quantum state scatter data, the specific classification criteria used in the quantum state reading criterion are not specifically limited.

[0080] Among all two-bit quantum logic gate operations, the controllable phase gate in the two-bit entanglement gate is a relatively important one. Theoretically, it has been proven that the combination of any single-bit quantum logic gate and a controllable phase gate can realize any quantum logic gate operation in a complex system.

[0081] For example, the specific operation process of the embodiment of the present application is illustrated below by taking the CZ gate in the controllable phase gate as an example.

[0082] In a quantum chip, coupled qubits Q2 and Q3 are selected, where qubit Q2 is the high-frequency qubit and qubit Q3 is the low-frequency qubit. Assume that the control waveform for the CZ gate operation is a flat-top Gaussian wave. The mathematical expression for the CZ gate control waveform is:

[0083]

[0084] Where Z(t) represents the control waveform of the CZ gate, A is the amplitude of the waveform, erf represents the error function, and the mathematical expression of the error function is σ is the width of the Gaussian filter used for smoothing, τ c is the center length of the waveform, τ b is the length of the buffer signal with zero amplitude set on both sides of the waveform. The total length of the CZ gate control waveform is τ c +2τ b .

[0085] In this example, the parameters of the control waveform of the CZ gate are set as follows: the amplitude A of the waveform is 1V, the width σ of the Gaussian filter is 1.25, the total length of the waveform is 90ns, and the center length τ of the waveform is c =60ns, the length of the buffer signal τ b =15ns.

[0086] Qubit Q2 is selected as the control bit for the CZ gate operation, and qubit Q3 is selected as the target bit for the CZ gate operation. The CZ gate control waveform can control the frequencies of qubits Q2 and Q3 to resonate, thereby preventing them from crossing near the resonance points of the |11> and |20> states. The |20> state indicates that one qubit is in a highly excited state while the other is in the ground state, indicating that both qubits are at the 20 energy level.

[0087] Specifically, the control waveform of the CZ gate is to regulate the resonance of the first transition frequency f01 of the quantum bit Q2 and the second transition frequency f12 of the quantum bit Q3, wherein the first transition frequency is the transition frequency of the quantum state of the quantum bit Q2 from the ground state to the excited state, and the second transition frequency is the transition frequency of the quantum state of the quantum bit Q3 from the excited state to the highly excited state.

[0088] It should be noted that the ground state (|0> state) and excited state (|1> state) of a single quantum bit are written in the form of a matrix: |0> state:

[10] T ,|1>State:

[01] T Therefore, the state basis vectors of the two qubits are written in the form of a matrix: |00> state:

[1000] T ,|01>State:

[0100] T ,|10>State:

[0010] T ,|11>State:

[0001] T Similarly, the meaning of the |20> state can be deduced, that is, its matrix dimension is extended from four to six, and the corresponding position is recorded as 1, indicating occupation.

[0089] Assume that multiple CZ gate control waveforms are applied continuously to qubit Q2, each with identical parameters. Because the CZ gate error contains leakage error, multiple CZ gates can be applied to qubit Q2 to accumulate the leakage error at the 20-level. Finally, the final state of qubit Q3 is measured to determine whether a |2> state spot exists. This |2> state spot represents the amplified leakage error.

[0090] See Figure 4 According to the steps of the method of the embodiment of the present application, qubit Q2 and qubit Q3 are first prepared to the excited state, so that qubit Q2 and qubit Q3 are in the |11> state. Then, N (N>3) control waveforms of the CZ gate are continuously applied to qubit Q2, and N zero waveforms with the same width as the control waveform of the CZ gate are continuously applied to qubit Q3. Then, the final state of qubit Q3 is measured, and the above operation is repeated multiple times (such as about 2000 times). Finally, the final state information of all data including qubit Q3 in the ground state, excited state and highly excited state can be obtained. Finally, the final state information of qubit Q3 is processed into quantum state scatter data in the IQ coordinate system, and the obtained quantum state scatter data is analyzed using the binary reading criterion of the qubit quantum state to measure the |2> state circular spot, thereby obtaining the error of the amplified CZ gate. Please refer to Figures 5A-5E , which are the test results of applying 5, 10, 12, 15, and 18 CZ gate control waveforms to qubit Q2, respectively. It can be seen that with the increase in the number of CZ gate control waveforms, the leakage error of qubits Q2 and Q3 at the 20 energy level is also accumulating. At the same time, the |2> state circular spot formed by the |2> state leakage can be seen more and more clearly in the IQ coordinate system.

[0091] Therefore, the method of the present embodiment can effectively measure the leakage error in the error of a two-bit quantum logic gate. Since this error is related to the accuracy of the control waveform parameters of the two-bit quantum logic gate, it can provide a basis for studying the control waveform of high-precision two-bit quantum logic gates. On this basis, by modifying the control waveform parameters of different two-bit quantum logic gates and observing the probability of the resulting |2> state circular spot in the quantum state scatter data, it is possible to determine which parameters of the two-bit quantum logic gate's control waveform contribute most to the error. This allows the identification of a set of high-precision control waveform parameters for the two-bit quantum logic gate that minimizes the leakage error, providing a basis for research into improving the fidelity of two-bit quantum logic gates.

[0092] See Figure 6Another embodiment of the present application provides an error measurement device for a two-bit quantum logic gate, comprising:

[0093] The quantum state initialization module 201 is used to prepare the quantum state of two coupled quantum bits to a |11> state, wherein the |11> state indicates that the quantum states of the two quantum bits are both excited states.

[0094] The frequency control module 202 is used to continuously apply multiple two-bit quantum logic gate operations to the two quantum bits.

[0095] The quantum state measurement module 203 is used to measure the final state information of one of the quantum bits.

[0096] The error observation module 204 is used to obtain the error of the two-bit quantum logic gate based on the final state information.

[0097] It is understandable that the quantum state initialization module 201, the frequency control module 202, the quantum state measurement module 203 and the error observation module 204 can be combined in one device for implementation, or any one of the modules can be split into multiple sub-modules, or at least part of the functions of one or more of the quantum state initialization module 201, the frequency control module 202, the quantum state measurement module 203 and the error observation module 204 can be combined with at least part of the functions of other modules and implemented in one functional module. According to an embodiment of the present application, at least one of the quantum state initialization module 201, the frequency control module 202, the quantum state measurement module 203 and the error observation module 204 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable way of integrating or packaging the circuit, or in an appropriate combination of software, hardware and firmware. Alternatively, at least one of the quantum state initialization module 201, the frequency control module 202, the quantum state measurement module 203 and the error observation module 204 can be at least partially implemented as a computer program module, and when the program is run by a computer, the function of the corresponding module can be executed.

[0098] Another embodiment of the present application proposes a quantum computer, including the error measurement device for the two-bit quantum logic gate as described above, or using the error measurement method for the two-bit quantum logic gate as described in any of the above items to obtain the error of the two-bit quantum logic gate.

[0099] Yet another embodiment of the present application provides a readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it can implement the error measurement method of the two-bit quantum logic gate as described in any one of the above items.

[0100] The readable storage medium can be a tangible device that can keep and store the instruction used by the instruction execution device, for example, can be but not limited to electric storage device, magnetic storage device, optical storage device, electromagnetic storage device, semiconductor storage device or above-mentioned any suitable combination.The more specific example (non-exhaustive list) of readable storage medium comprises: portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical coding device, for example, punch card or the convex structure in the groove that is stored thereon of instruction and above-mentioned any suitable combination.Computer program described herein can be downloaded to each calculating / processing device from readable storage medium, or by network, for example, the Internet, local area network, wide area network and / or wireless network, is downloaded to external computer or external storage device.Network can comprise copper transmission cable, optical fiber transmission, wireless transmission, router, firewall, switch, gateway computer and / or edge server. The network adapter card or network interface in each computing / processing device receives the computer program from the network and forwards the computer program for storage in a readable storage medium in each computing / processing device. The computer program for performing the operations of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, various aspects of the present invention are implemented by utilizing state information of a computer program to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), which can execute computer-readable program instructions.

[0101] Various aspects of the present invention are described herein with reference to the flowcharts and / or block diagrams of the methods, apparatus, and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams, as well as the combination of blocks in the flowcharts and / or block diagrams, can be implemented by computer programs. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine such that when these programs are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowcharts and / or block diagrams. These computer programs can also be stored in a readable storage medium, which causes the computer, programmable data processing device, and / or other device to operate in a specific manner, so that the readable storage medium storing the computer program comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowcharts and / or block diagrams.

[0102] The computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0103] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "example," or "specific example" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, those skilled in the art may combine and reconcile different embodiments or examples described in this specification.

[0104] The above is only a preferred embodiment of the present application and does not limit the present application in any way. Any person skilled in the art who, without departing from the scope of the technical solution of the present application, makes any equivalent substitution or modification to the technical solution and technical content disclosed in the present application shall be deemed to have not departed from the content of the technical solution of the present application and shall still fall within the scope of protection of the present application.

Claims

1. A method for measuring the error of a two-bit quantum logic gate, characterized in that: include: preparing the quantum states of the two coupled qubits to a |11> state, wherein the |11> state is used to indicate that the quantum states of the two qubits are both excited states; Continuously applying a plurality of two-bit quantum logic gate operations to the two quantum bits; Measuring the final state information of one of the quantum bits; wherein the final state information includes all data of the quantum state of the quantum bit being a ground state, an excited state, and a highly excited state; The error of the two-bit quantum logic gate is obtained based on the data of the highly excited state in the final state information.

2. The method according to claim 1, wherein The step of preparing the initial state of the two coupled quantum bits to a |11> state comprises: Initializing the quantum states of the two qubits to a |00> state, wherein the |00> state is used to indicate that the quantum states of the two qubits are both ground states; A π pulse is applied to each of the two quantum bits simultaneously to prepare the quantum states of the two quantum bits to a |11> state.

3. The method according to claim 1, wherein The step of continuously applying a plurality of two-bit quantum logic gate operations to the two quantum bits comprises: Marking the two qubits as a low-frequency qubit and a high-frequency qubit, respectively; A plurality of the two-bit quantum logic gate operations are continuously applied to the low-frequency quantum bit and / or the high-frequency quantum bit.

4. The method according to claim 3, wherein The measuring of the final state information of one of the quantum bits comprises: Measure the final state information of the low-frequency quantum bit or the high-frequency quantum bit, wherein the final state information includes data on the quantum state of the low-frequency quantum bit or the high-frequency quantum bit being in a ground state, an excited state, and a highly excited state after being controlled.

5. The method according to claim 4, wherein If a plurality of two-bit quantum logic gates are continuously applied to the low-frequency quantum bit, the final state information of the high-frequency quantum bit is measured; If a plurality of two-bit quantum logic gates are continuously applied to the high-frequency quantum bit, the final state information of the low-frequency quantum bit is measured; If a plurality of two-bit quantum logic gates are continuously applied to the low-frequency quantum bit and the high-frequency quantum bit simultaneously, the final state information of the low-frequency quantum bit or the high-frequency quantum bit is measured.

6. The method according to claim 1, wherein The obtaining of the error of the two-bit quantum logic gate based on the data of the highly excited state in the final state information includes: Processing the final state information into quantum state scattered point data in an IQ coordinate system; A quantum state reading criterion is used to obtain the highly excited state scatter data contained in the quantum state scatter data, wherein the quantum state reading criterion is used to distinguish the ground state data, excited state data and highly excited state data in the quantum state scatter data, and the highly excited state scatter data is the error of the two-bit quantum logic gate.

7. The method according to claim 1, wherein The number of the two-bit quantum logic gates is no less than 3.

8. The method according to any one of claims 1 to 7, wherein: The two-bit quantum logic gate adopts a controllable phase gate.

9. The method according to claim 8, wherein The two-bit quantum logic gate adopts a CZ gate.

10. The method according to claim 9, wherein The control waveform of the CZ gate adopts a flat-top Gaussian wave, and the control waveform parameters of each CZ gate are the same.

11. An error measurement device for a two-bit quantum logic gate, characterized in that: include: A quantum state initialization module, configured to prepare the quantum states of two coupled qubits to a |11> state, wherein the |11> state indicates that the quantum states of the two qubits are both excited states; a frequency control module, configured to continuously apply a plurality of two-bit quantum logic gate operations to the two quantum bits; A quantum state measurement module, configured to measure the final state information of one of the qubits; wherein the final state information includes all data of the quantum state of the qubit, namely, the ground state, the excited state, and the highly excited state; An error observation module is used to obtain the error of the two-bit quantum logic gate based on the data of the highly excited state in the final state information.

12. A quantum computer, characterized in that: An error measurement device comprising a two-bit quantum logic gate as claimed in claim 11.

13. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it can implement the error measurement method of the two-bit quantum logic gate as described in any one of claims 1 to 10.

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