Display panel, display unit and driving method thereof

Abstract

The display unit comprises a driving current module, a composite channel module and a third channel module. The driving current module is configured to output a driving current to a first node according to a data voltage. One end of the composite channel module is electrically connected with the first node, and the other end is used for loading a reference power voltage, and the composite channel module comprises a first channel module and a second channel module connected in series, and comprises a second control circuit. The first channel module comprises a first light emitting element and a first control circuit connected in parallel. The second channel module comprises a second light emitting element and a third control circuit connected in parallel. The second control circuit is used for controlling whether the composite channel module is electrically connected. One end of the third channel module is electrically connected with the first node, and the other end is used for loading the reference power voltage; and the third channel module comprises a first light emitting element and a fourth control circuit connected in series. The display unit can improve the resolution of the display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular, to a display panel, a display unit and a driving method thereof. BACKGROUND

[0002] In the field of OLED display, one sub-pixel is driven by one pixel driving circuit, and each sub-pixel is tiled in the pixel layer. However, with the increase of resolution, the layout area of the pixel driving circuit restricts the resolution more and more.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a display panel, a display unit and a driving method thereof, which can improve the resolution of the display panel.

[0005] According to a first aspect of the present disclosure, a display unit is provided, comprising:

[0006] a driving current module configured to output a driving current to a first node according to a data voltage;

[0007] a composite path module comprising a first path module and a second path module connected in series, and comprising a second control circuit; one end of the composite path module is electrically connected to the first node, and the other end is used to load a reference power voltage; the first path module comprises a first light emitting element and a first control circuit connected in parallel with the first light emitting element; the second path module comprises a second light emitting element and a third control circuit connected in parallel with the second light emitting element; the second control circuit is used to control whether the composite path module is electrically connected;

[0008] a third path module comprising a third light emitting element and a fourth control circuit connected in series, one end of the third path module is electrically connected to the first node, and the other end is used to load the reference power voltage.

[0009] According to an embodiment of the present disclosure, the driving current module comprises:

[0010] a driving transistor, a first end of the driving transistor is used to load a driving power voltage, a second end of the driving transistor is electrically connected to the first node, and a gate of the driving transistor is electrically connected to a second node; the driving transistor can output a driving current to the first node under the control of the voltage on the second node;

[0011] a data writing unit configured to write the data voltage to the second node in response to a first scan signal;

[0012] a first capacitor having a first end electrically connected to the second node and a second end electrically connected to the first node;

[0013] a sensing unit configured to load an initialization voltage to the first node in response to a second scan signal.

[0014] According to an embodiment of the present disclosure, the data writing unit comprises a data writing transistor; a first end of the data writing transistor is configured to load the data voltage, a second end of the data writing transistor is electrically connected to the second node, and a gate of the data writing transistor is configured to load the first scan signal.

[0015] The sensing unit comprises a sensing transistor; a first end of the sensing transistor is configured to load the initialization voltage, a second end of the sensing transistor is electrically connected to the first node, and a gate of the sensing transistor is configured to load the second scan signal.

[0016] According to an embodiment of the present disclosure, the first control circuit comprises a sixth transistor and a first control sub-circuit.

[0017] A first end of the sixth transistor is connected to an anode of the first light emitting element, a second end of the sixth transistor is connected to a cathode of the first light emitting element, a gate of the sixth transistor is electrically connected to a fifth node and is configured to be turned on or turned off under the control of a voltage on the fifth node, and the first control sub-circuit is configured to control the voltage on the fifth node.

[0018] According to an embodiment of the present disclosure, the first control sub-circuit comprises a second transistor and a second capacitor; a first end of the second transistor is configured to load a first control signal, a second end of the second transistor and a first end of the second capacitor are electrically connected to the fifth node, a gate of the second transistor is configured to load a third scan signal, and a second end of the second capacitor is configured to load the reference power voltage.

[0019] According to an embodiment of the present disclosure, the third control circuit comprises an eighth transistor and a third control sub-circuit.

[0020] The second end of the eighth transistor and the cathode of the second light emitting element are electrically connected; the first end of the eighth transistor is electrically connected with the anode of the second light emitting element, or the first end of the eighth transistor is electrically connected with the anode of the second light emitting element through the second control circuit; the gate of the eighth transistor is electrically connected with the seventh node, and is turned on or turned off under the control of the voltage on the seventh node; and the third control sub-circuit is used for controlling the voltage on the seventh node.

[0021] According to an embodiment of the present disclosure, the third control sub-circuit comprises a ninth transistor and a fourth capacitor; the first end of the ninth transistor is used for loading a third control signal; the second end of the ninth transistor and the first end of the fourth capacitor are electrically connected with the seventh node; the gate of the ninth transistor is used for loading a third scan signal, and the second end of the fourth capacitor is used for loading the reference power supply voltage.

[0022] According to an embodiment of the present disclosure, the second control circuit comprises a seventh transistor and a second control sub-circuit; the seventh transistor is arranged in series with the first light emitting element and in parallel with the first control circuit, or the seventh transistor is arranged in series with the first path module and the second path module, or the seventh transistor is arranged in series with the second light emitting element and in parallel with the third control circuit.

[0023] The gate of the seventh transistor is electrically connected with the sixth node, and is turned on or turned off under the control of the voltage on the sixth node; and the second control sub-circuit is used for controlling the voltage on the sixth node.

[0024] According to an embodiment of the present disclosure, the second control sub-circuit comprises a third transistor and a third capacitor; the first end of the third transistor is used for loading a second control signal, and the second end of the third transistor and the first end of the third capacitor are electrically connected with the sixth node; the gate of the third transistor is used for loading a third scan signal, and the second end of the third capacitor is used for loading the reference power supply voltage.

[0025] According to an embodiment of the present disclosure, the anode of the first light emitting element and one end of the first control circuit are electrically connected with the first node, and the cathode of the first light emitting element and the other end of the first control circuit are electrically connected with the third node.

[0026] The cathode of the second light emitting element and one end of the third control circuit are used for loading the reference power supply voltage, the anode of the second light emitting element is electrically connected with the second end of the seventh transistor, and the first end of the seventh transistor and the other end of the third control circuit are electrically connected with the third node.

[0027] According to an embodiment of the present disclosure, the fourth control circuit comprises a tenth transistor and a fourth control sub-circuit; a first end of the tenth transistor is electrically connected with the first node, a second end of the tenth transistor is electrically connected with an anode of the third light emitting element, and a cathode of the third light emitting element is used for loading the reference power supply voltage;

[0028] A gate of the tenth transistor is electrically connected with an eighth node, and is used for being turned on or turned off under control of a voltage on the eighth node; and the fourth control sub-circuit is used for controlling the voltage on the eighth node.

[0029] According to an embodiment of the present disclosure, the fourth control sub-circuit comprises an eleventh transistor and a fifth capacitor; a first end of the eleventh transistor is used for loading a fourth control signal, a second end of the eleventh transistor and a first end of the fifth capacitor are electrically connected with the eighth node; a gate of the eleventh transistor is used for loading a third scan signal, and a second end of the fifth capacitor is used for loading the reference power supply voltage.

[0030] According to an embodiment of the present disclosure, the driving current module comprises a data writing transistor, a driving transistor, a sensing transistor and a first capacitor; the data writing transistor is used for loading the data voltage to a second node in response to a first scan signal, and the sensing transistor is used for loading an initialization voltage to the first node in response to a second scan signal; a first end of the first capacitor is electrically connected with the second node, and a second end of the first capacitor is electrically connected with the first node; a first end of the driving transistor is used for loading a driving power supply voltage, a gate of the driving transistor is electrically connected with the second node, and a second end of the driving transistor is electrically connected with the first node; the driving transistor is configured to be capable of outputting a driving current to the first node under control of a voltage on the second node.

[0031] The first control circuit comprises a sixth transistor, a second transistor and a second capacitor; a first end of the sixth transistor and an anode of the first light emitting element are electrically connected with the first node, a second end of the sixth transistor and a cathode of the first light emitting element are electrically connected with a third node, a gate of the sixth transistor, a second end of the second transistor and a first end of the second capacitor are electrically connected with a fifth node, the second transistor is used for loading a first control signal to the fifth node in response to a third scan signal, and a second end of the second capacitor is used for loading a reference power supply voltage.

[0032] The second control circuit comprises a seventh transistor, a third transistor and a third capacitor, a first end of the seventh transistor is electrically connected with the third node, a second end of the seventh transistor is electrically connected with an anode of the second light emitting element, a gate of the seventh transistor, a second end of the third transistor and a first end of the third capacitor are electrically connected with a sixth node, the third transistor is used for loading a second control signal to the sixth node in response to the third scan signal; a second end of the third capacitor is used for loading the reference power supply voltage;

[0033] The third control circuit comprises an eighth transistor, a ninth transistor and a fourth capacitor; a first end of the eighth transistor is electrically connected with the third node, a second end of the eighth transistor and a cathode of the second light emitting element are used for loading the reference power supply voltage, a gate of the eighth transistor, a second end of the ninth transistor and a first end of the fourth capacitor are electrically connected with a seventh node, the ninth transistor is used for loading a third control signal to the seventh node in response to the third scan signal, a second end of the fourth capacitor is used for loading the reference power supply voltage;

[0034] The fourth control circuit comprises a tenth transistor, an eleventh transistor and a fifth capacitor; a first end of the tenth transistor is electrically connected with the first node, a second end of the tenth transistor is electrically connected with an anode of the third light emitting element, a gate of the tenth transistor, a second end of the eleventh transistor and a first end of the fifth capacitor are electrically connected with an eighth node, the eleventh transistor is used for loading a fourth control signal to the eighth node in response to the third scan signal, a second end of the fifth capacitor is used for loading the reference power supply voltage.

[0035] According to an embodiment of the present disclosure, the first light emitting element, the second light emitting element and the third light emitting element are arranged in a stack.

[0036] According to a second aspect of the present disclosure, a display panel is provided, comprising the display unit as described above.

[0037] According to a third aspect of the present disclosure, a driving method of the display unit is provided, applied to the display unit as described above, wherein the driving method comprises:

[0038] In the first stage, after the data voltage of the first light emitting element is written into the driving current module, the composite channel module is electrically connected, and the first control circuit is disconnected, the third control circuit is disconnected, and the fourth control circuit is disconnected;

[0039] In the second stage, after causing the data voltage of the second light emitting element to be written into the drive current module, causing the composite pass module to be electrically passed, and causing the third control circuit to be electrically disconnected, the first control circuit to be electrically disconnected, and the fourth control circuit to be electrically disconnected.

[0040] In the third stage, after causing the data voltage of the third light emitting element to be written into the drive current module, causing the composite pass module to be electrically disconnected, and causing the fourth control circuit to be electrically passed.

[0041] According to a fourth aspect of the present disclosure, there is provided a driving method of a display unit, applied to the display unit described above, wherein the driving method comprises:

[0042] In the first sub-stage of the first stage, the sensing transistor is loaded with the second scan signal and the initialization voltage; the second transistor is loaded with the third scan signal and an active level of the first control signal to cause the sixth transistor to be turned on; the third transistor is loaded with the third scan signal and an active level of the second control signal to cause the seventh transistor to be turned on; and the eleventh transistor is loaded with the third scan signal and an active level of the fourth control signal to cause the tenth transistor to be turned on.

[0043] In the second sub-stage of the first stage, the data write transistor is loaded with the first scan signal and the data voltage of the first light emitting element to cause the data voltage of the first light emitting element to be written into the second node; the second transistor is loaded with the third scan signal and an inactive level of the first control signal to cause the sixth transistor to be turned off; the ninth transistor is loaded with the third scan signal and an active level of the third control signal to cause the eighth transistor to be turned on; and the eleventh transistor is loaded with the third scan signal and an inactive level of the fourth control signal to cause the tenth transistor to be turned off.

[0044] In the third sub-stage of the first stage, the data write transistor is not loaded with the first scan signal to cause the data write transistor to be turned off; the sensing transistor is not loaded with the second scan signal to cause the sensing transistor to be turned off; and the second transistor, the third transistor, the ninth transistor, and the eleventh transistor are not loaded with the third scan signal to cause the second transistor, the third transistor, the ninth transistor, and the eleventh transistor to be turned off.

[0045] in a first sub-phase of the second phase, the sensing transistor is loaded with the second scan signal and the initialization voltage; the second transistor is loaded with the third scan signal and an active level of the first control signal to turn on the sixth transistor; the third transistor is loaded with the third scan signal and an active level of the second control signal to turn on the seventh transistor; the eleventh transistor is loaded with the third scan signal and an active level of the fourth control signal to turn on the tenth transistor;

[0046] in a second sub-phase of the second phase, the data write transistor is loaded with the first scan signal and the data voltage of the second light emitting element to cause the data voltage of the second light emitting element to be written to the second node; the second transistor is loaded with the third scan signal and an active level of the first control signal to turn on the sixth transistor; the third transistor is loaded with the third scan signal and an active level of the second control signal to turn on the seventh transistor; the ninth transistor is loaded with the third scan signal and an inactive level of the third control signal to turn off the eighth transistor; the eleventh transistor is loaded with the third scan signal and an inactive level of the fourth control signal to turn off the tenth transistor;

[0047] in a third sub-phase of the second phase, the data write transistor is not loaded with the first scan signal to turn off the data write transistor; the sensing transistor is not loaded with the second scan signal to turn off the sensing transistor; the second transistor, the third transistor, the ninth transistor, and the eleventh transistor are not loaded with the third scan signal to turn off the second transistor, the third transistor, the ninth transistor, and the eleventh transistor;

[0048] in a first sub-phase of the third phase, the sensing transistor is loaded with the second scan signal and the initialization voltage; the second transistor is loaded with the third scan signal and an active level of the first control signal to turn on the sixth transistor; the third transistor is loaded with the third scan signal and an active level of the second control signal to turn on the seventh transistor; the eleventh transistor is loaded with the third scan signal and an active level of the fourth control signal to turn on the tenth transistor;

[0049] In a second sub-stage of the third stage, the data write transistor is loaded with the first scan signal and the data voltage of the third light emitting element, so that the data voltage of the third light emitting element is written to the second node; the third transistor is loaded with the third scan signal and an inactive level of the second control signal, so that the seventh transistor is turned off; the ninth transistor is loaded with the third scan signal and an inactive level of the third control signal, so that the eighth transistor is turned off; the eleventh transistor is loaded with the third scan signal and an active level of the fourth control signal, so that the tenth transistor is turned on;

[0050] In a third sub-stage of the third stage, the data write transistor is not loaded with the first scan signal, so that the data write transistor is turned off; the sensing transistor is not loaded with the second scan signal, so that the sensing transistor is turned off; the second transistor, the third transistor, the ninth transistor and the eleventh transistor are not loaded with the third scan signal, so that the second transistor, the third transistor, the ninth transistor and the eleventh transistor are turned off.

[0051] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and are not limiting to the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is readily apparent to one of ordinary skill in the art that the accompanying drawings are merely exemplary of embodiments of the present disclosure and are therefore not limiting of the scope of the present disclosure as set forth in the claims.

[0053] Figure 1 FIG. 1 is a structural schematic diagram of a display panel in the related art.

[0054] Figure 2 FIG. 2 is a structural schematic diagram of a display panel in an embodiment of the present disclosure.

[0055] Figure 3 FIG. 3 is a principle schematic diagram of a display unit in an embodiment of the present disclosure.

[0056] Figure 4 FIG. 4 is a flow schematic diagram of a driving method of a display unit in an embodiment of the present disclosure.

[0057] Figure 5 FIG. 5 is a principle schematic diagram of a display unit in an embodiment of the present disclosure.

[0058] Figure 6For one embodiment of the present disclosure, a timing diagram of the driving of the display unit.

[0059] Figure 7 For one embodiment of the present disclosure, a state diagram of the display unit in the third sub-stage of the first stage.

[0060] Figure 8 For one embodiment of the present disclosure, a state diagram of the display unit in the third sub-stage of the second stage.

[0061] Figure 9 For one embodiment of the present disclosure, a state diagram of the display unit in the third sub-stage of the third stage.

[0062] Figure 10 For another embodiment of the present disclosure, a timing diagram of the driving of the display unit.

[0063] Figure 11 For another embodiment of the present disclosure, a schematic diagram of the principle of the display unit.

[0064] Figure 12 For another embodiment of the present disclosure, a schematic diagram of the principle of the display unit. DETAILED DESCRIPTION

[0065] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus a detailed description of the same will not be repeated. In addition, the drawings are only schematic and are non-limiting exemplary, and should not be interpreted as limiting the scope of the disclosure.

[0066] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component as the device is positioned in a particular orientation, such terminology is used herein for convenience only and is not limiting of the device's orientation. It is to be understood that the device can be inverted, and, thus, such terminology as "upper" and "lower" can be understood to refer to the device in its inverted orientation. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is formed "directly on" the other structure or that the structure is formed "indirectly on" the other structure via one or more intervening structures.

[0067] The words "one", "a", "an", "the", and "said" are used to mean one or more of something, unless context clearly indicates otherwise; the word "comprises" and variations such as "comprising" or "comprise" means including, but not limited to, and the words "consisting of" and variations such as "consists of" or "consisting of" means including, but not limited to, and the words "first", "second", and "third", etc. are merely labels used to distinguish between two or more elements unless the context indicates otherwise.

[0068] A transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and a current can flow through the drain, the channel region, and the source. The channel region refers to a region through which a current mainly flows. In the embodiments of the present disclosure, in the case of using a transistor with opposite polarity or in the case of a change in the direction of current in the operation of a circuit, the functions of the "source" and the "drain" are sometimes exchanged with each other, that is, the "source" and the "drain" can be exchanged with each other. In the embodiments of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first terminal of the transistor, and the other is referred to as a second terminal of the transistor.

[0069] Figure 1 A structure diagram of a display panel PNL in the related art is shown. Referring to Figure 1 The display panel PNL is provided with a first display unit, a second display unit, and a third display unit. The first display unit includes a first light emitting element RLD and a pixel driving circuit PDC driving the first light emitting element RLD. The second display unit includes a second light emitting element GLD and a pixel driving circuit PDC driving the second light emitting element GLD. The third display unit includes a third light emitting element BLD and a pixel driving circuit PDC driving the third light emitting element BLD. The first light emitting element RLD, the second light emitting element GLD, and the third light emitting element BLD do not overlap with each other and emit light under the driving of the respective pixel driving circuits PDC. In an example, the first light emitting element RLD, the second light emitting element GLD, and the third light emitting element BLD can emit light at the same time at least at some time.

[0070] The embodiments of the present disclosure provide another display panel PNL and display unit UU thereof. Referring to Figure 2The display panel PNL includes display units UU arranged in an array, each display unit UU including a first light emitting element RLD, a third light emitting element BLD, and a second light emitting element GLD, and a composite driving circuit for driving the first light emitting element RLD, the second light emitting element GLD, and the third light emitting element BLD. In this embodiment, the composite driving circuit can realize time-sharing driving of the first light emitting element RLD, the second light emitting element GLD, and the third light emitting element BLD, i.e., one pixel driving circuit can realize driving of three different light emitting elements, rather than one pixel driving circuit driving only one light emitting element. Compared with arranging three pixel driving circuits, the composite driving circuit of the embodiment of the present disclosure can reduce the number of electronic elements (such as transistors and capacitors), thereby facilitating reduction of the layout area of the pixel driving circuit and reduction of the restriction of the layout area of the pixel driving circuit on the resolution of the display panel PNL, i.e., facilitating improvement of the resolution of the display panel PNL.

[0071] In an example, referring to Figure 2 In the display unit UU, the first light emitting element RLD, the second light emitting element GLD, and the third light emitting element BLD can overlap with each other, rather than being arranged in layers without overlapping with each other. In this way, the space competition between the light emitting elements can be reduced, so that different light emitting elements reuse the same pixel opening, which facilitates improvement of the light emitting area of a single light emitting element, which makes the aperture ratio of the display panel PNL improved. Improvement of the aperture ratio of the display panel PNL can improve the light emitting brightness of the display panel PNL and facilitate reduction of the power consumption of the display panel PNL. Moreover, the light emitting area of the light emitting element is increased, which can reduce the light emitting brightness of the light emitting element, thereby improving the service life of the light emitting element, so that the service life of the display panel PNL can be prolonged. Moreover, in this example, the aperture ratio of the display panel PNL can be greatly improved (e.g., by 300%) by overlapping the first light emitting element RLD, the second light emitting element GLD, and the third light emitting element BLD with each other, which can make the sub-pixel have a larger opening size in the case of the display panel PNL having a super-high resolution, overcoming the restriction of the light emitting area of the sub-pixel on the resolution of the display panel PNL.

[0072] In an example, the display panel PNL can be an AR display panel, a VR display panel, a naked-eye 3D display panel, or other types of display panels, especially display panels requiring high brightness and high resolution.

[0073] Optionally, the first light emitting element RLD, the second light emitting element GLD and the third light emitting element BLD can be thin film light emitting elements, for example, can be OLEDs, PLEDs or QLEDs. In an example, the first light emitting element RLD, the second light emitting element GLD and the third light emitting element BLD are OLEDs. In this example, the first light emitting element RLD, the second light emitting element GLD and the third light emitting element BLD can have a larger light emitting area by being at least partially stacked on each other, and thus can improve the lifetime by reducing the light emitting brightness, and can improve the problem of low OLED lifetime.

[0074] Optionally, the first light emitting element RLD, the second light emitting element GLD and the third light emitting element BLD can be stacked on each other in a manner of cooperation of upright setting and inverted setting. In the embodiments of the present disclosure, upright setting of a light emitting element refers to light emitting from the common electrode side of the light emitting element; inverted setting of a light emitting element refers to light emitting from the pixel electrode side of the light emitting element. Of course, the light emitting element can also emit light from both sides. In an example, the third light emitting element BLD is a blue light emitting element, which can adopt an inverted setting manner, so that the light emitting efficiency of the third light emitting element BLD is higher. In another example, the third light emitting element BLD can be located on the side closest to the light emitting side of the display panel PNL, so as to improve the light emitting efficiency of the third light emitting element BLD.

[0075] Optionally, the first light emitting element RLD, the second light emitting element GLD and the third light emitting element BLD can be light emitting elements of different colors, for example, the first light emitting element RLD can be a red light emitting element, the second light emitting element GLD can be a green light emitting element, and the third light emitting element BLD can be a blue light emitting element. Of course, at least one of the first light emitting element RLD, the second light emitting element GLD and the third light emitting element BLD can also be a light emitting element of other colors, for example, can be a yellow light emitting element, an orange light emitting element, etc.

[0076] In the embodiments of the present disclosure, referring to Figure 3 , the display unit UU includes:

[0077] The driving current module DRM is configured to output a driving current to the first node N1 according to the data voltage Vdata;

[0078] The composite path module MA comprises a first path module and a second path module connected in series, and comprises a second control circuit CSY; one end of the composite path module MA is electrically connected with the first node N1, and the other end is electrically connected with the fourth node N4 used for loading a reference power supply voltage VSS; the first path module comprises a first light emitting element RLD and a first control circuit CSR connected in parallel with the first light emitting element RLD; the second path module comprises a second light emitting element GLD and a third control circuit CSG connected in parallel with the second light emitting element GLD; the second control circuit CSY is used for controlling whether the composite path module MA is electrically connected or not.

[0079] The third path module MB comprises a third light emitting element BLD and a fourth control circuit CSB connected in series, one end of the third path module MB is electrically connected with the first node N1, and the other end is used for loading the reference power supply voltage VSS.

[0080] In this embodiment, the driving current module DRM, the first control circuit CSR, the third control circuit CSG, the fourth control circuit CSB and the second control circuit CSY jointly constitute a composite driving circuit of the display unit UU, and the composite driving circuit can realize the time-sharing driving of the first light emitting element RLD, the second light emitting element GLD and the third light emitting element BLD.

[0081] Referring to Figure 4 The display unit UU can be driven by the following driving method:

[0082] In step S110, in the first stage P1, after the data voltage Vdata of the first light emitting element RLD is written into the driving current module DRM, the composite path module MA is electrically connected, and the first control circuit CSR is turned off, the third control circuit CSG is turned on, and the fourth control circuit CSB is turned off.

[0083] In step S120, in the second stage P2, after the data voltage Vdata of the second light emitting element GLD is written into the driving current module DRM, the composite path module MA is electrically connected, and the third control circuit CSG is turned off, the first control circuit CSR is turned on, and the fourth control circuit CSB is turned off.

[0084] In step S130, in the third stage P3, after the data voltage Vdata of the third light emitting element BLD is written into the driving current module DRM, the composite path module MA is turned off, and the fourth control circuit CSB is turned on.

[0085] Thus, the display unit UU can cause the first light emitting element RLD to emit light in the first phase P1, the second light emitting element GLD to emit light in the second phase P2, and the third light emitting element BLD to emit light in the third phase P3, so as to realize time-sharing driving of different light emitting elements.

[0086] In an embodiment of the present disclosure, referring to Figure 3 The driving current module DRM comprises:

[0087] a driving transistor T4, a first end of the driving transistor T4 is used to load a driving power supply voltage VDD, a second end of the driving transistor T4 is electrically connected with the first node N1, and a gate of the driving transistor T4 is electrically connected with the second node N2; the driving transistor T4 can output a driving current to the first node N1 under the control of the voltage on the second node N2;

[0088] a data writing unit U1, used to write the data voltage Vdata to the second node N2 in response to a first scanning signal G1;

[0089] a first capacitor CST1, a first end of the first capacitor CST1 is electrically connected with the second node N2, and a second end of the first capacitor CST1 is electrically connected with the first node N1;

[0090] a sensing unit U2, used to load an initialization voltage Vinit to the first node N1 in response to a second scanning signal G2.

[0091] In this embodiment, when the first scanning signal G1 is loaded to the data writing unit U1, the data voltage Vdata can be written to the second node N2, so that the data voltage Vdata written to the second node N2 can control the size of the driving current that the driving transistor T4 can output. It can be understood that the driving transistor T4 can output the driving current in response to the voltage on the second node N2 only when one of the composite path module MA or the third path module MB is in electrical path, or when the sensing unit U2 is in electrical path; the driving transistor T4 fails to output the driving current when the driving transistor T4 is not in electrical path. When the second scanning signal G2 is loaded to the sensing unit U2, the initialization voltage Vinit can be written to the first node N1, so as to reset the first node N1. In an example, the voltage value of the initialization voltage Vinit is the same as that of the reference power supply voltage VSS.

[0092] In an example, referring to Figure 3The data writing unit U1 comprises a data writing transistor T1. A first end of the data writing transistor T1 is used to load a data voltage Vdata. A second end of the data writing transistor T1 is electrically connected with the second node N2. A gate of the data writing transistor T1 is used to load the first scan signal G1. The sensing unit U2 comprises a sensing transistor T5. A first end of the sensing transistor T5 is used to load the initialization voltage Vinit. A second end of the sensing transistor T5 is electrically connected with the first node N1. A gate of the sensing transistor T5 is used to load the second scan signal G2.

[0093] Optionally, referring to Figure 5 The display panel PNL is provided with a data wire DL used to load the data voltage Vdata, a first scan wire used to load the first scan signal G1, a second scan wire used to load the second scan signal G2, and a sensing wire SL used for sensing. The first end of the data writing transistor T1 is electrically connected with the data wire DL. The gate of the data writing transistor T1 is electrically connected with the first scan wire. The gate of the sensing transistor T5 is electrically connected with the second scan wire. The first end of the sensing transistor T5 is electrically connected with the sensing wire SL. In this embodiment, the sensing wire SL is used to load the initialization voltage Vinit to the display unit UU to realize the reset of the display unit UU, in addition to being used to transmit the sensing signal to compensate the driving transistor T4.

[0094] In this embodiment, the first scan wire is used to load the first scan signal G1. It can be understood that the first scan signal G1 can be a pulse signal, which has an effective level of the first scan signal G1 and an ineffective level of the first scan signal G1. Loading the first scan signal G1 to the display unit UU means loading the effective level of the first scan signal G1 to the first scan wire connected with the display unit UU. In other words, when it is needed to turn on the data writing transistor T1, the effective level of the first scan signal G1 is loaded to the gate of the data writing transistor T1. When it is not needed to turn on the data writing transistor T1, the ineffective level of the first scan signal G1 is loaded to the gate of the data writing transistor T1.

[0095] In this embodiment, the second scan wire is used to load the second scan signal G2. It can be understood that the second scan signal G2 can be a pulse signal, which has an effective level of the second scan signal G2 and an ineffective level of the second scan signal G2. Loading the second scan signal G2 to the display unit UU means loading the effective level of the second scan signal G2 to the second scan wire to which the display unit UU is connected. In other words, when it is needed to make the sensing transistor T5 conduct, the effective level of the second scan signal G2 is loaded to the gate of the sensing transistor T5; when it is not needed to make the sensing transistor T5 conduct, the ineffective level of the second scan signal G2 is loaded to the gate of the sensing transistor T5.

[0096] In the embodiment of the present disclosure, the driving current module DRM is a 3T1C circuit. It can be understood that in other embodiments of the present disclosure, the driving current module DRM can also adopt other circuits, for example, a 7T1C circuit, an 8T1C circuit, etc.

[0097] In an embodiment of the present disclosure, referring to Figure 3 , the first control circuit CSR includes a sixth transistor T6 and a first control sub-circuit U6;

[0098] The first end of the sixth transistor T6 is connected with the anode of the first light emitting element RLD, the second end of the sixth transistor T6 is connected with the cathode of the first light emitting element RLD, and the sixth transistor T6 is used to be turned on or turned off under the control of the voltage on the fifth node N5; the first control sub-circuit U6 is used to control the voltage on the fifth node N5. When the first control circuit CSR is turned on, specifically, when the sixth transistor T6 is turned on, the first light emitting element RLD can be short-circuited, so that the first light emitting element RLD does not emit light. When the composite path module MA is electrically connected and the sixth transistor T6 is turned off, the first light emitting element RLD emits light.

[0099] In an example, the first control sub-circuit U6 includes a second transistor T2 and a second capacitor CST2; the first end of the second transistor T2 is used to load a first control signal CKA, the second end of the second transistor T2 and the first end of the second capacitor CST2 are electrically connected with the fifth node N5, the gate of the second transistor T2 is used to load a third scan signal G3, and the second end of the second capacitor CST2 is used to load a reference power supply voltage VSS. In this example, the first control signal CKA has an effective level of the first control signal CKA and an ineffective level of the first control signal CKA, the effective level of the first control signal CKA can make the sixth transistor T6 electrically conduct, and the ineffective level of the first control signal CKA can make the sixth transistor T6 electrically cut off.

[0100] In an example, referring toFigure 5 The display panel PNL is provided with a first control wire CKAL for loading the first control signal CKA, and the first control wire CKAL is electrically connected with the first end of the second transistor T2. When the second transistor T2 is turned on in response to the third scanning signal G3 and the first control wire CKAL loads the effective level of the first control signal CKA, the effective level of the first control signal CKA can be written into the fifth node N5 and make the sixth transistor T6 turn on; after the second transistor T2 is turned off, the effective level of the first control signal CKA can be maintained by the second capacitor CST2, thereby making the sixth transistor T6 maintain the turned-on state. Correspondingly, when the second transistor T2 is turned on in response to the third scanning signal G3 and the first control wire CKAL loads the ineffective level of the first control signal CKA, the ineffective level of the first control signal CKA can be written into the fifth node N5 and make the sixth transistor T6 turn off; after the second transistor T2 is turned off, the ineffective level of the first control signal CKA can be maintained by the second capacitor CST2, thereby making the sixth transistor T6 maintain the turned-off state.

[0101] In this embodiment, the third scanning signal G3 is a pulse signal, which can have an effective level of the third scanning signal G3 and an ineffective level of the third scanning signal G3. Loading the third scanning signal G3 to the display unit UU means loading the effective level of the third scanning signal G3 to the display unit UU. For example, the effective level of the third scanning signal G3 can be loaded to the second transistor T2 to make the second transistor T2 turn on, and the ineffective level of the third scanning signal G3 can be loaded to the second transistor T2 to make the second transistor T2 turn off. Optionally, the display panel PNL is provided with a third scanning wire for loading the third scanning signal G3, and the gate of the second transistor T2 is electrically connected with the third scanning wire.

[0102] In an embodiment of the present disclosure, referring to Figure 3 The third control circuit CSG includes an eighth transistor T8 and a third control sub-circuit U8; the second end of the eighth transistor T8 and the cathode of the second light emitting element GLD are electrically connected; the first end of the eighth transistor T8 is electrically connected with the anode of the second light emitting element GLD, or the first end of the eighth transistor T8 is electrically connected with the anode of the second light emitting element GLD through the second control circuit CSY; the eighth transistor T8 is used to turn on or turn off under the control of the voltage on the seventh node N7; and the third control sub-circuit U8 is used to control the voltage on the seventh node N7.

[0103] When the third control circuit CSG is electrically conducted, specifically, when the eighth transistor T8 is turned on, the second light emitting element GLD can be short-circuited, and thus the second light emitting element GLD does not emit light. When the composite path module MA is electrically conducted and the eighth transistor T8 is turned off, the second light emitting element GLD emits light.

[0104] In an example, the third control sub-circuit U8 includes a ninth transistor T9 and a fourth capacitor Cst4; a first end of the ninth transistor T9 is configured to load a third control signal CKC; a second end of the ninth transistor T9 and a first end of the fourth capacitor Cst4 are electrically connected to the seventh node N7; a gate of the ninth transistor T9 is configured to load a third scan signal G3, and a second end of the fourth capacitor Cst4 is configured to load the reference power supply voltage VSS. In this example, the third control signal CKC has an effective level of the third control signal CKC and an ineffective level of the third control signal CKC, the effective level of the third control signal CKC can make the eighth transistor T8 electrically conducted, and the ineffective level of the third control signal CKC can make the eighth transistor T8 electrically turned off.

[0105] In an example, referring to Figure 5 , the display panel PNL is provided with a third control wire CKCL configured to load the third control signal CKC, and the first end of the ninth transistor T9 is electrically connected to the third control wire CKCL. When the ninth transistor T9 is turned on in response to the third scan signal G3 and the third control wire CKCL loads the effective level of the third control signal CKC, the effective level of the third control signal CKC can be written to the seventh node N7 and make the eighth transistor T8 turned on; after the ninth transistor T9 is turned off, the effective level of the third control signal CKC can be maintained by the fourth capacitor Cst4, and thus the eighth transistor T8 is maintained in the turned-on state. Correspondingly, when the ninth transistor T9 is turned on in response to the third scan signal G3 and the third control wire CKCL loads the ineffective level of the third control signal CKC, the ineffective level of the third control signal CKC can be written to the seventh node N7 and make the eighth transistor T8 turned off; after the ninth transistor T9 is turned off, the ineffective level of the third control signal CKC can be maintained by the fourth capacitor Cst4, and thus the eighth transistor T8 is maintained in the turned-off state.

[0106] In this embodiment, the effective level of the third scan signal G3 can be loaded to the ninth transistor T9 to make the ninth transistor T9 turned on, and the ineffective level of the third scan signal G3 can be loaded to the ninth transistor T9 to make the ninth transistor T9 turned off. Optionally, the display panel PNL is provided with a third scan wire configured to load the third scan signal G3, and the gate of the ninth transistor T9 is electrically connected to the third scan wire.

[0107] In one embodiment of the present disclosure, referring to Figure 3 , Figure 11 and Figure 12 , the second control circuit CSY comprises a seventh transistor T7 and a second control sub-circuit U7. The seventh transistor T7 is arranged in series with the first light emitting element RLD and in parallel with the first control circuit CSR (as shown in Figure 11 ), or the seventh transistor T7 is arranged in series with the first path module and the second path module (as shown in Figure 12 ), or the seventh transistor T7 is arranged in series with the second light emitting element GLD and in parallel with the third control circuit CSG (as shown in Figure 7 ); the seventh transistor T7 is used to be turned on or turned off under the control of the voltage on the sixth node N6; and the second control sub-circuit U7 is used to control the voltage on the sixth node N6.

[0108] Referring to Figure 11 , when the seventh transistor T7 is arranged in series with the first light emitting element RLD and in parallel with the first control circuit CSR, the simultaneous disconnection of the second control circuit CSY and the first control circuit CSR can make the composite path module MA electrically disconnected, specifically, the simultaneous disconnection of the sixth transistor T6 and the seventh transistor T7 can make the composite path module MA electrically disconnected. Correspondingly, the conduction of any one of the sixth transistor T6 and the seventh transistor T7 can make the composite path module MA in electrical path.

[0109] Referring to Figure 12 , when the seventh transistor T7 is arranged in series with the first path module and the second path module, the disconnection of the seventh transistor T7 can make the composite path module MA electrically disconnected. Correspondingly, when the seventh transistor T7 is turned on, the composite path module MA is in electrical path.

[0110] Referring to Figure 3 , when the seventh transistor T7 is arranged in series with the second light emitting element GLD and in parallel with the third control circuit CSG, the simultaneous disconnection of the second control circuit CSY and the third control circuit CSG can make the composite path module MA electrically disconnected, specifically, the simultaneous disconnection of the seventh transistor T7 and the eighth transistor T8 can make the composite path module MA electrically disconnected. Correspondingly, the conduction of any one of the eighth transistor T8 and the seventh transistor T7 can make the composite path module MA in electrical path.

[0111] In an embodiment of the present disclosure, the second control sub-circuit U7 comprises a third transistor T3 and a third capacitor CST3; a first end of the third transistor T3 is configured to load a second control signal CKB, a second end of the third transistor T3 and a first end of the third capacitor CST3 are electrically connected to the sixth node N6; a gate of the third transistor T3 is configured to load a third scan signal G3, and a second end of the third capacitor CST3 is configured to load the reference power supply voltage VSS.

[0112] In this example, the second control signal CKB has an effective level of the second control signal CKB and an ineffective level of the second control signal CKB, the effective level of the second control signal CKB can make the seventh transistor T7 conductive, and the ineffective level of the second control signal CKB can make the seventh transistor T7 non-conductive.

[0113] In an example, referring to Figure 5 , the display panel PNL is provided with a second control wire CKBL configured to load the second control signal CKB, and the second control wire CKBL is electrically connected to the first end of the third transistor T3. When the third transistor T3 is turned on in response to the third scan signal G3 and the second control wire CKBL loads the effective level of the second control signal CKB, the effective level of the second control signal CKB can be written to the sixth node N6 and make the seventh transistor T7 conductive; after the third transistor T3 is turned off, the effective level of the second control signal CKB can be maintained by the third capacitor CST3, thereby maintaining the seventh transistor T7 in a conductive state. Correspondingly, when the third transistor T3 is turned on in response to the third scan signal G3 and the second control wire CKBL loads the ineffective level of the second control signal CKB, the ineffective level of the second control signal CKB can be written to the sixth node N6 and make the seventh transistor T7 non-conductive; after the third transistor T3 is turned off, the ineffective level of the second control signal CKB can be maintained by the third capacitor CST3, thereby maintaining the seventh transistor T7 in a non-conductive state.

[0114] In this embodiment, the third transistor T3 can be loaded with the effective level of the third scan signal G3 to make the third transistor T3 conductive, and the third transistor T3 can be loaded with the ineffective level of the third scan signal G3 to make the third transistor T3 non-conductive. Optionally, the display panel PNL is provided with a third scan wire configured to load the third scan signal G3, and the gate of the third transistor T3 is electrically connected to the third scan wire.

[0115] As an example, an anode of the first light emitting element RLD and one end of the first control circuit CSR are electrically connected to the first node N1, and a cathode of the first light emitting element RLD and another end of the first control circuit CSR are electrically connected to the third node N3. Specifically, the anode of the first light emitting element RLD and a first end of the sixth transistor T6 are electrically connected to the first node N1, and the cathode of the first light emitting element RLD and a second end of the sixth transistor T6 are electrically connected to the third node N3. A cathode of the second light emitting element GLD and one end (for example, a second end of the eighth transistor T8) of the third control circuit CSG are used to load the reference power supply voltage VSS, an anode of the second light emitting element GLD is electrically connected to a second end of the seventh transistor T7, and a first end of the seventh transistor T7 and another end (a first end of the eighth transistor T8) of the third control circuit CSG are electrically connected to the third node N3.

[0116] In an embodiment of the present disclosure, referring to Figure 3 , the fourth control circuit CSB includes a tenth transistor T10 and a fourth control sub-circuit U10. A first end of the tenth transistor T10 is electrically connected to the first node N1, a second end of the tenth transistor T10 is electrically connected to an anode of the third light emitting element BLD, and a cathode of the third light emitting element BLD is used to load the reference power supply voltage VSS. A gate of the tenth transistor T10 is electrically connected to the eighth node N8 for being turned on or turned off under the control of a voltage on the eighth node N8, and the fourth control sub-circuit U10 is used to control the voltage on the eighth node N8. When the fourth control circuit CSB is electrically turned on, specifically, when the tenth transistor T10 is turned on, the third path module MB is electrically connected, so that the third light emitting element BLD can emit light.

[0117] In an example, the first control sub-circuit U6 includes an eleventh transistor T11 and a fifth capacitor Cst5. A first end of the eleventh transistor T11 is used to load a fourth control signal CKD, a second end of the eleventh transistor T11 and a first end of the fifth capacitor Cst5 are electrically connected to the eighth node N8, a gate of the eleventh transistor T11 is used to load a third scanning signal G3, and a second end of the fifth capacitor Cst5 is used to load the reference power supply voltage VSS. In this example, the fourth control signal CKD has an effective level of the fourth control signal CKD and an ineffective level of the fourth control signal CKD. The effective level of the fourth control signal CKD can make the tenth transistor T10 electrically turned on, and the ineffective level of the fourth control signal CKD can make the tenth transistor T10 electrically turned off.

[0118] In an example, referring to Figure 5The display panel PNL is provided with a fourth control trace CKDL for loading the fourth control signal CKD. The fourth control trace CKDL is electrically connected to the first terminal of the eleventh transistor T11. When the eleventh transistor T11 is turned on in response to the third scan signal G3 and the fourth control trace CKDL is loaded with the effective level of the fourth control signal CKD, the effective level of the fourth control signal CKD can be written to the eighth node N8, causing the tenth transistor T10 to turn on. After the eleventh transistor T11 is turned off, the effective level of the fourth control signal CKD can be maintained by the fifth capacitor CST5, thereby keeping the tenth transistor T10 in the on state. Correspondingly, when the eleventh transistor T11 is turned on in response to the third scan signal G3 and the fourth control trace CKDL is loaded with the ineffective level of the fourth control signal CKD, the ineffective level of the fourth control signal CKD can be written to the eighth node N8, causing the tenth transistor T10 to turn off. After the eleventh transistor T11 is turned off, the ineffective level of the fourth control signal CKD can be maintained by the fifth capacitor CST5, thereby keeping the tenth transistor T10 in the off state.

[0119] In this embodiment, the eleventh transistor T11 can be turned on by applying an effective level of the third scan signal G3, and turned off by applying an ineffective level of the third scan signal G3. Optionally, the display panel PNL is provided with a third scan trace for applying the third scan signal G3, and the gate of the eleventh transistor T11 is electrically connected to the third scan trace.

[0120] As follows, Figure 3 and Figure 5 Taking the circuit structure of the example display unit UU as an example, the driving method and driving principle of the display unit UU will be further explained and illustrated.

[0121] In this example, the drive current module DRM includes a data writing transistor T1, a drive transistor T4, a sensing transistor T5, and a first capacitor CST1. The data writing transistor T1 is used to load the data voltage Vdata to the second node N2 in response to a first scan signal G1. The sensing transistor T5 is used to load the initialization voltage Vinit to the first node N1 in response to a second scan signal G2. The first terminal of the first capacitor CST1 is electrically connected to the second node N2, and the other terminal is electrically connected to the first node N1. The first terminal of the drive transistor T4 is used to load the drive power supply voltage VDD. The gate of the drive transistor T4 is electrically connected to the second node N2, and the second terminal of the drive transistor T4 is electrically connected to the first node N1. The drive transistor T4 is configured to output a drive current to the first node N1 under the control of the voltage of the second node N2.

[0122] In this example, the first control circuit CSR includes a sixth transistor T6, a second transistor T2 and a second capacitor CST2; a first terminal of the sixth transistor T6 and an anode of the first light emitting element RLD are electrically connected to the first node N1, a second terminal of the sixth transistor T6 and a cathode of the first light emitting element RLD are electrically connected to the third node N3, a gate of the sixth transistor T6, a second terminal of the second transistor T2 and one terminal of the second capacitor CST2 are electrically connected to the fifth node N5, the second transistor T2 is configured to load the first control signal CKA to the fifth node N5 in response to a third scan signal G3, the other terminal of the second capacitor CST2 is configured to load a reference supply voltage VSS.

[0123] In this example, the second control circuit CSY includes a seventh transistor T7, a third transistor T3 and a third capacitor CST3; a first terminal of the seventh transistor T7 is electrically connected to the third node N3, a second terminal of the seventh transistor T7 is electrically connected to an anode of the second light emitting element GLD, a gate of the seventh transistor T7, a second terminal of the third transistor T3 and one terminal of the third capacitor CST3 are electrically connected to the sixth node N6, the third transistor T3 is configured to load the second control signal CKB to the sixth node N6 in response to the third scan signal G3; the other terminal of the third capacitor CST3 is configured to load the reference supply voltage VSS.

[0124] In this example, the third control circuit CSG includes an eighth transistor T8, a ninth transistor T9 and a fourth capacitor CST4; a first terminal of the eighth transistor T8 is electrically connected to the third node N3, a second terminal of the eighth transistor T8 and a cathode of the second light emitting element GLD are configured to load the reference supply voltage VSS, a gate of the eighth transistor T8, a second terminal of the ninth transistor T9 and one terminal of the fourth capacitor CST4 are electrically connected to the seventh node N7, the ninth transistor T9 is configured to load the third control signal CKC to the seventh node N7 in response to the third scan signal G3, the other terminal of the fourth capacitor CST4 is configured to load the reference supply voltage VSS.

[0125] In this example, the fourth control circuit CSB includes a tenth transistor T10, an eleventh transistor T11 and a fifth capacitor Cst5; a first terminal of the tenth transistor T10 is electrically connected with the first node N1, a second terminal of the tenth transistor T10 is electrically connected with the anode of the third light emitting element BLD, a gate of the tenth transistor T10, a second terminal of the eleventh transistor T11 and a first terminal of the fifth capacitor Cst5 are electrically connected with the eighth node N8, the eleventh transistor T11 is configured to load a fourth control signal CKD to the eighth node N8 in response to the third scan signal G3, and the second capacitor Cst2 is configured to load the reference power supply voltage VSS.

[0126] Figure 6 The timing of each signal in a driving method of the display unit UU of the above example is illustrated. In Figure 6 In the example, the active level of each signal is high, and the inactive level of each signal is low. It can be understood that in other embodiments of the present disclosure, the active level of any one signal can also be low, and the inactive level thereof is high accordingly.

[0127] In the first sub-stage t1 of the first stage P1:

[0128] The second scan signal G2 (i.e. the active level of the second scan signal G2) is loaded to the sensing transistor T5, and the initialization voltage Vinit whose voltage value is equal to that of the reference power supply voltage VSS is loaded to the sensing wire SL; the sensing transistor T5 is turned on in response to the second scan signal G2, and the voltage of the first node N1 is the initialization voltage Vinit, thereby resetting the first node N1 and the anode of the first light emitting element RLD.

[0129] The third scan signal G3 (i.e. the active level of the third scan signal G3) is loaded to the second transistor T2, and the active level of the first control signal CKA is loaded to the first control wire CKAL; the second transistor T2 is turned on in response to the third scan signal G3, so that the voltage of the fifth node N5 is the active level of the first control signal CKA, which turns on the sixth transistor T6, and further makes the voltage of the third node N3 be the initialization voltage Vinit, thereby resetting the third node N3.

[0130] The third transistor T3 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the active level of the second control signal CKB is loaded to the second control line CKBL; the third transistor T3 is turned on in response to the third scan signal G3, so that the voltage of the sixth node N6 is the active level of the second control signal CKB, which makes the seventh transistor T7 turned on, and then makes the voltage of the anode of the second light emitting element GLD be the initialization voltage Vinit, realizing the reset of the anode of the second light emitting element GLD.

[0131] The eleventh transistor T11 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the active level of the fourth control signal CKD is loaded to the fourth control line CKDL; the eleventh transistor T11 is turned on in response to the third scan signal G3, so that the voltage of the eighth node N8 is the active level of the fourth control signal CKD, which makes the tenth transistor T10 turned on, and then makes the voltage of the anode of the third light emitting element BLD be the initialization voltage Vinit, realizing the reset of the anode of the third light emitting element BLD.

[0132] Thus, in the first sub-stage t1 of the first stage P1, the reset of the anode of the first light emitting element RLD, the anode of the second light emitting element GLD and the anode of the third light emitting element BLD can be realized.

[0133] Referring to Figure 6 In the first sub-stage t1 of the first stage P1 of this example, the first scan signal G1 (i.e. the active level of the first scan signal G1) can also be loaded to the data writing transistor T1 and the data voltage Vdata of the first light emitting element RLD is loaded to the data line DL; the data writing transistor T1 is turned on in response to the first scan signal G1, and the data voltage Vdata of the first light emitting element RLD is written to the second node N2. It can be understood that the data voltage Vdata of the first light emitting element RLD can also not be written to the second node N2 in this stage.

[0134] Referring to Figure 6 In the first sub-stage t1 of the first stage P1 of this example, the third scan signal G3 (i.e. the active level of the third scan signal G3) can also be loaded to the ninth transistor T9 and the active level of the third control signal CKC is loaded to the third control line CKCL; the ninth transistor T9 is turned on in response to the third scan signal G3, so that the voltage of the seventh node N7 is the active level of the fourth control signal CKD, which makes the eighth transistor T8 turned on. It can be understood that the third scan signal G3 can also not be loaded to the ninth transistor T9 in this stage, or the active level of the third control signal CKC can also not be loaded to the third control line CKCL.

[0135] In the second sub-stage t2 of the first stage P1:

[0136] The first scan signal G1 (i.e. the active level of the first scan signal G1) is applied to the data write transistor T1 and the data voltage Vdata of the first light emitting element RLD is applied to the data line DL; the data write transistor T1 is turned on in response to the first scan signal G1 and the data voltage Vdata of the first light emitting element RLD is written to the second node N2.

[0137] The third scan signal G3 (i.e. the active level of the third scan signal G3) is applied to the second transistor T2 and the inactive level of the first control signal CKA is applied to the first control line CKAL, the voltage of the fifth node N5 is the inactive level of the first control signal CKA, which makes the sixth transistor T6 turn off.

[0138] The third scan signal G3 (i.e. the active level of the third scan signal G3) is applied to the ninth transistor T9 and the active level of the third control signal CKC is applied to the third control line CKCL, the voltage of the seventh node N7 is the active level of the third control signal CKC, which makes the eighth transistor T8 turn on.

[0139] The third scan signal G3 (i.e. the active level of the third scan signal G3) is applied to the eleventh transistor T11 and the inactive level of the fourth control signal CKD is applied to the fourth control line CKDL, the voltage of the eighth node N8 is the inactive level of the fourth control signal CKD, which makes the tenth transistor T10 turn off.

[0140] Thus, the sixth transistor T6 turns off and the eighth transistor T8 turns on, which makes the composite pass module MA turn on; when there is a driving current flowing through the composite pass module MA, the driving current flows through the first light emitting element RLD. The tenth transistor T10 turns off and makes the third pass module MB turn off.

[0141] Referring to Figure 6 In the second sub-stage t2 of the first stage P1 of the example, the initialization voltage Vinit can also be applied to the sensing line SL and the second scan signal G2 is applied to the sensing transistor T5, which makes the driving current outputted by the driving transistor T4 under the control of the voltage on the second node N2 flow into the sensing line SL. This makes the first light emitting element RLD be shorted by the sensing line SL and not emit light. Of course, in this stage, the second scan signal G2 can not be applied to the sensing transistor T5 or the initialization voltage Vinit can not be applied to the sensing line SL.

[0142] Referring to Figure 6In the second sub-stage t2 of the first stage P1 of this example, the third transistor T3 can also be loaded with the third scan signal G3 and the second control line CKBL can also be loaded with the inactive level of the second control signal CKB, so that the voltage of the sixth node N6 is the inactive level of the second control signal CKB, which makes the seventh transistor T7 be turned off. It can be understood that the third transistor T3 can also not be loaded with the third scan signal G3 or the second control line CKBL can also not be loaded with the inactive level of the second control signal CKB; in the case that the eighth transistor T8 is turned on, the second light emitting element GLD has been short-circuited and will not emit light. Of course, making the seventh transistor T7 remain turned off is conducive to avoiding the second light emitting element GLD emitting light under the driving of the leakage current, which can reduce the possible cross talk.

[0143] In the third sub-stage t3 of the first stage P1, referring to Figure 6 and Figure 7 The data write transistor T1 is not loaded with the first scan signal G1 so as to be turned off. For example, the data write transistor T1 is loaded with the inactive level of the first scan signal G1 so as to remain turned off. At this time, the voltage on the second node N2 is maintained as the data voltage Vdata of the first light emitting element RLD.

[0144] The sensing transistor T5 is not loaded with the second scan signal G2 so as to be turned off. For example, the sensing transistor T5 is loaded with the inactive level of the second scan signal G2 so as to remain turned off. The second transistor T2, the third transistor T3, the ninth transistor T9 and the eleventh transistor T11 are not loaded with the third scan signal G3 so as to be turned off. For example, the second transistor T2 is loaded with the inactive level of the third scan signal G3 so as to remain turned off, the third transistor T3 is loaded with the inactive level of the third scan signal G3 so as to remain turned off, the ninth transistor T9 is loaded with the inactive level of the third scan signal G3 so as to remain turned off, and the eleventh transistor T11 is loaded with the inactive level of the third scan signal G3 so as to remain turned off. In this way, the states of the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are locked, which makes the driving current generated by the driving transistor T4 flow through the first light emitting element RLD, and in turn the first light emitting element RLD can be driven to emit light.

[0145] In the first sub-stage t4 of the second stage P2:

[0146] The second scan signal G2 (i.e. the active level of the second scan signal G2) is loaded to the sensing transistor T5 and the initialization voltage Vinit whose voltage value is equal to that of the reference power supply voltage VSS is loaded to the sensing wire SL; the sensing transistor T5 is turned on in response to the second scan signal G2, the voltage of the first node N1 is the initialization voltage Vinit, and the reset of the first node N1 and the anode of the first light emitting element RLD is realized.

[0147] The third scan signal G3 (i.e. the active level of the third scan signal G3) is loaded to the second transistor T2 and the active level of the first control signal CKA is loaded to the first control wire CKAL; the second transistor T2 is turned on in response to the third scan signal G3, so that the voltage of the fifth node N5 is the active level of the first control signal CKA, which makes the sixth transistor T6 turned on, and then the voltage of the third node N3 is the initialization voltage Vinit, and the reset of the third node N3 is realized.

[0148] The third scan signal G3 (i.e. the active level of the third scan signal G3) is loaded to the third transistor T3 and the active level of the second control signal CKB is loaded to the second control wire CKBL; the third transistor T3 is turned on in response to the third scan signal G3, so that the voltage of the sixth node N6 is the active level of the second control signal CKB, which makes the seventh transistor T7 turned on, and then the voltage of the anode of the second light emitting element GLD is the initialization voltage Vinit, and the reset of the anode of the second light emitting element GLD is realized.

[0149] The third scan signal G3 (i.e. the active level of the third scan signal G3) is loaded to the eleventh transistor T11 and the active level of the fourth control signal CKD is loaded to the fourth control wire CKDL; the eleventh transistor T11 is turned on in response to the third scan signal G3, so that the voltage of the eighth node N8 is the active level of the fourth control signal CKD, which makes the tenth transistor T10 turned on, and then the voltage of the anode of the third light emitting element BLD is the initialization voltage Vinit, and the reset of the anode of the third light emitting element BLD is realized.

[0150] Thus, in the first sub-stage t4 of the second stage P2, the reset of the anode of the first light emitting element RLD, the anode of the second light emitting element GLD and the anode of the third light emitting element BLD can be realized.

[0151] Referring to Figure 6In the first sub-stage t4 of the second stage P2 of this example, the first scan signal G1 (i.e. the active level of the first scan signal G1) can also be loaded to the data write transistor T1 and the data voltage Vdata of the second light emitting element GLD can also be loaded to the data line DL; the data write transistor T1 is turned on in response to the first scan signal G1 and the data voltage Vdata of the second light emitting element GLD is written to the second node N2. It can be appreciated that the data voltage Vdata of the second light emitting element GLD can not be written to the second node N2 in this stage.

[0152] Referring to Figure 6 In the first sub-stage t4 of the second stage P2 of this example, the third scan signal G3 (i.e. the active level of the third scan signal G3) can also be loaded to the ninth transistor T9 and the active level of the third control signal CKC can also be loaded to the third control line CKCL; the ninth transistor T9 is turned on in response to the third scan signal G3 so that the voltage at the seventh node N7 is the active level of the fourth control signal CKD, which turns on the eighth transistor T8. It can be appreciated that the third scan signal G3 can not be loaded to the ninth transistor T9 or the active level of the third control signal CKC can not be loaded to the third control line CKCL in this stage.

[0153] In the second sub-stage t5 of the second stage P2:

[0154] The first scan signal G1 (i.e. the active level of the first scan signal G1) is loaded to the data write transistor T1 and the data voltage Vdata of the second light emitting element GLD is loaded to the data line DL; the data write transistor T1 is turned on in response to the first scan signal G1 and the data voltage Vdata of the second light emitting element GLD is written to the second node N2.

[0155] The third scan signal G3 (i.e. the active level of the third scan signal G3) is loaded to the second transistor T2 and the active level of the first control signal CKA is loaded to the first control line CKAL, so that the voltage at the fifth node N5 is the active level of the first control signal CKA, which turns on the sixth transistor T6 and in turn shorts the first light emitting element RLD.

[0156] The third scan signal G3 is loaded to the third transistor T3 and the active level of the second control signal CKB is loaded to the second control line CKBL, so that the voltage at the sixth node N6 is the active level of the second control signal CKB, which turns on the seventh transistor T7.

[0157] The ninth transistor T9 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the fourth control line CKDL is loaded with the inactive level of the fourth control signal CKD, and the voltage of the eighth node N8 is the inactive level of the fourth control signal CKD, which makes the tenth transistor T10 turn off.

[0158] The eleventh transistor T11 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the fourth control line CKDL is loaded with the inactive level of the fourth control signal CKD, and the voltage of the eighth node N8 is the inactive level of the fourth control signal CKD, which makes the tenth transistor T10 turn off.

[0159] Thus, the sixth transistor T6 turns on, the seventh transistor T7 turns on and the eighth transistor T8 turns off, which makes the composite pass module MA turn on; when there is a driving current flowing through the composite pass module MA, the driving current flows through the second light emitting element GLD. The tenth transistor T10 turns off so that the third pass module MB turns off.

[0160] Referring to Figure 6 In the second sub-stage t5 of the second stage P2 of the example, the initialization voltage Vinit can also be loaded to the sensing line SL and the second scan signal G2 is loaded to the sensing transistor T5, which makes the driving current outputted by the driving transistor T4 under the control of the voltage on the second node N2 flow into the sensing line SL. This makes the second light emitting element GLD be short-circuited by the sensing line SL and not emit light. Of course, in this stage, the second scan signal G2 can not be loaded to the sensing transistor T5 or the initialization voltage Vinit can not be loaded to the sensing line SL.

[0161] In the third sub-stage t6 of the second stage P2, referring to Figure 6 and Figure 8 The first scan signal G1 is not loaded to the data write transistor T1 so that the data write transistor T1 turns off. For example, the inactive level of the first scan signal G1 is loaded to the data write transistor T1 so that the data write transistor T1 remains off. At this time, the voltage on the second node N2 is maintained as the data voltage Vdata of the second light emitting element GLD.

[0162] The second scan signal G2 is not loaded to the sensing transistor T5 to make the sensing transistor T5 turn off. For example, the invalid level of the second scan signal G2 is loaded to the sensing transistor T5 to make the sensing transistor T5 keep turning off. The third scan signal G3 is not loaded to the second transistor T2, the third transistor T3, the ninth transistor T9 and the eleventh transistor T11 to make the second transistor T2, the third transistor T3, the ninth transistor T9 and the eleventh transistor T11 turn off. For example, the invalid level of the third scan signal G3 is loaded to the second transistor T2 to make the second transistor T2 keep turning off, the invalid level of the third scan signal G3 is loaded to the third transistor T3 to make the third transistor T3 keep turning off, the invalid level of the third scan signal G3 is loaded to the ninth transistor T9 to make the ninth transistor T9 keep turning off, and the invalid level of the third scan signal G3 is loaded to the eleventh transistor T11 to make the eleventh transistor T11 keep turning off. In this way, the states of the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are locked, which makes the driving current generated by the driving transistor T4 flow through the second light emitting element GLD, and thus the second light emitting element GLD can be driven to emit light.

[0163] In the first sub-stage t7 of the third stage P3:

[0164] The second scan signal G2 (i.e. the valid level of the second scan signal G2) is loaded to the sensing transistor T5, and the initialization voltage Vinit whose voltage value is equal to that of the reference power voltage VSS is loaded to the sensing wire SL; the sensing transistor T5 turns on in response to the second scan signal G2, and the voltage of the first node N1 is the initialization voltage Vinit, so that the first node N1 and the anode of the first light emitting element RLD are reset.

[0165] The third scan signal G3 (i.e. the valid level of the third scan signal G3) is loaded to the second transistor T2, and the valid level of the first control signal CKA is loaded to the first control wire CKAL; the second transistor T2 turns on in response to the third scan signal G3, so that the voltage of the fifth node N5 is the valid level of the first control signal CKA, which makes the sixth transistor T6 turn on, and thus the voltage of the third node N3 is the initialization voltage Vinit, so that the third node N3 is reset.

[0166] The third transistor T3 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the active level of the second control signal CKB is loaded to the second control line CKBL; the third transistor T3 is turned on in response to the third scan signal G3, so that the voltage of the sixth node N6 is the active level of the second control signal CKB, which makes the seventh transistor T7 turned on, and then makes the voltage of the anode of the second light emitting element GLD be the initialization voltage Vinit, realizing the reset of the anode of the second light emitting element GLD.

[0167] The eleventh transistor T11 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the active level of the fourth control signal CKD is loaded to the fourth control line CKDL; the eleventh transistor T11 is turned on in response to the third scan signal G3, so that the voltage of the eighth node N8 is the active level of the fourth control signal CKD, which makes the tenth transistor T10 turned on, and then makes the voltage of the anode of the third light emitting element BLD be the initialization voltage Vinit, realizing the reset of the anode of the third light emitting element BLD.

[0168] Thus, in the first sub-stage t7 of the third stage P3, the reset of the anode of the first light emitting element RLD, the anode of the second light emitting element GLD and the anode of the third light emitting element BLD can be realized.

[0169] Referring to Figure 6 In the first sub-stage t7 of the third stage P3 of this example, the first scan signal G1 (i.e. the active level of the first scan signal G1) can also be loaded to the data writing transistor T1 and the data voltage Vdata of the third light emitting element BLD can also be loaded to the data line DL; the data writing transistor T1 is turned on in response to the first scan signal G1, and the data voltage Vdata of the third light emitting element BLD is written to the second node N2. It can be understood that the data voltage Vdata of the third light emitting element BLD can also not be written to the second node N2 in this stage.

[0170] Referring to Figure 6 In the first sub-stage t7 of the third stage P3 of this example, the third scan signal G3 (i.e. the active level of the third scan signal G3) can also be loaded to the ninth transistor T9 and the active level of the third control signal CKC can also be loaded to the third control line CKCL; the ninth transistor T9 is turned on in response to the third scan signal G3, so that the voltage of the seventh node N7 is the active level of the fourth control signal CKD, which makes the eighth transistor T8 turned on. It can be understood that the third scan signal G3 can also not be loaded to the ninth transistor T9 in this stage, or the active level of the third control signal CKC can also not be loaded to the third control line CKCL.

[0171] In the second sub-stage t8 of the third stage P3:

[0172] The data write transistor T1 is loaded with the first scan signal G1 (i.e. the active level of the first scan signal G1) and the data voltage Vdata of the third light emitting element BLD is loaded to the data line DL; the data write transistor T1 is turned on in response to the first scan signal G1, and the data voltage Vdata of the third light emitting element BLD is written to the second node N2.

[0173] The third transistor T3 is loaded with the third scan signal G3 and the inactive level of the second control signal CKB is loaded to the second control line CKBL, the voltage of the sixth node N6 is the inactive level of the second control signal CKB, which makes the seventh transistor T7 turn off.

[0174] The ninth transistor T9 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the inactive level of the third control signal CKC is loaded to the third control line CKCL, the voltage of the seventh node N7 is the inactive level of the third control signal CKC, which makes the eighth transistor T8 turn off.

[0175] The eleventh transistor T11 is loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the active level of the fourth control signal CKD is loaded to the fourth control line CKDL, the voltage of the eighth node N8 is the active level of the fourth control signal CKD, which makes the tenth transistor T10 turn on.

[0176] In this way, the seventh transistor T7 turns off and the eighth transistor T8 turns off, which makes the composite pass module MA turn on; the tenth transistor T10 turns on, which makes the third pass module MB turn on.

[0177] Referring to Figure 6 In the second sub-stage t8 of the third stage P3 of the example, the second transistor T2 can also be loaded with the third scan signal G3 (i.e. the active level of the third scan signal G3) and the active level of the first control signal CKA is loaded to the first control line CKAL, the voltage of the fifth node N5 is the active level of the first control signal CKA, which makes the sixth transistor T6 turn on, and in turn makes the first light emitting element RLD be short-circuited. It can be understood that the second transistor T2 can also not be loaded with the third scan signal G3 or the first control line CKAL can also not be loaded with the active level of the first control signal CKA. Whether the sixth transistor T6 turns on or turns off, the composite pass module MA has already been broken, and will not make the first light emitting element RLD emit light.

[0178] Referring to Figure 6In the second sub-stage t8 of the third stage P3 of this example, an initialization voltage Vinit can also be loaded to the sense line SL and a second scan signal G2 is loaded to the sense transistor T5, which makes the drive current outputted by the drive transistor T4 under the control of the voltage on the second node N2 to flow into the sense line SL. This makes the third light emitting element BLD be short-circuited by the sense line SL and not emit light. Of course, in this stage, the second scan signal G2 can not be loaded to the sense transistor T5 or the initialization voltage Vinit can not be loaded to the sense line SL.

[0179] In the third sub-stage t9 of the third stage P3, see Figure 6 and Figure 9 the data write transistor T1 is not loaded with the first scan signal G1 so that the data write transistor T1 is turned off. For example, the data write transistor T1 is loaded with an invalid level of the first scan signal G1 so that the data write transistor T1 remains turned off. At this time, the voltage on the second node N2 is maintained as the data voltage Vdata of the third light emitting element BLD.

[0180] the sense transistor T5 is not loaded with the second scan signal G2 so that the sense transistor T5 is turned off. For example, the sense transistor T5 is loaded with an invalid level of the second scan signal G2 so that the sense transistor T5 remains turned off. The second transistor T2, the third transistor T3, the ninth transistor T9 and the eleventh transistor T11 are not loaded with the third scan signal G3 so that the second transistor T2, the third transistor T3, the ninth transistor T9 and the eleventh transistor T11 are turned off. For example, the second transistor T2 is loaded with an invalid level of the third scan signal G3 so that the second transistor T2 remains turned off, the third transistor T3 is loaded with an invalid level of the third scan signal G3 so that the third transistor T3 remains turned off, the ninth transistor T9 is loaded with an invalid level of the third scan signal G3 so that the ninth transistor T9 remains turned off, and the eleventh transistor T11 is loaded with an invalid level of the third scan signal G3 so that the eleventh transistor T11 remains turned off. In this way, the states of the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are locked, which makes the drive current generated by the drive transistor T4 to flow through the third light emitting element BLD and in turn drive the third light emitting element BLD to emit light.

[0181] Figure 10 Another driving method of the above exemplary display unit UU is given, see Figure 10 which is different from the above exemplary driving method only in that: Figure 6

[0182] ​In the first sub-stage t1 of the first stage P1, the first sub-stage t4 of the second stage P2, and the first sub-stage t7 of the third stage P3, the invalid level of the third control signal CKC instead of the valid level of the third control signal CKC is loaded on the third control line CKCL. In this way, the eighth transistor T8 remains off in the first sub-stage t1 of the first stage P1, the first sub-stage t4 of the second stage P2, and the first sub-stage t7 of the third stage P3, which still allows the anodes of the respective light emitting elements to be reset. In particular, when the voltage value of the initialization voltage Vinit and the voltage value of the reference power supply voltage VSS are different, the eighth transistor T8 remaining off allows the two power sources of the initialization voltage Vinit and the reference power supply voltage VSS to be isolated from each other.

[0183] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display unit, comprising: a driving current module configured to output a driving current to a first node according to a data voltage; a composite path module comprising a first path module and a second path module connected in series, and comprising a second control circuit; one end of the composite path module is electrically connected with the first node, and the other end is used for loading a reference power voltage; the first path module comprises a first light emitting element and a first control circuit connected in parallel with the first light emitting element; the second path module comprises a second light emitting element and a third control circuit connected in parallel with the second light emitting element; the second control circuit is used for controlling whether the composite path module is electrically connected; a third path module comprising a third light emitting element and a fourth control circuit connected in series, one end of the third path module is electrically connected with the first node, and the other end is used for loading the reference power voltage.

2. The display unit of claim 1, wherein, The driving current module comprises: a driving transistor, a first end of the driving transistor is used for loading a driving power voltage, a second end of the driving transistor is electrically connected with the first node, and a gate of the driving transistor is electrically connected with a second node; the driving transistor is capable of outputting a driving current to the first node under the control of a voltage on the second node; a data writing unit used for writing the data voltage to the second node in response to a first scan signal; a first capacitor, a first end of the first capacitor is electrically connected with the second node, and a second end of the first capacitor is electrically connected with the first node; a sensing unit used for loading an initialization voltage to the first node in response to a second scan signal.

3. The display unit of claim 2, wherein, The data writing unit comprises a data writing transistor; a first end of the data writing transistor is used for loading the data voltage, a second end of the data writing transistor is electrically connected with the second node, and a gate of the data writing transistor is used for loading the first scan signal; The sensing unit comprises a sensing transistor; a first end of the sensing transistor is used for loading the initialization voltage, a second end of the sensing transistor is electrically connected with the first node, and a gate of the sensing transistor is used for loading the second scan signal.

4. The display unit of claim 1, wherein, The first control circuit comprises a sixth transistor and a first control sub-circuit; a first end of the sixth transistor is connected with an anode of the first light emitting element, a second end of the sixth transistor is connected with a cathode of the first light emitting element; a gate of the sixth transistor is electrically connected with a fifth node, and is used for being turned on or turned off under the control of a voltage on the fifth node; the first control sub-circuit is used for controlling the voltage on the fifth node.

5. The display unit of claim 4, wherein, The first control sub-circuit comprises a second transistor and a second capacitor; a first end of the second transistor is used for loading a first control signal, a second end of the second transistor and a first end of the second capacitor are electrically connected with the fifth node, a gate of the second transistor is used for loading a third scan signal, and a second end of the second capacitor is used for loading the reference power voltage.

6. The display unit of claim 1, wherein, The third control circuit comprises an eighth transistor and a third control sub-circuit; The second end of the eighth transistor and the cathode of the second light emitting element are electrically connected; the first end of the eighth transistor is electrically connected with the anode of the second light emitting element, or the first end of the eighth transistor is electrically connected with the anode of the second light emitting element through the second control circuit; the gate of the eighth transistor is electrically connected with the seventh node, and is turned on or turned off under the control of the voltage on the seventh node; and the third control sub-circuit is used for controlling the voltage on the seventh node.

7. The display unit of claim 6, wherein, The third control sub-circuit comprises a ninth transistor and a fourth capacitor; the first end of the ninth transistor is used for loading a third control signal; the second end of the ninth transistor and the first end of the fourth capacitor are electrically connected with the seventh node; the gate of the ninth transistor is used for loading a third scanning signal, and the second end of the fourth capacitor is used for loading the reference power supply voltage.

8. The display unit of claim 1, wherein, The second control circuit comprises a seventh transistor and a second control sub-circuit; the seventh transistor is arranged in series with the first light emitting element and in parallel with the first control circuit, or the seventh transistor is arranged in series with the first path module and the second path module, or the seventh transistor is arranged in series with the second light emitting element and in parallel with the third control circuit; The gate of the seventh transistor is electrically connected with the sixth node, and is turned on or turned off under the control of the voltage on the sixth node; and the second control sub-circuit is used for controlling the voltage on the sixth node.

9. The display unit of claim 8, wherein, The second control sub-circuit comprises a third transistor and a third capacitor; the first end of the third transistor is used for loading a second control signal, and the second end of the third transistor and the first end of the third capacitor are electrically connected with the sixth node; the gate of the third transistor is used for loading a third scanning signal, and the second end of the third capacitor is used for loading the reference power supply voltage.

10. The display unit of claim 8, wherein, The anode of the first light emitting element and one end of the first control circuit are electrically connected with the first node, and the cathode of the first light emitting element and the other end of the first control circuit are electrically connected with the third node; The cathode of the second light emitting element and one end of the third control circuit are used for loading the reference power supply voltage, the anode of the second light emitting element is electrically connected with the second end of the seventh transistor, and the first end of the seventh transistor and the other end of the third control circuit are electrically connected with the third node.

11. The display unit of claim 1, wherein, The fourth control circuit comprises a tenth transistor and a fourth control sub-circuit; the first end of the tenth transistor is electrically connected with the first node, the second end of the tenth transistor is electrically connected with the anode of the third light emitting element, and the cathode of the third light emitting element is used for loading the reference power supply voltage; The gate of the tenth transistor is electrically connected with the eighth node, and is turned on or turned off under the control of the voltage on the eighth node; and the fourth control sub-circuit is used for controlling the voltage on the eighth node.

12. The display unit of claim 11, wherein, The fourth control sub-circuit comprises an eleventh transistor and a fifth capacitor; a first end of the eleventh transistor is used for loading a fourth control signal, a second end of the eleventh transistor and a first end of the fifth capacitor are electrically connected with the eighth node; a gate of the eleventh transistor is used for loading a third scan signal, and a second end of the fifth capacitor is used for loading the reference power supply voltage.

13. The display unit of claim 1, wherein, The driving current module comprises a data writing transistor, a driving transistor, a sensing transistor and a first capacitor; the data writing transistor is used for loading the data voltage to a second node in response to a first scan signal, and the sensing transistor is used for loading an initialization voltage to the first node in response to a second scan signal; a first end of the first capacitor is electrically connected with the second node, and a second end of the first capacitor is electrically connected with the first node; a first end of the driving transistor is used for loading a driving power supply voltage, a gate of the driving transistor is electrically connected with the second node, and a second end of the driving transistor is electrically connected with the first node; The driving transistor is configured to output a driving current to the first node under the control of the voltage on the second node; The first control circuit comprises a sixth transistor, a second transistor and a second capacitor; a first end of the sixth transistor and an anode of the first light emitting element are electrically connected with the first node, a second end of the sixth transistor and a cathode of the first light emitting element are electrically connected with a third node, a gate of the sixth transistor, a second end of the second transistor and a first end of the second capacitor are electrically connected with a fifth node, the second transistor is used for loading a first control signal to the fifth node in response to a third scan signal, and a second end of the second capacitor is used for loading a reference power supply voltage; The second control circuit comprises a seventh transistor, a third transistor and a third capacitor; a first end of the seventh transistor is electrically connected with the third node, a second end of the seventh transistor is electrically connected with an anode of the second light emitting element, a gate of the seventh transistor, a second end of the third transistor and a first end of the third capacitor are electrically connected with a sixth node, the third transistor is used for loading a second control signal to the sixth node in response to the third scan signal; and a second end of the third capacitor is used for loading the reference power supply voltage; The third control circuit comprises an eighth transistor, a ninth transistor and a fourth capacitor; a first end of the eighth transistor is electrically connected with the third node, a second end of the eighth transistor and a cathode of the second light emitting element are used for loading the reference power supply voltage, a gate of the eighth transistor, a second end of the ninth transistor and a first end of the fourth capacitor are electrically connected with a seventh node, the ninth transistor is used for loading a third control signal to the seventh node in response to the third scan signal, and a second end of the fourth capacitor is used for loading the reference power supply voltage; The fourth control circuit comprises a tenth transistor, an eleventh transistor and a fifth capacitor; a first end of the tenth transistor is electrically connected with the first node, a second end of the tenth transistor is electrically connected with an anode of the third light emitting element, a gate of the tenth transistor, a second end of the eleventh transistor and a first end of the fifth capacitor are electrically connected with an eighth node, the eleventh transistor is used for loading a fourth control signal to the eighth node in response to the third scan signal, and a second end of the fifth capacitor is used for loading the reference power voltage.

14. The display unit according to any one of claims 1 to 13, wherein The first light emitting element, the second light emitting element and the third light emitting element are arranged in layers.

15. A display panel comprising the display unit of any one of claims 1-14.

16. A driving method of a display unit according to any one of claims 1 to 14, wherein The driving method comprises: In a first stage, after the data voltage of the first light emitting element is written into the driving current module, the composite path module is electrically connected, and the first control circuit is disconnected, the third control circuit is connected, and the fourth control circuit is disconnected; In a second stage, after the data voltage of the second light emitting element is written into the driving current module, the composite path module is electrically connected, and the third control circuit is disconnected, the first control circuit is connected, and the fourth control circuit is disconnected; In a third stage, after the data voltage of the third light emitting element is written into the driving current module, the composite path module is disconnected and the fourth control circuit is electrically connected.

17. A driving method of a display unit according to claim 13, wherein The driving method comprises: In a first sub-stage of the first stage, the second scan signal and the initialization voltage are loaded to the sensing transistor, the third scan signal and an effective level of the first control signal are loaded to the second transistor to make the sixth transistor connected, the third scan signal and an effective level of the second control signal are loaded to the third transistor to make the seventh transistor connected, and the third scan signal and an effective level of the fourth control signal are loaded to the eleventh transistor to make the tenth transistor connected; In a second sub-stage of the first stage, the first scan signal and the data voltage of the first light emitting element are loaded to the data writing transistor to make the data voltage of the first light emitting element written into the second node, the third scan signal and an ineffective level of the first control signal are loaded to the second transistor to make the sixth transistor cut off, the third scan signal and an effective level of the third control signal are loaded to the ninth transistor to make the eighth transistor connected, and the third scan signal and an ineffective level of the fourth control signal are loaded to the eleventh transistor to make the tenth transistor cut off; In a second stage, after the data voltage of the second light emitting element is written into the driving current module, the composite path module is electrically connected, and the third control circuit is disconnected, the first control circuit is connected, and the fourth control circuit is disconnected; In a third stage, after the data voltage of the third light emitting element is written into the driving current module, the composite path module is disconnected and the fourth control circuit is electrically connected. The driving method comprises: In a first sub-stage of the first stage, the second scan signal and the initialization voltage are loaded to the sensing transistor, the third scan signal and an effective level of the first control signal are loaded to the second transistor to make the sixth transistor connected, the third scan signal and an effective level of the second control signal are loaded to the third transistor to make the seventh transistor connected, and the third scan signal and an effective level of the fourth control signal are loaded to the eleventh transistor to make the tenth transistor connected; In a second sub-stage of the first stage, the first scan signal and the data voltage of the first light emitting element are loaded to the data writing transistor to make the data voltage of the first light emitting element written into the second node, the third scan signal and an ineffective level of the first control signal are loaded to the second transistor to make the sixth transistor cut off, the third scan signal and an effective level of the third control signal are loaded to the ninth transistor to make the eighth transistor connected, and the third scan signal and an ineffective level of the fourth control signal are loaded to the eleventh transistor to make the tenth transistor cut off; In a third sub-phase of the first phase, the data write transistor is not loaded with the first scan signal to render the data write transistor off; the sensing transistor is not loaded with the second scan signal to render the sensing transistor off; the second transistor, the third transistor, the ninth transistor, and the eleventh transistor are not loaded with the third scan signal to render the second transistor, the third transistor, the ninth transistor, and the eleventh transistor off; In a first sub-phase of the second phase, the sensing transistor is loaded with the second scan signal and the initialization voltage; the second transistor is loaded with the third scan signal and an active level of the first control signal to render the sixth transistor on; the third transistor is loaded with the third scan signal and an active level of the second control signal to render the seventh transistor on; the eleventh transistor is loaded with the third scan signal and an active level of the fourth control signal to render the tenth transistor on; In a second sub-phase of the second phase, the data write transistor is loaded with the first scan signal and a data voltage of the second light emitting element to render the data voltage of the second light emitting element written to the second node; the second transistor is loaded with the third scan signal and an active level of the first control signal to render the sixth transistor on; the third transistor is loaded with the third scan signal and an active level of the second control signal to render the seventh transistor on; the ninth transistor is loaded with the third scan signal and an inactive level of the third control signal to render the eighth transistor off; the eleventh transistor is loaded with the third scan signal and an inactive level of the fourth control signal to render the tenth transistor off; In a third sub-phase of the second phase, the data write transistor is not loaded with the first scan signal to render the data write transistor off; the sensing transistor is not loaded with the second scan signal to render the sensing transistor off; the second transistor, the third transistor, the ninth transistor, and the eleventh transistor are not loaded with the third scan signal to render the second transistor, the third transistor, the ninth transistor, and the eleventh transistor off; In a first sub-phase of the third phase, the sensing transistor is loaded with the second scan signal and the initialization voltage; the second transistor is loaded with the third scan signal and an active level of the first control signal to render the sixth transistor on; the third transistor is loaded with the third scan signal and an active level of the second control signal to render the seventh transistor on; the eleventh transistor is loaded with the third scan signal and an active level of the fourth control signal to render the tenth transistor on; In a second sub-stage of the third stage, the data write transistor is loaded with the first scan signal and the data voltage of the third light emitting element, such that the data voltage of the third light emitting element is written to the second node; the third transistor is loaded with the third scan signal and an inactive level of the second control signal, such that the seventh transistor is turned off; the ninth transistor is loaded with the third scan signal and an inactive level of the third control signal, such that the eighth transistor is turned off; the eleventh transistor is loaded with the third scan signal and an active level of the fourth control signal, such that the tenth transistor is turned on; In a third sub-stage of the third stage, the data write transistor is not loaded with the first scan signal, such that the data write transistor is turned off; the sensing transistor is not loaded with the second scan signal, such that the sensing transistor is turned off; the second transistor, the third transistor, the ninth transistor and the eleventh transistor are not loaded with the third scan signal, such that the second transistor, the third transistor, the ninth transistor and the eleventh transistor are turned off.

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