An attribute-driven persistent fault analysis method

Abstract

The application discloses a kind of attribute-driven persistent fault analysis methods, first establish basic logic unit formalization fault model library and the formalization fault model of cryptographic algorithm kernel;Then the random simulation of cryptographic algorithm kernel formalization fault model is carried out;Again the fault information that satisfies is automatically extracted fault attribute;Next, the persistent fault injection attack of cryptographic algorithm is carried out;Finally, the persistent fault analysis of cryptographic algorithm is realized using fault attribute as constraint.The present application establishes fault propagation model without complex mathematical operation, and has no strict requirement for the position and quantity of fault injection, reduces the number of fault ciphertext used and key search complexity, compared with the existing fault injection analysis technology, the application method is more widely used.

Description

Technical Field

[0001] This invention belongs to the field of security detection technology for cryptographic algorithm implementation, specifically relating to an attribute-driven persistent fault analysis method. Background Technology

[0002] Fault injection attacks actively interfere with the normal operation of cryptographic devices through external means, obtaining the key by analyzing the fault information in the ciphertext. This is an effective cryptanalysis method. Fault injection attacks consist of two phases: fault injection and fault analysis. Common fault injection methods include voltage, electromagnetic, laser, and clock glitches. Based on the number of faults, they can be categorized as single-bit, single-byte, and multi-byte faults. Based on the injection method, they can be classified as random, persistent, and permanent faults. Random faults refer to those where the specific value and location of the injected fault cannot be controlled, and the fault disappears after each encryption; these are also called transient faults. Persistent faults remain unchanged and effective indefinitely if the chip operates normally without power outages or restarts. Persistent faults are generally caused by irreversible changes in components, permanently altering their original logic. Relatively speaking, persistent faults are currently the most widely studied form of fault injection. In the fault analysis phase, the attacker analyzes the ciphertext information after the fault injection attack to crack the encryption algorithm key.

[0003] Currently, commonly used key recovery methods for encryption algorithms include differential analysis and statistical analysis. Typical fault analysis methods include Differential Fault Attack (DFA) and Statistical Fault Analysis (SFA). DFA obtains a fault pattern by comparing correct and faulty ciphertexts, then performs mathematical analysis to recover the key. This process generally requires complex mathematical derivations and has strict requirements on the location and quantity of fault injections. SFA is a statistically based ciphertext-only fault analysis method, but it requires analyzing a large number of faulty ciphertexts to recover the key.

[0004] It is evident that existing fault analysis methods generally require complex mathematical derivations or statistical analyses to achieve key recovery, and have strict requirements on the location and number of faults. There are very few attribute-driven methods for key recovery. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention provides an attribute-driven persistent fault analysis method. First, a formal fault model library for basic logical units and a formal fault model for cryptographic algorithm kernels are established. Then, random simulations are performed on the formal fault models of the cryptographic algorithm kernels. Next, fault attributes satisfied by fault information are automatically extracted. Then, persistent fault injection attacks are performed on the cryptographic algorithm. Finally, persistent fault analysis of the cryptographic algorithm is achieved using fault attributes as constraints. This invention does not require complex mathematical calculations to establish the fault propagation model, and it has no strict requirements on the location and number of fault injections, reducing the amount of faulty ciphertext used and the complexity of key search. Compared with existing fault injection analysis techniques, this invention has a wider range of applications.

[0006] The technical solution adopted by this invention to solve its technical problem includes the following steps:

[0007] Step 1: Establish a formal fault model library for basic logic units;

[0008] The fault model represents the fault state by adding a label to each logic unit. When the fault label of a signal is '1', it indicates that the signal has failed. The fault model is constructed by analyzing the propagation of fault labels in the circuit. The fault label corresponding to the input signal can only propagate to the fault label of the output signal if and only if the input data affects the value of the output data.

[0009] Let A and B be the input signals, and O be the output signal. e For signal A, the fault tag is B. e Let B be the fault label for signal B; then the logical expression for the two-input OR gate fault model is: The logical expression for the two-input AND gate fault model is as follows: The logical expression for the NOT gate fault model is O e =A e This leads to the formation of a formal fault model library for basic logic units.

[0010] Step 2: Establish a formal fault model for the cryptographic algorithm kernel;

[0011] The hardware implementation of the cryptographic algorithm can be mapped to a gate-level netlist or basic logic unit after logic synthesis. By mapping the corresponding basic logic unit in the hardware design of the cryptographic algorithm to the formal fault model library of basic logic unit constructed in step 1, a formal fault model of the cryptographic algorithm is generated.

[0012] Step 3: Perform stochastic simulation of the formal fault model of the cryptographic algorithm kernel;

[0013] The formal fault model of the cryptographic algorithm kernel established in step 2 is subjected to random simulation; a random number generator generates random plaintext to provide different stimuli to the fault propagation model; the model is simulated using simulation tools; the non-zero bytes in the fault label in the simulation results are the fault information; the fault ciphertext is classified and organized according to the position and number of the initial fault bytes.

[0014] Step 4: Automatically extract the fault attributes that the fault information meets;

[0015] Attribute extraction is performed based on the fault information obtained in step 3;

[0016] Based on the distribution of fault information of different categories, the location attributes are obtained. The Boolean expression that the fault information satisfies is extracted as the fault-related attributes using the logic simplification tool. The formalization tool is used for verification. If the verification passes, the attribute is correct. Otherwise, the attribute is a false positive, that is, not all fault patterns satisfy the attribute. In this case, the number of fault information needs to be increased in step 3 and the fault-related attributes need to be extracted again.

[0017] Step 5: Perform a persistent fault injection attack on the cryptographic algorithm;

[0018] A persistent fault injection attack is performed on the cryptographic algorithm by injecting a persistent fault into the S-box table, causing a change in a certain S-box value in the S-box table;

[0019] Step 6: Use fault attributes as constraints to perform persistent fault analysis on cryptographic algorithms;

[0020] The fault attributes extracted in step 4 are used to perform fault analysis on the attack results in step 5; due to the characteristics of persistent faults, all fault information that occurs initially is the same. Based on the distribution characteristics of fault information in the ciphertext, it is matched with the location attribute to lock the location of the fault occurrence. The round key differential is obtained based on the consistency of the fault.

[0021] Fault analysis is divided into two cases: known persistent fault injection locations and unknown persistent fault injection locations.

[0022] If the location of the persistent fault injection is known, i.e. the location of the fault in the S-box table, and the location of the fault during the iteration of the cryptographic algorithm is obtained by attribute matching, this condition can be used as a known condition and combined with the correct ciphertext to determine the unique key bytes.

[0023] When the injection location of a persistent fault is unknown, it is necessary to guess the injection location i in the S-box table, with the corresponding S-box value being S(i). If the S-box value is in bytes, then the location search space is 2. 8The encryption algorithm shows that the key information is closely related to S(i). The key byte that makes the fault information in the correct and incorrect ciphertext pair satisfy the attribute constraints is searched as a candidate value. If the candidate value is not unique, the number of correct and incorrect ciphertext pairs analyzed is increased until the candidate value is unique.

[0024] Furthermore, in step 1, establishing a formal fault model library for basic logic units involves adding fault tags to the input and output signals of the basic logic units to identify the flow of fault information, establishing fault models for the basic logic units, and describing them using a standard hardware design language.

[0025] Furthermore, in step 3, the formal fault model of the cryptographic algorithm kernel is simulated using EDA simulation tools, and random plaintext generated by random numbers is used as the simulation stimulus.

[0026] Furthermore, in step 4, the fault attributes that are automatically extracted from the fault information are obtained by extracting the fault location attribute based on the distribution of fault bytes in the simulation results, mapping the fault information in the simulation results into a truth table, extracting the invariant behavior in the fault information as fault-related attributes through logical simplification, and improving the accuracy of attribute extraction by increasing the number of fault information.

[0027] Furthermore, step 5 involves performing a persistent fault injection attack on the cryptographic algorithm by interfering with the normal operation of the cryptographic device through laser or voltage fault injection devices, or by adding a fault injection module to the cryptographic algorithm design, so that the simulation attack achieves the same attack effect as a physical attack.

[0028] Furthermore, step 6, which utilizes fault attributes as constraints to perform persistent fault analysis on cryptographic algorithms, can achieve key search and recovery through standard EDA formal verification tools, or through software programming languages.

[0029] The beneficial effects of this invention are as follows:

[0030] 1. This invention proposes an attribute-driven persistent fault injection analysis method, which establishes a formal fault propagation model for cryptographic algorithm implementation to achieve accurate measurement of fault propagation.

[0031] 2. The fault propagation model established by this invention does not require complex mathematical calculations and has no strict requirements on the location and number of fault injections. Compared with existing fault injection analysis techniques, the method of this invention has a wider range of applications.

[0032] 3. This invention automatically extracts invariant behaviors during the fault propagation process as fault attributes. Formal verification methods can be used to search for key information that makes the fault information in the correct and incorrect ciphertext pairs conform to the fault attributes, which is the encryption key. This reduces the complexity of key search and automates fault attack analysis, making it more efficient than existing methods. Attached Figure Description

[0033] Figure 1 This is the overall flowchart of the method of the present invention.

[0034] Figure 2 This is a flowchart of the simulation test of the fault model of the cryptographic algorithm of the present invention to obtain fault information.

[0035] Figure 3 This is a schematic diagram of the process for automatically extracting fault-related attributes according to the present invention.

[0036] Figure 4 This is a schematic diagram of the attribute-driven persistent fault analysis of the present invention.

[0037] Figure 5 These are example diagrams of the simulation results of the AES formal fault model of the present invention. (a) The initial fault byte positions are byte0 and byte1, and (b) The initial fault byte positions are byte0 and byte5. Detailed Implementation

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] Existing fault analysis methods generally require complex mathematical operations or data statistics, necessitating the injection of specific types of faults at specific locations, which has significant limitations. Persistent faults, as a novel fault injection method, have been widely studied; however, this method, based on statistical principles, requires statistical analysis of a large number of fault-injected ciphertexts to recover the key, resulting in high computational complexity. The purpose of this invention is to propose an attribute-driven persistent fault analysis method. By establishing a formal fault propagation model of cryptographic algorithms, it achieves accurate tracking of fault propagation and automatically extracts fault-related attributes from the fault propagation characteristics. Fault analysis is then achieved by searching for key information that satisfies the fault attributes. Compared to existing fault analysis methods, the method proposed in this invention has no strict requirements on the location and number of fault injections, reduces the number of fault-injected ciphertexts used and the complexity of key search, and can also perform fault analysis in the case of multi-byte fault injection.

[0040] This invention proposes an attribute-driven persistent failure analysis method for cryptographic algorithms. The method involves three stages: formal failure model establishment, automated failure attribute extraction, and persistent failure injection attack analysis. Figure 1As shown. Formal fault model establishment involves creating a fine-grained fault model for cryptographic algorithm hardware design, enabling precise measurement of fault propagation. Automated fault attribute extraction extracts invariant behaviors in the fault propagation process as fault attributes based on simulation results of the fault model, providing effective support for fault analysis. Persistent fault injection attack analysis involves filtering key information that allows both correct and incorrect ciphertexts to satisfy fault attributes, using these as candidate values ​​to achieve key breaking.

[0041] Step 1: Establish a formal fault model library for basic logic units;

[0042] Fault information propagation must satisfy the logical constraints of the basic unit. For example, if one input signal in a two-input OR gate is '1', then the output must be '1', regardless of the other input signal. The fault model represents the fault state by adding a label to each logic unit. When the fault label of a signal is '1', it indicates that the signal has failed. By analyzing the propagation of fault labels in the circuit, a fault model is constructed. The fault label corresponding to the input signal can propagate to the fault label of the output signal if and only if the input data affects the value of the output data, thus achieving accurate measurement of fault propagation. Table 1 shows a partial truth table of the two-input OR gate fault model, where A and B are input signals, O is the output signal, and * e This is a fault tag for signal *. Fault tag A is used when neither input signal A nor B is faulty. e and B e When both input signals are '0', the output of the fault model will be consistent with the logic gate. Therefore, Table 1 only shows the truth table of the fault model when the input signal fails. Combining the truth table, the logical expression of the two-input OR gate fault model can be obtained as follows: Similarly, the logical expression for the two-input AND gate fault model can be obtained as follows: The logical expression of the NOT gate fault model is simpler. e =A e A similar approach can be used to establish fault propagation models for other basic logic units of integrated circuits, such as NAND gates and NOR gates, forming a formal fault model library for basic logic units.

[0043] Table 1. Partial Truth Table for Two-Input OR Gate Fault Model

[0044]

[0045] Step 2: Establish a formal fault model for the cryptographic algorithm kernel;

[0046] The hardware implementation of a cryptographic algorithm can be mapped to a gate-level netlist or basic logic unit after logical synthesis. By mapping the corresponding basic logic unit in the hardware design of the cryptographic algorithm to the formal fault model library of the basic logic unit constructed in step 1, a formal fault model of the cryptographic algorithm is generated, which can accurately describe the propagation of fault information.

[0047] Step 3: Perform stochastic simulation of the formal fault model of the cryptographic algorithm kernel;

[0048] The formal fault model of the cryptographic algorithm established in step 2 is subjected to random simulation. The specific process is as follows: Figure 2 As shown, a random number generator generates random plaintext to provide different stimuli to the fault propagation model. The model is simulated using simulation tools. In the simulation results, the non-zero bytes in the fault label are the fault information. The fault ciphertext is classified and organized according to the position and number of the initial fault bytes. The influence of different fault injection positions and numbers on the fault distribution in the ciphertext is analyzed, providing data support for realizing fault attributes.

[0049] Step 4: Automatically extract the fault attributes that the fault information meets;

[0050] Based on the fault information obtained in step 3, attribute extraction is performed. Location attributes can be obtained according to the distribution of fault information of different categories. A logical simplification tool is used to extract Boolean expressions that satisfy the relationships between fault information as fault-related attributes, such as... Figure 3 As shown. If the simulation results contain all fault patterns, the extracted fault attributes are guaranteed to be correct. However, when the fault pattern space is large, attribute extraction is performed based on the simulation results of only some fault patterns. To check whether the generated attributes are complete and cover all possible fault patterns, further attribute checks are needed to improve attribute coverage. We use formal tools for verification. If the verification passes, the attribute is correct; otherwise, the attribute is a false positive, meaning that not all fault patterns satisfy the attribute, and the attribute needs to be re-extracted. Generally, increasing the amount of fault information can increase the accuracy of the extracted fault attributes.

[0051] Step 5: Perform a persistent fault injection attack on the cryptographic algorithm.

[0052] Persistent fault injection attacks are used to target cryptographic algorithms. Typically, for common block cipher algorithms, this involves injecting persistent faults into the S-box lookup table, causing a change in a specific S-box value within the table.

[0053] Step 6: Utilize fault attributes as constraints to perform persistent fault analysis on cryptographic algorithms.

[0054] The fault attributes extracted in step 4 are used to perform fault analysis on the attack result in step 5. Due to the characteristics of persistent faults, all initially occurring fault information is identical. Based on the distribution characteristics of fault information in the ciphertext and matching with location attributes, the location of the fault can be pinpointed. The round key difference is obtained based on the consistency of the faults. For example, if the fault occurs in the last round of the encryption iteration, and the S-box input of the faulty byte is consistent, the key difference for the last round can be obtained by combining the faulty bytes in the ciphertext result. Using the key difference, further fault analysis is conducted on the correct and incorrect ciphertext pairs. Figure 4 Fault analysis is divided into two cases: known persistent fault injection locations and unknown persistent fault injection locations. If the persistent fault injection location is known, i.e., the location of the fault in the S-box table, the location where the fault occurred during the iteration process of the cryptographic algorithm can be obtained through attribute matching. This condition, combined with the correct ciphertext, can then be used as a known condition to determine the unique key byte. The second case is when the persistent fault injection location is unknown. It is necessary to guess the persistent fault injection location i in the S-box table, with the corresponding S-box value S(i). If the S-box value is in bytes, then the location search space is 2^i. 8 As can be seen from the encryption algorithm, the key information is closely related to S(i). The search is performed to find the key byte that satisfies the attribute constraints of the fault information in the correct and incorrect ciphertext pairs as the candidate value. If the candidate value is not unique, the number of correct and incorrect ciphertext pairs analyzed is increased until the candidate value is unique.

[0055] Step 1 involves establishing a formal fault model library for basic logic units by adding fault tags to the input and output signals of the basic logic units to identify the flow of fault information and establishing fault models for the basic logic units. These models are typically described using standard hardware design languages.

[0056] In step 2, the formal fault model of the cryptographic algorithm kernel is established by inputting register transfer level code or gate-level netlist. The basic logic units in the cryptographic algorithm mapping design are mapped to the basic logic unit formal fault model library to form a formal fault propagation model of the cryptographic algorithm, thereby achieving accurate measurement of fault propagation.

[0057] In step 3, the formal fault model of the cryptographic algorithm core is simulated using a random simulation. Standard EDA simulation tools can be used to simulate the fault model of the cryptographic algorithm, and random plaintext generated by random numbers can be used as simulation stimulus.

[0058] In step 3, the formal fault model of the cryptographic algorithm core is subjected to random simulation. The simulation results need to be classified according to the location and number of bytes of the fault, and the fault information of the fault bytes in the corresponding simulation results is obtained to provide sufficient data support for extracting fault attributes.

[0059] In step 4, the fault attributes automatically extracted from the fault information can be used to extract fault location attributes based on the distribution of fault bytes in the simulation results. The fault information in the simulation results is mapped to a truth table, and invariant behaviors in the fault information are extracted as fault-related attributes through logical simplification. The accuracy of attribute extraction can be improved by increasing the amount of fault information.

[0060] In step 4, the fault attributes that are automatically extracted and satisfied can be verified using formal tools to ensure that all fault patterns can satisfy the relevant fault attributes.

[0061] Step 5 involves performing a persistent fault injection attack on the cryptographic algorithm. This can be achieved by interfering with the normal operation of the cryptographic device through fault injection devices such as lasers or voltages, or by incorporating a fault injection module into the design of the cryptographic algorithm, so that the simulation attack can achieve the same attack effect as a physical attack.

[0062] Step 6 utilizes fault attributes as constraints to achieve persistent fault analysis of cryptographic algorithms. Key search and recovery can be achieved through standard EDA formal verification tools, or through software programming languages.

[0063] Taking the AES encryption algorithm implementation as an example, this invention illustrates the attribute-driven persistent fault analysis method. The hardware environment used for implementation included: Intel Core i7, Ubuntu 18.0, Windows 10, a voltage fault injection device, and a Sakura-x development board. The method proposed in this invention was implemented using the GCC compilation environment, the formalization tool Yosys, and the standard EDA tools Modelsim and Multisim.

[0064] The specific implementation of this invention is as follows:

[0065] 1) Establish an AES formal fault model

[0066] The AES hardware encryption design implemented in the standard hardware description language Verilog is logically synthesized to generate a gate-level netlist. The basic units in the AES hardware design are then mapped to a formal fault model library of basic logic units to establish an AES formal fault model.

[0067] 2) Simulate the formal fault model using AES.

[0068] Plaintext was generated using a random number generator as input stimulus for the fault model. The simulation included the location and number of all fault occurrences, and the corresponding results were organized by category. Taking the injection of a persistent fault into the 0th byte of the S-box lookup table as an example, assuming the injected fault changes S(0) from 0x63 to 71, Figure 5The image illustrates the propagation of a 2-byte fault in the AES cryptographic algorithm after one round of iterations. Here, `din` represents the plaintext input, `key` represents the round key input, and the fault labels for `din` and `key` are `din_e` and `key_e`, respectively. `sub_e`, `shr_e`, `mix_e`, and `dout_e` represent the fault labels for byte substitution, row shifting, column obfuscation, and round key addition transformation in AES, respectively. (Comparison) Figure 5 As shown in (a) and (b), the row shift transformation in the AES encryption algorithm alters the position of the initial fault, affecting the distribution of the fault during the column obfuscation transformation, and further influencing fault propagation. Due to the characteristics of the column obfuscation transformation, the transformations of each column in the state matrix are independent. Therefore, if the fault byte is distributed across different columns of the state matrix after the row shift transformation, then the fault bytes will be independent during the fault propagation process in each iteration. Figure 5 In (a), after row shifting, the two fault bytes are located in different columns of the state matrix and do not affect each other during round-by-round fault propagation. Figure 5 In (b), the two fault bytes are distributed in the same column of the state matrix after row shift transformation. The fault propagation of the two fault bytes affects each other. It can be seen that the fault distribution in the iterative result is closely related to the position of the fault bytes in the column confusion transformation.

[0069] 3) Extract the fault attributes satisfied during the AES fault propagation process.

[0070] As shown in step 2), even if the number of faulty bytes is the same but their positions are different, the distribution of faulty bytes after encryption iteration may also be different. First, observe the fault distribution in the ciphertext to determine the fault characteristics in the ciphertext under different fault positions and numbers. Then, use Multisim's logic simplification function to process the fault information and obtain the logical relationships between the fault information. Table 2 shows the positional attributes satisfied by the fault in a column of the AES state matrix after rounds of iteration when a multi-byte fault occurs. Different fault information is represented by fb0, fb1, and fb2, respectively, with 0x00 indicating that the corresponding byte has no fault information. After logic simplification, the logical relationships between faulty bytes can be obtained as fault-related attributes, as shown in Table 3. f represents the injected persistent fault. Table 3 lists some of the fault-related attributes satisfied by faulty bytes after logic simplification. Similarly, relevant attributes can be extracted when faults occur in other positions, providing a valid basis for subsequent fault analysis.

[0071] Table 2 shows the fault location attributes of the subsequent iterations after a multi-byte fault occurs in a certain column of the AES state matrix.

[0072]

[0073] Table 3 shows some fault-related attributes satisfied by AES fault information.

[0074]

[0075] 4) Implement AES persistent fault injection attack

[0076] In the AES cryptographic algorithm encryption process, a fault injection module is added to simulate physical fault injection. This module achieves continuous fault injection by randomly modifying a certain S-box value in the S-box table and collecting the correct and incorrect ciphertext after encryption.

[0077] 5) Attribute-driven persistent failure analysis

[0078] Based on the fault distribution characteristics, the initial fault location is determined. When the initial fault occurs at the m-th and n-th bytes of the last round, and given the persistent fault characteristics, bytes m and n are identical, the difference ΔK of the corresponding key bytes can be obtained from the ciphertext. 10 mn =K 10 m ^K 10 n =C m ^C n Similarly, the key differential for all bytes in the last round can be obtained. When the fault location i injected into the S-box is known, it can be obtained from K. 10 p =S(i)^C p By directly obtaining the key byte corresponding to the faulty byte p, and combining it with key differential, at least one pair of correct and incorrect ciphertexts is needed to recover the round key. When the fault location injected into the S-box is unknown, and the fault location is guessed to be i, then the key information for the faulty byte q is K. 10 q =S(i)^C q If the fault occurs in round 9, the guessed key information is used to recover the input of the correct and incorrect ciphertext pairs in round 10. It is then determined whether the fault information in the input of round 10 meets the fault-related attributes. If it does, it can be used as a candidate key value. When the candidate value is unique, it is the correct key byte. Other key bytes can be recovered using key differential. At this time, at least 2 pairs of correct and incorrect ciphertexts are needed to recover the round key.

Claims

1. An attribute-driven persistent fault analysis method, characterized in that, Includes the following steps: Step 1: Establish a formal fault model library for basic logic units; The fault model represents the fault state by adding a label to each logic unit. When the fault label of a signal is '1', it indicates that the signal has failed. The fault model is constructed by analyzing the propagation of fault labels in the circuit. The fault label corresponding to the input signal can only propagate to the fault label of the output signal if and only if the input data affects the value of the output data. Let A and B be the input signals, and O be the output signal. e For signal A, the fault tag is B. e Let B be the fault label for signal B; then the logical expression for the two-input OR gate fault model is: The logical expression for the two-input AND gate fault model is: ; The logical expression for the NOT gate fault model is: This leads to the formation of a formal fault model library for basic logic units. Step 2: Establish a formal fault model for the cryptographic algorithm kernel; The hardware implementation of the cryptographic algorithm can be mapped to a gate-level netlist or basic logic unit after logical synthesis. By mapping the corresponding basic logic unit in the hardware design of the cryptographic algorithm to the formal fault model library of basic logic unit constructed in step 1, a formal fault model of the cryptographic algorithm core is generated. Step 3: Perform stochastic simulation on the formal fault model of the cryptographic algorithm kernel; Random simulations were performed on the formal fault model of the cryptographic algorithm kernel established in step 2; A random number generator generates random plaintext to provide different stimuli to the fault model. The fault model is simulated using simulation tools. The non-zero bytes in the fault label in the simulation results are the fault information. The fault ciphertext is classified and organized according to the position and number of the initial fault bytes. Step 4: Automatically extract the fault attributes that the fault information meets; Attribute extraction is performed based on the fault information obtained in step 3; Based on the distribution of fault information of different categories, the fault location attributes are obtained, and the Boolean expressions that the fault information satisfies are extracted as fault-related attributes using a logic simplification tool. Use formal tools to verify. If the verification passes, the attribute is correct. Otherwise, the attribute is a false positive, meaning that not all fault patterns satisfy the attribute. Step 3 is needed to increase the number of fault information and re-extract the fault-related attributes. Step 5: Perform a persistent fault injection attack on the cryptographic algorithm; A persistent fault injection attack is performed on the cryptographic algorithm by injecting a persistent fault into the S-box table, causing a change in a certain S-box value in the S-box table; Step 6: Use fault attributes as constraints to perform persistent fault analysis on cryptographic algorithms; The fault attributes extracted in step 4 are used to perform fault analysis on the attack results in step 5; due to the characteristics of persistent faults, all fault information that occurs initially is the same. Based on the distribution characteristics of fault information in the ciphertext, it is matched with the location attribute to lock the location of the fault occurrence. The round key differential is obtained based on the consistency of the fault. Fault analysis is divided into two cases: known persistent fault injection locations and unknown persistent fault injection locations. If the location of the persistent fault injection is known, i.e. the location of the fault in the S-box table, and the location of the fault during the iteration of the cryptographic algorithm is obtained by attribute matching, this condition can be used as a known condition and combined with the correct ciphertext to determine the unique key bytes. When the injection location of a persistent fault is unknown, it is necessary to guess the injection location of the persistent fault in the S-box table. i The corresponding S-box value is S( i If the S-box value is in bytes, then the position search space is 2. 8 ; The encryption algorithm tells us the key information and S( i Closely related, the search makes the key byte in the correct and incorrect ciphertext pair that satisfies the attribute constraints as a candidate value. If the candidate value is not unique, the number of correct and incorrect ciphertext pairs analyzed is increased until the candidate value is unique.

2. The attribute-driven persistent fault analysis method according to claim 1, characterized in that, In step 1, establishing a formal fault model library for basic logic units involves adding fault tags to the input and output signals of basic logic units to identify the flow of fault information, establishing fault models for basic logic units, and describing them using a standard hardware design language.

3. The attribute-driven persistent fault analysis method according to claim 1, characterized in that, In step 3, the formal fault model of the cryptographic algorithm kernel is simulated using EDA simulation tools, and random plaintext generated by random numbers is used as the simulation stimulus.

4. The attribute-driven persistent fault analysis method according to claim 1, characterized in that, In step 4, the fault attributes that are automatically extracted from the fault information are obtained by extracting the fault location attribute based on the distribution of fault bytes in the simulation results, mapping the fault information in the simulation results into a truth table, extracting the invariant behavior in the fault information as fault-related attributes through logical simplification, and improving the accuracy of attribute extraction by increasing the number of fault information.

5. The attribute-driven persistent fault analysis method according to claim 1, characterized in that, Step 5, which involves performing a persistent fault injection attack on the cryptographic algorithm, involves interfering with the normal operation of the cryptographic device using laser or voltage fault injection devices, or adding a fault injection module to the cryptographic algorithm design, so that the simulation attack achieves the same attack effect as a physical attack.

6. The attribute-driven persistent fault analysis method according to claim 1, characterized in that, Step 6 utilizes fault attributes as constraints to achieve persistent fault analysis of cryptographic algorithms. This can be achieved through key search and recovery using standard EDA formal verification tools, or through software programming languages.

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