A QFN chip soldering method and soldering system

Abstract

The application discloses a QFN chip welding method, comprising the following steps: designing and manufacturing a soldering arrangement part with a corresponding leakage hole area on the QFN chip to be welded; covering the soldering arrangement part on the QFN chip in a position corresponding manner; arranging soldering tin on the QFN chip to be welded by using the leakage hole area; placing the QFN chip with arranged soldering tin on the PCB printed board in a position corresponding manner, so that the QFN chip to be welded is aligned with the corresponding part on the PCB printed board; heating the soldering tin, so that the QFN chip is welded on the set position on the PCB printed board. The method can reduce the difficulty of replacing the QFN chip, and improve the success rate of repair.

Description

Technical Field

[0001] This application generally relates to the field of military electronic module repair technology, and in particular to a QFN chip welding method and welding system. Background Technology

[0002] QFN (Quad Flat No-Leader) chips are generally used in military electronic modules, where they are soldered onto a PCB (Printed Circuit Board) along with other chips or devices. A QFN chip can only be soldered to corresponding locations on the PCB at designated points; other parts of the QFN chip cannot be soldered to the PCB, otherwise, the chip's functionality will be affected. In practical use, when a QFN chip malfunction is detected, the PCB needs to be reworked to replace the faulty chip. The existing method is as follows: first, the faulty QFN chip is removed from the PCB; then, a stencil with perforations corresponding to the designated solder placement positions on the QFN chip is placed over the corresponding locations on the PCB, and solder is initially applied through the perforations; finally, a functional QFN chip is soldered to the corresponding locations on the PCB using the solder points as described above. However, this method requires a high degree of precision in stencil placement. The area on the PCB where the QFN chip is removed is inevitably surrounded by other chips or components, creating unavoidable interference with the stencil placement. Therefore, ensuring precise stencil placement is difficult. Inaccurate stencil placement directly affects the connection between the designated area on the QFN chip and the corresponding area on the PCB, leading to repair failure. Therefore, reducing the difficulty of replacing QFN chips on the PCB and improving the success rate of QFN chip repair has become an urgent problem to be solved in this field. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a QFN chip soldering method and soldering system that can reduce the difficulty of replacing QFN chips and improve the success rate of rework.

[0004] The specific technical solution is as follows:

[0005] First aspect

[0006] This application provides a QFN chip soldering method, characterized by comprising the following steps:

[0007] Design and fabricate solder arrangement components with corresponding hole areas to be soldered on the QFN chip;

[0008] The solder arrangement is applied to the QFN chip in a corresponding manner;

[0009] Solder is applied to the solderable portion of the QFN chip using the via area;

[0010] Heating the solder causes it to form solder bumps;

[0011] The QFN chip with solder applied is placed on the PCB in a corresponding manner, so that the part of the QFN chip to be soldered is aligned with the corresponding part on the PCB.

[0012] The solder is heated so that the QFN chip is soldered to a predetermined position on the PCB printed circuit board.

[0013] As a further limitation of this application, the step of placing the QFN chip with solder applied onto the PCB in a positional manner includes the following steps beforehand:

[0014] The ends of the solder bumps arranged through the hole area are inserted into the solder pool containing liquid solder to increase the height of the solder bumps.

[0015] As a further limitation of this application, the heating of the solder specifically includes the following steps:

[0016] The soldered areas on the QFN chip are locally heated.

[0017] As a further limitation of this application, the solder arrangement is a stencil.

[0018] As a further limitation of this application, the thickness of the stencil is greater than or equal to a set thickness, which is the maximum height of the solder bump to avoid short circuits at other locations.

[0019] Second aspect

[0020] This application provides a QFN chip bonding system for implementing the QFN chip bonding method described above.

[0021] The beneficial effects of this application are:

[0022] This application designs and fabricates a solder arrangement component with corresponding via areas on the QFN chip to be soldered, and then places the solder arrangement component onto the QFN chip at corresponding positions. This allows solder to be applied to the areas on the QFN chip to be soldered through the via areas. This eliminates the need to place a stencil on a corresponding location on the PCB board surrounding other components, ensuring that solder is applied only to the areas on the QFN chip to be soldered, while other areas remain unsoldered. Therefore, this method significantly improves the convenience and accuracy of soldering. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0024] Figure 1 A flowchart illustrating the steps of the QFN chip soldering method provided in this application embodiment. Detailed Implementation

[0025] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] Example 1

[0028] Please refer to Figure 1 The QFN chip welding method provided in this embodiment includes the following steps:

[0029] S1: Design and fabricate a solder arrangement with a corresponding hole area to be soldered on the QFN chip;

[0030] S2: Cover the QFN chip with the solder arrangement components in a positional manner;

[0031] S3: Apply solder to the part of the QFN chip to be soldered using the hole area;

[0032] S4: Heat the solder to form solder bumps;

[0033] S5: Place the QFN chip with solder applied onto the PCB in a corresponding manner, so that the part of the QFN chip to be soldered is aligned with the corresponding part on the PCB.

[0034] S6: Heat the solder so that the QFN chip is soldered to a predetermined position on the PCB.

[0035] This application designs and fabricates a solder arrangement component with corresponding via areas on the QFN chip to be soldered, and then places the solder arrangement component onto the QFN chip at corresponding positions. This allows solder to be applied to the areas on the QFN chip to be soldered through the via areas. This eliminates the need to place a stencil on a corresponding location on the PCB board surrounding other components, ensuring that solder is applied only to the areas on the QFN chip to be soldered, while other areas remain unsoldered. Therefore, this method significantly improves the convenience and accuracy of soldering.

[0036] In a preferred embodiment that further improves the success rate of QFN chip soldering, the step of placing the QFN chip with solder applied onto the PCB in a corresponding manner includes the following steps beforehand:

[0037] The ends of the solder bumps arranged through the hole area are inserted into the solder pool containing liquid solder to increase the height of the solder bumps.

[0038] By following the above steps, soldering on other parts of the QFN chip can be avoided, preventing unnecessary short circuits with corresponding parts on the PCB and thus affecting the QFN chip's functionality. Therefore, this solution further improves the QFN chip soldering success rate.

[0039] In a preferred embodiment that further improves the success rate of QFN chip soldering, heating the solder specifically includes the following steps:

[0040] The soldered areas on the QFN chip are locally heated.

[0041] This solution prevents other parts of the QFN chip from being overheated and causing functional damage. Furthermore, it prevents overheated solder from flowing and causing unnecessary short circuits between the QFN chip and the PCB, thus preventing functional damage. Therefore, this solution further improves the QFN chip soldering success rate.

[0042] The solder arrangement is a steel mesh.

[0043] The thickness of the steel mesh is greater than or equal to a set thickness, which is the maximum height of the solder bump to avoid short circuits at other locations.

[0044] The specific implementation methods for the above methods are as follows:

[0045] 1. QFN Device Solder Pre-applied Process: Design and fabricate a stencil with corresponding openings that match the pad layout of the device requiring repair. The stencil is made of 0.12mm thick steel sheet. Place the device with its bottom side facing up, aligning it with the stencil openings, and apply solder paste to the device pads. Remove the device with the pre-applied solder paste and place it face down on a high-temperature reflow soldering tray. Send the device into the reflow oven and use a standard reflow soldering procedure to melt the solder on the bottom pads of the device, forming a QFN packaged device with "bumps".

[0046] 2. Applying solder paste to QFN packaged devices with "bumps": Create a 0.1mm thick solder paste "sweat pool". Vertically place the QFN packaged device with "bumps" into the solder pool. The bumps will pick up some solder paste while the bottom of the package will not touch the solder paste.

[0047] 3. Component mounting and soldering: Using a rework station, QFN packaged components with "bumps" after being dipped in solder paste are mounted to the designated positions on the rework printed circuit board, and localized heating rework soldering is performed to achieve the rework of QFN components on the printed circuit board.

[0048] The advantage of this invention is that, through this method, for QFN type devices that are difficult to rework due to the dense components around them, the amount of solder is precisely controlled by printing solder paste on the pads at the bottom of the device. At the same time, the solder paste is applied, which ensures the quality of the rework and greatly reduces the difficulty of rework, and significantly improves the success rate and reliability of rework.

[0049] Example 2

[0050] This embodiment provides a soldering system for soldering a replaced QFN chip to a PCB printed circuit board with other components, which is used to implement the QFN chip soldering method described above.

[0051] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A QFN chip soldering method, characterized in that, Includes the following steps: Design and fabricate solder arrangement components with corresponding hole areas to be soldered on the QFN chip; The solder arrangement is applied to the QFN chip in a corresponding manner; the solder arrangement is a stencil with a thickness of 0.12mm. Solder is applied to the solderable portion of the QFN chip using the via area; Heating the solder causes it to form solder bumps; The QFN chip with solder applied is placed on the PCB according to its position, so that the part to be soldered on the QFN chip is aligned with the corresponding part on the PCB. The solder is heated so that the QFN chip is soldered to a predetermined position on the PCB; before placing the QFN chip with solder on it onto the PCB in a corresponding manner, the following steps are also included: The ends of the solder bumps arranged through the hole area are inserted into the solder pool containing liquid solder to increase the height of the solder bumps. The thickness of the solder pool is 0.1 mm.

2. The QFN chip soldering method according to claim 1, characterized in that, The heating of the solder specifically includes the following steps: The soldered areas on the QFN chip are locally heated.

3. The QFN chip soldering method according to claim 1, characterized in that, The thickness of the steel mesh is greater than or equal to a set thickness, which is the maximum height of the solder bump to avoid short circuits at other locations.

4. A QFN chip bonding system, characterized in that, Used to implement the QFN chip soldering method as described in any one of claims 1-3.

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