Linear voltage regulator circuit

Abstract

The application discloses a linear voltage regulator circuit, comprising: a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node; a voltage regulation loop configured to sense a voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node, such that an output voltage at the output node is regulated; and a current regulation loop configured to sense a load current flowing through the power transistor and modulate the control signal to cause the power transistor to output a constant current to the output node; wherein the linear voltage regulator circuit is configured to turn on one of the voltage regulation loop or the current regulation loop based on a comparison result of the load current and a target value, so that when the output load increases to heavy load or even overload, the sub-pole inside the LDO can be changed to the main pole through loop switching, and the stability problem of the LDO loop is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of linear regulator technology, and more specifically, to a linear voltage regulator circuit. Background Technology

[0002] In modern electronic products, chips have become indispensable core components. Especially with the increasingly advanced integrated circuit manufacturing processes and the human desire to integrate more complex functions within the limited chip area, a type of small system chip called a System-on-Chip (SOC) has emerged. This type of SOC chip typically includes a microprocessor (MCU), analog IP cores, digital IP cores, embedded memory modules, external communication interface modules, and power management modules. In actual chip design, SOC chips often use devices with different voltage ratings (such as 1V, 1.5V, 1.8V, 3.3V, 5V, etc.) to achieve the desired balance between area, speed, and power consumption, requiring corresponding power supply voltages.

[0003] Portable electronic products mostly use lithium batteries as their external power source. The voltage range of lithium batteries is 2.6V to 3.6V, which obviously cannot directly power low-voltage modules. Therefore, different power supply voltages need to be designed inside the SOC chip to power the relevant modules. Low dropout regulators (LDOs) are often used for on-chip power management of mobile consumer electronic device chips because of their simple structure, low static power consumption, and low output voltage ripple.

[0004] Figure 1 A schematic circuit diagram of a conventional linear voltage regulator circuit is shown. (For example...) Figure 1 As shown, the linear regulator 100 includes a reference voltage module BGR, an error amplifier EA, a power transistor MP, voltage divider resistors R1 and R2, and a compensation capacitor C1. To improve loop stability, traditional LDOs typically require an external capacitor at the output, leading to reduced chip integration (more PAD pins) and increased peripheral costs. However, LDOs without external capacitors suffer from poor transient response and loop instability due to reduced capacitance, causing undershoot or overshoot at the LDO output when transitioning from light load to heavy load or even experiencing overcurrent. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a linear regulator circuit with current foldback current limiting and adaptive switching of the main pole, which can ensure loop stability and limit load current without the need for internal compensation capacitors.

[0006] According to an embodiment of the present invention, a linear regulator circuit is provided, comprising: a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node; a voltage regulation loop configured to sense the voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node, thereby regulating the output voltage at the output node; and a current regulation loop configured to sense a load current flowing through the power transistor and modulate the control signal to cause the power transistor to output a constant current to the output node; wherein the linear regulator circuit is configured to activate either the voltage regulation loop or the current regulation loop based on a comparison result of the load current and a target value.

[0007] Optionally, the linear regulator circuit is configured to: activate the voltage regulation loop and deactivate the current regulation loop when the load current does not reach the target value; and activate the current regulation loop and deactivate the voltage regulation loop when the load current reaches the target value.

[0008] Optionally, the current regulation loop is a current limiting circuit with current foldback function.

[0009] Optionally, the voltage regulation loop includes: a differential input circuit having a first input configured to receive a feedback voltage at the output node and a second input configured to receive a reference voltage; and a first gain amplifier circuit having an input coupled to the output of the differential input circuit and an output configured to generate the control signal for application to the control terminal of the power transistor.

[0010] Optionally, the voltage regulation loop further includes: a first bias circuit coupled between the first-stage power supply voltage and ground potential, configured to provide a first bias current to the differential input circuit; and a feedback resistor network coupled between the output node and ground potential, configured to provide the feedback voltage to the differential input circuit.

[0011] Optionally, the differential input circuit also has a power supply terminal configured to receive a first-stage power supply voltage and a ground terminal coupled to ground potential.

[0012] Optionally, the first gain amplifier circuit further includes a power supply terminal configured to receive a second-stage power supply voltage and a ground terminal coupled to ground potential.

[0013] Optionally, the first bias circuit includes: a current source having a first terminal coupled to a first-stage power supply voltage; a first resistor having a first terminal coupled to a second terminal of the current source; a third transistor having a first terminal coupled to the second terminal of the first resistor, and a control terminal coupled to the first terminal of the first resistor to receive a first bias voltage; a fourth transistor having a control terminal coupled to the control terminal of the third transistor; a first transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal coupled to the second terminal of the first resistor to receive a second bias voltage, and a second terminal coupled to ground potential; a second transistor having a first terminal coupled to the second terminal of the fourth transistor, a control terminal coupled to the control terminal of the first transistor, and a second terminal coupled to ground potential; and a fifth transistor having a first terminal coupled to the first-stage power supply voltage, and a control terminal and a second terminal coupled to the first terminal of the fourth transistor.

[0014] Optionally, the differential input circuit includes: a sixth transistor having a first terminal coupled to the first-stage power supply voltage and a control terminal coupled to the control terminal of the fifth transistor; a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor and a control terminal coupled to the reference voltage; an eighth transistor having a first terminal coupled to the second terminal of the sixth transistor and a control terminal coupled to the feedback voltage; a ninth transistor having a first terminal coupled to the second terminal of the seventh transistor and a control terminal, and a second terminal coupled to ground potential; and a tenth transistor having a first terminal coupled to the second terminal of the eighth transistor, with the intermediate tap node of both serving as the output of the differential input circuit, a control terminal coupled to the control terminal of the ninth transistor, and a second terminal coupled to ground potential.

[0015] Optionally, the current regulation loop includes: a current sensing circuit configured to sense the load current to obtain a sensed current; a current comparison circuit configured to compare the sensed current with a preset reference current to generate a current limiting control signal; and a second gain amplifier circuit having an input configured to receive the current limiting control signal and an output configured to generate the control signal for application to the control terminal of the power transistor.

[0016] Optionally, the voltage regulation loop and the current regulation loop share a single gain amplifier circuit.

[0017] Optionally, the gain amplifier circuit includes: a thirteenth transistor having a first terminal coupled to a second-stage power supply voltage, and a control terminal and a second terminal coupled to a control terminal of the power transistor; a third resistor having a first terminal coupled to the thirteenth transistor; a twelfth transistor having a first terminal coupled to the second terminal of the third resistor, and a second terminal coupled to ground potential; and a second resistor having a first terminal coupled to the output of the differential input circuit, and a second terminal coupled to the twelfth transistor.

[0018] Optionally, the current regulation loop further includes: a feedback control circuit having a first terminal coupled to the output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limiting control signal, wherein the feedback control circuit is configured to be controlled by the current limiting control signal to conduct the current path of the output of the differential input circuit to ground, so as to shut down the voltage regulation loop.

[0019] Optionally, the major pole of the linear regulator circuit is located at the output node, and the minor pole is located at the output of the differential input circuit, wherein the frequency at the minor pole is set by the feedback control circuit.

[0020] Optionally, the feedback control circuit includes an eleventh transistor having a first terminal coupled to the output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limiting control signal.

[0021] Optionally, the current regulation loop further includes: a second bias circuit coupled between the output node and ground potential, configured to provide a second bias current to the current comparison circuit, the current comparison circuit determining the magnitude of the reference current based on the second bias current.

[0022] Optionally, the current sensing circuit includes: a fourteenth transistor having a first terminal coupled to a second-stage power supply voltage, a control terminal coupled to a control terminal of the power transistor, and a second terminal configured to supply the sensed current.

[0023] Optionally, the current comparison circuit includes: a nineteenth transistor having a first terminal coupled to a second terminal of the fourteenth transistor and a control terminal coupled to the second bias circuit; a twentieth transistor having a first terminal coupled to the second terminal of the nineteenth transistor and a control terminal, and a second terminal coupled to the ground potential; a twenty-first transistor having a first terminal coupled to the control terminal of the twentieth transistor and a second terminal coupled to the ground potential; an eighteenth transistor having a first terminal coupled to the output node and a control terminal coupled to the second bias circuit; a twenty-third transistor having a first terminal coupled to the second terminal of the eighteenth transistor and a control terminal, and the control terminal of the twenty-third transistor is also coupled to the control terminal of the twenty-first transistor; and a twenty-second transistor having a first terminal coupled to the control terminal of the twenty-third transistor, a control terminal coupled to the control terminal of the twentieth transistor, and a second terminal coupled to the ground potential, wherein the eighteenth transistor is configured to generate the reference current, and the intermediate tap node of the nineteenth and twentieth transistors is configured to provide the current limiting control signal.

[0024] Optionally, the second bias circuit includes: a seventeenth transistor having a first terminal coupled to the output node, and a control terminal and a second terminal coupled to the control terminals of the eighteenth and nineteenth transistors; a sixteenth transistor having a first terminal coupled to the second terminal of the seventeenth transistor, and a control terminal configured to receive a first bias voltage; and a fifteenth transistor having a first terminal coupled to the second terminal of the sixteenth transistor, a control terminal configured to receive a second bias voltage, and a second terminal coupled to the ground potential.

[0025] Optionally, the current comparison circuit further includes: a fourth resistor coupled between the second terminal of the fourteenth transistor and the first terminal of the nineteenth transistor; and a diode coupled between the first terminal of the nineteenth transistor and the ground potential.

[0026] In summary, this invention provides a linear regulator circuit with current foldback limiting and adaptive switching of the dominant pole. It eliminates the need for internal compensation capacitors and, unlike existing structures without external capacitors, places the dominant pole at the output node of the LDO. When the output load is low to medium, the output node acting as the dominant pole ensures system loop stability and a stable output signal. As the output load increases to heavy or even overload conditions, the linear regulator circuit switches loop control to a current regulation loop and biases the voltage regulation loop. This loop switching transforms the secondary pole within the LDO into the dominant pole, effectively improving the stability of the LDO loop. Simultaneously, it limits the load current to a certain range, effectively reducing the damage to the circuit from large currents under overload conditions, resulting in higher circuit stability. Attached Figure Description

[0027] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0028] Figure 1 A schematic circuit diagram of a conventional linear voltage regulator circuit is shown.

[0029] Figure 2 A schematic block diagram of a linear regulator circuit according to an embodiment of the present invention is shown;

[0030] Figure 3 A schematic circuit diagram of a linear regulator circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0031] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0032] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0033] In this application, the power transistor is a transistor operating in linear mode to provide a current path, including a type selected from bipolar transistors or field-effect transistors. The input and output terminals of the power transistor are respectively the high-potential and low-potential ends on the current path, and the control terminal is used to receive a drive signal to control the voltage drop of the power transistor. The power transistor can be a PMOS (N-Metal-Oxide-Semiconductor) transistor or an NMOS (N-Metal-Oxide-Semiconductor) transistor. The first terminal, second terminal, and control terminal of the PMOS transistor are the source, drain, and gate, respectively; the first terminal, second terminal, and control terminal of the NMOS transistor are the drain, source, and gate, respectively.

[0034] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0035] refer to Figure 2 , Figure 2 A schematic block diagram of a linear regulator circuit according to an embodiment of the present invention is shown. The linear regulator circuit 200 is configured to support operation in one condition (e.g., under light load) to enable a voltage regulation loop 210 to regulate the voltage delivery at the load, and to support operation in another condition (e.g., under output overload) to enable a current regulation loop to regulate the current delivery to the load. A power transistor MP has a source-drain current path coupled between a second-stage supply voltage AVCC and an output voltage Vout node, and is configured to provide current to the output node. Specifically, the power transistor MP is implemented as a PMOS transistor, with its drain coupled to the second-stage supply voltage AVCC and its source coupled to the output voltage Vout node. The gate terminal of the power transistor MP is configured to receive a control signal PG, which serves as the gate voltage of the power transistor MP and controls the current flowing through the power transistor MP.

[0036] Voltage regulation loop 210 is configured to sense the voltage at the output voltage Vout node and modulate the control signal PG such that the power transistor MP delivers current to the output voltage Vout node to regulate the output voltage Vout to a level where the feedback voltage Vfb is substantially equal to the reference voltage Vref. Specifically, voltage regulation loop 210 uses a feedback resistor network 214 coupled to the output voltage Vout node to sense the output voltage Vout at the load. The feedback resistor network 214 is formed, for example, by multiple resistors connected in series, and generates the feedback voltage Vfb at the tap nodes of the resistors.

[0037] Specifically, the voltage regulation loop 210 further includes a first bias circuit 211, a differential input circuit 212, and a gain amplifier circuit 213. The first bias circuit 211 is coupled between the first-stage power supply voltage VINT and ground potential VSS, and is configured to provide a first bias current to the differential input circuit 212. The differential input circuit 212 has a first input configured to receive a feedback voltage Vfb at the output node and a second input configured to receive a reference voltage Vref. The reference voltage Vref is a bandgap reference from within the chip and is approximately independent of temperature and power supply voltage variations. The gain amplifier circuit 213 has an input coupled to the output of the differential input circuit 212 and an output configured to generate a control signal PG for application to the gate of the power transistor MP. Among them, the differential input circuit 212 constitutes the first stage of the traditional error amplifier, which is composed of differential input pairs and current mirror loads, and completes the conversion from dual-ended input to single-ended output; the gain amplifier circuit 213 constitutes the second stage of the traditional error amplifier, which can provide high gain for the output. At the same time, the poles contained in the second stage circuit are all high-frequency poles, which is beneficial to the stable output of the LDO circuit.

[0038] In one embodiment of the present invention, the error amplifier provided in the embodiment of the present invention can be an OTA (operational transconductance amplifier), and the present invention does not impose specific limitations on it.

[0039] Furthermore, the linear regulator circuit 200 of this embodiment has a dual power rail structure. The differential input circuit 212 also has a power supply terminal configured to receive the first-stage power supply voltage VINT and a ground terminal coupled to ground potential VSS. The gain amplifier circuit 213 also has a power supply terminal configured to receive the second-stage power supply voltage AVCC and a ground terminal coupled to ground potential VSS. The second-stage power supply voltage AVCC is higher than the first-stage power supply voltage VINT. By adopting a dual power rail structure, the linear regulator circuit 200 of this embodiment can improve both efficiency and PSR (Power Supply Rejection).

[0040] The current regulation loop 220 is configured to sense the load current flowing through the power transistor MP and modulate the control signal PG so that the power transistor MP can output a constant current to the load. The current regulation loop 220 includes a current sensing circuit 221, a current comparison circuit 222, a gain amplifier circuit 213, a feedback control circuit 223, and a second bias circuit 224. The current sensing circuit 221 is configured to sense the load current flowing through the power transistor MP to obtain a sensed current Is. The current comparison circuit 222 is configured to compare the sensed current Is with a preset reference current, determine whether the load current has reached an overcurrent threshold based on the comparison result, and generate a current limiting control signal SG. The magnitude of the reference current is determined based on a second bias current provided by the second bias circuit 224. The feedback control circuit 223 is coupled between the output of the differential input circuit 212 and the ground potential VSS, and is configured to be controlled by the current limiting control signal SG to conduct the current path from the output of the differential input circuit to ground, thereby turning off the voltage regulation loop 210. At the same time, the feedback control circuit 223 pulls down the potential at the input terminal of the gain amplifier circuit 213, and then pulls up the gate voltage of the power transistor MP through the gain amplifier circuit 213. The current regulation loop 220 thus modulates the gate voltage of the gate terminal of the power transistor MP, so that the power transistor MP outputs a limited constant current to the output node.

[0041] The operation of the linear regulator circuit 200 of this invention is as follows: Assuming the output voltage Vout is at a level where the feedback voltage Vfb is much smaller than the reference voltage Vref, and the load current is far below the overcurrent threshold, this current is sensed by the current sensing circuit 221. At this time, the current regulation loop 220 is closed, and the voltage regulation loop 210 is open, with the voltage regulation loop 210 dominating the LDO output. The voltage regulation loop 210 controls the power transistor MP by modulating the control signal PG to increase the amplitude of the current delivered to the load. When the load current increases to the point that the sensed current exceeds the reference current, the current comparison circuit 222 in the current regulation loop 220 triggers the feedback control circuit 223 to open. The feedback control circuit 223 pulls down the output of the differential input circuit 212 in the voltage regulation loop 210, causing the differential input circuit 212 in the voltage regulation loop 210 to stop working, thus closing the voltage regulation loop 210, and allowing the current regulation loop 220 to dominate the LDO output.

[0042] In some embodiments, the current regulation loop 220 is a current-limiting circuit with current foldback function, which allows the LDO output to experience brief overload without immediately switching to current-limiting modulation mode, thus maximizing the system's rapid response to load changes. Furthermore, after an overcurrent occurs, the current regulation loop 220 will not exit modulation until the load current decreases to a lower value, after which the voltage regulation loop 210 will modulate the output voltage.

[0043] In this embodiment, the dominant pole of the linear regulator circuit 200 is located at the output node (i.e., Figure 1 The secondary pole is located at point C in the voltage regulation loop 210, while the secondary pole is located at the output of the differential input circuit 212 (i.e., point C in the voltage regulation loop 210). Figure 1 (Point A in the diagram). When the output load of the circuit is low to medium, the frequency of the dominant pole C is at a low frequency, and the secondary pole A is outside the GBW (gain-bandwidth product). Therefore, the voltage regulation loop 210 of this LDO, as a single-pole system, can ensure loop stability. As the output load gradually increases, the frequency of the dominant pole C is pushed to a higher frequency as the load resistance decreases. At this time, the frequency of the secondary pole A will be less than the loop bandwidth of the entire linear regulator circuit, making the signal output by the output node unstable. When the load current triggers an overcurrent, the linear regulator circuit 200 provided in this embodiment of the invention switches to loop control via the current regulation loop 220. The feedback control circuit 223 draws away the current output of the differential input circuit 212, causing the current mirror load in the differential input circuit 212 to enter the cutoff region. This transforms the secondary pole A into a low-impedance node, increases the frequency of the secondary pole A, and causes the original dominant pole C to leave the loop. The original secondary pole A then becomes the dominant pole of the current loop, ensuring a good phase margin. As a result, the system still has good transient characteristics and outputs a stable signal even under heavy load or overload.

[0044] Figure 3 A schematic circuit diagram of a linear voltage regulator circuit according to an embodiment of the present invention is shown. Figure 3As shown, the first bias circuit 211 includes a current source Ib, a resistor R1, NMOS transistors M1 to M4, and a PMOS transistor M5. The first terminal of the current source Ib is coupled to the first-stage power supply voltage VINT, and the second terminal is coupled to the first terminal of resistor R1. The second terminal of resistor R1 is coupled to the drain of NMOS transistor M3. The first terminal of resistor R1 is configured to provide a first bias voltage Vcn, and the second terminal is configured to provide a second bias voltage Vbn. The gates of NMOS transistors M3 and M4 are both coupled to the first terminal of resistor R1 to receive the first bias voltage Vcn, and the gates of NMOS transistors M1 and M2 are both coupled to the second terminal of resistor R1 to receive the second bias voltage Vbn. The drain of NMOS transistor M1 is coupled to the source of NMOS transistor M3, and the source is coupled to ground potential VSS. The drain of NMOS transistor M2 is coupled to the source of NMOS transistor M4, and the source is coupled to ground potential VSS. PMOS transistor M5 is connected as a diode, with its drain coupled to the first-stage power supply voltage VINT, and its gate and drain coupled to the drain of NMOS transistor M4. PMOS transistor M5 provides bias current to differential input circuit 212 in a mirror manner.

[0045] The differential input circuit 212 is a standard five-transistor operational amplifier, including PMOS transistors M6-M8 and NMOS transistors M9 and M10. PMOS transistor M6 serves as the tail current source, PMOS transistors M7 and M8 form the differential input pair, and NMOS transistors M9 and M10 are connected in a current mirror structure as the active load of the current mirror. Specifically, the source of PMOS transistor M6 is coupled to the first-stage power supply voltage VINT, its gate is coupled to the gate of PMOS transistor M5 to form a current mirror structure, and its drain is coupled to the sources of PMOS transistors M7 and M8. The gate of PMOS transistor M7 is configured as the first input of the differential input circuit 212 to receive the reference voltage Vref, and the gate of PMOS transistor M8 is configured as the second input of the differential input circuit 212 to receive the feedback voltage Vfb. The sources of NMOS transistors M9 and M10 are both coupled to ground potential VSS, and their gates are coupled to the drain of NMOS transistor M9. The drain of NMOS transistor M9 is also coupled to the drain of PMOS transistor M7, and the drain of NMOS transistor M10 is coupled to the drain of PMOS transistor M8. The common node of the two transistors serves as the output of the differential input circuit 212.

[0046] The gain amplifier circuit 213 includes resistors R2 and R3, an NMOS transistor M12, and a PMOS transistor M13. The PMOS transistor M13 is diode-connected, with its source coupled to the second-stage power supply voltage AVCC, and its gate and drain coupled to the gate of the power transistor MP. The first terminal of resistor R3 is coupled to the drain of the PMOS transistor M13, and the second terminal is coupled to the drain of the NMOS transistor M12. The source of the NMOS transistor M12 is coupled to ground potential VSS. The first terminal of resistor R2 is coupled to the output of the differential input circuit 212, and the second terminal is coupled to the gate of the NMOS transistor M12. The NMOS transistor M12 forms a source follower structure, and the PMOS transistor M13 forms a PMOS active load. Resistors R2 and R3 are used to protect the NMOS transistor M12 from damage by high voltage. In this embodiment, the gain amplifier circuit 213 can convert the output of the differential input circuit 212 from low voltage to high voltage, while simultaneously increasing the parasitic pole of the power transistor gate, reducing the impact of the power transistor gate pole on loop stability, and contributing to the stable output of the LDO circuit.

[0047] The feedback resistor network 214 includes resistors R5 to R7. Resistors R7, R6 and R5 are coupled sequentially between the output pole of the LDO and the ground potential VSS. The intermediate tap node of resistors R5 and R6 is used to provide the feedback voltage Vfb.

[0048] The current sensing circuit 221 includes a PMOS transistor M14. The source of PMOS transistor M14 and the source of power transistor MP are both coupled to the second-stage power supply voltage AVCC. The gate of PMOS transistor M14 is coupled to the gate of power transistor MP, and the drain is configured to provide the sensing current Is. The load current is equal to the sum of the current flowing through sampling transistor M14 and the current flowing through power transistor MP. Since the current of sampling transistor M14 is very small and can be ignored, the load current is approximately equal to the current flowing through power transistor MP. Sampling transistor M14 is used to sample the current flowing through power transistor MP, that is, to sample the load current. The aspect ratio of sampling transistor M14 has a fixed proportional relationship with that of power transistor MP. For example, when the load current is 1A, the sensing current Is is 1μA.

[0049] The second bias circuit 224 includes a PMOS transistor M17 and NMOS transistors M15 and M16. PMOS transistor M17 is a diode structure, with its source coupled to the output node of the circuit, and its gate and drain coupled to the drain of NMOS transistor M16. The gate of NMOS transistor M16 is configured to receive a first bias voltage Vcn, and its source is coupled to the drain of NMOS transistor M15. The gate of NMOS transistor M15 is configured to receive a second bias voltage Vbn, and its source is coupled to ground potential VSS. PMOS transistor M17 provides a second bias current of a certain value to the current comparison circuit 222 in a mirror manner. The current comparison circuit 222 determines the magnitude of the reference current based on the second bias current.

[0050] The current comparison circuit 222 includes PMOS transistors M18 and M19, and NMOS transistors M20 to M23. The source of PMOS transistor M19 is configured to receive the sensed current Is, and its gate is coupled to the gate of PMOS transistor M17. The source of PMOS transistor M18 is coupled to the source of PMOS transistor M17, and its gate is coupled to the gate and drain of PMOS transistor M17, forming a current mirror structure with PMOS transistor M17. The second bias current is obtained through the mirrored current. Both NMOS transistors M20 and M23 are diode-connected. The gate and drain of NMOS transistor M20 are coupled to the drain of PMOS transistor M19, and the common node between PMOS transistor M19 and NMOS transistor M20 is used to provide the current limiting control signal SG. The source is coupled to ground potential VSS. The gate and drain of NMOS transistor M23 are coupled to the drain of PMOS transistor M18, and the source is coupled to ground potential VSS. The drain of NMOS transistor M21 is coupled to the gate and drain of NMOS transistor M20, the gate is coupled to the gate and drain of NMOS transistor M23, and the source is coupled to ground potential VSS. The drain of NMOS transistor M22 is coupled to the gate and drain of NMOS transistor M23, the gate is coupled to the gate and drain of NMOS transistor M20, and the source is coupled to ground potential VSS.

[0051] Furthermore, the linear regulator circuit 200 of this embodiment also includes a resistor R4 and a diode D1, wherein the resistor R4 is coupled between the drain of the PMOS transistor M14 and the source of the PMOS transistor M19. The diode D1 is a clamping diode, whose anode is coupled to ground potential VSS and whose cathode is coupled to the source of the PMOS transistor M19, to protect the PMOS transistor M19 from damage by high voltage.

[0052] In the above embodiments, diode connection refers to the case where the gate and drain of a MOSFET are directly coupled together.

[0053] In some embodiments, the thresholds for triggering overcurrent and overcurrent recovery of the linear regulator circuit 200 are adjusted by the size ratio of NMOS transistors M20 to M23 in the current comparison circuit 222. For example, assuming the size ratio of NMOS transistors M20 to M23 is: M20:M21:M22:M23 = 20:10:1:2, when the output load is a low to medium load, the sensed current Is is very small. At this time, almost no current flows through NMOS transistors M20 and M22, and all the current flows through NMOS transistors M21 and M23. Therefore, the current limiting control signal SG is pulled low, which in turn pulls the gate of NMOS transistor M11 low and turns it off. The entire circuit is dominated by the voltage regulation loop 210 to control the output of the LDO. When the output load is heavy or even overloaded, the sensed current Is increases significantly, exceeding five times the current reflected in the PMOS transistor M18. Because NMOS transistor M21 cannot fully absorb the sensed current Is, NMOS transistor M20 is turned on, and NMOS transistor M22 shunts the current originally flowing through NMOS transistor M23 via its mirror. Since NMOS transistor M21 forms a current mirror structure with NMOS transistor M23, the current flowing through it continues to decrease. This causes the current-limiting control signal SG to be pulled high through a positive feedback loop, which in turn pulls the gate of NMOS transistor M11 high and turns it on. At this time, voltage regulation loop 210 is turned off, and current regulation loop 220 dominates the LDO output. Similarly, when the sensed current Is is lower than 1 / 20 of the current reflected in the PMOS transistor M18, the circuit exits the current-limiting modulation mode, and voltage regulation loop 210 once again dominates the LDO output.

[0054] Accordingly, embodiments of the present invention also provide an electronic device, the electronic device including the linear regulator circuit 200 provided in any of the above embodiments.

[0055] In one embodiment of the present invention, the electronic device provided by the present invention can be a portable electronic device such as a cellular phone.

[0056] In summary, this invention provides a linear regulator circuit with current foldback limiting and adaptive switching of the dominant pole. It eliminates the need for internal compensation capacitors and, unlike existing structures without external capacitors, places the dominant pole at the output node of the LDO. When the output load is low to medium, the output node acting as the dominant pole ensures system loop stability and a stable output signal. As the output load increases to heavy or even overload conditions, the linear regulator circuit switches loop control to a current regulation loop and biases the voltage regulation loop. This loop switching transforms the secondary pole within the LDO into the dominant pole, effectively improving the stability of the LDO loop. Simultaneously, it limits the load current to a certain range, effectively reducing the damage to the circuit from large currents under overload conditions, resulting in higher circuit stability.

[0057] It should be noted that relational terms such as "first" and "second" used herein are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A linear voltage regulator circuit, comprising: A power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node; A voltage regulation loop is configured to sense the voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node, thereby regulating the output voltage at the output node; as well as A current regulation loop is configured to sense the load current flowing through the power transistor and modulate the control signal so that the power transistor outputs a constant current to the output node; The linear regulator circuit is configured to activate either the voltage regulation loop or the current regulation loop based on a comparison between the load current and the target value. The voltage regulation loop includes: A differential input circuit has a first input configured to receive a feedback voltage at the output node and a second input configured to receive a reference voltage; and A gain amplifier circuit having an input coupled to the output of the differential input circuit and an output configured to generate a control signal for application to the control terminal of the power transistor. The current regulation loop includes: A current sensing circuit is configured to sense the load current to obtain a sensed current; A current comparison circuit is configured to compare the sensed current with a preset reference current to generate a current-limiting control signal; and The feedback control circuit has a first terminal coupled to the output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limiting control signal. The feedback control circuit is configured to be controlled by the current limiting control signal to turn on the current path from the output of the differential input circuit to ground, thereby shutting down the voltage regulation loop. The primary pole of the linear regulator circuit is located at the output node, and the secondary pole is located at the output of the differential input circuit. The feedback control circuit is used to increase the frequency of the secondary pole when the voltage regulation loop is closed.

2. The linear regulator circuit according to claim 1, wherein, The linear regulator circuit is configured to: activate the voltage regulation loop and deactivate the current regulation loop when the load current does not reach the target value; and activate the current regulation loop and deactivate the voltage regulation loop when the load current reaches the target value.

3. The linear regulator circuit according to claim 1, wherein, The current regulation loop is a current limiting circuit with current foldback function.

4. The linear regulator circuit according to claim 1, wherein, The voltage regulation loop further includes: A first bias circuit, coupled between the first-stage power supply voltage and ground potential, is configured to provide a first bias current to the differential input circuit; and A feedback resistor network, coupled between the output node and ground potential, is configured to provide the feedback voltage to the differential input circuit.

5. The linear regulator circuit according to claim 1, wherein, The differential input circuit also has a power supply terminal configured to receive a first-stage power supply voltage and a ground terminal coupled to ground potential.

6. The linear regulator circuit according to claim 1, wherein, The gain amplifier circuit also has a power supply terminal configured to receive a second-stage power supply voltage and a ground terminal coupled to ground potential.

7. The linear regulator circuit according to claim 4, wherein, The first bias circuit includes: A current source having a first terminal coupled to a first-stage power supply voltage; A first resistor having a first terminal coupled to a second terminal of the current source; The third transistor has a first terminal coupled to the second terminal of the first resistor and a control terminal coupled to the first terminal of the first resistor to receive a first bias voltage. A fourth transistor having a control terminal coupled to the control terminal of the third transistor; The first transistor has a first terminal coupled to the second terminal of the third transistor, a control terminal coupled to the second terminal of the first resistor to receive a second bias voltage, and a second terminal coupled to ground potential; The second transistor has a first terminal coupled to a second terminal of the fourth transistor, a control terminal coupled to a control terminal of the first transistor, and a second terminal coupled to ground potential; and The fifth transistor has a first terminal coupled to the first stage power supply voltage, and a control terminal and a second terminal coupled to the first terminal of the fourth transistor.

8. The linear regulator circuit according to claim 7, wherein, The differential input circuit includes: The sixth transistor has a first terminal coupled to the first stage power supply voltage and a control terminal coupled to the control terminal of the fifth transistor; A seventh transistor having a first terminal coupled to a second terminal of the sixth transistor, and a control terminal coupled to the reference voltage; The eighth transistor has a first terminal coupled to the second terminal of the sixth transistor, and a control terminal coupled to the feedback voltage; A ninth transistor having a first terminal and a control terminal coupled to a second terminal of the seventh transistor, and a second terminal coupled to ground potential; and The tenth transistor has a first terminal coupled to the second terminal of the eighth transistor, with the intermediate tap node of the two serving as the output of the differential input circuit, a control terminal coupled to the control terminal of the ninth transistor, and a second terminal coupled to the ground potential.

9. The linear regulator circuit according to claim 1, wherein, The gain amplifier circuit includes: The thirteenth transistor has a first terminal coupled to a second-stage power supply voltage, and a control terminal and a second terminal coupled to a control terminal of the power transistor; A third resistor has a first terminal coupled to the thirteenth transistor; The twelfth transistor has a first terminal coupled to the second terminal of the third resistor, and a second terminal coupled to ground potential; and The second resistor has a first terminal coupled to the output of the differential input circuit and a second terminal coupled to the twelfth transistor.

10. The linear regulator circuit according to claim 1, wherein, The feedback control circuit includes: The eleventh transistor has a first terminal coupled to the output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limiting control signal.

11. The linear regulator circuit according to claim 1, wherein, The current regulation loop also includes: A second bias circuit, coupled between the output node and ground potential, is configured to provide a second bias current to the current comparison circuit, which determines the magnitude of the reference current based on the second bias current.

12. The linear regulator circuit according to claim 11, wherein, The current sensing circuit includes: The fourteenth transistor has a first terminal coupled to a second-stage power supply voltage, a control terminal coupled to a control terminal of the power transistor, and a second terminal configured to supply the sensed current.

13. The linear regulator circuit according to claim 12, wherein, The current comparison circuit includes: The nineteenth transistor has a first terminal coupled to the second terminal of the fourteenth transistor, and a control terminal coupled to the second bias circuit; The twentieth transistor has a first terminal and a control terminal coupled to the second terminal of the nineteenth transistor, and a second terminal coupled to the ground potential; The 21st transistor has a first terminal coupled to the control terminal of the 20th transistor and a second terminal coupled to the ground potential; The eighteenth transistor has a first terminal coupled to the output node and a control terminal coupled to the second bias circuit; The twenty-third transistor has a first terminal coupled to the second terminal of the eighteenth transistor and a control terminal, and the control terminal of the twenty-third transistor is also coupled to the control terminal of the twenty-first transistor; and The twenty-second transistor has a first terminal coupled to the control terminal of the twenty-third transistor, a control terminal coupled to the control terminal of the twentyth transistor, and a second terminal coupled to the ground potential. The eighteenth transistor is configured to generate the reference current, and the intermediate tap nodes of the nineteenth and twentieth transistors are configured to provide the current limiting control signal.

14. The linear regulator circuit according to claim 13, wherein, The second bias circuit includes: The seventeenth transistor has a first terminal coupled to the output node, and a control terminal and a second terminal coupled to the control terminals of the eighteenth and nineteenth transistors; The sixteenth transistor has a first terminal coupled to the second terminal of the seventeenth transistor, and a control terminal configured to receive a first bias voltage; and The fifteenth transistor has a first terminal coupled to the second terminal of the sixteenth transistor, a control terminal configured to receive a second bias voltage, and a second terminal coupled to the ground potential.

15. The linear regulator circuit according to claim 14, wherein, The current comparison circuit further includes: A fourth resistor is coupled between the second terminal of the fourteenth transistor and the first terminal of the nineteenth transistor; and A diode is coupled between the first terminal of the nineteenth transistor and the ground potential.

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