A data interleaving method and apparatus

Abstract

The application discloses a data interleaving method and device, and relates to the field of optical fiber communication systems.The method comprises the following steps: dividing an input bit data stream into a plurality of first data blocks by taking 4 bits as a unit, exchanging 2 bits of data in the middle of each first data block; dividing the exchanged bit data stream into second data blocks by taking 512 bits as a unit, and performing intra-block interleaving; and performing inter-block interleaving on the bit data stream after the intra-block interleaving through two random access memories.The application guarantees the original probability distribution characteristics of the PCS technology, and improves the ability of correcting burst errors in the joint application of the FEC technology and the PCS technology.

Description

Technical Field

[0001] This application relates to the field of optical fiber communication systems, specifically to a data interleaving method and apparatus. Background Technology

[0002] With the rapid development of emerging businesses such as video conferencing, cloud computing, and the Internet of Things, the demand for fiber optic communication capacity is experiencing explosive growth. Fiber optic communication offers advantages such as high capacity, high speed, and resistance to electromagnetic interference, but it also presents some challenges, such as limited bandwidth of optoelectronic conversion devices, fiber dispersion, and nonlinear effects. Furthermore, signals are inevitably affected by noise sources during transmission, leading to signal degradation and bit errors, thus impacting overall system performance. These problems become increasingly severe as communication speeds continue to increase. Therefore, various technical solutions have been proposed to address these issues.

[0003] One technical approach is to utilize advanced Forward Error Correction (FEC) to improve the reliability of signal transmission. FEC calculates and generates checksum symbols based on the transmitted information sequence. These checksum symbols and information sequence symbols are mutually constrained by defined rules, and the checksum symbols are inserted into the transmitted information sequence according to a certain pattern to complete FEC encoding. When the encoded data is sent to the signal receiver through the modulator, channel, and demodulator, FEC decoding uses the checksum symbols in the transmitted data to determine whether the data content has been contaminated by noise sources, and locates and corrects errors. In this way, data can be transmitted with a low bit error rate.

[0004] In practical transmission channels, besides additive noise interference, burst interference is also very common. Burst interference often causes a large number of consecutive bit errors, exceeding the error correction capability of error-correcting codes and degrading communication quality. The solution to burst errors is to combine FEC coding with data interleaving. The principle of data interleaving is to shuffle the FEC-coded data stream according to rules before outputting it, making the previously adjacent data much farther apart (greater than the bit error length caused by burst interference). If the interleaved data encounters burst interference during channel transmission, a long string of consecutive data will inevitably be corrupted. After the data stream reaches the receiving end, the receiving end first deinterleaves it according to the same data interleaving rules as the sending end, restoring the data stream to its original order before interleaving after FEC coding at the sending end. Therefore, after deinterleaving, the consecutive data corrupted by burst interference in the data stream affected by channel interference are shuffled to a much greater distance, which is beneficial for FEC decoding and error correction at the receiving end. This is also an important reason why data interleaving technology is widely used today.

[0005] Another employed technique is constellation graph coding: Probabilistic Constellation Shaping (PCS). PCS includes geometric shaping and probabilistic shaping. Probabilistic shaping preserves the original uniform distribution of constellation points by adding redundancy, re-encoding and mapping the input, increasing the transmission probability of constellation points in the inner circle and decreasing the transmission probability of constellation points in the outer circle, thus making the input distribution tend towards a Gaussian distribution. Because PCS only changes the probability distribution of constellation points without altering their position and shape, it is more flexible in application and has a significant positive impact on improving system capacity and error rate performance.

[0006] Currently, coherent optical communication systems combine the aforementioned FEC and PCS technologies, which significantly improves the bit error rate and enhances system flexibility and reliability.

[0007] FEC is a technology that can correct random errors on a line, but its ability to correct burst errors is low. PCS technology also does not have the ability to correct burst errors. Therefore, a major drawback of the combined application of PCS and FEC technologies is that the ability to correct burst errors is very low. Summary of the Invention

[0008] This application provides a data interleaving method and apparatus to address the problem of low ability to correct sudden errors in related technologies.

[0009] Firstly, a data interleaving method is provided, including the following steps:

[0010] The input bit data stream is divided into multiple first data blocks in units of 4 bits, and the 2 bits of data in the middle of each first data block are swapped.

[0011] The swapped bit data stream is divided into second data blocks of 512 bits each, and then interleaved within each block.

[0012] The bit data stream after intra-block interleaving is inter-block interleaved through two random access memories.

[0013] In some embodiments, the inter-block interleaving includes:

[0014] Generate write addresses for two random access memories respectively;

[0015] Write the bit data stream after intra-block swapping to the first random access memory RAM0, and write the write address of RAM0 as data to the second random access memory RAM1;

[0016] After RAM0 completes the data writing, the read data from RAM1 is used as the read address of RAM0 to read data from RAM0 into the register array. The read data from RAM1 is then delayed and written as write data to RAM1.

[0017] In some embodiments, the register array is 42×512 in size, and each row of data is represented by reg[j][511:0], where j is an integer and 0≤j≤41;

[0018] The register array is divided into four blocks of equal width and depth. Starting from j=0, 8 bits of data are output from each block in each round, and the output order of data in each block is from back to front and from top to bottom, until j=20, completing one round of output. The next round continues to output data according to the rules of the previous round, until all data in the register array is output in 16 rounds.

[0019] In some embodiments, the width of RAM0 is 512 and the depth is 336, and the write address for RAM0 includes:

[0020] The write address for sequential numbers less than or equal to 15 is

[0021]

[0022] The write address for a sequence number greater than 15 is wr_addr i =wr_addr (i-16) +16, where wr_addr is the write address of RAM0, i is the sequential number, i is an integer and i≥0;

[0023] After a round of writing 512 bits of data, the read data from RAM1 is delayed and then used as the write address for RAM0.

[0024] In some embodiments, the RAM1 has a width of 9 and a depth of 672, and the read address of RAM1 is:

[0025] When the read address sequence number is less than or equal to 41, the read address is:

[0026]

[0027] When the read address sequence number is greater than 41, the read address is rd_addr. i =rd_addr (i-42) +2, where rd_addr is the read address of RAM1, i is the sequential number, i is an integer and i≥0.

[0028] In some embodiments, during the intra-block interleaving, the width of the interleaved matrix is ​​16 and the depth is 32, and the data in the matrix is ​​output row by row from top to bottom.

[0029] On the other hand, a data interleaving device is provided, comprising:

[0030] The bit-swapping module is used to divide the input bit data stream into multiple first data blocks in units of 4 bits, and swap the 2 bits of data in the middle of each first data block.

[0031] The intra-block interleaving module is used to divide the bit data stream after the bit switching module into second data blocks of 512 bits and perform intra-block interleaving.

[0032] The inter-block interleaving module is used to interleave the bit data streams that are interleaved within a block through two random access memories.

[0033] In some embodiments, the inter-block interleaving module includes a first random access memory (RAM0), a second random access memory (RAM1), a RAM0 write address generation unit, a RAM1 write address generation unit, a RAM1 read address generation unit, and a register array.

[0034] The RAM0 write address generation unit is used to generate the initial write address of RAM0, the RAM1 write address generation unit is used to generate the write address of RAM1, and the RAM1 read address generation unit is used to generate the read address of RAM1.

[0035] RAM0 is used to cache the bit data swapped within the block, and RAM1 is used to cache the write address corresponding to the data in RAM0;

[0036] The register array is used to store data read from RAM0. The read address of RAM0 is the read data of RAM1. The read data of RAM1 is delayed and then written to RAM1 as write data.

[0037] In some embodiments, the register array size is 42×512, and each row of data is represented by reg[j][511:0], where j is an integer and 0≤j≤41;

[0038] The register array is divided into four blocks of equal width and depth. Starting from j=0, 8 bits of data are output from each block in each round, and the output order of data in each block is from back to front and from top to bottom, until j=20, completing one round of output. The next round continues to output data according to the rules of the previous round, until all data in the register array is output in 16 rounds.

[0039] In some embodiments, the width of RAM0 is 512 and the depth is 336, and the write address for RAM0 includes:

[0040] The write address for sequential numbers less than or equal to 15 is

[0041]

[0042] The write address for a sequence number greater than 15 is wr_addr i =wr_addr (i-16) +16, where wr_addr is the write address of RAM0, i is the sequential number, i is an integer and i≥0;

[0043] After writing 512 bits of data in one round, the read data from RAM1 is delayed and then used as the write address for RAM0.

[0044] The RAM1 has a width of 9 and a depth of 672. The write address of RAM1 is a sequence that increments by 1 starting from 0. The read address of RAM1 is:

[0045] When the read address sequence number is less than or equal to 41, the read address is:

[0046]

[0047] When the read address sequence number is greater than 41, the read address is rd_addr. i =rd_addr (i-42) +2, where rd_addr is the read address of RAM1, i is the sequential number, i is an integer and i≥0.

[0048] The beneficial effects of the technical solution provided in this application include:

[0049] Through different interleaving methods, bits at odd positions in the input bitstream remain in odd positions after interleaving, and bits at even positions remain in even positions after interleaving. This ensures the original probability distribution characteristics of the PCS technology, thereby guaranteeing PCS compatibility. At the same time, it separates adjacent bits in the input as far apart as possible, thus providing better resistance to burst errors. In the combined application of FEC and PCS technologies, it enhances the ability to correct burst errors. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a flowchart of the data interleaving method according to an embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of the intra-block interleaving matrix according to an embodiment of the present invention;

[0053] Figure 3 This is a flowchart illustrating inter-block interleaving in an embodiment of the present invention;

[0054] Figure 4 This is a flowchart illustrating the inter-block interleaving process of RAM1 according to an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of the inter-block interleaving module structure according to an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of a digital coherent optical communication system according to an embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] This application provides a data interleaving method and apparatus that can solve the problem of low ability to correct burst errors in the combined application of FEC and PCS technologies.

[0059] like Figure 1 As shown, an embodiment of a data interleaving method is provided, including the following steps:

[0060] S1. Divide the input bit data stream into multiple first data blocks in units of 4 bits, and swap the 2 bits of data in the middle of each first data block.

[0061] For example, according to the order of the input bit stream, the 4 bits in the first data block are numbered as bit 1, bit 2, bit 3, and bit 4 in sequence; the 2 bits in the middle of the first data block, bit 2 and bit 3, are swapped, and the order of the 4 bits in the first data block becomes bit 1, bit 3, bit 2, and bit 4.

[0062] S2. Divide the bit data stream after the exchange in step S1 into a second data block of 512 bits and perform intra-block interleaving.

[0063] S3. The bit data stream after intra-block interleaving is inter-block interleaved through two random access memories.

[0064] In some embodiments, the matrix structure after interleaving within the block of step S2 is as follows: Figure 2 As shown, the matrix is ​​32×16, with a width of 16 and a depth of 32. Figure 2The numbers in the matrix represent the data numbers in the bitstream after the swap in step S1. The data in the matrix are output row by row in top-to-bottom order. For example, in the bitstream data after the swap in step S1, bit number 33, after intra-block interleaving, is located in row 1, column 2, becoming bit number 1 in the output bitstream. Bit number 66, after intra-block interleaving, is located in row 2, column 3, becoming bit number 2 in the output bitstream. As another example, bit number 479, after intra-block interleaving, is located in row 32, column 16, becoming bit number 511 in the output bitstream.

[0065] In step S3 above, inter-block interleaving includes the following steps:

[0066] Write addresses for two random access memories are generated respectively. For better description, the two random access memories are referred to as the first random access memory RAM0 and the second random access memory RAM1.

[0067] The interleaved bit data stream in step S2 is written to RAM0, and the write address of RAM0 is written to RAM1 as data.

[0068] After RAM0 completes the data writing, the read data from RAM1 is used as the read address of RAM0 to read data from RAM0 into the register array. The read data from RAM1 is then delayed and written as write data to RAM1.

[0069] like Figure 3 As shown, in some embodiments, the steps of RAM0 in inter-block interleaving are as follows:

[0070] 301a.RAM0 initialization write address.

[0071] 302a. RAM0 write operation: The interleaved bit data stream within the block is written to RAM0.

[0072] 303a. Determine whether RAM0 initialization is complete (i.e., whether all addresses have been written to). If yes, proceed to 304a; otherwise, proceed to 302a.

[0073] 304a. RAM0 performs a read operation, obtaining the read address from RAM1.

[0074] 305a. RAM0 outputs data to the register array. Specifically, the data read from RAM0 is sequentially output to the register array. After reading data from RAM0, new data is written to RAM0 using the same address.

[0075] According to step 301a above, RAM0 is initialized with a write address, providing an embodiment for generating the write address of RAM0. In this embodiment, RAM0 has a width of 512 and a depth of 336. When i ≤ 15, that is, the write address with a sequential number less than or equal to 15 is:

[0076]

[0077] When i > 15, that is, the write address for the sequential number greater than 15 is: wr_addr i =wr_addr (i-16) +16, where wr_addr is the write address of RAM0, i is the sequential number, i is an integer and i≥0.

[0078] Following the steps described above, after writing 512 bits of data in one round, the read data from RAM1 is delayed and then used as the write address for RAM0 to continue writing the subsequent bit data stream. In some embodiments, the read data from RAM1 is delayed by one clock cycle. This avoids read-write conflicts, that is, it prevents RAM0 from being read from and written to the same address at the same time. This delay time is set according to different situations; in other embodiments, it can be other times.

[0079] Furthermore, inter-block interleaving also includes the step of outputting data from the register array. The register array is 42×512 in size, and each row of data is represented by reg[j][511:0], where j is an integer and 0≤j≤41. The register array is divided into four blocks of equal width and depth. Starting from j=0, 8 bits of data are output from each block in each round, and the output order within each block is from back to front and from top to bottom, until j=20, completing one round of output; the next round continues to output data according to the rules of the previous round, until all data in the register array is output in 16 rounds.

[0080] Specifically, starting from j=0, the register array outputs bit data in the following order: {reg[j][511:504],reg[j][255:248],reg[j+21][511:504],reg[j+21][255:248],reg[j][503:496],reg[j][247:240],reg[j+21][503:496],reg[j+21][247:240]}, until j=20, completing the first round of data output.

[0081] Starting again from j=0, output the bits adjacent to the previously output bit data: {reg[j][495:488],reg[j][239:232],reg[j+21][495:488],reg[j+21][239:232],reg[j][487:480],reg[j][231:224],reg[j+21][487:480],reg[j+21][231:224]}, until j=20, completing the second round of data output. Following this rule, after 16 rounds of output, all data in the output register array is completed.

[0082] like Figure 4 As shown, in some embodiments, the steps of RAM1 in inter-block interleaving are as follows:

[0083] 301b. RAM1 initialization write address: The write address of RAM1 is a sequence that increments by 1 starting from 0.

[0084] 302b. RAM1 write operation: The address where the data in RAM0 is located (i.e. the write address of RAM0) is written as data to RAM1.

[0085] 303b. Determine whether RAM1 initialization is complete (i.e., whether all addresses have been written to). If yes, proceed to 304b; otherwise, proceed to 302b.

[0086] 304b. Read data from RAM1 and use it as the read address for RAM0. The data read from RAM1 is used as input data, delayed by 1 clock cycle, and then written back into RAM1.

[0087] In step 304b above, data is read from RAM1. RAM1 has a width of 9 and a depth of 672. The write address of RAM1 is a sequence that increments by 1 starting from 0. The read address in RAM1 is generated as follows:

[0088] When i ≤ 41, that is, when the read address sequence number is less than or equal to 41, the read address is:

[0089]

[0090] When i > 41, that is, when the read address sequence number is greater than 41, the read address is rd_addr. i =rd_addr (i-42)+2, where rd_addr is the read address of RAM1, and i is the sequence number, where i is an integer and i≥0. It is understandable that although RAM0 and RAM1 have their own workflows, they can operate simultaneously during inter-block interleaving. First, initialization addresses for RAM0 and RAM1 need to be generated, including the initial write address for RAM0, the initial write address for RAM1, and the read address for RAM1. RAM0 and RAM1 operate simultaneously; RAM0 writes the interleaved data within the block, and RAM1 writes the address where the data in RAM0 is located as the data in RAM1. After writing all addresses in RAM0, RAM0 begins read operations, obtaining the read address from RAM1 (i.e., the read data from RAM1). After a delay, the read address is used as the new write address to continue writing data to RAM0. After RAM0 obtains its first read address, RAM1 begins outputting data to RAM0, delaying the output data by one clock cycle, and then writing it as new data to RAM1. After that, RAM0 and RAM1 will behave according to the above logic. The data output by RAM0 will be input into the register array and then concatenated.

[0091] This application also provides an embodiment of a data interleaving device that can be used to implement the above method. The device includes a bit switching module, an intra-block interleaving module, and an inter-block interleaving module.

[0092] The bit-swapping module is used to divide the input bit data stream into multiple first data blocks in units of 4 bits, and swap the 2 bits of data in the middle of each first data block.

[0093] The intra-block interleaving module is used to divide the bit data stream after the bit switching module into second data blocks of 512 bits and perform intra-block interleaving.

[0094] The inter-block interleaving module is used to interleave the bit data streams that are interleaved within a block through two random access memories.

[0095] like Figure 5 As shown, the intra-block interleaving module includes a first random access memory (RAM0), a second random access memory (RAM1), a RAM0 write address generation unit, a RAM1 write address generation unit, a RAM1 read address generation unit, and a register array. The RAM0 write address generation unit is used to generate the initial write address of RAM0, the RAM1 write address generation unit is used to generate the write address of RAM1, and the RAM1 read address generation unit is used to generate the read address of RAM1.

[0096] RAM0 is used to cache the bit data after the block is swapped. The initial write address of RAM0 is generated by the RAM0 write address generation unit. After 512 bits of data are written in one round, the read data of RAM1 is delayed and used as the write address of RAM0.

[0097] Specifically, RAM0 has a width of 512 and a depth of 336. The write addresses for RAM0 include: write addresses with sequential numbers less than or equal to 15.

[0098]

[0099] The write address for a sequence number greater than 15 is wr_addr i =wr_addr (i-16) +16, where wr_addr is the write address of RAM0, i is the sequential number, i is an integer and i≥0;

[0100] After one round of writing 512 bits of data, the read data of RAM1 is delayed by 1 clock cycle and used as the write address of RAM0.

[0101] RAM1 is used to cache the write addresses corresponding to data in RAM0. The read address of RAM0 is the read data of RAM1, and the read data of RAM1 is written to RAM1 as write data after a delay. The register array is used to store the data read from RAM0 and output it according to certain rules.

[0102] Specifically, RAM1 has a width of 9 and a depth of 672. The write address of RAM1 is a sequence that increments by 1 starting from 0; the read address of RAM1 is:

[0103] When the read address sequence number is less than or equal to 41, the read address is:

[0104]

[0105] When the read address sequence number is greater than 41, the read address is rd_addr. i =rd_addr (i-42) +2, where rd_addr is the read address of RAM1, i is the sequential number, i is an integer and i≥0.

[0106] The register array above is 42×512 in size. Each row of data is represented by reg[j][511:0], where j is an integer and 0≤j≤41. The register array is divided into four blocks of equal width and depth. Starting from j=0, 8 bits of data are output from each block in each round, and the output order of data in each block is from back to front and from top to bottom, until j=20, completing one round of output. The next round continues to output data according to the rules of the previous round, until all data in the register array is output in 16 rounds.

[0107] Specifically, starting from j=0, the register array outputs bit data in the following order: {reg[j][511:504],reg[j][255:248],reg[j+21][511:504],reg[j+21][255:248],reg[j][503:496],reg[j][247:240],reg[j+21][503:496],reg[j+21][247:240]}, until j=20, completing the first round of data output;

[0108] Starting again from j=0, output the bits adjacent to the previously output bit data: {reg[j][495:488],reg[j][239:232],reg[j+21][495:488],reg[j+21][239:232],reg[j][487:480],reg[j][231:224],reg[j+21][487:480],reg[j+21][231:224]}, until j=20, completing the second round of data output; according to this rule, after 16 rounds of output, all data in the output register array is output.

[0109] like Figure 6 As shown, an embodiment of this application applied to a digital coherent optical communication system is provided. The transmitting end includes a PCS distributed matching unit, an FEC encoder, an interleaving device, a DSP transmitter, and a modulator. The receiving end includes a demodulator, a DSP receiver, a deinterleaving device, an FEC decoder, and a PCS distributed inverse matching unit. The transmitting and receiving ends transmit data through a channel. Because the interleaving device at the transmitting end uses the interleaving method of this application, and the deinterleaving device at the receiving end uses a corresponding deinterleaving method, the system's tolerance to line burst errors can be greatly improved, and it can be simultaneously compatible with FEC and PCS technologies.

[0110] The data interleaving method and apparatus of this application ensure that bits at odd positions in the input bitstream remain in odd positions after interleaving, and bits at even positions remain in even positions after interleaving. This preserves the original probability distribution characteristics of the PCS technology, thus ensuring compatibility with PCS performance. Simultaneously, it separates adjacent input bits to as far apart as possible, thereby providing better resistance to burst errors. Joint simulations of embodiments of this application with PCS and Open Forward Error Correction (OFEC, defined in the OpenZR+Multi-Source Agreement) show that applying the technology of this application can correct 1500 to 1600 burst error symbols in signal transmission, demonstrating that this application has excellent resistance to burst errors.

[0111] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0112] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A data interleaving method, characterized by, Including the following steps: The input bit data stream is divided into multiple first data blocks in units of 4 bits, and the 2 bits of data in the middle of each first data block are swapped. The swapped bit data stream is divided into second data blocks of 512 bits each, and then interleaved within each block. The bit data stream after intra-block interleaving is inter-block interleaved through two random access memories.

2. The data interleaving method of claim 1 wherein, The inter-block interleaving includes: Generate write addresses for two random access memories respectively; Write the bit data stream after intra-block swapping to the first random access memory RAM0, and write the write address of RAM0 as data to the second random access memory RAM1; After RAM0 completes the data writing, the read data from RAM1 is used as the read address of RAM0 to read data from RAM0 into the register array. The read data from RAM1 is then delayed and written as write data to RAM1.

3. The data interleaving method of claim 2 wherein, The register array is 42×512 in size, and each row of data is represented by reg[j][511:0], where j is an integer and 0≤j≤41; The register array is divided into four blocks of equal width and depth. Starting from j=0, 8 bits of data are output from each block in each round, and the output order of data in each block is from back to front and from top to bottom, until j=20, completing one round of output. The next round continues to output data according to the rules of the previous round, until all data in the register array is output in 16 rounds.

4. The data interleaving method of claim 2 wherein, The width of RAM0 is 512 and the depth is 336. The write address for RAM0 includes: The write address for sequential numbers less than or equal to 15 is The write address with sequential number greater than 15 is wr_addr i = wr_addr (i-16) + 16, wherein wr_addr is a write address of RAM0, i is a sequential number, i is an integer and i≥0; After a round of writing 512 bits of data, the read data from RAM1 is delayed and then used as the write address for RAM0.

5. The data interleaving method of claim 4 wherein, The RAM1 has a width of 9 and a depth of 672. The read address of RAM1 is: When the read address sequence number is less than or equal to 41, the read address is: When the read address sequence number is greater than 41, the read address is rd_addr. i =rd_addr (i-42) +2, where rd_addr is the read address of RAM1, i is the sequential number, i is an integer and i≥0.

6. The data interleaving method of claim 1 wherein, In the intra-block interleaving, the width of the interleaved matrix is ​​16 and the depth is 32. The data in the matrix is ​​output row by row from top to bottom.

7. A data interleaving apparatus, characterized by comprising: include: The bit-swapping module is used to divide the input bit data stream into multiple first data blocks in units of 4 bits, and swap the 2 bits of data in the middle of each first data block. The intra-block interleaving module is used to divide the bit data stream after the bit switching module into second data blocks of 512 bits and perform intra-block interleaving. The inter-block interleaving module is used to interleave the bit data streams that are interleaved within a block through two random access memories.

8. The data interleaving apparatus as described in claim 7, characterized in that, The inter-block interleaving module includes a first random access memory (RAM0), a second random access memory (RAM1), a RAM0 write address generation unit, a RAM1 write address generation unit, a RAM1 read address generation unit, and a register array. The RAM0 write address generation unit is used to generate the initial write address of RAM0, the RAM1 write address generation unit is used to generate the write address of RAM1, and the RAM1 read address generation unit is used to generate the read address of RAM1. RAM0 is used to cache the bit data swapped within the block, and RAM1 is used to cache the write address corresponding to the data in RAM0; The register array is used to store data read from RAM0. The read address of RAM0 is the read data of RAM1. The read data of RAM1 is delayed and then written to RAM1 as write data.

9. The data interleaving device of claim 8 wherein, The register array is 42×512 in size. Each row of data is represented by reg[j][511:0], where j is an integer and 0≤j≤41. The register array is divided into four blocks of equal width and depth. Starting from j=0, 8 bits of data are output from each block in each round, and the output order of data in each block is from back to front and from top to bottom, until j=20, completing one round of output. The next round continues to output data according to the rules of the previous round, until all data in the register array is output in 16 rounds.

10. The data interleaving device of claim 8 wherein, The width of RAM0 is 512 and the depth is 336. The write address for RAM0 includes: The write address for sequential numbers less than or equal to 15 is The write address with sequential number greater than 15 is wr_addr i = wr_addr (i-16) + 16, wherein wr_addr is a write address of RAM0, i is a sequential number, i is an integer and i≥0; After writing 512 bits of data in one round, the read data from RAM1 is delayed and then used as the write address for RAM0. The RAM1 has a width of 9 and a depth of 672. The write address of RAM1 is a sequence that increments by 1 starting from 0. The read address of RAM1 is: When the read address sequence number is less than or equal to 41, the read address is: When the read address sequential number is greater than 41, the read address is rd_addr i = rd_addr (i-42) + 2, wherein rd_addr is the read address of the RAM1, i is the sequential number, i is an integer and i ≥ 0.

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