Receiver with multiple transmission mode settings

Abstract

A receiver with multiple transmission mode settings is disclosed. The receiver includes a termination resistance circuit, a reference voltage generator, a comparator, a filter, and a digital circuit. The termination resistance circuit outputs a common mode voltage in a calibration mode and outputs a plurality of input signals in a plurality of transmission modes. The reference voltage generator outputs the common mode voltage in the calibration mode and provides a plurality of reference voltages in the transmission modes. The comparator generates a first signal from the common mode voltage in the calibration mode and performs offset correction in response to an offset correction signal, and compares the reference voltages with the input signals in the transmission modes to generate the first signal. The filter outputs the first signal as an output signal in the calibration mode and generates the output signal from the first signal in the transmission modes. The digital circuit outputs the offset correction signal in response to the output signal.

Description

Technical Field

[0001] This application relates to the field of receivers, and more specifically to receivers with multiple transmission mode settings. Background Technology

[0002] To establish a connection with other devices, the receiver needs to determine whether the received signal conforms to the handshake signal specified under the transmission protocol. In the prior art, different transmission protocols specify handshake signals with different signal characteristics, which may require the receiver to set up multiple circuits for identification. Therefore, in multi-transmission mode applications, the number of circuits in the receiver will increase significantly, resulting in an excessive increase in circuit area and cost. Summary of the Invention

[0003] In some embodiments, one of the objectives of this application is to provide a receiver that is cost-effective and has multiple transmission mode applications to improve upon the shortcomings of the prior art.

[0004] In some embodiments, the receiver includes a terminating resistor circuit, a reference voltage generator, a comparator, a filter, and digital circuitry. The terminating resistor circuit outputs a common-mode voltage in a calibration mode and outputs multiple input signals in multiple transmission modes. The reference voltage generator outputs the common-mode voltage in the calibration mode and provides multiple reference voltages in the transmission modes. The comparator generates a first signal based on the common-mode voltage in the calibration mode and performs offset correction in response to an offset correction signal, and compares the reference voltage with the input signals in the transmission modes to generate the first signal. The filter outputs the first signal as an output signal in the calibration mode and generates the output signal based on the first signal in the transmission modes. The digital circuitry outputs the offset correction signal based on the output signal.

[0005] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, showing preferred embodiments. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a receiver drawn according to some embodiments of this application;

[0007] Figure 2 Drawings based on some embodiments of this application Figure 1 A schematic diagram of the signal detection circuit;

[0008] Figure 3 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the terminating resistor circuit;

[0009] Figure 4 Drawings based on some embodiments of this application Figure 2 A schematic diagram of a reference voltage generator;

[0010] Figure 5 Drawings based on some embodiments of this application Figure 2 A schematic diagram of a comparator;

[0011] Figure 6 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the filter;

[0012] Figure 7A Drawings based on some embodiments of this application Figure 6 A schematic diagram of the filter circuit;

[0013] Figure 7B Drawings based on some embodiments of this application Figure 7A A waveform diagram of part of the signal;

[0014] Figure 8A Drawings based on some embodiments of this application Figure 6 A schematic diagram of the filter circuit;

[0015] Figure 8B Drawings based on some embodiments of this application Figure 8A A waveform diagram of part of the signal;

[0016] Figure 9 Drawings based on some embodiments of this application Figure 2 A schematic diagram of a digital-to-analog converter;

[0017] Figure 10 Drawings based on some embodiments of this application Figure 2 The operation flowchart of the signal detection circuit in calibration mode;

[0018] Figure 11A Drawings based on some embodiments of this application Figure 2 The operation flowchart of the signal detection circuit in the first transmission mode; and

[0019] Figure 11B The operation flowchart of the signal detection circuit in the figure in the second transmission mode is drawn according to some embodiments of this application.

[0020] Figure label:

[0021] 100: Receiver;

[0022] 110: Signal detection circuit;

[0023] 120: Data receiving circuit;

[0024] 210: Terminating resistor circuit;

[0025] 220: Reference voltage generator;

[0026] 230: Comparator;

[0027] 240: Filter;

[0028] 250: Digital circuits;

[0029] 260: Digital-to-analog converter;

[0030] 410: Voltage divider circuit;

[0031] 510, 520: Input pair circuit;

[0032] 515, 525, 612, 622: Current sources;

[0033] 530: Differential to single-ended circuit;

[0034] 610, 620: Filter circuits;

[0035] 614, 626: Inverters;

[0036] 624: Buffer;

[0037] 910: Current source;

[0038] 920: Decoder;

[0039] C1, C2, C+, C-: Capacitors;

[0040] IN, IP: Current signals;

[0041] MN1, MN2, MN3, M[0]~M[m]: transistors;

[0042] N1, N2: Nodes;

[0043] OC: Offset correction signal;

[0044] P[0]~P[m], N[0]~N[m]: Control signals;

[0045] P1, P2: Transistors;

[0046] R11, R12, RO1, RO2: Resistors;

[0047] RT1, RT2: terminating resistors;

[0048] S1~S3, S21, S22: Signals;

[0049] S1001~S1004, S1101~S1105, S1104', S1105': Operation;

[0050] SC, SCB: Correction control signals;

[0051] SM, SM1, SM2: Mode control signals;

[0052] SO: Output signal;

[0053] SW1+, SW1-, SW2+, SW2-, SW3+, SW3-, SW4+, SW4-, SW5~SW7: Switches;

[0054] VCM: Common-mode voltage;

[0055] VD: Drive voltage;

[0056] VDD: Supply voltage;

[0057] VIN, VIP: Input signal;

[0058] VREF1, VREF2: Reference voltages;

[0059] t1, t2, tf1, tf2: Time periods. Detailed Implementation

[0060] All terms used herein have their ordinary meanings. The definitions of the terms above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0061] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can refer to a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0062] Figure 1 This is a schematic diagram of a receiver 100 according to some embodiments of this application. In some embodiments, the receiver 100 can be applied to various wired transmissions, including, but not limited to, Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), etc.

[0063] Receiver 100 includes a signal detection circuit 110 and a data receiving circuit 120. The signal detection circuit 110 detects whether the received input signals VIP and VIN belong to a handshake signal under a preset transmission protocol, and then establishes a connection based on the handshake signal. After confirming the connection is established, the data receiving circuit 120 can start to process data based on subsequent input signals VIP and VIN. In some embodiments, the signal detection circuit 110 can be applied to multiple transmission modes using a single comparator, thereby reducing circuit cost.

[0064] Figure 2 Drawings based on some embodiments of this application Figure 1 A schematic diagram of the signal detection circuit 110 is shown. The signal detection circuit 110 includes a terminating resistor circuit 210, a reference voltage generator 220, a comparator 230, a filter 240, a digital circuit 250, and a digital-to-analog converter 260.

[0065] The terminating resistor circuit 210 provides impedance matching to receive the input signals VIP and VIN. Specifically, the terminating resistor circuit 210 can operate in either a calibration mode or one of multiple transmission modes in response to the calibration control signals SC and SCB. The terminating resistor circuit 210 can output a common-mode voltage VCM in calibration mode and output the input signals VIP and VIN in multiple transmission modes. The configuration of the terminating resistor circuit 210 will be described in [reference needed]. Figure 3 This is an explanation, but this application is not limited to this.

[0066] Reference voltage generator 220 generates a common-mode voltage VCM and multiple reference voltages VREF1 and VREF2 based on the supply voltage VDD. Specifically, reference voltage generator 220 can respond to multiple correction control signals SCB and SC operating in any of multiple transmission modes or correction mode. Reference voltage generator 220 can output the common-mode voltage VCM in correction mode and output multiple reference voltages VREF1 and VREF2 in multiple transmission modes. The configuration method for reference voltage generator 220 will be described in [reference / reference / details]. Figure 4 This is an explanation, but this application is not limited to this.

[0067] Comparator 230 can generate signal S1 based on common-mode voltage VCM in correction mode, thereby performing offset correction in response to offset correction signal OC, and comparing multiple reference voltages VREF1 and VREF2 with multiple input signals VIP and VIN in multiple transmission modes to generate signal S1. In some embodiments, comparator 230 can have different circuit configurations in different transmission modes in response to mode control signal SM. The configuration of comparator 230 will be described below. Figure 5This is an explanation, but this application is not limited to this.

[0068] Filter 240 can selectively operate in any one of multiple transmission modes or in correction mode in response to multiple mode control signals SM1 and SM2 and correction control signal SC, and output a corresponding output signal SO. For example, filter 240 can operate in correction mode in response to correction control signal SC, and output signal S1 as output signal SO in correction mode. Filter 240 can operate in a first transmission mode in response to mode control signal SM1, and perform low-pass filtering on signal S1 in the first transmission mode to generate output signal SO. Alternatively, filter 240 can operate in a second transmission mode in response to mode control signal SM2, and generate output signal SO based on signal S1 in the second transmission mode, where output signal SO is the envelope signal of signal S1. The configuration of filter 240 will be referred to below. Figure 6 , Figure 7A , Figure 7B , Figure 8A and Figure 8B This is an explanation, but this application is not limited to this.

[0069] In some embodiments, digital circuit 250 may be implemented by several digital logic circuits to perform a specific operational procedure based on the output signal SO. For example, when receiver 100 operates in calibration mode, digital circuit 250 may execute a calibration algorithm (e.g., but not limited to, a Sequential Approximation Register (SAR) algorithm) based on the output signal SO, thereby outputting an offset calibration signal OC to correct the offset in comparator 230 caused by process variations or other undesirable factors. Alternatively, when receiver 100 operates in any of a plurality of transmission modes, digital circuit 250 may detect, based on the output signal SO, whether the currently received input signal VIP and input signal VIP are handshake signals defined under the protocol corresponding to the corresponding transmission mode, to determine whether to establish a connection with the device (not shown) that sent input signal VIP and input signal VIP. In some embodiments, digital circuit 250 may further generate the aforementioned plurality of calibration control signals SC and SCB, and mode control signals SM, SM1, and SM2.

[0070] The digital-to-analog converter 260 extracts current signals IP and IN from comparator 230 based on the offset correction signal OC to correct comparator 230. For example, in correction mode, the digital-to-analog converter 260 can extract current signals IP and IN based on the offset correction signal OC, so that the level of the internal node of comparator 230 can be corrected to a target level, thereby eliminating the offset of comparator 230. The configuration method of the digital-to-analog converter 260 will be described below. Figure 9 This is an explanation, but this application is not limited to this.

[0071] Figure 3 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the terminating resistor circuit 210 is shown below. In some embodiments, the terminating resistor circuit 210 may include multiple terminating resistors RT1 and RT2, multiple switches SW1+ and SW1-, multiple switches SW2+ and SW2-, multiple capacitors C+ and C-, and multiple resistors R11 and R12. The multiple terminating resistors RT1 and RT2 are coupled to ground and receive multiple input signals VIP and VIN. Specifically, the first terminals of the multiple terminating resistors RT1 and RT2 respectively receive the input signals VIP and VIN, and are respectively coupled to the first terminals of the multiple switches SW1+ and SW1-. The second terminals of the multiple terminating resistors RT1 and RT2 are coupled to ground.

[0072] Multiple switches SW1+ and SW1- are coupled to multiple terminating resistors RT1 and RT2, and are turned on in multiple transmission modes but not in correction mode. Specifically, the second terminals of the multiple switches SW1+ and SW1- are respectively coupled to multiple switches SW2+ and SW2- and multiple capacitors C+ and C-. The control terminals of the multiple switches SW1+ and SW1- receive a correction control signal SCB. That is, the multiple switches SW1+ and SW1- can be selectively turned on according to the correction control signal SCB.

[0073] In some embodiments, when the receiver 100 operates in calibration mode, the calibration control signal SC has an enable level (e.g., but not limited to, the level corresponding to logic value 1), and the calibration control signal SCB has a disable level (e.g., but not limited to, the level corresponding to logic value 0). On the other hand, when the receiver 100 operates in any of the plurality of transmission modes, the calibration control signal SC has a disable level, and the calibration control signal SCB has an enable level. Under this condition, when the receiver 100 operates in calibration mode, the plurality of switches SW1+ and SW1- may be de-energized in response to the calibration control signal SCB having the disable level. Thus, the plurality of switches SW1+ and SW1- will not transmit the plurality of input signals VIP and VIP to subsequent circuitry.

[0074] The first terminals of multiple switches SW2+ and SW2- are respectively coupled to the first terminals of multiple switches SW1+ and SW1-, and the second terminals of multiple switches SW2+ and SW2- are coupled to ground. The control terminals of multiple switches SW2+ and SW2- receive a correction control signal SC. That is, multiple switches SW2+ and SW2- can be selectively turned on according to the correction control signal SC. Under this condition, when the receiver 100 operates in correction mode, multiple switches SW2+ and SW2- can be turned on in response to the correction control signal SC with a disable level, thereby coupling the first terminals of multiple capacitors C+ and C- to ground. The first terminals of multiple resistors R11 and R12 are coupled to the second terminals of multiple capacitors C+ and C-, and the second terminals of multiple resistors R11 and R12 receive a common-mode voltage VCM.

[0075] With the above configuration, when the receiver 100 operates in calibration mode, multiple switches SW2+ and SW2- are turned on, while multiple switches SW1+ and SW1- are not turned on. Under this condition, multiple switches SW2+ and SW2- couple the first terminals of multiple capacitors C+ and C- to ground via multiple switches SW2+ and SW2-, and the second terminals of multiple capacitors C+ and C- receive the common-mode voltage VCM via multiple resistors R11 and R12, thereby providing the common-mode voltage VCM to comparator 230. Alternatively, when the receiver 100 operates in any of the multiple transmission modes, multiple switches SW1+ and SW1- are turned on, while multiple switches SW2+ and SW2- are not turned on. Under this condition, multiple capacitors C+ and C- can operate as an AC coupling circuit to receive the AC components of multiple input signals VIP and VIN via multiple switches SW1+ and SW1-. Multiple resistors R11 and R12 can be used to superimpose the common-mode voltage VCM onto these AC components, and the superimposed result (equivalent to the shifted input signals VIP and VIN) is output to comparator 230.

[0076] Figure 4 Drawings based on some embodiments of this application Figure 2A schematic diagram of the reference voltage generator 220 is shown. The reference voltage generator 220 includes a voltage divider circuit 410, multiple switches SW3+ and SW3-, and multiple switches SW4+ and SW4-. The voltage divider circuit 410 may include multiple series-connected resistors and current sources, which can divide the supply voltage VDD to generate reference voltage VREF1, common-mode voltage VCM, and reference voltage VREF2. The first terminals of the multiple switches SW3+ and SW3- are coupled to the voltage divider circuit 410 to receive the common-mode voltage VCM, the second terminals of the multiple switches SW3 and SW3- are coupled to the comparator 230, and the control terminals of the multiple switches SW3 and SW3- receive a correction control signal SC. That is, when the receiver 100 operates in correction mode, the multiple switches SW3+ and SW3- can turn on in response to the correction control signal SC to transmit the common-mode voltage VCM to the comparator 230. Conversely, when the receiver 100 operates in other transmission modes, the multiple switches SW3+ and SW3- can turn off in response to the correction control signal SC.

[0077] The first terminals of multiple switches SW4+ and SW4- are coupled to a voltage divider circuit 410 to receive multiple reference voltages VREF1 and VREF2, respectively. The second terminals of multiple switches SW4 and SW4- are coupled to the second terminals of multiple switches SW3 and SW3- and a comparator 230, and the control terminals of multiple switches SW4 and SW4- receive a correction control signal SCB. When the receiver 100 operates in correction mode, multiple switches SW4 and SW4- are de-energized in response to the correction control signal SCB. Conversely, when the receiver 100 operates in other transmission modes, multiple switches SW4 and SW4- are energized in response to the correction control signal SCB to transmit multiple reference voltages VREF1 and VREF2 to the comparator 230.

[0078] Figure 5 Drawings based on some embodiments of this application Figure 2A schematic diagram of comparator 230 is shown. Comparator 230 includes multiple resistors RO1 and RO2, multiple input pair circuits 510 and 520, multiple current sources 515 and 525, and a differential-to-single-ended circuit 530. The multiple input pair circuits 510 and 520 operate as a cross-coupled input pair, coupled to the multiple resistors RO1 and RO2, thereby generating multiple signals S21 and S22. The multiple current sources 515 and 525 drive the multiple input pair circuits 510 and 520 respectively. In calibration mode, the inputs to the multiple input pair circuits 510 and 520 are all common-mode voltage VCM, allowing the multiple input pair circuits 510 and 520 to generate multiple signals S21 and S22 based on the common-mode signal VCM. Under this condition, the multiple signals S21 and S22 ideally would have the same level. In practical applications, comparator 230 may be affected by offset, causing the levels of the multiple signals S21 and S22 to differ under this condition. Therefore, in the correction mode, the digital-to-analog converter 260 can extract the current signal IN and the current signal IP from the multiple nodes that generate multiple signals S21 and S22 respectively, thereby correcting the level of these nodes and reducing the impact of offset.

[0079] On the other hand, in any of the multiple transmission modes, the inputs of the multiple input pair circuits 510 and 520 are switched to multiple input signals VIP and VIN, and multiple reference signals VREF1 and VREF2, so that the multiple input pair circuits 510 and 520 can generate multiple signals S21 and S22 based on the multiple input signals VIP and VIN and the multiple reference voltages VREF1 and VREF2. For example, the input pair circuit 510 can compare the input signal VIP with the reference voltage VREF1, and the input pair circuit 520 can compare the input signal VIN with the reference voltage VREF2, thereby generating corresponding signals S21 and S22. The differential-to-single-ended circuit 530 can generate signal S1 based on signals S21 and S22.

[0080] As can be seen from the above embodiments, comparator 230 can have different circuit configurations in multiple transmission modes. The resistance values ​​of multiple resistors RO1 and RO2 can be adjusted according to the mode control signal SM to provide different resistance values. For example, according to the mode control signal SM, the resistance values ​​of multiple resistors RO1 and RO2 in the first transmission mode can be different from their resistance values ​​in the second transmission mode. Alternatively, the current values ​​of multiple current sources 515 and 525 can be adjusted according to the mode control signal SM to provide different current values. For example, according to the mode control signal SM, the current values ​​of multiple current sources 515 and 525 in the first transmission mode can be different from their current values ​​in the second transmission mode. In some embodiments, the mode control signal SM can be mode control signal SM1, mode control signal SM2, or another signal generated based on at least one of the above two.

[0081] Figure 6 Drawings based on some embodiments of this application Figure 2 A schematic diagram of filter 240 is shown. Filter 240 includes multiple switches SW5-SW7, filter circuit 610, and filter circuit 620. Switch SW5 is not turned on in multiple transmission modes, but is turned on in correction mode to output signal S1 as output signal SO. For example, switch SW5 can be turned on according to the correction control signal SC to output signal S1 as output signal SO. That is, when receiver 100 operates in correction mode, filter 240 does not process signal S1, but directly outputs signal S1 as output signal SO.

[0082] Filter circuit 610 generates signal S2 based on signal S1. Filter circuit 610 generates signal S3 based on signal S1. Switch SW6 is coupled to filter circuit 610 to receive signal S2. Switch SW6 is not turned on in correction mode and is turned on in a first transmission mode among multiple transmission modes, outputting signal S2 as output signal SO. In some embodiments, when receiver 100 is configured to operate in the first transmission mode, mode control signal SM1 may have a first logic value (e.g., but not limited to, logic value 1), and mode control signal SM2 may have a second logic value (e.g., but not limited to, logic value 0). Conversely, when receiver 100 is configured to operate in the first transmission mode, mode control signal SM2 may have a first logic value, and mode control signal SM1 may have a second logic value. Under this condition, switch SW6 may be turned on according to mode control signal SM1, thereby outputting signal S2 as output signal SO in the first transmission mode.

[0083] Filter circuit 620 generates signal S3 based on signal S1. Switch SW7 is coupled to filter circuit 620 to receive signal S3. Switch SW7 is not turned on in correction mode, but is turned on in the second transmission mode of multiple transmission modes, outputting signal S3 as output signal SO. For example, switch SW6 can be turned on according to mode control signal SM2, thereby outputting signal S3 as output signal SO in the second transmission mode.

[0084] Figure 7A Drawings based on some embodiments of this application Figure 6 A schematic diagram of filter circuit 610 is shown. In some embodiments, filter circuit 610 is configured to process handshake signals under a first transmission mode (e.g., but not limited to, USB mode). Filter circuit 610 includes transistor P1, current source 612, capacitor C1, and inverter 614. A first terminal (e.g., the source) of transistor P1 receives a supply voltage VDD, a second terminal of transistor P1 is coupled to node N1, and a control terminal (e.g., the gate) of transistor P1 receives a signal S1. Transistor P1 can be selectively turned on according to signal S1 to transmit the supply voltage VDD to node N1, thereby adjusting the level of node N1. Current source 614 is coupled to node N1 to draw current from node N1. Capacitor C1 is coupled between node N1 and ground. Inverter 614 generates signal S2 according to the level of node N1.

[0085] Figure 7B Drawings based on some embodiments of this application Figure 7A A waveform diagram of a portion of the signal. For example... Figure 7B As shown, the filter circuit 610 is configured to perform low-pass filtering on signal S1 to remove high-frequency noise from signal S1. For example, if the pulse width (e.g., time period t1) of a high-level pulse in signal S1 is too short (e.g., less than time period tf1), the corresponding pulse will not be output as part of signal S2. Alternatively, if the pulse width of a high-level pulse in signal S1 is sufficiently large (e.g., greater than or equal to time period tf1), the corresponding pulse will be output as part of signal S2. That is, when the pulse in signal S1 has a long high-level time period, the time during which transistor P1 is not conducting will be extended, allowing current source 612 to pull down the level of node N1 during that time period, thereby allowing inverter 614 to generate a corresponding pulse on signal S2. On the other hand, when the pulse in signal S1 has a short high-level time period, the time during which transistor P1 is conducting will be relatively longer, causing the level of node N1 to be limited by the supply voltage VDD, thereby preventing inverter 614 from generating a corresponding pulse on signal S2.

[0086] In some embodiments, the first transmission mode may be, but is not limited to, USB mode. Based on the USB 3.0 specification, the handshake signal used during the handshake phase between the transmitting and receiving ends is a low-frequency signal. Therefore, the circuit behavior of the filter circuit 610 described above can be used to detect this handshake signal without outputting the higher-speed data signal as signal S2.

[0087] Figure 8A Drawings based on some embodiments of this application Figure 6 A schematic diagram of filter circuit 620 is shown. In some embodiments, filter circuit 620 is configured to process handshake signals under a second transmission mode (e.g., but not limited to, SATA mode). Filter circuit 620 includes inverter 626, transistor P2, current source 622, capacitor C2, and buffer 624. Inverter 626 generates signal S4 according to signal S1. A first terminal (e.g., source) of transistor P2 receives a supply voltage VDD, a second terminal of transistor P2 is coupled to node N2, and a control terminal (e.g., gate) of transistor P2 receives signal S4. Transistor P2 can be selectively turned on according to signal S4 to transmit the supply voltage VDD to node N2, thereby adjusting the level of node N2. Current source 624 is coupled to node N2 to draw current from node N2. Capacitor C2 is coupled between node N2 and ground. Buffer 624 can generate signal S3 according to the level of node N2. In some embodiments, buffer 624 may be implemented by, but not limited to, an even number of inverters connected in series.

[0088] Figure 8B Drawings based on some embodiments of this application Figure 8A A waveform diagram of a portion of the signal. For example... Figure 8B As shown, the filter circuit 620 is configured to perform envelope detection on signal S1 to generate signal S3 based on signal S1, where signal S3 is the envelope signal of signal S1. For example, when the pulse width of a low-level pulse in signal S1 (e.g., time period t2) is not large enough (e.g., less than time period tf2), the envelope of the corresponding pulse will be output as part of signal S2. Alternatively, when the pulse width of a low-level pulse in signal S1 is large enough (e.g., greater than or equal to time period tf2), the pulse width of the corresponding pulse in signal S2 will be increased by time period tf2.

[0089] To put it another way, when the pulse in signal S1 has a short period of low-level duration, transistor P2 will be continuously turned on, causing node N2 to be charged by the supply voltage VDD, thus allowing inverter 624 to generate the corresponding envelope signal component on signal S3. On the other hand, when the pulse in signal S1 has a long enough period of low-level duration, transistor P2 will be off for a relatively longer time, causing the level of node N2 to be pulled low by current source 624, thus allowing inverter 614 to extend the pulse width of the corresponding pulse in signal S2.

[0090] In some embodiments, the second transmission mode may be, but is not limited to, SATA mode. Based on the SATA specification, the handshake signal used during the handshake phase is a series of pulse signals. Therefore, the circuit behavior of the filter circuit 620 described above can be used to detect this handshake signal and shape the multiple pulse signals in the handshake signal into an envelope signal for corresponding signal processing by the digital circuit 250.

[0091] Figure 9 Drawings based on some embodiments of this application Figure 2 A schematic diagram of a digital-to-analog converter 260 is shown. In some embodiments, the digital-to-analog converter 260 may be a current-driven digital-to-analog converter. The digital-to-analog converter 260 includes multiple transistors MN1 to MN3, multiple transistors M[0] to M[m], multiple switches S[0] to S[m-1], a current source 910, and a decoder 920. The decoder 920 can generate multiple control signals P[0] to P[m] and multiple control signals N[0] to N[m] based on the m+1 bits in the offset correction signal OC, where the value m may be a positive integer greater than 1. In some embodiments, one corresponding to one of the multiple control signals P[0] to P[m] has the opposite logic value to one corresponding to one of the multiple control signals N[0] to N[m]. For example, if control signal P[m] has a logic value of 1, then control signal N[m] has a logic value of 0. And so on, the correspondence between the remaining control signals can be understood.

[0092] Transistor MN1 is a diode-connected transistor and is driven by current source 910 to generate a drive voltage VD. Multiple transistors M[0] to M[m] operate as multiple unit current sources. Transistor M[m] is driven by the drive voltage VD to draw current from transistor MN2 or transistor MN3. Multiple switches S[0] to S[m-1] are controlled by multiple control signals P[0] to P[m-1] to selectively transmit the drive voltage VD to multiple transistors M[0] to M[m-1]. For example, when switch S[m-1] is turned on according to control signal P[m-1], transistor M[m-1] can receive the drive voltage VD and turn on accordingly to draw current from transistor MN2 and / or transistor MN3. When switches S[m-1] and S[m-2] are turned on according to control signals P[m-1] and P[m-2], transistors M[m-1] and M[m-2] can receive the driving voltage VD and turn on accordingly to draw current from transistor MN2 or transistor MN3. Similarly, if multiple switches S[0] to S[m-1] are turned on according to multiple control signals P[0] to P[m-1], multiple transistors M[0] to M[m-1] can receive the driving voltage VD and turn on accordingly to draw current from transistor MN2 or transistor MN3.

[0093] The first terminal (e.g., the source) of transistor MN2 is coupled to the node of the output signal S22 in comparator 230 to draw current IP. The second terminal (e.g., the drain) of transistor MN2 is coupled to multiple transistors M[0] to M[m], and the control terminal (e.g., the gate) of transistor MN2 receives the control signal P[m]. Similarly, the first terminal of transistor MN3 is coupled to the node of the output signal S21 in comparator 230 to draw current IN. The second terminal of transistor MN3 is coupled to multiple transistors M[0] to M[m], and the control terminal of transistor MN3 receives the control signal N[m]. Transistors MN2 and MN3 can be selectively turned on according to the control signal P[m] and the control signal N[m], respectively, to draw current IP and / or current IN from comparator 230.

[0094] Figure 10 Drawings based on some embodiments of this application Figure 2 The flowchart shows the operation of the signal detection circuit 110 in calibration mode. For ease of understanding, please refer to the corresponding schematic diagrams in the foregoing embodiments.

[0095] In operation S1001, in response to the correction control signals SC and SCB, switches SW1+ and SW1- are de-conducting while switches SW2+ and SW2- are conducting, causing the terminating resistor circuit 210 to output a common-mode voltage VCM. In operation S1002, in response to the correction control signals SC and SCB, switches SW3+ and SW3- are conducting while switches SW4+ and SW4- are de-conducting, causing the reference voltage generator 220 to output a common-mode voltage VCM.

[0096] In operation S1003, comparator 230 generates signal S1 in response to the common-mode voltage VCM. Also in operation S1003, in response to the correction control signal SC and multiple mode control signals SM1 and SM2, switch SW5 is turned on while multiple switches SW6 and SW7 are turned off, causing filter 240 to output signal S1 as output signal SO. In operation S1004, digital circuit 250 generates offset correction signal OC based on output signal SO, thereby controlling digital-to-analog converter 260 to extract current signal IP or current signal IN to correct comparator 230.

[0097] Figure 11A Drawings based on some embodiments of this application Figure 2 The operation flowchart of the signal detection circuit 110 in the first transmission mode is shown. For ease of understanding of this operation, please also refer to the schematic diagrams corresponding to the foregoing embodiments.

[0098] In operation S1101, in response to the correction control signals SC and SCB, switches SW1+ and SW1- are turned on while switches SW2+ and SW2- are turned off, causing the terminating resistor circuit 210 to output input signals VIP and VIN. In operation S1102, in response to the correction control signals SC and SCB, switches SW3+ and SW3- are turned off while switches SW4+ and SW4- are turned on, causing the reference voltage generator 220 to output multiple reference voltages VREF1 and VREF2.

[0099] In operation S1103, comparator 230 generates signal S1 in response to multiple input signals VIP and VIN. In operation S1104, in response to the correction control signal SC and multiple mode control signals SM1 and SM2, switch SW6 is turned on and multiple switches SW5 and SW7 are turned off, causing filter 240 to generate signal S2 based on signal S1 and output signal S2 as output signal SO. In operation S1105, digital circuit 250 determines whether input signals VIP and VIN are the handshake signals corresponding to the first transmission mode based on the output signal SO.

[0100] Figure 11B Drawings based on some embodiments of this application Figure 2The operation flowchart of the signal detection circuit 110 in the second transmission mode is shown below. For ease of understanding of this operation, please also refer to the schematic diagrams corresponding to the aforementioned embodiments. Figure 11B The multiple operations S1101, S1102 and S1103 are the same as Figure 11A Therefore, I will not repeat the details here.

[0101] Unlike Figure 11A Operation S1104 in Figure 11B In operation S1104', in response to the correction control signal SC and multiple mode control signals SM1 and SM2, switch SW7 is turned on and multiple switches SW5 and SW6 are turned off, causing filter 240 to generate signal S3 based on signal S1 and output signal S3 as output signal SO. In operation S1105', digital circuit 250 determines whether input signal VIP and input signal VIN are the handshake signals corresponding to the second transmission mode based on output signal SO.

[0102] The above Figure 10 , Figure 11A With / or Figure 11B The various operations can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. Figure 10 , Figure 11A With / or Figure 11B The operations described are merely examples and are not intended to be performed in the specific order shown in these examples. Without departing from the operational methods and scope of the various embodiments of this application, in Figure 10 , Figure 11A With / or Figure 11B Various operations can be added, replaced, omitted, or executed in different orders as appropriate (e.g., they can be executed simultaneously or partially simultaneously).

[0103] In summary, the receiver and signal detection circuits in some embodiments of this application can use a single comparator to implement multiple transmission modes and integrate a comparator offset correction mechanism. Therefore, the accuracy of comparator detection can be improved while simultaneously reducing circuit costs.

[0104] Although the embodiments of this application are described above, the various embodiments are not intended to limit this application. Those skilled in the art can make variations to the technical features of this application based on the express or implied content of this application. All such variations may fall within the scope of patent protection sought in this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.

Claims

1. A receiver, characterized by comprises: a termination resistor circuit that outputs a common mode voltage in a calibration mode and outputs input signals in transmission modes; a reference voltage generator that outputs the common mode voltage in the calibration mode and provides reference voltages in the transmission modes; a comparator that generates a first signal based on the common mode voltage in the calibration mode and performs offset correction in response to an offset correction signal, and compares the reference voltages with the input signals to generate the first signal in the transmission modes; a filter that outputs the first signal as an output signal in the calibration mode, and generates the output signal based on the first signal in the transmission modes; and a digital circuit that outputs the offset correction signal based on the output signal.

2. The receiver of claim 1, wherein, The filter low-pass filters the first signal to generate the output signal in a first transmission mode of the transmission modes, and generates the output signal based on the first signal in a second transmission mode of the transmission modes, and the output signal in the second transmission mode is an envelope signal of the first signal.

3. The receiver of claim 1, wherein, The transmission modes include a universal serial bus mode and a serial advanced technology attachment mode.

4. The receiver of claim 1, wherein, The termination resistor circuit comprises: termination resistors coupled to ground and receiving the input signals; first switches coupled to the termination resistors and turned on in the transmission modes and turned off in the calibration mode; second switches coupled to the first switches and turned on in the calibration mode and turned off in the transmission modes; capacitors coupled to the first switches and the second switches; and first resistors coupled to the capacitors and receiving the common mode voltage.

5. The receiver of claim 1, wherein, The reference voltage generator comprises: a voltage dividing circuit that generates the reference voltages and the common mode voltage; and first switches turned on in the calibration mode to transmit the common mode voltage to the comparator; and second switches turned on in the transmission modes to transmit the reference voltages to the comparator.

6. The receiver of claim 1, wherein, The filter comprises: a first switch turned off in the transmission modes and turned on in the calibration mode to output the first signal as the output signal; a first filter circuit that generates a second signal based on the first signal; a second filter circuit that generates a third signal based on the first signal; a second switch turned on in a first transmission mode of the transmission modes to output the second signal as the output signal; and a third switch turned on in a second transmission mode of the transmission modes to output the third signal as the output signal.

7. The receiver of claim 6, wherein, The first filter circuit comprises: a transistor selectively turned on based on the first signal to adjust a level of a node; a current source coupled to the node; a capacitor coupled between the node and ground; and an inverter that generates the second signal based on the level of the node.

8. The receiver of claim 6, wherein, The second filter circuit comprises: an inverter that generates a fourth signal based on the first signal; a transistor selectively turned on according to the fourth signal to adjust a level of a node; a current source coupled to the node; a capacitor coupled between the node and ground; and a buffer to generate the third signal according to the level of the node.

9. The receiver of claim 1, wherein, Further comprising: a digital-to-analog converter to draw a plurality of current signals from the comparator according to the offset correction signal to correct the comparator.

10. The receiver of claim 1, wherein, the comparator has different circuit configurations in the transmission modes.

11. The receiver of claim 1, wherein, the comparator comprises: a plurality of resistors; a plurality of input pair circuits coupled to the resistors to generate a plurality of second signals according to the common mode voltage in the correction mode and to generate the second signals according to the input signal and the reference voltage in the transmission modes; a differential-to-single-ended circuit to generate the first signal according to the second signals; and a plurality of current sources to drive the input pair circuits.

12. The receiver of claim 11, wherein, the resistors have different resistance values in a first transmission mode of the transmission modes than in a second transmission mode of the transmission modes.

13. The receiver of claim 11, wherein, the current sources have different current values in a first transmission mode of the transmission modes than in a second transmission mode of the transmission modes.

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