Transmitter output signal power measuring device

Abstract

Aspects of the present disclosure relate to an apparatus for wireless communication. The apparatus can include a set of power detectors configured to generate a set of analog signals respectively related to a set of output signal power levels of a set of transmit chains of a transmitter, an analog summer, a set of switching devices configured to transmit a selected one or more signals of the set of analog signals to the analog summer and substantially isolate a non-selected one or more power detectors of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more signals of the set of analog signals, an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal, and a controller configured to control the set of switching devices.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 17 / 211,769, filed on March 24, 2021, and assigned to the assignee of this application, which is hereby expressly incorporated herein as fully set forth below and used for all applicable purposes. Technical Field

[0003] This disclosure relates generally to wireless communication devices, and particularly to a transmitter output signal power measurement device. Background Technology

[0004] Wireless communication devices typically include transceivers or transmitters for transmitting radio frequency (RF) signals to another wireless communication device, such as a base station (BS) or user equipment (UE). To improve transmit gain (and receive gain), the transceiver or transmitter is configured with a set of transmit chains, each coupled to a set of antennas (e.g., an antenna array). The transmit chains can be configured to beamform through the antenna array, resulting in a significant increase in transmit gain in a specific direction and a significant decrease in transmit gain in other directions. The direction of maximum gain is generally directed towards the destination wireless communication device from which the RF signal is transmitted.

[0005] Each transmitter in a transmitter chain includes a power amplifier (PA) to amplify the transmitted signal so that the destination device can successfully receive and process it. However, the transmitted signal power output by the PA should be below a certain limit to prevent damage to the PA. Furthermore, for safety and interference control purposes, there are governmental or other regulations that limit the total output signal power of the transmitter. Therefore, to protect the PA and meet regulatory requirements, the transmitter's output signal power should be measured and controlled. Summary of the Invention

[0006] The following presents a simplified overview of one or more implementations to provide a basic understanding of such implementations. This invention is not a comprehensive overview of all considered implementations, nor is it intended to identify key or essential elements of all implementations, nor to depict the scope of any or all implementations. The sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that follows.

[0007] One aspect of this disclosure relates to an apparatus. The apparatus includes: a set of power detectors, each coupled to a set of transmit chains of a transmitter; an analog adder; a first set of switching devices, each coupled between the inputs of the set of power detectors and the analog adder; and an analog-to-digital converter (ADC) including an input coupled to the output of the analog adder and an output configured to generate a first digital signal related to the output power of the transmitter.

[0008] Another aspect of this disclosure relates to an apparatus. The apparatus includes: a set of power detectors configured to generate a set of analog signals, each relating to a power level of a set of output signals from a set of transmit chains of a transmitter; an analog adder; a first set of switching devices configured to transmit one or more selected from the set of analog signals to the analog adder and substantially isolate one or more unselected from the set of power detectors from the analog adder, wherein the analog adder is configured to generate an accumulated analog signal based on the sum of one or more selected from the set of analog signals; an analog-to-digital converter (ADC) configured to generate a first digital signal based on the accumulated analog signal; and a controller configured to control the first set of switching devices.

[0009] Another aspect of this disclosure relates to a method. The method includes generating a set of analog signals, each associated with a set of output signal power levels of a set of transmit chains of a transmitter; summing one or more selected from the set of analog signals to generate an accumulated analog signal; and digitizing the accumulated analog signal to generate a digital signal.

[0010] Another aspect of this disclosure relates to an apparatus. The apparatus includes components for generating a set of analog signals, each related to a set of output signal power levels of a set of transmit chains of a transmitter; components for summing one or more selected from the set of analog signals to generate an accumulated analog signal; and components for digitizing the accumulated analog signal to generate a digital signal.

[0011] To achieve the foregoing and related objectives, one or more implementations include the features fully described below and specifically pointed out in the claims. The following description and figures illustrate certain illustrative aspects of one or more implementations in detail. However, these aspects indicate only a few of the various ways in which the principles of various implementations can be adopted, and the description of implementations is intended to include all such aspects and their equivalents. Attached Figure Description

[0012] Figure 1 A block diagram of an example transmitter of a wireless communication device according to one aspect of this disclosure is shown.

[0013] Figure 2A block diagram / schematic representation of an example transmitter output signal power measurement circuit according to another aspect of this disclosure is shown.

[0014] Figure 3 A block diagram / schematic representation of another example transmitter output signal power measurement circuit according to another aspect of this disclosure is shown.

[0015] Figure 4 A schematic diagram of an example power detector according to another aspect of this disclosure is illustrated.

[0016] Figure 5 A block diagram / schematic representation of another example transmitter output signal power measurement circuit according to another aspect of this disclosure is shown.

[0017] Figure 6A The diagram illustrates a schematic of another example transmitter output signal power measurement circuit according to another aspect of this disclosure.

[0018] Figure 6B The illustration shows a device in power measurement mode according to another aspect of this disclosure. Figure 6A A schematic diagram of an example transmitter output signal power measurement circuit.

[0019] Figure 6C The illustration shows a device in offset calibration mode according to another aspect of this disclosure. Figure 6A A schematic diagram of an example transmitter output signal power measurement circuit.

[0020] Figure 6D The illustration shows a device in offset calibration mode according to another aspect of this disclosure. Figure 6A A schematic diagram of an example transmitter output signal power measurement circuit.

[0021] Figure 7 The figure shows a timing diagram illustrating an example operation of a transmitter output signal power measurement circuit according to another aspect of this disclosure.

[0022] Figure 8 A block diagram of an example decimation filter according to another aspect of this disclosure is illustrated.

[0023] Figure 9 A block diagram of an example offset correction circuit according to another aspect of this disclosure is shown.

[0024] Figure 10 A flowchart illustrating an example method for detecting the output signal power of a transmitter according to another aspect of this disclosure is shown.

[0025] Figure 11 A block diagram of an example wireless communication device according to another aspect of this disclosure is illustrated. Detailed Implementation

[0026] The specific embodiments described below with reference to the accompanying drawings are intended as descriptions of various configurations, and not as representations of only configurations in which the concepts described herein can be practiced. The specific embodiments include particular details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0027] Figure 1 The illustration shows a block diagram of an example transmitter 100 of a wireless communication device according to one aspect of the present disclosure. Transmitter 100 includes a modem (demodulator) 105, a mixer 110, a local oscillator (LO) 115, a radio frequency (RF) filter 120, a set of transmit chains 125-1 to 125-N, and a set of antennas ANT1 to ANT configured as an antenna array. N The transmitter 100 also includes a power measurement circuit 150 and a power / beamforming controller 155. The transmitter chains 125-1 to 125-N each include a set of preamplifiers 130-1 to 130-N, a set of phase shifters 135-1 to 135-N, and a set of power amplifiers PA1 to PA2. N A set of couplers X1 to X N and a set of power detectors PDET1 to PDET N It should be understood that the configuration or architecture of each of the transmitter chains 125-1 to 125-N may vary (e.g., in other configurations of transmitter chains 125-1 to 125-N, the phase detector may be located in different positions), but for the concepts described herein, a power detector or a power detector coupled to it should be included.

[0028] Data to be transmitted to the destination wireless communication device is applied to modem 105. Modem 105 processes the data (e.g., performs error correction coding on the data, scrambles the data, performs quadrature modulation on the coded and / or scrambled data to generate symbols, performs inverse fast Fourier transform (IFFT) on the symbols to generate orthogonal frequency division multiplexing (OFDM) signals, and converts OFDM signals to analog signals, etc.) to generate a baseband transmit signal BBTX. Mixer 110 mixes the baseband transmit signal BBTX with the LO signal generated by LO 115 to generate a mixed signal. RF filter 120 filters the mixed signal to substantially remove the lower frequency components of the mixed signal to generate an RF signal. The RF signal is applied to the inputs of the set of transmit chains 125-1 to 125-N.

[0029] Although in this example the baseband transmit signal BBTX is directly converted into an RF signal via mixer 110, LO 115, and RF filter 120, it should be understood that the transceiver can perform multiple upconversions, such as one conversion from baseband (BB) to intermediate frequency (IF) and another conversion from IF to RF. Furthermore, modem 105, power measurement circuitry 150, and power / beamforming controller 155 may be part of a baseband chip or IC, and the upconversion circuitry (e.g., mixer 110, LO 115, and RF filter 120) and the transmit chains 125-1 to 125-N may be decoupled from the baseband chip or IC. The configuration and architecture of the baseband and IF / RF sections of transmitter 100 can vary significantly.

[0030] Depending on whether the RF signal is omnidirectional or directional, one or more of the transmitter chains 125-1 to 125-N can preamplify, phase-shift, and power amplify the RF signal. For example, the preamplifiers 130-1 to 130-N are configured to achieve gains A1 to A2 respectively. N Amplify the RF signal. The phase shifters 135-1 to 135-N are configured to shift the pre-amplified RF signal by φ1 to φN, respectively. Power amplifiers PA1 to PA2 N Configured to power amplify the pre-amplified and phase-shifted RF signals to generate a set of RF transmit signals RFTX1 to RFTX, respectively. N RF transmission signals RFTX1 to RFTX N Antennas ANT1 to ANT are provided to this group of antennas. N (For example, an antenna array) is used to wirelessly transmit to one or more destination wireless communication devices.

[0031] For transmitter output signal power measurement, detection, and control, this group of power detectors PDET1 to PDET... N Each via the coupler set X1 to X N Receive the RF transmission signals RFTX1 to RFTX of this group. N The sample. This group of power detectors PDET1 to PDET. N The sampled RF transmit signals RFTX1 to RFTX N Rectification and filtering are performed to generate a set of analog signals P1 to P1 respectively. N The set of analog signals P1 to P... N (Can be voltage or current), respectively connected to the RF transmit signals RFTX1 to RFTX at the outputs of the transmit chains 125-1 to 125-N. N The power level is related. This group of analog signals P1 to P... N It is provided to the power measurement circuit 150.

[0032] Based on the control signal CNTL1 (e.g., codebook) from the modem 105, the power measurement circuit 150 processes the analog signals P1 to P2. N The set of values ​​is used to generate a power signal P that indicates or relates to the detection of the total output signal power of transmitter 100. T For example, the detected power signal P T It can be substantially averaged with one or more selected analog signals P1 to P over a programmable time interval. N The sum is related, and for the power detectors PDET1 to PDET N Analog signals P1 to P1 caused by non-ideal operation or process defects in the group N Offsets in the group (e.g., DC voltage or current offsets) and any nonlinearities for the power measurement circuit 150 are corrected, as discussed further herein.

[0033] Based on another control signal CNTL2 from modem 105, power / beamforming controller 155 receives and processes the detected power signal PT to control the gain A1 to A2 of the preamplifiers 130-1 to 130-N respectively. N And the phase shifts φ1 to φN of the group of phase shifters 135-1 to 135-N. This is done to control the total output signal power of the transmitter 100, thereby preventing damage to the power amplifiers PA1 to PA2. N And it complies with government or other regulatory requirements. Additionally, in the case of directional transmission, the power / beamforming controller 155 sets the gain A1 to A2 of the preamplifier group 130-1 to 130-N. N The phase shifters 135-1 to 135-N are phase shifted by φ1 to φN to adjust the antenna arrays ANT1 to ANT2. N The resulting radiation pattern beamforming results in a gain that is substantially maximized or greater in a particular direction (e.g., toward the destination wireless communication device) compared to other directions.

[0034] Figure 2 A diagram of an example transmitter output power measurement circuit 200 according to another aspect of this disclosure is illustrated. The power measurement circuit 200 may be an example detailed implementation of the power measurement circuit 150 discussed earlier. Specifically, the power measurement circuit 200 includes a set of switching devices SW1 to SW2. N The circuit includes a switching network 205, an analog adder 215, an analog-to-digital converter (ADC) 220, and digital processing circuitry 225. The power measurement circuit 200 may also include a switch controller 210 coupled to the group of switching devices SW1 to SW2. N To control their corresponding open / closed states.

[0035] The group of switching devices SW1 to SW in the switching network 205 N Coupled to the power detectors PDET1 to PDET in this group N Between the inputs of analog adder 215 and one or more of the inputs. More specifically, this group of switching devices SW1 to SW2... N Includes a first set of terminals, which are coupled to the power detectors PDET1 to PDET. N To receive the set of analog signals P1 to P1 respectively from it N The group of switching devices SW1 to SW N This includes a second set of terminals that are coupled to one or a set of inputs of the analog adder 215. This set of switching devices SW1 to SW2... N Includes a set of control inputs coupled to a switch controller 210 to receive control signals from it to control their respective open / closed states. The switch controller 210 may in turn be coupled to a modem 105 to receive a control signal CNTL1 that manages one or more selected switching devices SW1 to SW2. N The time of closing (and opening of one or more unselected switching devices).

[0036] As an example of power measurement mode operation, based on the current transmit profile set by modem 105, transmit chains 125-2 and 125-3 are activated to generate RF transmit signals RFTX2 and RFTX3 respectively based on the RF signal from RF filter 120; while other transmit chains 125-1 and 125-4 to 125-N are inactive. In other words, power measurement channels 2 to 3 are active and channels 1 and 4-N are inactive. Therefore, in response to control signal CNTL1 from modem 105, switch controller 210 closes switching devices SW2 to SW3 and opens switching devices SW1 to SW4 to SW5-3. N The closing of switching devices SW2-SW3 sends analog signals P2 and P3 from power detectors PDET2 and PDET3 to one or more inputs of analog adder 215. Switching devices SW1 to SW4 to SW N The disconnection essentially turns the unselected channel power detectors PDET1 and PDET4 to PDET. N The analog adder 215 is isolated to prevent noise and / or transmit power leakage (e.g., via antenna-to-antenna coupling and / or transmit chain-to-transmit chain coupling) from being applied to one or more inputs of the analog adder 215.

[0037] Analog adder 215 adds one or more selected analog signals P1 to P2 received from switching network 205. NSummation is performed to generate a cumulative analog signal P related to the sum of the received analog signals. S In the example above, analog adder 215 receives analog signals P2 and P3 from switch network 205 and generates a cumulative analog signal P based on the sum of analog signals P2 and P3. S Therefore, the accumulated analog signal P S It is an indication of or related to the output signal power of transmitter 100.

[0038] The ADC 220 will accumulate the analog signal P S Converted into digital signal P DS The digital processing circuit 225 can perform various digital processing operations, such as decimating / averaging the digital signal P over a programmable time interval (e.g., one or more OFDM symbol intervals of the transmitted signal). DS And for power detectors PDET1 to PDET N The set of offsets is used to correct or modify the decimated / averaged digital signal. When transmitter 100 fails to transmit due to a manufacturing defect in the power detectors, this set of power detectors PDET1 to PDET2... N A set of offsets can be generated. These offsets may vary with temperature. If not corrected, the offsets may be interpreted as transmitted power, which leads to an incorrect detection power signal P. T Errors in the digital processing circuit 225. The digital processing circuit 225 can also correct any nonlinearities in the analog adder 215, which may also affect the obtained detected power signal P. T Errors are generated in the process.

[0039] In offset calibration mode, transmitter 100 does not transmit a signal. As discussed further herein, transmitter 100 does not transmit a signal during the time interval between the receive time interval and the subsequent transmit time interval (commonly referred to as the R2T time interval). In calibration mode, switch controller 210 closes the switching device associated with the power detector, whose offset will be measured for use in power measurement mode, and opens the remaining switching devices. (This is related to power detectors PDET1 to PDET...) N The associated offset can be measured in a time-division multiplexing manner.

[0040] For example, if the offset associated with the power detector PDET1 is to be measured, the switch controller 210 closes the switching device SW1 and opens the switching device SW2 to SW. NThe closed switching device SW1 sends an offset to analog adder 215, which in turn sends the offset to ADC 220. ADC 220 digitizes the offset and sends it to digital processing circuit 225, which stores it in memory and subsequently uses it to correct the intermediate detection power signal P. INT To generate the detection power signal P T Measured in a similar manner with other power detectors PDET2 to PDET. N The associated offsets, wherein the memory of the digital processing circuit 225 stores the offsets associated with the power detectors PDET2 to PDET1 respectively. N The associated offset. As mentioned above, the offset of the power detector can be measured during each R2T time interval.

[0041] Figure 3 A block diagram / schematic representation of another example transmitter output power measurement circuit 300 according to another aspect of this disclosure is shown. The power measurement circuit 300 may be another example detailed implementation of the previously discussed power measurement circuit 150. In this example, the power detectors PDET1 to PDET... N The generated set of analog signals P1 to P N These are a set of voltages V1 to V N Therefore, as further discussed herein, the analog adder in the power measurement circuit 300 can be a passive voltage adder. However, it should be understood that the analog adder can be an active analog adder, such as a switched capacitor-based adder. Furthermore, if the power detector is configured to output current instead of voltage, the analog adder can also be configured as a current adder.

[0042] Specifically, the power measurement circuit 300 includes a set of switching devices SW1 to SW2. N The circuit includes a switching network 305, an analog adder 315, an analog-to-digital converter (ADC) 320, and digital processing circuitry 325. The power measurement circuit 300 may also include components coupled to the set of switching devices SW1 to SW2. N The switch controller 310 controls their respective open / closed states.

[0043] The group of switching devices SW1 to SW in the switching network 305 N These power detectors PDET1 to PDET are respectively coupled to the group of power detectors. N Between a set of inputs of the analog adder 315. More specifically, this set of switching devices SW1 to SW2. N Includes a first set of terminals, which are coupled to the power detectors PDET1 to PDET. N To receive the group of voltages V1 to V from it respectivelyN The group of switching devices SW1 to SW N This includes a second set of terminals, each coupled to a set of inputs of the analog adder 315. This set of switching devices SW1 to SW2... N This includes a set of control inputs coupled to a switch controller 310 to receive control signals from which to control their respective open / closed states. The switch controller 310 can also be coupled to a modem 105 to receive a control signal CNTL1 that manages one or more selected switching devices SW1 to SW2. N The time of closing (and opening of one or more unselected switching devices).

[0044] The analog adder 315 includes a set of resistors R1 to R2. N The first group of switching devices SW 11 To SW N1 Second group of switching devices SW 12 To SW N2 The group of resistors R1 to R... N The first group of switching devices SW1 to SW1 are respectively coupled to the switching network 305. N Between. The first group of switching devices SW 11 To SW N1 Resistors R1 to R2 are respectively coupled in this group. N Between the input of the ADC 320 and the second set of switching devices SW. 12 To SW N2 Resistors R1 to R2 are respectively coupled in this group. N and reference voltage source V REF Between. The first group of switching devices SW 11 To SW N1 Second group of switching devices SW 12 To SW N2 It includes a set of control inputs coupled to the switch controller 310 to receive control signals from it to control their respective open / closed states.

[0045] Considering the same power measurement mode example described above, based on the current transmit profile set by modem 105, transmit chains 125-2 and 125-3 are activated to generate RF transmit signals RFTX2 and RFTX3 respectively based on the RF signal from RF filter 120; while other transmit chains 125-1 and 125-4 to 125-N are inactive (e.g., channels 2 to 3 are active, channels 1 and 4-N are inactive). Therefore, in response to the control signal CNTL1 from modem 105, switch controller 310 closes switching devices SW2 to SW3 of switch network 305 and opens switching devices SW1 to SW4 to SW5.N Switching device SW 2- Closing SW3 sends voltages V2 and V3 from power detectors PDET2 and PDET3 to resistors R2 and R3 of analog adder 315. Switching devices SW1 to SW4 to SW N The disconnection essentially associates the analog adder 315 with the power detectors PDET1 and PDET4, which are linked to the unselected channel, to PDET. N Isolation is provided to prevent noise and / or transmit power leakage (e.g., via antenna-to-antenna coupling and / or transmit chain-to-transmit chain coupling) from being applied to the input of analog adder 315.

[0046] Furthermore, in response to the control signal CNTL1, the switch controller 310 closes the first set of switching devices SW of the analog adder 315. 21 and SW 31 (Active Channel) and disconnect the switching device SW 11 and SW 41 To SW N1 (Inactive channel). Additionally, the switch controller 310 disconnects the second set of switching devices SW of the analog adder 315. 22 and SW 32 (Active channel) and close the switching device SW 12 and SW 42 To SW N2 (Inactive channel). Switching element SW 21 and SW 31 The closure of the circuit causes currents, based on the power detector voltages V2 and V3, to flow through resistors R2 and R3 to the input of the ADC 320. The currents at the input of the ADC 320 are summed to generate the accumulated analog signal P. S Switching element SW 12 and SW 42 To SW N2 The closing of resistors R1 and R4 will connect to R N Coupled to reference voltage source V REF The reference voltage source V REF It acts as a virtual ground to reduce noise associated with circuitry in unselected channels. Switching device SW 11 SW 41 To SW N1 SW 22 and SW 32 The disconnection essentially links the input of the ADC 320 to the reference voltage source V. REF Virtual isolation. The accumulated analog signal PS is an indication of or related to the output signal power level of transmitter 100.

[0047] The ADC 320 will accumulate the analog signal P S Converted into digital signal P DS The digital processing circuit 325 can perform various digital processing operations, such as decimating / averaging the digital signal P over a programmable time interval (e.g., one or more OFDM symbol intervals of the transmitted signal). DS For the power detectors PDET1 to PDET in this group N The associated offset is used to correct the decimated / averaged digital signal. The digital processing circuit 325 can also correct any nonlinearity in the analog adder 315, which may also affect the obtained detected power signal P. T Errors are generated in the process.

[0048] As discussed, in the offset calibration mode indicated in the modem control signal CNTL1, transmitter 100 does not transmit a signal. In this mode, switch controller 310 closes the switching device associated with the power detector, whose offset will be measured for subsequent use in the power measurement mode, and opens the remaining switching devices. For example, if the offset associated with power detector PDET1 is to be measured, switch controller 310 closes switching device SW1 (active channel) of switch network 305 and opens switching devices SW2 to SW... N (Inactive channel), close the switching device SW 11 (Active Channel), disconnect switching device SW 21 To SW N1 (Inactive channel) and switching device SW 12 (Active channel), and the switching device SW of the closed analog adder 315. 22 To SW N2 (Inactive channel).

[0049] Closed switching devices SW1 and SW 11 The offset is sent to the input of the ADC 320. The closed switching device SW... 22 To SW N2 Resistors R2 to R2 associated with the unselected channel N Coupled to the reference voltage source V REF The provided virtual ground. The disconnected switching device SW12 essentially isolates the input of the ADC 320 from the virtual ground. The ADC 320 digitizes the offset and sends it to the digital processing circuit 325, which stores it in memory and subsequently uses it to correct the intermediate detection power signal P. INT To generate detection power P T Measured in a similar manner with other power detectors PDET2 to PDET. NThe associated offsets, wherein the memory of the digital processing circuit 325 stores the offsets associated with the power detectors PDET2 to PDET1 respectively. N The associated offset. As mentioned above, it can be time-division multiplexed in R. 2T The offset of the power detector is measured during the time interval.

[0050] Figure 4 A schematic diagram of an example power detector 400 according to another aspect of this disclosure is illustrated. The power detector 400 may include the associated couplers X1 to X2 discussed earlier. N (For example, X) j The power detector PDET1 to PDET N (e.g., PDET) j Detailed example implementations of any of the following are provided. It should be understood that other power detector configurations can be used with the power measurement circuitry described herein. Power detector 400 includes a power detector coupled to an associated coupler 450 (e.g., coupler X). j The rectifier 410, the transimpedance amplifier (TIA) 430 coupled to the rectifier 410, and the reference voltage generator 420 coupled to the TIA 430. The RFTX is located near the coupler 450. j This indicates the corresponding output signal for the corresponding RF transmit chain. It should be understood that coupler 450 can provide RFTX to power detector 400 via resistors or resistor networks, and / or one or more switching devices. j Other circuits are used to replace the signal sample.

[0051] More specifically, rectifier 410 includes a first current source I1, which is series-coupled with a diode-coupled field-effect transistor (FET) M1 (e.g., an n-channel metal-oxide-semiconductor (NMOS) FET) between a high-voltage rail Vdd and a low-voltage rail (e.g., ground). Rectifier 410 also includes a second current source I2, which is series-coupled with an inductor L and a second FET M2 (e.g., an NMOS FET) between the high-voltage rail Vdd and ground. A capacitor C1 is coupled between the node between the second current source I2 and the inductor L and ground. Rectifier 410 also includes a resistor R. 41 The resistor is coupled between the gates of field-effect transistor M1 and field-effect transistor M2. Capacitor C2 is coupled between the gate of FET M2 and the switching device SW. A and SW B Between the common first terminals. Switching device SW A Includes the second terminal coupled to coupler 450. Switching device SW B Includes a second terminal coupled to ground.

[0052] Reference voltage generator 420 provides DC reference voltage V for TIA 440. N The reference voltage generator 420 includes a current source I3, which is connected to a resistor R. 42 Series coupling is established between the upper voltage rail Vdd and ground. The reference voltage generator 420 also includes a resistor R. 42 A capacitor C3 is connected in parallel. Additionally, the reference voltage generator 420 includes an operational amplifier 425 configured as a buffer, which includes components coupled to the current source I3 and a resistor R. 42 The positive input terminal of the node and the output terminal coupled to the negative input terminal of operational amplifier 425. The DC reference voltage VN is generated at the output terminal of operational amplifier 425.

[0053] TIA 430 includes operational amplifier 435, which has a negative input terminal coupled to a node between the current source I2 and the inductor L of rectifier 410. Operational amplifier 435 also includes a positive input terminal coupled to the output terminal of operational amplifier 425 of reference voltage generator 420. TIA 430 also includes a feedback capacitor C4 and a feedback resistor R. 43 Both are coupled in parallel between the output terminal and the negative input terminal of operational amplifier 435. The output terminal of operational amplifier 435 is configured to generate a corresponding RF transmit signal RFTX associated with the associated transmit chain in power measurement mode. j The voltage V associated with the power level P And in calibration mode, it is associated with the DC offset of the power detector 400.

[0054] During operation, in power measurement mode, the switching device SW A Close and switch device SW B Disconnect. The sampled RF signal from coupler 450 is rectified by the low-pass filter (LPF) function of FET M2 combined with resistor R41 and capacitor C2. The rectified RF signal causes the gate voltage of FET M2 to change with the RF transmit signal RFTX. j The power level varies; and therefore, the current through FET M2 also varies with the RF transmitted signal RFTX. j The power level varies. Because current source I2 generates a constant current, the difference between the current generated by current source I2 and the current through FET M2 produces a current I4 flowing to TIA 430. Current I4 flows through resistor R. 43 To generate I4*R 43 +V N The relevant voltage V P Therefore, the voltage V PIndicates the RF transmit signal RFTX of the associated transmit chain j The power level or its associated power level.

[0055] In offset calibration mode, the switching device SWA is in the off state and the switching device SW B The circuit is in a closed state. In this configuration, virtually no RF signal is applied from coupler 450 to rectifier 410. Ideally, current sources I1 and I2 generate the same current. And due to the current mirror configuration of FETs M1 and M2 when no RF is applied to rectifier 410, ideally, the current through FET M2 is the same as the current generated by current source I1 (which is the same as the current generated by current source I2). Therefore, ideally, current I4 is zero (0). However, due to a process defect, current sources I1 and I2 do not generate the same current; and therefore, there is a difference between the current generated by current source I2 and the current through FET M2, resulting in a non-zero current I4. Current I4 flows to TIA 430, which generates a current higher than V. N voltage V P The voltage V P This is referred to in this paper as the DC offset of power detector 400.

[0056] Figure 5 A block diagram / schematic representation of another example transmitter output signal power measurement circuit 500 according to another aspect of this disclosure is shown. The power measurement circuit 500 is configured to process signals measured by the power detectors PDET1 to PDET2 respectively. N The generated differential voltage V P1 / V N1 To V PN / V NN The power measurement circuit 500 also includes a differential successive approximation ADC 520 (also known as a sigma-delta quantizer). Additionally, regarding digital processing, the power measurement circuit 500 includes a decimation filter and offset cancellation circuitry.

[0057] Specifically, the power measurement circuit 500 includes a switching network 505, an analog adder 515, an ADC 520, a decimation filter 550, and an offset cancellation circuit 555. As shown, the switching network 505 and the analog adder 515 can be implemented in a set of slices as shown to provide analog signals associated with various transmit chains used for vertical and horizontal spatial processing. The power measurement circuit 500 also includes a switch controller 510 coupled to the modem 105. The switching network 505 includes a first subgroup of switching devices SW. P1 To SW PN The first subgroup of switching devices SW P1 To SW PNIncludes a first terminal, which is coupled to the group of power detectors PDET1 to PDET respectively. N The positive terminals of a set of differential outputs. The first sub-group of switching devices SW P1 To SW PN This includes a second terminal coupled together. The switch network 505 also includes a second subgroup of switching devices SW. N1 To SW NN The second subgroup of switching devices SW N1 To SW NN This includes power detectors PDET1 to PDET1, which are respectively coupled to the group of power detectors. N The first terminal of the negative terminal of this group of differential outputs. The second subgroup of switching devices SW N1 To SW N N Including the second terminal coupled together. Switching device SW P1 To SW PN and SW N1 To SW NN The subgroup includes a set of control inputs that are coupled to the switch controller 510.

[0058] The analog adder 515 includes resistor R P and switching devices SW PA The resistor R P and switching devices SW PA Series coupling of the first subgroup of switching devices SW P1 To SW PN The common second terminal is between the negative terminal of the ADC 520 and the differential input of the ADC 520. Similarly, the analog adder 515 includes a second subgroup of switching devices SW that are series-coupled. N1 To SW NN The resistor R between the common second terminal and the positive terminal of the differential input of the ADC520 N and switching devices SW NA The analog adder 515 also includes a switching device SW. PB The switching device SW PB Coupled to resistor R P and reference voltage source V REF Between. Additionally, the analog adder 515 includes switching device SW. NB The switching device SW NB Coupled to resistor R N and reference voltage source V REF Between. Switching device SW PA SW PB SW NA and SW NBIt includes a set of control inputs that are coupled to the switch controller 510.

[0059] ADC 520 includes operational amplifier 525, which includes a negative and a positive terminal of the differential input of ADC 520. Operational amplifier 525 includes a differential output, which includes a positive and a negative terminal. A feedback capacitor C is coupled between the positive output terminal and the negative input terminal of operational amplifier 525. Another feedback capacitor C is coupled between the negative output terminal and the positive input terminal of operational amplifier 525. ADC 520 also includes successive approximation register (SAR) 530, which includes a differential input coupled to the differential output of operational amplifier 525. SAR 530 includes a feedback output coupled to the input of digital-to-analog converter (DAC) 545. DAC 545 includes a differential output, whose positive and negative terminals are coupled to the negative and positive input terminals of operational amplifier 525, respectively. SAR 530 includes a data output for generating a digital signal PDS and a clock output for generating a clock (CLK) at a frequency having a sampling rate of the digital signal PDS.

[0060] The data and clock outputs of the SAR 530 are coupled to the input of the decimation filter 550. The decimation filter 550 decouples the digital signal P... DS Averaging and decimation are performed to generate a sampling rate lower than that of the digital signal P. DS The intermediate detection power signal P at the sampling rate INT The decimation filter 550 includes an output that is coupled to the input of the offset cancellation circuit 555, where an intermediate detection power signal P is generated. INT The offset cancellation circuit 555 is based on the previous offset cancellation circuit from the power detectors PDET1 to PDET1 during calibration mode. N The measured offset is used to correct / modify the intermediate detection power signal P. INT Furthermore, the intermediate detection power signal P can be further corrected for the nonlinearity of the analog adder 515. INT To generate a transmitter detection power signal P T .

[0061] Considering a power measurement mode example, based on the current transmit profile set by modem 105, transmit chains 125-2 and 125-3 are active (e.g., active channels 2 to 3) to generate RF transmit signals RFTX2 and RFTX3 respectively based on the RF signal from RF filter 120; while other transmit chains 125-1 and 125-4 to 125-N are inactive (e.g., inactive channels 1 and 4-N). Therefore, based on modem control signal CNTL1, switch controller 510 closes the differential switching device SW of switch network 505.P2 / SW N2 and SW P3 / SW N3 (Active channel) and disconnect the remaining differential switching devices SW P1 / SW N1 and SW P4 / SW N4 To SW PN / SW NN (Inactive channel). Differential switching device SW P2 / SW N2 and SW P3 / SW N3 The closing of the differential voltage V P2 / V N2 and V P3 / V N3 The differential input is sent to the analog adder 515. Differential switching device SW P1 / SW N1 and SW P4 / SW N4 To SW PN / SW NN The disconnection essentially connects the differential input of analog adder 515 to power detectors PDET1 and PDET4, which are associated with inactive channels, respectively. N isolation.

[0062] Furthermore, based on the modem control signal CNTL1, the switch controller 510 closes the switching device SW of the analog adder 515. PA and SW NA And disconnect the switching device SW of analog adder 515. PB and SW NB Based on the differential voltage V of the power detector P2 / V N2 and V P3 / V N3 Switching element SW PA and SW NA The closure of the resistor causes current to flow through the resistor R. P and R N The current flows to the differential input of the ADC 520. The current at the differential input of the ADC 520 is summed to produce the accumulated analog signal PS. Switching device SW PB and SW NB The disconnection essentially links the differential input of the ADC 520 to the reference voltage source V. REF Provides virtual ground isolation. Accumulates analog signal P S It is an indication of or related to the output signal power of transmitter 100.

[0063] Through a series of successive approximation cycles, the ADC 520 accumulates the analog signal P. S Converted into digital signal PDS and expressed as digital signal P DS The sampling rate generates the frequency of the clock (CLK). As mentioned earlier, the decimation filter 550 pairs the digital signal P. DS Averaging and decimation are performed to generate a sampling rate lower than that of the digital signal P. DS The intermediate detection power signal P at the sampling rate INT The offset cancellation circuit 555 is based on the previous offset cancellation circuit from the power detectors PDET1 to PDET1 during calibration mode. N The measured offset is used to correct / modify the intermediate detection power signal P. INT Furthermore, the intermediate detection power signal P can be further corrected for nonlinearities associated with the analog adder 515. INT To generate the transmitter detection power signal P T .

[0064] As discussed, in offset calibration mode, transmitter 100 does not transmit a signal based on modem control signal CNTL1. Switch controller 510 closes the differential switch associated with the power detector, whose offset will be measured for subsequent use in power measurement mode, and disconnects the remaining differential switches. For example, if the offset associated with power detector PDET1 is to be measured, switch controller 510 closes the differential switch SW of switch network 505. P1 / SW N1 (Active channel), and disconnect the differential switching device SW P2 / SW N2 To SW PN / SW NN (Inactive channel), closed differential switch SW PA / SW NA And disconnect the differential switch SW of analog adder 515. PB / SW NB .

[0065] Differential switching device SW P1 / SW N1 The closing will cause the differential offset voltage V P1 / V N1 The differential input is sent to the analog adder 515. Differential switching device SW P2 / SW N2 To SW PN / SW NN The disconnection essentially connects the differential input of analog adder 515 to the power detectors PDET2 to PDET2, which are associated with the inactive channel, respectively. NIsolation. Based on offset differential voltage V P1 / V N1 Switching element SW PA and SW NA The closure of the resistor causes current to flow through the resistor R. P and R N The current flows to the differential input of the ADC 520. The current at the differential input of the ADC 520 is summed to produce the accumulated analog signal P. S Switching device SW PB and SW NB The disconnection essentially links the differential input of the ADC 520 to the reference voltage source V. REF Virtual isolation.

[0066] By successively approximating the cycle, the ADC 520 digitizes the differential offset voltage and sends it to the decimation filter 550 for averaging and decimation purposes. The averaged / decimated offset voltage is then sent to the offset cancellation circuit 555, which stores it in memory for subsequent correction / modification of the intermediate detection power signal P. INT Measured in a similar manner with other power detectors PDET2 to PDET. N The associated offset voltages, wherein the memory of the offset cancellation circuit 555 stores the voltages associated with the power detectors PDET2 to PDET1 respectively. N The associated offset. As mentioned above, it can be time-division multiplexed in R. 2T The offset of the power detector is measured during the time interval.

[0067] Figure 6A A schematic diagram of an example power measurement circuit 600 according to another aspect of this disclosure is illustrated. In this example, the power measurement circuit 600 includes a switch network configured as a switch matrix. That is, each input of the switch network can be simultaneously and selectively coupled to one or more of a set of N outputs of the switch network.

[0068] In power measurement mode, each switching device couples its input to the output corresponding to the channel being measured; for example, switching device SW1 couples input "1" to output "1", where "1" identifies the channel being measured. In calibration mode, each switching device couples the input of the corresponding channel to be calibrated to two or more of the N outputs of the switching network. Since the offset voltage of each power detector may be relatively small, coupling the input to two or more of the N outputs in the switching network effectively increases the gain associated with routing the offset to the ADC by two or more times (e.g., N times); allowing the ADC and subsequent digital processing circuitry to measure the offset more accurately.

[0069] Specifically, the power measurement circuit 600 includes a switching network 605, an analog adder 615, and a switching controller 610. The power management circuit 600 may also include an ADC and digital processing circuitry as discussed herein with respect to other example implementations.

[0070] The switching network 605 includes a group of N switching devices SW1 to SW2. N This group of N switching devices SW1 to SW N Includes coupling to a set of power detectors PDET1 to PDET N The input terminals are used to receive a set of voltages V1 to V1 respectively. N Each of the switching devices includes a set of throwers configured to couple its input terminal to its output terminal and to the output terminals of one or more other switching devices among N-1 switching devices. For example, switching device SW1 may be configured to couple its input terminal to its output terminal and the output terminal of switching device SW2 to SW1. N Switching device SW2 can be configured to couple its input terminal to its output terminal and to couple the output terminal of switching device SW1 to SW3 to SW4. N Switching device SW3 can be configured to couple its input terminals to its output terminals and to couple the output terminals of switching devices SW1 to SW2 and SW4 to SW1. N ;etc.

[0071] Analog adder 615 can be configured similarly to analog adder 315. That is, analog adder 615 includes a set of resistors R1 to R2. N The first group of switching devices SW 11 To SW N1 Second group of switching devices SW 12 To SW N2 The group of resistors R1 to R... N The group of switching devices SW1 to SW1, respectively coupled to the switching network 605 N and the first group of switching devices SW 11 To SW N1 Between. The first group of switching devices SW 11 To SW N1 Coupled to the group of resistors R1 to R N Between the input of the ADC and the second set of switching devices SW. 12 To SW N2 Coupled to the group of resistors R1 to R N and reference voltage source V REFBetween. The switch controller 610, which can be coupled to modem 105 to receive control signal CNTL1, is respectively coupled to the group of switching devices SW1 to SW1 of switch network 605. N A set of control inputs, and the first set of switching devices SW 11 To SW N1 Second group of switching devices SW 12 To SW N2 A set of control inputs.

[0072] Figure 6B A schematic diagram of an example power measurement circuit 600 in power measurement mode according to another aspect of this disclosure is illustrated. In power management mode, the power measurement circuit 600 is configured to provide an accumulated analog signal P to the ADC related to the total output signal power of the transmitter 100. S .exist Figure 6B In the example, RF transmit chains 125-2 and 125-N can transmit signals to antennas ANT2 and ANT3, respectively. N Provides RF transmit signals RFTX2 and RFTX N Used for transmission (channels 2 and N are active); the remaining transmission chains 125-1 and 125-3 to 125-N-1 are disabled (channels 1 and 3 to N-1 are inactive).

[0073] via control signal CNTL1, modem 105 provides information to switch controller 610 about which transmit chains are enabled and which are disabled; and, in response, switch controller 610 closes switching devices SW2 and SW. N And disconnect the switching devices SW1 and SW3 of the switching network 605 to SW N-1 Furthermore, in response to the control signal CNTL1, the switch controller 610 closes the first set of switching devices SW of the analog adder 615. 21 and SW N1 (Active Channel) and disconnect the switching device SW 11 and SW 31 To SW N-11 (Inactive channel). Additionally, in response to control signal CNTL1, switch controller 610 closes switch device SW. 12 SW 32 To S WN-22 (Inactive channel), and disconnect the second set of switching devices SW of analog adder 615. 22 and SW N2 (Active Channel)

[0074] Therefore, the power detectors PDET2 and PDET of the enable emitter chains 125-2 and 125-N are... NThe voltages V2 and V N Through closed switching devices SW2 and SW respectively N Provided to analog adder 615. Disconnected switching devices SW1 and SW3 to SW N-1 The analog adder 615 is connected to the power detectors PDET1 and PDET3 to PDET3 of the power-disabled emitter chains 125-1, 125-3 to 125-N-1, respectively. N Basic isolation. Closed switching device SW 21 and SW N1 Through resistors R2 and R N Transmitting current, as voltages V2 and V N The summation of the inputs to the ADC generates an accumulated analog signal P for digitization purposes. S Switching device SW 12 and SW 32 To SW N-12 The closing of the reference voltage source V REF Virtual coupling is provided to these switching devices for noise reduction purposes. Switching device SW 11 SW 22 SW 31 To SW N-11 and SW N2 The disconnection essentially links the ADC input to the reference voltage source V. REF Virtual isolation.

[0075] Figure 6C A schematic diagram of an example power measurement circuit 600 in offset calibration mode according to another aspect of this disclosure is illustrated. In offset calibration mode, the power measurement circuit 600 is configured to provide the set of power detectors PDET1 to PDET to the ADC in a time-division multiplexed manner. N offset voltage V OFS1 To V OFSN .exist Figure 6C In the example, for digitization purposes, the offset voltage V of the power detector PDET2 is... OFS2 The input provided to the ADC.

[0076] Modem 105 instructs switch controller 610 to execute commands via control signal CNTL1 to power detectors PDET1 to PDET. N Associated offset calibration. In this example, the offset voltage V of the power detector PDET2 is measured. OFS2 During the time-division multiplexing cycle, the switch controller 610 configures the switching device SW2 to couple its input terminals to the switching devices SW1 to SW2 respectively. N The output terminals. The switch controller 610 is also equipped with switching devices SW1 and SW3 to SW4.N This is to decouple their input terminals from the output terminals of the switch network 605. Furthermore, the switch controller 610 closes the first set of switching devices SW in the second set of switching devices of the analog adder 615. 11 To SW N1 And disconnect the second set of switching devices SW 12 To SW N2 .

[0077] Therefore, the offset voltage V of the power detector PDET2 OFS2 respectively via the input terminal of switching device SW2 and switching device SW1 to SW N The output terminals are supplied to the analog adder 615. Switching devices SW1 and SW3 to SW N Configured to decouple their input terminals from the output terminals of the switching network 605, the switching devices essentially connect the analog adder 615 to the power detectors PDET1 and PDET3 associated with the inactive channel, respectively. N Isolation. Closed switching device SW 11 To SW N1 The current is routed through resistor R1 to R N The offset voltage V to be summed at the input of the ADC OFS2 The result is used to digitally generate an offset signal from the power detector PDET2. Switching device SW 12 To SW N2 The disconnection essentially links the ADC input to the reference voltage source V. REF Virtual isolation.

[0078] Figure 6D A schematic diagram of an example power measurement circuit 600 in offset calibration mode according to another aspect of this disclosure is illustrated. Figure 6C In the example, the switching network 605 and the analog adder 615 are configured to provide the offset voltage V of the power detector PDET2 to the input of the ADC via N channels of the analog adder 615. OFS2 However, it should be understood that the offset voltage of any power detector can be provided to the input of the ADC via fewer than N channels. For example, in Figure 6D In the example, the offset voltage V of the power detector PDET2 OFS2 Channels 1 to 3 (where N>3) of the analog adder 615 are provided to the input of the ADC.

[0079] Modem 105 instructs switch controller 610 to execute commands via control signal CNTL1 to power detectors PDET1 to PDET. NAssociated DC offset calibration. In this example, the offset V of the power detector PDET2 is measured. OFS2 During the time-division multiplexing cycle, the switch controller 610 configures the switch device SW2 to couple its input terminals to the output terminals of the switch devices SW1 to SW3, respectively. The switch controller 610 also configures the switch devices SW1 and SW3 to SW2... N This is to decouple their input terminals from the output terminals of the switch network 605. Furthermore, the switch controller 610 closes the switching devices SW. 11 To SW 31 And disconnect the switching device SW 12 To SW 32 (Active channel), and close the switching device SW 42 To SW N2 And disconnect the switching device SW of the analog adder 615. 41 and SW N1 (Inactive channel).

[0080] Therefore, the offset voltage V of the power detector PDET2 OFS2 The input terminals of switching device SW2 and the output terminals of switching devices SW1 to SW3 are respectively supplied to the analog adder 615. Switching devices SW1 and SW3 to SW3... N Configured to decouple their input terminals from the output terminals of the switching network 605 to connect the analog adder 615 to the power detectors PDET1 and PDET3 associated with the inactive channel, respectively. N Basic isolation. Closed switching device SW 11 To SW 31 The current is routed through resistors R1 to R3, serving as the offset voltage V to be summed at the input for digitization purposes. OFS2 The result. Switching device SW 42 To SW N2 The closing will be caused by the reference voltage source V REF Virtual coupling is provided to these switching devices for noise reduction purposes. Furthermore, the switching device SW... 41 To SW N1 The disconnection essentially links the ADC input to the reference voltage source V. REF Virtual isolation.

[0081] Figure 7The figure illustrates a timing diagram depicting an example operation of a transmitter output power measurement 700 according to another aspect of this disclosure. The horizontal axis of the graph represents time. The various time intervals depicted as connected rectangles represent modes of operation of the modem 105. For example, from left to right, the modem 105 operates in a receive (Rx) mode, followed by a receive-to-transmit (R2T) switching mode, and then a transmit mode comprising a set of OFDM transmit symbol intervals S1 to SK.

[0082] As previously stated, since transmitter 100 does not transmit any signal, modem 105 can configure the power measurement circuitry to offset calibration mode during the R2T conversion interval. It should be understood that modem 105 can also configure the power measurement circuitry to offset calibration mode during the receive (Rx) interval. Modem 105 can configure the power measurement circuitry to measure the transmitter's output signal power over one or more OFDM symbol intervals (such as the OFDM symbol intervals S2 to S4 shown). Although not strictly necessary, the power management circuitry can be configured to begin transmitter power measurement after the first OFDM symbol S1 to allow time for the power measurement circuitry to be configured.

[0083] Figure 8 A block diagram of an example decimation filter 800 according to another aspect of this disclosure is illustrated. The decimation filter 800 may be an example detailed implementation of the previously discussed decimation filter 550. The decimation filter 800 includes a moving average circuit 805, a delay unit 810, an accumulator 815, a counter 820, a multiplier 825, and a divider 830.

[0084] The moving average circuit 805 includes an input coupled to the output of the ADC 520 to receive the digital signal PDS and the clock (CLK), and to perform L1 sampling on the digital signal PDS over a programmable length. DS Averaging is performed to generate a moving average signal P. AVG Due to the digital signal P DS It is a digitized, cumulative analog signal P that is related to or indicates the power of the transmitter's output signal. S Therefore, the moving average signal P AVG1 With digital signal P DS The average transmitter output signal power over the time interval of the L1 sample is correlated with or indicated by the power.

[0085] The accumulator 815 includes a first input coupled to the output of the moving average circuit 805 and a second input coupled to the clock output of the ADC 520 to receive the clock (CLK), and accumulates the moving average signal P over the L2 sample time interval. AVG To generate the cumulative moving average signal PACM Counter 820 is configured to track the number of samples L2 in response to a start / stop signal. In this regard, counter 820 receives a clock (CLK) and a start / stop signal via delay unit 810. Delay unit 810 delays the start / stop signal by a programmable interval of length L1, such that once the moving average circuit 805 generates a moving average signal P based on the L1 samples... AVG Counter 820 starts counting. Multiplier 825 multiplies L1 and L2 to generate LT, where LT represents the accumulation signal P. ACM The total number of samples on which it is based. Divider 830 will accumulate the signal P. ACM Divide by the total number of samples LT to generate the intermediate power signal P. INT Intermediate power signal P INT This is related to or indicates the transmitter output signal power (second order) averaged over an interval of LT samples. The decimation filter 800 has the desired signal-to-quantization ratio (SNQR) and relatively low average error performance.

[0086] Figure 9 A block diagram of an example offset cancellation circuit 900 according to another aspect of this disclosure is illustrated. The offset cancellation circuit 900 may be an example detailed implementation of the previously discussed offset cancellation circuit 555. The offset cancellation circuit 900 includes a memory 910, a correction circuit 915, and a controller 920 (e.g., a finite state machine (FSM)). The controller 920 may be coupled to a modem 105 to receive a control signal CNTL1.

[0087] In the offset calibration mode indicated by modem 105, memory 910 is configured to receive a set of intermediate power signals P in a time-division multiplexed manner. INT The intermediate power signal P of this group INT It can be connected to the power detectors PDET1 to PDET respectively. N The offset is related. Controller 920 causes memory 910 to store the group of intermediate power signals P. INT Stored in, for example, a table, which is also provided to the group of power detectors PDET1 to PDET respectively. N The mapping is as follows. Memory 910 can store other correction parameters, such as corrections for nonlinearities introduced by the analog adder described herein. Nonlinearity corrections can be determined during the factory calibration process.

[0088] In the power measurement mode indicated by modem 105, controller 920 causes memory 910 to receive intermediate power signal P. INT As mentioned earlier, the intermediate power signal P INTThis can be the average or second-order average of the output signal power of transmitter 100 over a certain time interval (e.g., one or more OFDM symbol intervals). Under the control of controller 920, correction circuit 915 accesses the intermediate power signal P from memory 910. INT And one or more associated offsets, and use one or more associated offsets to correct / modify the intermediate power signal P. INT To generate the transmitter detection power signal P T .

[0089] One or more associated offsets are associated with a power detector of an enabled transmit chain, which is used to generate an intermediate power signal P. INT The transmitted signal. For example, if the enabled transmit chains are 125-2 and 125-3 (and the remaining transmit chains 125-1 and 125-4 through 125-N are disabled), the offset associated with power detectors PDET2 and PDET3 is used to correct the intermediate power signal P. INT (with the disabled emitter chains 125-1 and 125-4 to 125-N power detectors PDET1 and PDET4 to PDET) N The associated offset is not used for the intermediate power signal P during the current measurement period. INT ).

[0090] Figure 10 A flowchart illustrating an example method 1000 for measuring the output power of a transmitter signal according to another aspect of this disclosure is shown. Method 1000 includes generating a set of analog signals (block 1010) respectively related to a set of output signal power levels of a set of transmit chains of the transmitter. Examples of components for generating a set of analog signals respectively related to the output signal power levels of a set of transmit chains of the transmitter include a set of power detectors PDET1 to PDET described herein. N .

[0091] Method 1000 further includes summing one or more selected from the set of analog signals to generate an accumulated analog signal (box 1020). Examples of components used for summing one or more selected from the set of analog signals to generate the accumulated analog signal include any analog adder described herein. Furthermore, method 1000 includes digitizing the accumulated analog signal to generate a digital signal (box 1030). Examples of components used for digitizing the accumulated analog signal to generate a digital signal include any ADC described herein.

[0092] Figure 11A block diagram of an example wireless communication device 1100 according to another aspect of this disclosure is illustrated. The wireless communication device 1100 includes an integrated circuit (IC) 1110, a transceiver 1150, and at least one antenna or antenna array 1160. The IC 1110, which can be configured as a system-on-a-chip (SOC), may include one or more digital processing cores 1120 and power measurement circuitry 1130. The one or more digital processing cores 1120 can implement the functions of the modem 105 discussed earlier. That is, the one or more digital processing cores 1120 can be configured to generate a baseband transmit signal BBTX.

[0093] The power measurement circuit 1130 can be configured as any of the power measurement circuits discussed previously. As previously discussed, one or more digital processing cores 1120 can provide a control signal CNTL1 to the power measurement circuit 1130, and the power measurement circuit 1130 can provide a transmitter detection power signal P to one or more digital processing cores 1120. T One or more digital processing cores 1120 can be based on the power measurement signal P. T This generates power / phase A / φ control signals. One or more digital processing cores 1120 can provide baseband transmit signals BBTX and power / phase A / φ control signals to transceiver 1150.

[0094] Transceiver 1150 may include mixer 110, LO 115, RF filter 120, and the previously discussed transmit chains 125-1 to 125-N. Therefore, transceiver 1150 generates the total RF transmit signal RXTX based on the baseband transmit signal BBTX and the power / phase A / φ control signal. The output power and beamforming of transceiver 1150 are controlled by the power / phase A / φ control signal. The power detectors PDET1 to PDET of transceiver 1150... N Analog signals P1 to P1, respectively, are provided that are related to or indicate the output signal power levels of transmitter chains 125-1 to 125-N. N As discussed above, the power measurement circuit 1130 is based on power detectors PDET1 to PDET2 respectively. N Analog signals P1 to P N One or more of them are used to generate the transceiver detection power signal P. T .

[0095] The following provides an overview of the various aspects of this disclosure:

[0096] Aspect 1: An apparatus comprising: a set of power detectors coupled to a set of transmit chains of a transmitter; an analog adder; a first set of switching devices coupled between the set of power detectors and the inputs of the analog adder; and an analog-to-digital converter (ADC) including an input coupled to the output of the analog adder and an output configured to generate a first digital signal related to the output power of the transmitter.

[0097] Aspect 2: The apparatus according to aspect 1, wherein the analog adder includes a set of resistors coupled between a first set of switching devices and the input of the ADC.

[0098] Aspect 3: The apparatus according to aspect 2, wherein the analog adder further includes a second set of switching devices, the second set of switching devices being coupled between the set of resistors and the input of the ADC.

[0099] Aspect 4: According to the apparatus of aspect 3, the analog adder further includes a third set of switching devices, which are coupled between the set of resistors and the reference voltage source.

[0100] Aspect 5: The apparatus according to any one of Aspects 1 to 4, wherein the group of power detectors each includes a group of differential outputs; the first group of switching devices includes a first subgroup of switching devices respectively coupled to the positive terminals of the group of differential outputs of the group of power detectors; and the first group of switching devices includes a second subgroup of switching devices respectively coupled to the negative terminals of the group of differential outputs of the group of power detectors.

[0101] Aspect 6: The apparatus according to aspect 5, wherein the input of the ADC includes a differential input, and wherein the analog adder includes: a first resistor coupled between a first subgroup switching device and a first terminal of the differential input of the ADC; and a second resistor coupled between a second subgroup switching device and a second terminal of the differential input of the ADC.

[0102] Aspect 7: The apparatus according to aspect 6, wherein the analog adder further comprises: a first switching device coupled between a first resistor and a first terminal of the ADC; and a second switching device coupled between a second resistor and a second terminal of the ADC.

[0103] Aspect 8: The apparatus according to aspect 7, wherein the analog adder further comprises: a third switching device coupled between the first resistor and the reference voltage source; and a fourth switching device coupled between the second resistor and the reference voltage source.

[0104] Aspect 9: The apparatus according to any one of aspects 1 to 8, wherein each of the first set of switching devices includes a set of throwers for selectively coupling a first terminal of the first set of switching devices to one or more second terminals of the first set of switching devices.

[0105] Aspect 10: The apparatus according to any one of Aspects 1 to 8, wherein the first group of switching devices is part of a switching matrix, wherein each of the first group of switching devices includes an input terminal configured to selectively and simultaneously couple to one or more output terminals of the first group of switching devices.

[0106] Aspect 11: The apparatus according to any one of aspects 1 to 10 further includes a controller that is coupled to a set of control inputs respectively to the first set of switching devices.

[0107] Aspect 12: The apparatus according to any one of aspects 1 to 11, wherein the ADC includes a successive approximation ADC.

[0108] Aspect 13: The apparatus according to any one of Aspects 1 to 12, wherein the ADC comprises: an operational amplifier including a differential input and a differential output, wherein the input of the ADC includes a differential input; a first capacitor coupled between a positive terminal of the differential output of the ADC and a negative terminal of the differential input of the ADC; a second capacitor coupled between a negative terminal of the differential output of the ADC and a positive terminal of the differential input of the ADC; a successive approximation register (SAR) including a differential input coupled to the differential output of the operational amplifier, a first output configured to generate a first digital signal, and a second output configured to generate a clock having a frequency related to the sampling rate of the first digital signal; and a digital-to-analog converter (DAC) including an input coupled to a third output of the SAR and a differential output coupled to the differential input of the operational amplifier.

[0109] Aspect 14: The apparatus according to any one of aspects 1 to 13 further includes digital processing circuitry, the digital processing circuitry including an input coupled to the output of the ADC and an output configured to generate a second digital signal based on the first digital signal.

[0110] Aspect 15: The apparatus according to aspect 14, wherein the digital processing circuitry includes a decimation filter.

[0111] Aspect 16: The apparatus according to aspect 15, wherein the decimation filter comprises: a moving average circuit including a first input and a second input coupled to a first output and a second output of an ADC, respectively; an accumulator including a first input coupled to the output of the moving average circuit and a second input coupled to the second input of the ADC; a counter including a first input coupled to the second output of the ADC and a second input configured to receive a delayed start / stop signal; and a divider including a first input coupled to the output of the accumulator, a second input coupled to the output of the counter, and an output configured to generate a second digital signal.

[0112] Aspect 17: The apparatus according to aspect 16, wherein the decimation filter further includes a delay unit configured to generate a delayed start / stop signal based on a programmable length of averaging of the first digital signal by a moving average circuit.

[0113] Aspect 18: The apparatus according to any one of aspects 14 to 17, wherein the digital processing circuitry includes an offset cancellation circuitry configured to modify the second digital signal based on a set of offsets respectively associated with one or more of the group of power detectors.

[0114] Aspect 19: An apparatus comprising: a set of power detectors configured to generate a set of analog signals respectively related to a set of output signal power levels of a set of transmit chains of a transmitter; an analog adder; a first set of switching devices configured to transmit one or more selected analog signals from the set of analog signals to the analog adder and substantially isolate one or more unselected power detectors from the set of power detectors from the analog adder, wherein the analog adder is configured to generate an accumulated analog signal based on the sum of the one or more selected analog signals from the set of analog signals; an analog-to-digital converter (ADC) configured to generate a first digital signal based on the accumulated analog signal; and a controller configured to control the first set of switching devices.

[0115] Aspect 20: The apparatus according to aspect 19, wherein the analog adder includes a set of resistors coupled between a first set of switching devices and the input of the ADC.

[0116] Aspect 21: According to the apparatus of aspect 20, the analog adder further includes a second set of switching devices, which are coupled between the set of resistors and the input of the ADC.

[0117] Aspect 22: According to the apparatus of aspect 21, the analog adder further includes a third set of switching devices, which are coupled between the set of resistors and the reference voltage source.

[0118] Aspect 23: The apparatus according to any one of Aspects 19 to 22, wherein the group of power detectors each includes a group of differential outputs; the first group of switching devices includes a first subgroup of switching devices respectively coupled to the positive terminals of the group of differential outputs of the group of power detectors; and the first group of switching devices includes a second subgroup of switching devices respectively coupled to the negative terminals of the group of differential outputs of the group of power detectors.

[0119] Aspect 24: The apparatus according to aspect 23, wherein the input of the ADC includes a differential input, and wherein the analog adder includes: a first resistor coupled between a first subgroup switching device and a first terminal of the differential input of the ADC; and a second resistor coupled between a second subgroup switching device and a second terminal of the differential input of the ADC.

[0120] Aspect 25: The apparatus according to any one of aspects 19 to 24, wherein each of the first set of switching devices includes a set of throwers for selectively coupling a corresponding first terminal to one or more second terminals of the first set of switching devices.

[0121] Aspect 26: The apparatus according to aspect 25, wherein the controller is configured in calibration mode to couple one selected of the first terminals to one or more selected of the second terminals of the first set of switching devices, and to decouple one or more unselected terminals of the first terminals from any of the second terminals of the first set of switching devices.

[0122] Aspect 27: A method comprising: generating a set of analog signals, each relating to a set of output signal power levels of a set of transmit chains of a transmitter; summing one or more selected from the set of analog signals to generate an accumulated analog signal; and digitizing the accumulated analog signal to generate a digital signal.

[0123] Aspect 28: The method according to aspect 27, wherein generating a set of analog signals is performed according to a measurement mode.

[0124] Aspect 29: The method according to aspect 28 further includes: in a calibration mode, generating, in a time-division multiplexing manner, a set of power detector offset voltages associated with the set of transmit chains of the transmitter; and digitizing the set of power detector offset voltages, wherein in a measurement mode, the digital signal is modified based on one or more offset voltages in the set of digitized power detector offset voltages.

[0125] Aspect 30: An apparatus comprising: means for generating a set of analog signals respectively related to a set of output signal power levels of a set of transmit chains of a transmitter; means for summing one or more selected from the set of analog signals to generate an accumulated analog signal; and means for digitizing the accumulated analog signal to generate a digital signal.

[0126] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A set of power detectors, each coupled to a set of transmitter chains; Analog adder; The first set of switching devices is coupled between the set of power detectors and the input of the analog adder, respectively; as well as An analog-to-digital converter (ADC) includes an input coupled to the output of the analog adder and an output configured to generate a first digital signal related to the output power of the transmitter.

2. The apparatus of claim 1, wherein the analog adder comprises a set of resistors, the set of resistors being coupled between the first set of switching devices and the input of the ADC.

3. The apparatus of claim 2, wherein the analog adder further comprises a second set of switching devices, the second set of switching devices being coupled between the set of resistors and the input of the ADC.

4. The apparatus of claim 3, wherein the analog adder further comprises a third set of switching devices, the third set of switching devices being coupled between the set of resistors and the reference voltage source.

5. The apparatus according to claim 1, wherein: Each of the power detectors includes a set of differential outputs; The first group of switching devices includes a first subgroup of switching devices, which are respectively coupled to the positive terminals of the differential outputs of the group of power detectors; as well as The first group of switching devices includes a second subgroup of switching devices, which are respectively coupled to the negative terminals of the differential outputs of the group of power detectors.

6. The apparatus of claim 5, wherein the input of the ADC comprises a differential input, and wherein the analog adder comprises: A first resistor is coupled between the first subgroup of switching devices and the first terminal of the differential input of the ADC; as well as A second resistor is coupled between the second subgroup of switching devices and the second terminal of the differential input of the ADC.

7. The apparatus of claim 6, wherein the analog adder further comprises: A first switching device is coupled between the first resistor and the first terminal of the ADC; as well as A second switching device is coupled between the second resistor and the second terminal of the ADC.

8. The apparatus of claim 7, wherein the analog adder further comprises: A third switching device is coupled between the first resistor and the reference voltage source; as well as A fourth switching device is coupled between the second resistor and the reference voltage source.

9. The apparatus of claim 1, wherein each of the first set of switching devices includes a set of droppers for selectively coupling a first terminal of the first set of switching devices to one or more second terminals of the first set of switching devices.

10. The apparatus of claim 1, wherein the first group of switching devices is part of a switching matrix, wherein each of the first group of switching devices includes an input terminal configured to selectively and simultaneously couple to one or more output terminals of the first group of switching devices.

11. The apparatus of claim 1, further comprising a controller, the controller being coupled to a set of control inputs of the first set of switching devices.

12. The apparatus of claim 1, wherein the ADC comprises a successive approximation ADC.

13. The apparatus of claim 1, wherein the ADC comprises: An operational amplifier, including a differential input and a differential output, wherein the input of the ADC includes the differential input; A first capacitor is coupled between the positive terminal of the differential output and the negative terminal of the differential input of the ADC; A second capacitor is coupled between the negative terminal of the differential output and the positive terminal of the differential input of the ADC; The successive approximation register (SAR) includes a differential input coupled to the differential output of the operational amplifier, a first output configured to generate the first digital signal, and a second output configured to generate a clock having a frequency related to the sampling rate of the first digital signal. as well as The digital-to-analog converter (DAC) includes an input coupled to a third output of the SAR and a differential output coupled to the differential input of the operational amplifier.

14. The apparatus of claim 1, further comprising digital processing circuitry including an input coupled to the output of the ADC and an output configured to generate a second digital signal based on the first digital signal.

15. The apparatus of claim 14, wherein the digital processing circuitry includes a decimation filter.

16. The apparatus according to claim 15, wherein, The output of the ADC is a first output, wherein the decimation filter includes: The moving average circuit includes a first input and a second input, respectively coupled to the first output and the second output of the ADC; The accumulator includes a first input coupled to the output of the moving average circuit and a second input coupled to the second output of the ADC; A counter, including a first input coupled to the second output of the ADC and a second input configured to receive a delayed start / stop signal; and The divider includes a first input coupled to the output of the accumulator, a second input coupled to the output of the counter, and an output configured to generate the second digital signal.

17. The apparatus of claim 16, wherein the decimation filter further comprises a delay unit configured to generate the delayed start / stop signal based on a programmable length of averaging of the first digital signal by the moving average circuit.

18. The apparatus of claim 14, wherein the digital processing circuitry includes an offset cancellation circuit configured to modify the second digital signal based on a set of offsets associated with one or more of the set of power detectors.

19. An apparatus comprising: A set of power detectors is configured to generate a set of analog signals, each related to a set of output signal power levels of a set of transmit chains of the transmitter; Analog adder; A first set of switching devices is configured to send one or more selected analog signals from the set of analog signals to the analog adder and to isolate one or more unselected power detectors from the set of power detectors from the analog adder, wherein the analog adder is configured to generate an accumulated analog signal based on the sum of the one or more selected analog signals from the set of analog signals; An analog-to-digital converter (ADC) includes an input coupled to the output of the analog adder and is configured to generate a first digital signal based on the accumulated analog signal; as well as The controller is configured to control the first group of switching devices.

20. The apparatus of claim 19, wherein the analog adder comprises a set of resistors, the set of resistors being coupled between the first set of switching devices and the input of the ADC.

21. The apparatus of claim 20, wherein the analog adder further comprises a second set of switching devices, the second set of switching devices being coupled between the set of resistors and the input of the ADC.

22. The apparatus of claim 21, wherein the analog adder further comprises a third set of switching devices, the third set of switching devices being coupled between the set of resistors and the reference voltage source.

23. The apparatus according to claim 19, wherein: Each of the power detectors includes a set of differential outputs; The first group of switching devices includes a first subgroup of switching devices, which are respectively coupled to the positive terminals of the differential outputs of the group of power detectors; as well as The first group of switching devices includes a second subgroup of switching devices, which are respectively coupled to the negative terminals of the differential outputs of the group of power detectors.

24. The apparatus of claim 23, wherein the input of the ADC comprises a differential input, and wherein the analog adder comprises: A first resistor is coupled between the first subgroup of switching devices and the first terminal of the differential input of the ADC; as well as A second resistor is coupled between the second subgroup of switching devices and the second terminal of the differential input of the ADC.

25. The apparatus of claim 19, wherein each of the first set of switching devices includes a set of droppers for selectively coupling a corresponding first terminal to one or more second terminals of the first set of switching devices.

26. The apparatus of claim 25, wherein the controller is configured in calibration mode to couple one selected terminal of the first terminals to one or more selected terminals of the second terminals of the first set of switching devices, and to decouple one or more unselected terminals of the first terminals from any of the terminals of the second terminals of the first set of switching devices.

27. A method for communication, comprising: Generate a set of analog signals, each related to a set of output signal power levels of a set of transmit chains of the transmitter; Summing one or more selected analog signals from the set of analog signals to generate a cumulative analog signal; as well as The accumulated analog signal is digitized to generate a digital signal.

28. The method of claim 27, wherein generating the set of analog signals is performed according to a measurement mode.

29. The method of claim 28, further comprising: In calibration mode, a set of power detector offset voltages associated with the set of transmit chains of the transmitter are generated in a time-division multiplexing manner; as well as The set of power detector offset voltages is digitized, wherein the digital signal is modified in measurement mode based on one or more offset voltages from the set of digitized power detector offset voltages.

30. An apparatus comprising: A component used to generate a set of analog signals that are respectively related to the power levels of a set of output signals of a set of transmit chains of the transmitter; A component for summing one or more analog signals selected from the set of analog signals to generate a cumulative analog signal; as well as A component used to digitize the accumulated analog signal to generate a digital signal.

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