A hardware search method and system, an electronic device, and a storage medium

Abstract

The present application provides a hardware search method and system, an electronic device, and a storage medium, belonging to the field of microelectronic digital circuit design. The method includes: obtaining an array from original data; setting a first string such that each bit of the string corresponds to an array element; selecting an element from the array as axis data; comparing the elements in the array with the axis data to obtain a plurality of first results, second results, and third results; arranging the various results respectively to obtain various result vectors; performing bitwise summation on the various result vectors respectively to obtain a first element quantity, a second element quantity, and a third element quantity; detecting the three types of element quantities to obtain a detection result; if the detection result indicates that the hardware search meets the requirements, then taking the axis data as target data. The present application can overcome the shortcomings of the existing search methods, such as long calculation cycles and difficulty in hardware implementation, and at the same time meet the requirements of less resource consumption and higher real-time performance.

Description

Technical Field

[0001] This application relates to the field of microelectronic digital circuit design, and particularly to a hardware search method and system, an electronic device, and a storage medium. Background Art

[0002] Finding the k-th (1 ≤ k ≤ N) smallest number in an array of length N is one of the common operations in data processing. With the development of communication technology, the amount of data to be processed has increased and the requirement for processing real-time performance has been improved. In recent years, many search methods have been proposed to solve this problem, and the search methods are divided into software methods and hardware methods according to the implementation manner.

[0003] In related technologies, the hardware methods mainly include sequential comparison, bitonic sorting, recursive search, etc.

[0004] The sequential comparison method uses N comparators to compare all elements in array A with A[i] (i = 0, …, N - 1) in the i-th iteration, and obtains the number c[i] of elements in A that are smaller than A[i]. After the comparison, the element with c[i] == k - 1 is found, so as to implement the search for the k-th smallest number. The sequential comparison method can be implemented by hardware, and the time complexity is Ο(N). Although this method is relatively simple, when N is large, on average, N / 2 comparisons are required to obtain the element with c[i] == k - 1, that is, the time complexity is Ο(N), and the time complexity is too large.

[0005] The bitonic sorting method uses a bitonic sorting network to sort the array. After sorting, the entire array is arranged in ascending order, and the k-th element after sorting is the k-th smallest element, and the time complexity is Ο((logN) 2 ). The time complexity of this method is also relatively large.

[0006] The recursive search method first selects the pivot data in each recursion, and then partitions the array, dividing the data smaller than the pivot data into the left sub-array and the data greater than or equal to the pivot data into the right sub-array. The position of the pivot data after partitioning is used to determine whether the k-th smallest element is in the left sub-array or the right sub-array, and then the recursive process is executed again on the sub-array where the k-th smallest element is located until there is only 1 element left in the sub-array. After the recursion ends, the remaining element is the k-th smallest element. This method is implemented by software, and the expected running time is Ο(N), and the time complexity in the worst case is Ο(N 2)。Although the recursive search method is relatively simple to implement in software, it is not suitable for direct hardware implementation. Because in the existing direct hardware implementation, each division requires pairwise comparison and exchange of elements to divide the data smaller than the pivot data into the left subarray and the data greater than or equal to the pivot data into the right subarray. This is equivalent to an N×N crossbar network in hardware implementation, which will consume a large amount of cross-interconnection lines and mux resources, resulting in a relatively high hardware complexity. If a non-full cross-interconnection serial method is used for implementation, it will require a long division time, making the hardware implementation meaningless.

[0007] It can be seen that the above search methods all require a long time, which will affect the efficiency of hardware implementation. In addition, due to the long time spent, problems such as large resource consumption will also occur. Summary of the Invention

[0008] The main purpose of the embodiments of the present application is to propose a hardware search method and system, an electronic device, and a storage medium, aiming to overcome the disadvantages of the existing search methods with long calculation cycles and difficulty in hardware implementation, and at the same time meet the requirements of less resource consumption and higher real-time performance.

[0009] To achieve the above object, a first aspect of the embodiments of the present application proposes a hardware search method, and the method includes:

[0010] Input the original data into the register array to obtain an ordered array, where the ordered array includes a plurality of elements arranged in sequence, set the subscript of the first element of the ordered array to 0, and starting from the first element, the subscripts of the plurality of elements increase in sequence;

[0011] Set a first string, the first string is a binary string, and each digit of the binary string is 1; where the last digit of the first string corresponds to the first element of the ordered array, and starting from the last digit, each digit of the first string corresponds to an element in the ordered array in sequence;

[0012] Select an element from the plurality of elements in the ordered array as the pivot data;

[0013] Compare the elements in the ordered array with the pivot data to obtain a plurality of first results, second results, and third results, where the first result is determined according to the elements smaller than the pivot data, the second result is determined according to the elements not smaller than the pivot data, and the third result is determined according to the elements equal to the pivot data;

[0014] Arrange multiple first results to obtain a first result vector; arrange multiple second results to obtain a second result vector; arrange multiple third results to obtain a third result vector;

[0015] Perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element count corresponding to the first result vector, a second element count corresponding to the second result vector, and a third element count corresponding to the third result vector;

[0016] Detect the first element count, the second element count, and the third element count to obtain a detection result, and the detection result is used to indicate whether the hardware search meets the requirements;

[0017] If the detection result indicates that the hardware search meets the requirements, then use the axis data as the target data, and the target data is the data ranked at a predetermined position when the numbers in the original data are sorted in ascending order.

[0018] In some embodiments, the comparing the elements in the ordered array with the axis data to obtain multiple first results, second results, and third results includes:

[0019] For each element, compare the element with the axis data;

[0020] If the element is less than the axis data and the digit corresponding to the element in the first string is 1, then determine that the first result corresponding to the element is 1; otherwise, determine that the first result corresponding to the element is 0;

[0021] If the element is not less than the axis data and the digit corresponding to the element in the first string is 1, then determine that the second result corresponding to the element is 1; otherwise, determine that the second result corresponding to the element is 0;

[0022] If the element is equal to the axis data and the digit corresponding to the element in the first string is 1, then determine that the third result corresponding to the element is 1; otherwise, determine that the third result corresponding to the element is 0.

[0023] In some embodiments, the selecting an element from the multiple elements in the ordered array as the axis data includes:

[0024] Perform a bitwise AND operation on the first string and a pre-generated random vector to obtain a first vector;

[0025] If the first vector is a vector of all zeros, select the element corresponding to the lowest bit that is 1 in the first string as the axis data, and generate a second vector, where the second vector is obtained by retaining the digit at the position corresponding to the axis data in the first string as 1 and setting the digits at the positions in the first string that do not correspond to the axis data to 0;

[0026] If the first vector is not a vector of all zeros, select the element corresponding to the lowest bit that is 1 in the first vector as the axis data, and generate a second vector, where the second vector is obtained by retaining the digit at the position corresponding to the axis data in the first vector as 1 and setting the digits at the positions in the first vector that do not correspond to the axis data to 0.

[0027] In some embodiments, the detecting the first element quantity, the second element quantity, and the third element quantity to obtain a detection result includes:

[0028] If the first element quantity, the second element quantity, and the third element quantity satisfy at least one of the following conditions, the detection result is that the hardware search meets the requirements;

[0029] The conditions include:

[0030] The sum of the first element quantity and the second element quantity is equal to the third element quantity;

[0031] The sum of the first element quantity and the second element quantity is not greater than 1;

[0032] The sum of the first element quantity and 1 is equal to the value corresponding to the predetermined ranking.

[0033] In some embodiments, if the detection result indicates that the hardware search does not meet the requirements, the method further includes:

[0034] Judge whether the value is less than the sum of the first element quantity and 1 to obtain a judgment result;

[0035] If the judgment result indicates that the value is less than the sum of the first element quantity and 1, keep the value unchanged and assign the second result vector to the first string;

[0036] Return to the step of selecting an element from the multiple elements in the ordered array as the axis data.

[0037] In some embodiments, if the judgment result indicates that the value is not less than the sum of the first element quantity and 1, the method further includes:

[0038] Subtract the numerical value from the first element quantity and 1 in sequence, and use the subtraction result as the updated numerical value corresponding to the predetermined rank;

[0039] Perform a NOT operation on the second vector to obtain a third vector;

[0040] Perform an AND operation on the second result vector and the third vector to obtain a fourth vector;

[0041] Assign the fourth vector to the first string;

[0042] Return to the step of selecting an element from multiple elements in the ordered array as axis data.

[0043] To achieve the above object, a second aspect of the embodiments of the present application proposes a hardware search system, the system includes:

[0044] A data input control unit, which is used to convert the input original data into an ordered array;

[0045] A control unit, the control unit is connected to the data input control unit, and the control unit is used to receive the ordered array and select an element from multiple elements in the ordered array as axis data; the control unit is used to set a first string;

[0046] A comparison unit, the comparison unit is respectively connected to the control unit and the data input control unit, and the comparison unit is used to receive the ordered array output by the data input control unit, and the axis data and the first string output by the control unit, and compare the elements in the ordered array with the axis data to obtain a plurality of first results, second results, and third results, wherein the first result is determined according to the elements less than the axis data, the second result is determined according to the elements not less than the axis data, and the third result is determined according to the elements equal to the axis data;

[0047] An aggregation unit, the aggregation unit is connected to the control unit and the comparison unit, and the aggregation unit is used to receive the plurality of first results, second results, and third results output by the comparison unit, arrange the plurality of first results to obtain a first result vector; arrange the plurality of second results to obtain a second result vector; arrange the plurality of third results to obtain a third result vector; and perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element quantity corresponding to the first result vector, a second element quantity corresponding to the second result vector, and a third element quantity corresponding to the third result vector;

[0048] The control unit is further configured to detect the number of the first elements, the number of the second elements, and the number of the third elements to obtain a detection result, where the detection result is used to indicate whether the hardware search meets the requirements; and when the detection result indicates that the hardware search meets the requirements, output the axis data as target data, where the target data is the data ranked at a predetermined position when the numbers in the original data are sorted in ascending order.

[0049] In some embodiments, the system further includes:

[0050] The comparison unit includes a comparator, and the comparator is configured to compare the elements in the ordered array with the axis data to obtain a plurality of first results, second results, and third results;

[0051] The aggregation unit includes an adder and a register. The adder is configured to perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain the number of the first elements corresponding to the first result vector, the number of the second elements corresponding to the second result vector, and the number of the third elements corresponding to the third result vector. The register is configured to store the first result vector, the second result vector, and the third result vector.

[0052] To achieve the above object, a third aspect of the embodiments of the present application provides an electronic device, where the electronic device includes a storage unit and a plurality of execution units. The storage unit is configured to store input data, and the storage unit is further configured to store calculation intermediate results. The execution unit executes the steps of the method described in the first aspect above.

[0053] To achieve the above object, a fourth aspect of the embodiments of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program or circuit configuration information, and when the computer program is executed by a processor, the method described in the first aspect above is implemented.

[0054] The hardware search method, system, electronic device, and storage medium proposed in this application input the original data into a register array to obtain an ordered array. The ordered array includes multiple elements arranged in sequence. The subscript of the first element of the ordered array is set to 0, and starting from the first element, the subscripts of the multiple elements increase sequentially. A first string is set. The first string is a binary string, and each digit of the binary string is 1. The rightmost digit of the first string corresponds to the first element of the ordered array. Starting from the rightmost digit, each digit of the first string corresponds to an element in the ordered array in sequence, and the situation of each number in the original data can be recorded through the first string. Further, among the multiple elements in the ordered array, an element is selected as the pivot data. The elements in the ordered array are compared with the pivot data to obtain multiple first results, second results, and third results. The first result is determined according to the elements smaller than the pivot data, the second result vector is determined according to the elements not smaller than the pivot data, and the third result vector is determined according to the elements equal to the pivot data. By combining the first string with data comparison, it is possible to achieve fast partitioning of array elements without moving the array elements. Since there is no need to move array elements, it can achieve the effect of less resource consumption. At the same time, it can utilize the characteristics of hardware parallelization to overcome the problem of slow implementation in the prior art and achieve the effect of improving processing speed and real-time performance. Further, the multiple first results are arranged to obtain a first result vector; the multiple second results are arranged to obtain a second result vector; the multiple third results are arranged to obtain a third result vector; the first result vector, the second result vector, and the third result vector are respectively summed bit by bit to obtain the first element quantity corresponding to the first result vector, the second element quantity corresponding to the second result vector, and the third element quantity corresponding to the third result vector, and the fast acquisition of the partitioning result can be achieved through bit-by-bit summation. Further, the first element quantity, the second element quantity, and the third element quantity are detected to obtain a detection result, and the detection result is used to indicate whether the hardware search meets the requirements. If the detection result indicates that the hardware search meets the requirements, the pivot data is used as the target data. The target data is the data ranked at a predetermined position when the numbers in the original data are arranged in ascending order, and it is possible to quickly determine whether the pivot data is the target data and then quickly perform the next operation to quickly output the target data. This method can overcome the disadvantages of long calculation cycles and difficulty in hardware implementation in the prior art search methods, and at the same time meet the requirements of less resource consumption and high real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a flowchart of the hardware search method provided by an embodiment of the present application;

[0056] Figure 2 is Figure 1 a flowchart of step S103 in

[0057] Figure 3 is Figure 1 the flowchart of step S104 in

[0058] Figure 4 is another flowchart of the hardware search method provided by the embodiments of the present application;

[0059] Figure 5 is another flowchart of the hardware search method provided by the embodiments of the present application;

[0060] Figure 6 is a schematic diagram of an implementation process of the hardware search method provided by the embodiments of the present application;

[0061] Figure 7 is a schematic diagram of the curve relationship between the average number of iterations of the hardware search method provided by the embodiments of the present application and the scale of the hardware search;

[0062] Figure 8 is a schematic diagram of the overall structure of the hardware search system provided by the embodiments of the present application;

[0063] Figure 9 is Figure 8 the schematic diagram of the structure of the data input control unit in

[0064] Figure 10 is Figure 8 the schematic diagram of the structure of the comparison unit in

[0065] Figure 11 is Figure 8 the schematic diagram of the structure of the aggregation unit in

[0066] Figure 12 is Figure 8 the schematic diagram of the state transition of the control unit in Detailed implementation manners

[0067] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0068] It should be noted that although the functional modules are divided in the system schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the system or the order in the flowchart. Terms such as "first" and "second" in the specification, claims and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein are for the purpose of describing embodiments of this application only and are not intended to limit this application.

[0070] Finding the k-th (1 ≤ k ≤ N) smallest number in an array of length N is one of the common operations in data processing. With the development of communication technology, the amount of data to be processed has increased and the requirement for processing real-time performance has been improved. In recent years, many search methods have been proposed to solve this problem, and the search methods are divided into software methods and hardware methods according to the implementation method.

[0071] In the related art, the hardware methods mainly include methods such as sequential comparison, bitonic sorting, and recursive search.

[0072] The sequential comparison method uses N comparators to sequentially compare all elements in the array A with A[i] (i = 0, …, N - 1) in the i-th iteration, and obtains the number c[i] of elements in A that are smaller than A[i]. After the comparison, the element with c[i] == k - 1 is found, so as to realize the search for the k-th smallest number. The sequential comparison method can be implemented by hardware, and the time complexity is Ο(N). Although this method is relatively simple, when N is large, on average, N / 2 comparisons are required to obtain the element with c[i] == k - 1, that is, the time complexity is Ο(N), and the time complexity is too large.

[0073] The bitonic sorting method uses a bitonic sorting network to sort the array. After sorting, the entire array is arranged in ascending order, and the k-th element after sorting is the k-th smallest element, and the time complexity is Ο((logN) 2 )). The time complexity of this method is also relatively large.

[0074] The recursive search method first selects the pivot data in each recursion, and then divides the array. The data smaller than the pivot data is divided into the left sub-array, and the data greater than or equal to the pivot data is divided into the right sub-array. The position of the pivot data after division is used to determine whether the k-th smallest element is in the left sub-array or the right sub-array, and then the recursive process is executed again on the sub-array where the k-th smallest element is located until there is only 1 element left in the sub-array. After the recursion ends, the remaining element is the k-th smallest element. This method is implemented by software, and the expected running time is Ο(N), and the time complexity in the worst case is Ο(N 2)。Although the recursive search method is relatively simple to implement in software, it is not suitable for direct hardware implementation. Because in the existing direct hardware implementation, each division requires pairwise comparison and exchange of elements to partition the data less than the pivot data into the left sub-array and the data greater than or equal to the pivot data into the right sub-array. This is equivalent to an N×N crossbar network in hardware implementation, which will consume a large amount of cross-interconnection lines and mux resources, resulting in a relatively high hardware complexity. If a non-full cross-interconnection serial method is used for implementation, it will require a long division time, making the hardware implementation meaningless.

[0075] It can be seen that the above search methods all take a relatively long time, which will affect the efficiency of hardware implementation. In addition, due to the long time taken, problems such as large resource consumption will also occur.

[0076] Based on this, the embodiments of the present application propose a hardware search method, system, electronic device and storage medium, aiming to overcome the disadvantages of the existing search methods with long calculation cycles and difficulty in hardware implementation, and at the same time meet the requirements of less resource consumption and higher real-time performance.

[0077] Since the present application has a relatively fast processing speed and high real-time performance, the present application can be applied to fields with high real-time requirements for data processing such as MIMO demodulation and Polar decoding in the communication field.

[0078] The hardware search method, system, electronic device and storage medium provided by the embodiments of the present application will be specifically described through the following embodiments. First, the hardware search method in the embodiments of the present application will be described.

[0079] Figure 1 is the flowchart of the hardware search method provided by the embodiments of the present application, Figure 1 and the method in may include but is not limited to steps S101 to S108.

[0080] Step S101, input the original data into the register array to obtain an ordered array, where the ordered array includes a plurality of elements arranged in sequence. Set the subscript of the first element of the ordered array to 0, and starting from the first element, the subscripts of the plurality of elements increase in sequence;

[0081] Step S102, set a first string, the first string is a binary string, and each digit of the binary string is 1; where the last digit of the first string corresponds to the first element of the ordered array, and starting from the last digit, each digit of the first string corresponds to an element in the ordered array in sequence;

[0082] Step S103, select an element from the plurality of elements in the ordered array as the pivot data;

[0083] Step S104: Compare the elements in the ordered array with the axis data to obtain multiple first results, second results, and third results. Among them, the first result is determined based on the elements smaller than the axis data, the second result vector is determined based on the elements not smaller than the axis data, and the third result vector is determined based on the elements equal to the axis data;

[0084] Step S105: Arrange the multiple first results to obtain a first result vector; arrange the multiple second results to obtain a second result vector; arrange the multiple third results to obtain a third result vector;

[0085] Step S106: Perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element quantity corresponding to the first result vector, a second element quantity corresponding to the second result vector, and a third element quantity corresponding to the third result vector;

[0086] Step S107: Detect the first element quantity, the second element quantity, and the third element quantity to obtain a detection result, and the detection result is used to indicate whether the hardware search meets the requirements;

[0087] Step S108: If the detection result indicates that the hardware search meets the requirements, then use the axis data as the target data. The target data is the data ranked at a predetermined position when the numbers in the original data are arranged in ascending order.

[0088] In step S101 of some embodiments, the original data is a set of data; the register array is a temporary storage space inside the hardware accelerator used to temporarily store data; the ordered array refers to the array generated corresponding to the original data. Among them, the ordered array includes multiple elements arranged in sequence. Set the subscript of the first element of the ordered array to 0, and starting from the first element in the array, the subscripts of the multiple elements increase sequentially. And the order of the elements in the ordered array is obtained based on the order in which each data in the original data is input into the register array. Assume there are N data in the original data, where N is an integer greater than 0. Input these N data into the register array to obtain an ordered array A[N], where A[N] includes A[0], A[1],..., A[N - 1].

[0089] In step S102 of some embodiments, a first string is set for the original data. The first string is a binary string, and each digit of the binary string is set to 1 initially. More specifically, the rightmost digit of the first string corresponds to the first element of the ordered array. Starting from the rightmost digit, each digit of the first string corresponds to an element in the ordered array in sequence. Assume the first string is en, en = {DATA_NUM{1’b1}}, where DATA_NUM refers to the number of elements in the ordered array, that is, the number of data of the original data; b represents binary. If N is 16, then en = 16’hFFFF = (1111_1111_1111_1111)2. Here, 16 in en indicates that there are 16 elements, h indicates hexadecimal, and hFFFF represented in binary is 1111_1111_1111_1111. Each digit of the first string corresponds to an element of the ordered array, and each digit of the first string is set to 1 initially. For example, the rightmost bit in en corresponds to the element with subscript 0 in the ordered array, and the second rightmost bit in en corresponds to the element with subscript 1 in the ordered array. If the first string is represented in array form, that is, en[N], where en[N] includes en[0], en[1],..., en[N - 1], en[0] corresponds to the rightmost bit of en. Additionally, en[0] corresponds to A[0], and en[N - 1] corresponds to A[N - 1].

[0090] In step S103 of some embodiments, the axis data pivot can be regarded as a reference element and is used to compare with all elements as a reference element in each comparison. The axis data is an element randomly selected from multiple elements in the ordered array.

[0091] In step S104 of some embodiments, the first result, the second result, and the third result are single-bit binary numbers, and the first result, the second result, and the third result take values of 0 or 1. The first result is determined according to the elements in the ordered array that are less than the axis data after comparing the elements in the ordered array with the axis data; the second result is determined according to the elements that are not less than the axis data, where not less than represents the logical relationship of greater than or equal to; the third result is determined according to the elements that are equal to the axis data.

[0092] In step S105 of some embodiments, the first result vector, the second result vector, and the third result vector all belong to binary vectors, also known as bit vectors or binary vectors in the computer field. Each bit of the vector can only be represented by 0 or 1, and the number of bits of each result vector is the same as that of the first string, which is determined by the number of elements in the ordered array. At the same time, arranging multiple first results in order can obtain the first result vector. Among them, the first result corresponding to the element with subscript 0 is placed at the end of the first result vector, the first result corresponding to the element with subscript 1 is placed at the second last position of the first result vector, and so on; Similarly, arranging multiple second results in order obtains the second result vector; arranging multiple third results in order obtains the third result vector. Taking the first result vector as an example, assume the first result vector is 1111_0011_0001_1000, which means that the first results of the elements with subscripts 3, 4, 8, 9, 12, 13, 14, and 15 in the ordered array are all 1, and at the same time, these elements are all less than the axis data.

[0093] Further, after arranging to obtain the first result vector, the second result vector, and the third result vector, the three result vectors are latched into a register bank. The register bank includes registers lt_vec, ge_vec, and eq_vec. Specifically, the register lt_vec is used to store the first result vector, the ge_vec is used to store the second result vector, and the eq_vec is used to store the third result vector. This method can store the result vectors corresponding to different results separately based on different registers, improve the rationality of vector storage, and improve the query efficiency of the stored result vectors.

[0094] In step S106 of some embodiments, bitwise summation refers to adding the values of all bits of the result vector. Assume the result vector is 1111_0011_0001_1000, then bitwise summation refers to 1+1+1+1+0+0+1+1+0+0+0+1+1+0+0+0 to get 8. Specifically, performing bitwise summation on the first result vector obtains the first element quantity corresponding to the first result vector, that is, the number of data in the ordered array that is less than the axis data, and the first element quantity is represented as lt_sum. Then, performing bitwise summation on the second result vector obtains the second element quantity corresponding to the second result vector, that is, the number of data in the ordered array that is not less than the axis data, and the second element quantity is represented as ge_sum. Further, performing bitwise summation on the third result vector obtains the third element quantity corresponding to the third result vector, that is, the number of data in the ordered array that is equal to the axis data, and the third element quantity is represented as eq_sum.

[0095] In step S107 of some embodiments, the number of first elements, the number of second elements, and the number of third elements are detected to obtain a detection result, which is used to indicate whether the hardware search meets the requirements.

[0096] In step S108 of some embodiments, the target data is the data ranked at a predetermined rank when the numbers in the original data are sorted in ascending order, that is, if the k-th smallest data is found in the original data, the target data is the data ranked among the top k when the numbers in the original data are sorted in ascending order, where k is an integer greater than 0 and less than or equal to N. If the detection result indicates that the hardware search meets the requirements, the axis data is used as the target data.

[0097] Steps S101 to S108 illustrated in the embodiments of the present application obtain an ordered array by inputting original data into a register array. The ordered array includes multiple elements arranged in sequence. The subscript of the first element of the ordered array is set to 0, and starting from the first element, the subscripts of the multiple elements increase sequentially. A first string is set. The first string is a binary string, and each digit of the binary string is 1. Among them, the rightmost digit of the first string corresponds to the first element of the ordered array. Starting from the rightmost digit, each digit of the first string corresponds to an element in the ordered array in sequence, and the situation of each number in the original data can be recorded through the first string. Further, among the multiple elements in the ordered array, an element is selected as the axis data. The elements in the ordered array are compared with the axis data to obtain multiple first results, second results, and third results. Among them, the first result is determined according to the elements smaller than the axis data, the second result vector is determined according to the elements not less than the axis data, and the third result vector is determined according to the elements equal to the axis data. By combining the first string with data comparison, the effect of quickly partitioning array elements can be achieved without moving array elements. Since there is no need to move array elements, the effect of less resource consumption can be achieved, and at the same time, the characteristics of hardware parallelization can be utilized to overcome the problem of slow implementation methods in the prior art, achieving the effect of improving processing speed and real-time performance. Further, the multiple first results are arranged to obtain a first result vector; the multiple second results are arranged to obtain a second result vector; the multiple third results are arranged to obtain a third result vector; the first result vector, the second result vector, and the third result vector are respectively summed bit by bit to obtain the first element quantity corresponding to the first result vector, the second element quantity corresponding to the second result vector, and the third element quantity corresponding to the third result vector. The quick acquisition of the partitioning result can be achieved through bit-by-bit summation. Further, the first element quantity, the second element quantity, and the third element quantity are detected to obtain a detection result. The detection result is used to indicate whether the hardware search meets the requirements. If the detection result indicates that the hardware search meets the requirements, the axis data is used as the target data. The target data is the data ranked at a predetermined position when the numbers in the original data are arranged in ascending order. It can quickly determine whether the axis data is the target data, and then quickly perform the next operation to quickly output the target data. This method can overcome the disadvantages of long calculation cycles and difficulty in hardware implementation of the existing search methods, and at the same time meet the requirements of less resource consumption and high real-time performance.

[0098] Please refer to Figure 2 , in step S103 of some embodiments, the hardware search method may further include but is not limited to steps S201 to S203:

[0099] Step S201: Perform a bitwise AND operation on the first string and a pre-generated random vector to obtain a first vector.

[0100] Step S202: If the first vector is an all-zero vector, select the element corresponding to the lowest bit of 1 in the first string as the axis data, and generate a second vector. The second vector is obtained by retaining the digit at the position corresponding to the axis data in the first string as 1 and setting the digits at the positions in the first string that do not correspond to the axis data to 0.

[0101] Step S203: If the first vector is a non-all-zero vector, select the element corresponding to the lowest bit of 1 in the first vector as the axis data, and generate a second vector. The second vector is obtained by retaining the digit at the position corresponding to the axis data in the first vector as 1 and setting the digits at the positions in the first vector that do not correspond to the axis data to 0.

[0102] In step S201 of some embodiments, the pre-generated random vector is a binary vector, and the number of bits of the vector is the same as the number of bits of the first string. There are various methods for generating the random vector, including but not limited to a linear feedback shift register (LFSR), a true random number generation module (TRNG), etc. The bitwise AND operation is to perform a logical AND operation on the corresponding binary digits of the two numbers involved in the operation. Only when the corresponding two binary digits are both 1, the result bit is 1; therefore, when one of the corresponding two binary digits is 0 or both binary digits are 0, the result bit is 0. The first vector is a binary vector and has the same number of bits as the first string, and can be named en_a. After obtaining the random vector, perform a bitwise AND operation on the first string and the random vector to obtain the first vector.

[0103] In step S202 of some embodiments, the all-zero vector refers to a binary vector with each bit being 0. In this embodiment, the lowest bit in the first string is the last bit, and the order from the last bit to the first bit is regarded as the order from the lowest bit to the highest bit. The second vector is a binary vector and has the same number of bits as the first string, and can be named en_f. If the first vector is an all-zero vector, then the element corresponding to the lowest bit that is 1 in the first string is selected as the axis data, and the second vector is generated. The second vector is obtained by keeping the digit at the position corresponding to the axis data in the first string as 1 and setting the digits at the positions not corresponding to the axis data in the first string to 0, that is, the second vector is a vector with the lowest bit that is 1 in the first string kept as 1 and other positions as 0. Among them, the lowest bit of en being 1 means representing en as a binary string, and starting from the lowest bit (the rightmost) of this binary string, searching sequentially towards the higher bits, and the bit where the first "1" is encountered. Suppose en is 1100_0011_0101_0000, and en_a is 0000_0000_0000_0000. Since en_a is an all-zero vector, the lowest bit that is 1 in en is selected, that is, the 5th bit from the right as the axis data, and the 5th bit from the right corresponds to the 5th element in the ordered array, that is, A[4]. Therefore, A[4] in the ordered array is used as the axis data, and en_f is 0000_0000_0001_0000.

[0104] In step S203 of some embodiments, the non-all-zero vector refers to a binary vector with at least one bit being 1. In this embodiment, the lowest bit in the first vector is the rightmost bit, and the order from right to left is regarded as the order from the lowest bit to the highest bit. The second vector is a binary vector and has the same number of bits as the first string, and can be named en_f. If the first vector is a non-all-zero vector, then the element corresponding to the lowest bit that is 1 in the first vector is selected as the axis data, and the second vector is generated. The second vector is obtained by keeping the digit at the position corresponding to the axis data in the first vector as 1 and setting the digits at the positions not corresponding to the axis data in the first vector to 0, that is, the second vector is a vector with the lowest bit that is 1 in the first vector kept as 1 and other positions as 0. Suppose en is 1100_0011_0101_0000, and en_a is 0000_0001_0100_0000. Since en_a is a non-all-zero vector, the lowest bit that is 1 in en_a is selected, that is, the 7th bit from the right as the axis data, and the 7th bit from the right corresponds to the 7th element in the ordered array, that is, A[6]. Therefore, A[6] in the ordered array is used as the axis data, and en_f is 0000_0000_0100_0000.

[0105] Note that whether it is a random vector, the first vector, or the second vector, their order is the same as that of the first string. Then, the order of the bits in the random vector, the first vector, and the second vector from right to left is the same as the order of the ordered array from subscript 0 to N - 1. Such a setting is for the convenience of calculation and does not require position conversion before calculation. However, the order of the string or vector can also not be specified, as long as position conversion is performed before calculation, the same effect can be achieved.

[0106] Through the above steps S201 to S203, the axis data can be randomly selected to divide the data with the axis data as the reference data. For some arrays with special data arrangements, randomly selecting the axis data for one round of division can obtain performance gain compared to fixedly selecting the axis data from the lowest bit or the highest bit. This is because for some arrays with special data arrangements, if the axis data is selected for division in a fixed order, there may be a situation where only one element can be removed in one division.

[0107] Please refer to Figure 3 , in step S104 of some embodiments, the hardware search method may further include but is not limited to steps S301 to S304:

[0108] Step S301, for each element, compare the element with the axis data;

[0109] Step S302, if the element is less than the axis data and the number corresponding to the element in the first string is 1, determine that the first result corresponding to the element is 1; otherwise, determine that the first result corresponding to the element is 0;

[0110] Step S303, if the element is not less than the axis data and the number corresponding to the element in the first string is 1, determine that the second result corresponding to the element is 1; otherwise, determine that the second result corresponding to the element is 0;

[0111] Step S304, if the element is equal to the axis data and the number corresponding to the element in the first string is 1, determine that the third result corresponding to the element is 1; otherwise, determine that the third result corresponding to the element is 0.

[0112] In step S301 of some embodiments, due to hardware parallelization, all elements of the ordered array are compared with the axis data in parallel. The comparison logic is the same. Here, an example is given by comparing an element in the ordered array with the axis data.

[0113] In step S302 of some embodiments, if the element is less than the axis data and the digit corresponding to the element in the first string is 1, then determine that the first result corresponding to the element is 1; otherwise, determine that the first result corresponding to the element is 0. Assume that the element with subscript 0 in the ordered array is 339, i.e., A[0]=339, the axis data is 401, and at the same time, use lt[N] to represent the first result, where lt[N] corresponds to A[N] one by one, and lt[0] is the comparison result between A[0] and the axis data, that is, lt[0] is the first result corresponding to A[0]. At this time, A[0] is less than the axis data. Among them, if the digit of the bit corresponding to A[0] in en is 1, it means that A[0] is not the element to be excluded, that is, A[0] needs to be compared with the axis data; if the digit of the bit corresponding to A[0] in en is 0, it means that A[0] is the element to be excluded. And when both conditions that A[0] is less than the axis data and the digit corresponding to A[0] in the first string is 1 are satisfied, it can be determined that the first result lt[0] corresponding to A[0] is 1; if at least one of the two conditions is not satisfied, it can be determined that the first result lt[0] corresponding to A[0] is 0. In other embodiments, first judge whether the data of the bit corresponding to A[0] in the first string en is 1. If en[0] is 1, then judge whether the element is less than the axis data; if en[0] is 0, there is no need to judge whether the element is less than the axis data, and directly determine that the first result corresponding to A[0] is 0, that is, lt[0]=0.

[0114] In step S303 of some embodiments, if the element is not less than the axis data and the digit corresponding to the element in the first string is 1, then determine that the second result corresponding to the element is 1; otherwise, determine that the second result corresponding to the element is 0. Suppose the element with subscript 0 in the ordered array is 503, that is, A[0]=503, the axis data is 401, and at the same time, ge[N] is used to represent the second result, where ge[N] corresponds to A[N] one by one, and ge[0] is the comparison result of A[0] and the axis data, that is, ge[0] is the second result corresponding to A[0]. At this time, A[0] is not less than the axis data. Among them, if the digit of the bit corresponding to A[0] in en is 1, it means that A[0] is not the element to be excluded, that is, A[0] needs to be compared with the axis data; if the digit of the bit corresponding to A[0] in en is 0, it means that A[0] is the element to be excluded. And when both conditions that A[0] is not less than the axis data and the digit corresponding to A[0] in the first string is 1 are satisfied, it can be determined that the second result ge[0] corresponding to A[0] is 1; if at least one of the two conditions is not satisfied, determine that the second result ge[0] corresponding to A[0] is 0. In other embodiments, first judge whether the data of the bit corresponding to A[0] in the first string en is 1. If en[0] is 1, then judge whether the element is not less than the axis data; if en[0] is 0, there is no need to judge whether the element is not less than the axis data, and directly determine that the second result corresponding to A[0] is 0, that is, ge[0]=0.

[0115] In step S304 of some embodiments, if the element is equal to the axis data and the digit corresponding to the element in the first string is 1, it is determined that the third result corresponding to the element is 1; otherwise, it is determined that the third result corresponding to the element is 0. Suppose the element with subscript 0 in the ordered array is 401, that is, A[0]=401, the axis data is 401, and at the same time, eq[N] is used to represent the third result, where eq[N] corresponds to A[N] one by one, and eq[0] is the comparison result of A[0] and the axis data, that is, ge[0] is the third result corresponding to A[0]. At this time, A[0] is equal to the axis data. If the digit of the bit corresponding to A[0] in en is 1, it means that A[0] is not the element to be excluded, that is, A[0] needs to be compared with the axis data; if the digit of the bit corresponding to A[0] in en is 0, it means that A[0] is the element to be excluded. When both conditions that A[0] is equal to the axis data and the digit corresponding to A[0] in the first string is 1 are satisfied, it can be determined that the third result corresponding to A[0] is 1; if at least one of the two conditions is not satisfied, it can be determined that the third result corresponding to A[0] is 0. In other embodiments, first, it is determined whether the data of the bit corresponding to A[0] in the first string en is 1. If en[0] is 1, then it is further determined whether the element is equal to the axis data; if en[0] is 0, it is not necessary to further determine whether the element is equal to the axis data, and directly determine that the third result corresponding to A[0] is 0, that is, eq[0]=0.

[0116] Through the above steps S301 to S304, data comparison can be performed on each element in the ordered array in parallel, improving the processing speed. At the same time, by combining the first string for comparing the element with the axis data, the processing speed can be further improved, thereby improving the efficiency of hardware search.

[0117] In step S105 of some embodiments, the order of the first string from right to left corresponds to the order of the subscripts of the ordered array from 0 to N-1. For the convenience of bit-by-bit comparison, the result vector is also set to be in the same direction as the first string, that is, the bits of the result vector from right to left correspond to the order of the subscripts of the ordered array from 0 to N-1. In some other embodiments, the leftmost bit of the first string can also be set to correspond to the first element of the ordered array, that is, the bits of the first string from left to right correspond to the order of the subscripts of the ordered array from 0 to N-1. Correspondingly, the leftmost bit of the result vector can also be set to correspond to the first element of the ordered array. In some other embodiments, there is no need to rigidly specify the directions of the first string and the result vector. It is only necessary to convert the respective orders into the corresponding orders when comparing, that is, compare the corresponding bits. Moreover, a first result is the value of a single binary bit that makes up the first result vector. After obtaining the first result, the first result corresponding to the element with subscript 0 is stored in the rightmost bit of the first result vector, the first result corresponding to the element with subscript 1 is stored in the second rightmost bit of the first result vector, and so on. A second result is the value of a single binary bit that makes up the second result vector. After obtaining the second result, the second result corresponding to the element with subscript 0 is stored in the rightmost bit of the second result vector, the second result corresponding to the element with subscript 1 is stored in the second rightmost bit of the second result vector, and so on. A third result is the value of a single binary bit that makes up the third result vector. After obtaining the third result, the third result corresponding to the element with subscript 0 is stored in the rightmost bit of the third result vector, the third result corresponding to the element with subscript 1 is stored in the second rightmost bit of the third result vector, and so on.

[0118] In step S106 of some embodiments, the hardware search method may further include but is not limited to the following steps:

[0119] If the number of first elements, the number of second elements, and the number of third elements satisfy at least one of the following three conditions, the detection result is that the hardware search meets the requirements; wherein, the conditions include:

[0120] (1) The sum of the number of first elements and the number of second elements is equal to the number of third elements, that is, eq_sum = (lt_sum + ge_sum);

[0121] (2) The sum of the number of first elements and the number of second elements is not greater than 1, that is, (lt_sum + ge_sum) ≤ 1;

[0122] (3) The sum of the number of first elements and 1 is equal to the value corresponding to the predetermined ranking, that is, pos = lt_sum + 1.

[0123] Among them, assuming that the hardware search meets the requirement as the finish criterion, and letting pos = k, it is represented in the code as finish = ((eq_sum == (lt_sum + ge_sum)) || ((lt_sum + ge_sum) <= 1) || (pos == lt_sum + 1)). When at least one of the three conditions is met, it indicates that the detection result is that the hardware search meets the requirement.

[0124] By adding the condition eq_sum = (lt_sum + ge_sum), it is possible to achieve a quick end to the iteration for the same elements. This condition is used to handle the case where all elements in the array are equal. If all elements in the array are equal, only 1 element can be excluded in each iteration, which will slow down the iteration rate. Therefore, the condition eq_sum = (lt_sum + ge_sum) is added. When this condition is met, all elements in the array are equal, and the k-th smallest element must be equal to any element in the array. At this time, directly output pivot as the result. This condition can eliminate the lengthy iteration convergence process.

[0125] By adding the condition (lt_sum + ge_sum) ≤ 1, the number of iterations can be reduced and the calculation speed can be improved. The situation where this condition is met is only when lt_sum = 0 and ge_sum = 1. In this case, it means that there is only one element left in the ordered array except for the excluded element. Therefore, it is possible to determine that this element is the target data without the need for the next iteration.

[0126] By adding the condition pos = lt_sum + 1, it is possible to determine that the axis data at this time is the k-th smallest data, that is, the target data.

[0127] Please refer to Figure 4 , after step S106 of some embodiments, if the detection result indicates that the hardware search does not meet the requirement, the hardware search method may further include but is not limited to steps S401 to S403:

[0128] Step S401, determine whether the value is less than the sum of the first element quantity and 1, and obtain a judgment result;

[0129] Step S402, if the judgment result indicates that the value is less than the sum of the first element quantity and 1, then keep the value unchanged and assign the second result vector to the first string;

[0130] Step S403, return to the step of selecting an element from multiple elements in the ordered array as the axis data.

[0131] In step S401 of some embodiments, the value refers to the value of pos. In the first iteration, pos = k. It should be noted that during the iteration process, k does not change, while pos changes. After obtaining the value and the number of the first elements, it is determined whether the value is less than the sum of the number of the first elements and 1, and a judgment result is obtained, that is, it is judged whether pos < (lt_sum + 1) is true. Among them, when pos < (lt_sum + 1) is true, the judgment result is 1, which means that the value is less than the sum of the number of the first elements and 1; when pos < (lt_sum + 1) is false, the judgment result is 0, which means that the value is not less than the sum of the number of the first elements and 1.

[0132] In step S402 of some embodiments, if the judgment result indicates that the value is less than the sum of the number of the first elements and 1, the value is kept unchanged, and the second result vector is assigned to the first string. That is, when the judgment result is 1, the value of pos is kept unchanged, and en = lt_vec.

[0133] In step S403 of some embodiments, it returns to the step of selecting an element from multiple elements in the ordered array as the axis data until the target data is output. At this time, the first string has changed. In the first iteration, all bits of the first string are set to 1, and in this iteration, the value of the first string is lt_vec, and lt_vec is the first result vector obtained in the previous iteration.

[0134] Through the above steps S401 to S403, it is possible to determine the value and the value of the first string by judging whether the value is less than the sum of the number of the first elements and 1, which can improve the efficiency and accuracy of iterative judgment. When the judgment situation meets certain conditions, it can quickly enter the iteration, effectively improve the processing speed, and thus meet the requirement of high real-time performance.

[0135] Please refer to Figure 5 , after step S401 of some embodiments, if the judgment result indicates that the value is not less than the sum of the number of the first elements and 1, the hardware search method may further include but is not limited to steps S501 to S505:

[0136] Step S501, subtract the value from the number of the first elements and 1 in sequence, and use the subtraction result as the updated value corresponding to the predetermined rank;

[0137] Step S502, perform a NOT operation on the second vector to obtain a third vector;

[0138] Step S503, perform an AND operation on the second result vector and the third vector to obtain a fourth vector;

[0139] Step S504, assign the fourth vector to the first string;

[0140] Step S505, return to the step of selecting an element from multiple elements in the ordered array as the axis data.

[0141] In step S501 of some embodiments, when the judgment result is 0, subtract the value from the first element quantity and 1 in sequence, and use the subtraction result as the updated value corresponding to the predetermined ranking. That is, let pos = pos – lt_sum – 1, and obtain the updated pos value corresponding to the predetermined ranking.

[0142] In step S502 of some embodiments, perform a NOT operation on the binary vector so that the original 1 becomes 0 and the original 0 becomes 1, to obtain a third vector. The third vector is a binary vector, whose number of bits is the same as that of the first string, and its direction is also the same as the order of the first string. Assume the binary vector en_f is 0000_0000_0001_0000, after performing a NOT operation on the binary vector en_f, the obtained third vector ~en_f is 1111_1111_1110_1111.

[0143] In step S503 of some embodiments, the AND operation is a bitwise AND operation. The fourth vector is a binary vector, whose number of bits is the same as that of the first string, and its direction is also the same as the order of the first string. Perform an AND operation on the second result vector and the third vector to obtain the fourth vector, and the fourth vector can be named ge_vec_elm. Assume the second result vector ge_vec is 0010_1100_0001_0000, after performing an AND operation with the third vector ~en_f, the obtained fourth vector ge_vec_elm is 0010_1100_0000_0000.

[0144] In step S504 of some embodiments, assign the fourth vector to the first string. That is, let en = ge_vec_elm. Wherein, ge_vec_elm = ge_vec & ~en_f.

[0145] In step S505 of some embodiments, return to the step of selecting an element from multiple elements in the ordered array as the axis data until the target data is output. At this time, the first string has changed. In the first iteration, all bits of the first string are set to 1, while in this iteration, the value of the first string is ge_vec_elm.

[0146] Through the above steps S501 to S505, data that does not meet the requirements can be eliminated in each iteration, and the remaining valid data can be recorded through the first string. Therefore, the remaining valid data can be obtained without moving the array elements, achieving the effect of reducing resource consumption.

[0147] The following combinesFigure 6 A specific application example of the hardware search method of the embodiment of the present application is described.

[0148] First, we need to find the fifth smallest number from the original data datain{822,394,206,776,987,542,512,171,322,906,611,829,460,24,1011,600}, that is, k=5.

[0149] Input the original data into the memory array to obtain A

[16] ={822,394,206,776,987,542,512,171,322,906,611,829,460,24,1011,600}, where the subscripts of the array elements start from 0, that is, 822 is A[0], which is the first element in the array, and the subscripts of the array elements increase successively.

[0150] Set the first character string en, let en=16'hFFFF=(1111_1111_1111_1111)2, pos=5.

[0151] Iteration 1:

[0152] Select axis data: select pivot = A[3] = 776 from orderedarray;

[0153] Compare data: Compare the elements in the ordered array with the axis data, and obtain the first result lt=16'hB5E6=(1011_0101_1110_0110)2, the second result ge=16'h4a19=(0100_1010_0001_1001)2, and the third result eq=16'h0008=(0000_0000_0000_1000)2.

[0154] Aggregate comparison results: Aggregate the first result, the second result, and the third result respectively to obtain a first result vector lt_vec=16'hB5E6=(1011_0101_1110_0110)2, a second result vector ge_vec=16'h4a19=(0100_1010_0001_1001)2, and a third result vector eq_vec=16'h0008=(0000_0000_0000_1000)2. Perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element number lt_sum=10 corresponding to the first result vector, a second element number ge_sum=6 corresponding to the second result vector, and a third element number eq_sum=1 corresponding to the third result vector.

[0155] Detect the reduction comparison result: Detect the number of the first elements, the number of the second elements, and the number of the third elements. The detection result indicates that the hardware search does not meet the requirements.

[0156] Judge the value less than the sum of the number of the first elements and 1: The judgment result is true.

[0157] Execute: Keep pos unchanged, pos = 5; Let en = lt_vec = 16’hB5E6 = (1011_0101_1110_0110)2.

[0158] Return to the step of selecting one element from multiple elements in the ordered array as the axis data.

[0159] The second iteration:

[0160] Select the axis data: pivot = A[8] = 322;

[0161] Compare the data: Obtain lt = 16’h2084 = (0010_0000_1000_0100)2, ge = 16’h9562 = (1001_0101_0110_0010)2, eq = 16’h0100 = (0000_0001_0000_0000)2.

[0162] Reduce the comparison result: Obtain lt_sum = 3, ge_sum = 7, eq_sum = 1. At the same time, obtain lt_vec = 16’h2084 = (0010_0000_1000_0100)2, ge_vec = 16’h9562 = (1001_0101_0110_0010)2, eq_vec = 16’h0100 = (0000_0001_0000_0000)2.

[0163] Detect the reduction comparison result: The detection result indicates that the hardware search does not meet the requirements.

[0164] Judge the value less than the sum of the number of the first elements and 1: The judgment result is false.

[0165] Execute: Let pos = pos - lt_sum - 1 = 1; Let en = ge_vec_elm = 16’h9462 = (1001_0100_0110_0010)2.

[0166] Return to the step of selecting one element from multiple elements in the ordered array as the axis data.

[0167] The third iteration:

[0168] Select the axis data: pivot = A

[12] = 460;

[0169] Comparison data: Obtained lt = 16’h0002 = (0000_0000_0000_0010)₂, ge = 16’h9460 = (1001_0100_0110_0000)₂, eq = 16’h1000 = (0001_0000_0000_0000)₂.

[0170] Aggregate comparison results: Obtained lt_sum = 1, ge_sum = 5, eq_sum = 1. Also obtained lt_vec = 16’h0002 = (0000_0000_0000_0010)₂, ge_vec = 16’h9460 = (1001_0100_0110_0000)₂, eq_vec = 16’h1000 = (0001_0000_0000_0000)₂.

[0171] Detect the aggregate comparison results: The detection result indicates that the hardware search did not meet the requirements.

[0172] Judge the value less than the sum of the first element count and 1: The judgment result is true.

[0173] Execute: Keep pos unchanged, pos = 1; Let en = ge_vec_elm = lt_vec = 16’h0002 = (0000_0000_0000_0010)₂.

[0174] Return to the step of selecting one element as the axis data from multiple elements in the ordered array.

[0175] The 4th iteration:

[0176] Select the axis data: pivot = A[1] = 394;

[0177] Comparison data: Obtained lt = 16’h0000 = (0000_0000_0000_0000)₂, ge = 16’h0002 = (0000_0000_0000_0010)₂, eq = 16’h0002 = (0000_0000_0000_0010)₂.

[0178] Aggregate comparison results: Obtained lt_sum = 0, ge_sum = 1, eq_sum = 1. Also obtained lt_vec = 16’h0000(0000_0000_0000_0000)₂, ge_vec = 16’h0002(0000_0000_0000_0010)₂, eq_vec = 16’h0002(0000_0000_0000_0010)₂.

[0179] Detect the convergence comparison result: The detection result indicates that the hardware search meets the requirements.

[0180] Output axis data: The k = 5th smallest number is pivot = 394.

[0181] The total number of iterations is 4 times.

[0182] Please refer to Figure 7 , Figure 7 which is a schematic diagram of the curve relationship between the average number of iterations of the hardware search method provided by the embodiments of the present application and the scale of the hardware search. The curve relationship between the number of iterations and the scale of the hardware search is expressed as the average time complexity. Figure 7 What is shown in is the average value of the number of iterations when the predetermined rank k is 5 and the number of original data N is respectively equal to 16, 32, 64, 128, 256, 512, 1024. Among them, the number of runs is 10,000 times, and the result number of iterations is averaged. It can be seen from the figure that the time complexity of the hardware search method of the embodiments of the present application is approximately equal to Ο(logN).

[0183] Please refer to Figure 8 ,the embodiments of the present application also provide a hardware search system, which can implement the above-mentioned hardware search method. The system includes:

[0184] A data input control unit 801, configured to convert the input original data into an ordered array;

[0185] A control unit 802, the control unit 802 is connected to the data input control unit 801. The control unit 802 is configured to receive the ordered array and select an element from multiple elements in the ordered array as the axis data; the control unit 802 is configured to set the first string;

[0186] A comparison unit 803, the comparison unit 803 is respectively connected to the control unit 802 and the data input control unit 801. The comparison unit 803 is configured to receive the ordered array output by the data input control unit 801, as well as the axis data and the first string output by the control unit 802, and compare the elements in the ordered array with the axis data to obtain multiple first results, second results, and third results. Among them, the first result is determined according to the elements smaller than the axis data, the second result is determined according to the elements not less than the axis data, and the third result is determined according to the elements equal to the axis data;

[0187] The convergence unit 804 is connected to the control unit 802 and the comparison unit 803. The convergence unit 804 is configured to receive a plurality of first results, second results, and third results output by the comparison unit 803, arrange the plurality of first results to obtain a first result vector; arrange the plurality of second results to obtain a second result vector; arrange the plurality of third results to obtain a third result vector; and perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element quantity corresponding to the first result vector, a second element quantity corresponding to the second result vector, and a third element quantity corresponding to the third result vector.

[0188] The control unit 802 is further configured to detect the first element quantity, the second element quantity, and the third element quantity to obtain a detection result, and the detection result is used to indicate whether the hardware search meets the requirements; and when the detection result indicates that the hardware search meets the requirements, output the axis data as the target data, where the target data is the data ranked at a predetermined position when the numbers in the original data are arranged in ascending order.

[0189] Please refer to Figure 9 , in some embodiments, the data input control unit 801 includes:

[0190] A register array 901, which is a temporary storage space inside the hardware accelerator for storing data. The register array 901 is configured to convert the input original data into an ordered array, and the ordered array will be output to the control unit 802 and the comparison unit 803.

[0191] Among them, the input data valid signal and the input data ready signal are used for the control of the input traffic. Specifically, when the control unit state machine is not in the idle state, it indicates that a search is in progress, and at this time, no new data should be input to the register array 901, so the input data ready signal is output as 0 externally. Only when the control unit state machine is in the idle state, is it allowed to input a new set of original data to be searched, and at this time, the input data ready signal is output as 1 externally. In addition, the external input of new data to be searched is represented by the input data valid signal. When the input data ready signal and the input data valid signal are both 1, it means that there is new data to be searched input externally and the circuit of the present invention is in the idle state. At this time, the register array 901 can be updated, and a new round of data search can be started.

[0192] Among them, the output data valid signal is used for data output. Specifically, after receiving the search completion signal, the output data valid signal will be pulled high for one clock cycle; at the same time, the search result is output through the target data interface.

[0193] Please refer to Figure 10 , in some embodiments, the comparison unit 803 includes:

[0194] Equal comparator 1001, the equal comparator 1001 is connected to the data input control unit 801, the control unit 802, and the aggregation unit 804. The equal comparator 1001 is used to compare the elements in the ordered array with the axis data, and to compare whether the i-th element A[i] is equal to the axis data pivot, where the value range of i is the same as that of N.

[0195] Less-than comparator 1002, the less-than comparator 1002 is connected to the data input control unit 801, the control unit 802, and the aggregation unit 804. The less-than comparator 1002 is used to compare the elements in the ordered array with the axis data, and to compare whether the i-th element A[i] is less than the axis data pivot.

[0196] The comparison unit 803 has an operation enable signal and a result output signal. The operation enable signal is used to activate the comparison unit 803 to perform a comparison on the input of the comparison unit 803. The result output signal is used to output the comparison result at the output end. There are a total of 3 output results, including the result of greater than or equal to, the result of less than, and the result of equal to.

[0197] Specifically, A[i] and the axis data pivot are input to the equal comparator 1001. If A[i] is equal to pivot, the equal comparator 1001 outputs 1; otherwise, the equal comparator 1001 outputs 0. At the same time, A[i] and the axis data pivot are input to the less-than comparator 1002. If A[i] is less than pivot, the less-than comparator 1002 outputs 1; otherwise, the less-than comparator 1002 outputs 0. When the equal comparator 1001 outputs 1 and en[i]=1, the third result eq[i] obtained after passing through the AND gate is 1; when the equal comparator 1001 outputs 0 or en[i]=0, the third result eq[i] obtained after passing through the AND gate is 0. When the less-than comparator 1002 outputs 1 and en[i]=1, the first result lt[i] obtained after passing through the AND gate is 1; when the less-than comparator 1002 outputs 0 or en[i]=0, the first result lt[i] obtained after passing through the AND gate is 0. When the less-than comparator 1002 outputs 0 and passes through the NOT gate to get 1, if en[i]=1 at this time, the second result ge[i] obtained after passing through the AND gate is 1; otherwise, the second result ge[i] is 0.

[0198] Please refer to Figure 11 , in some embodiments, the aggregation unit 804 includes:

[0199] An adder 1102 and a sum register 1101. The adder 1102 is connected to a control unit 802 and a comparison unit 803. The register 1101 is connected to the control unit 802 and the comparison unit 803. The adder is used to perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain the first element quantity corresponding to the first result vector, the second element quantity corresponding to the second result vector, and the third element quantity corresponding to the third result vector. The register is used to store the first result vector, the second result vector, and the third result vector. The register is also used to store multiple first results, second results, and third results output by the comparison unit 803.

[0200] Please refer to Figure 12 , in some embodiments, the control unit 802 includes:

[0201] Five states, namely the idle state IDLE, the pivot valid state PIVOT, the comparison state CMP, the aggregation state AGG, and the division state DIV.

[0202] The idle state indicates that it is not in the search state at this time. When the input data valid signal is 1, the idle state transitions to the pivot valid state.

[0203] The pivot valid state indicates that it is in the state of setting the first string and the axis data at this time. The pivot valid state unconditionally transitions to the comparison state and outputs the first string and the axis data.

[0204] The comparison state indicates that it is in the data comparison state at this time. When the data comparison is completed, the comparison state transitions to the aggregation state.

[0205] The aggregation state indicates that it is in the data aggregation state at this time, that is, the state of obtaining the first result vector, the second result vector, the third result vector, the first element quantity, the second element quantity, and the third element quantity. After obtaining each parameter, the aggregation state transitions to the division state.

[0206] The division state indicates that it is in the data division state at this time, that is, dividing the original data according to the first result vector, the second result vector, the third result vector, the first element quantity, the second element quantity, and the third element quantity to obtain the target data. Specifically, if the hardware search meets the requirements, the target data will be output and the division state will transition to the idle state; if the hardware search does not meet the requirements, it will transition from the division state to the pivot valid state.

[0207] The specific implementation manner of this hardware search system is basically the same as the specific embodiments of the above hardware search method, and will not be elaborated here.

[0208] An embodiment of the present application further provides an electronic device, which includes a storage unit and multiple execution units. The storage unit can store input data and can also store calculation intermediate results. The execution unit executes the above-mentioned hardware search method.

[0209] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program or circuit configuration information. When the computer program is executed by a processor, the above-mentioned hardware search method is implemented.

[0210] Among them, the computer program is used for the von Neumann structure including a CPU such as a single-chip microcomputer, and the circuit configuration information is used for hardware accelerators built with logic gates such as a Field Programmable Gate Array (FPGA).

[0211] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes a memory remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0212] The hardware search method, hardware search system, electronic device, and storage medium provided by the embodiments of the present application input the original data into a register array to obtain an ordered array. The ordered array includes a plurality of elements arranged in sequence. The subscript of the first element of the ordered array is set to 0, and starting from the first element, the subscripts of the plurality of elements increase in sequence. A first string is set. The first string is a binary string, and each digit of the binary string is 1. The rightmost digit of the first string corresponds to the first element of the ordered array. Starting from the rightmost digit, each digit of the first string corresponds to an element in the ordered array in sequence, and the situation of each number in the original data can be recorded through the first string. Further, an element is selected from the plurality of elements in the ordered array as the pivot data. The elements in the ordered array are compared with the pivot data to obtain a plurality of first results, second results, and third results. The first result is determined according to the elements smaller than the pivot data, the second result vector is determined according to the elements not less than the pivot data, and the third result vector is determined according to the elements equal to the pivot data. By combining the first string with data comparison, the effect of quickly partitioning array elements can be achieved without moving array elements. Since there is no need to move array elements, the effect of less resource consumption can be achieved, and at the same time, the characteristics of hardware parallelization can be utilized to overcome the problem of slow implementation in the prior art, achieving the effect of improving processing speed and real-time performance. Further, the plurality of first results are arranged to obtain a first result vector. The plurality of second results are arranged to obtain a second result vector. The plurality of third results are arranged to obtain a third result vector. The first result vector, the second result vector, and the third result vector are respectively summed bit by bit to obtain a first element quantity corresponding to the first result vector, a second element quantity corresponding to the second result vector, and a third element quantity corresponding to the third result vector. The quick acquisition of the partitioning result can be achieved through bit-by-bit summation. Further, the first element quantity, the second element quantity, and the third element quantity are detected to obtain a detection result. The detection result is used to indicate whether the hardware search meets the requirements. If the detection result indicates that the hardware search meets the requirements, the pivot data is used as the target data. The target data is the data ranked at a predetermined position when the numbers in the original data are arranged in ascending order. It can quickly determine whether the pivot data is the target data, and then quickly perform the next operation to quickly output the target data. This method can overcome the disadvantages of long calculation cycles and difficulty in hardware implementation of the existing search methods, and at the same time meet the requirements of less resource consumption and high real-time performance.

[0213] The embodiments described in the embodiments of the present application are to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art will know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0214] Those of ordinary skill in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0215] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A hardware lookup method, characterized in that, The method includes: Input the original data into the register array to obtain an ordered array, where the ordered array includes multiple elements arranged in sequence. Set the subscript of the first element of the ordered array to 0, and starting from the first element, the subscripts of the multiple elements increase sequentially; Set a first string, which is a binary string, and each digit of the binary string is 1; where the last digit of the first string corresponds to the first element of the ordered array, and starting from the last digit, each digit of the first string corresponds to an element in the ordered array in sequence; Select an element from the multiple elements in the ordered array as the axis data; Compare the elements in the ordered array with the axis data to obtain multiple first results, second results, and third results, where the first result is determined according to the elements less than the axis data, the second result is determined according to the elements not less than the axis data, and the third result is determined according to the elements equal to the axis data; Arrange the multiple first results to obtain a first result vector; arrange the multiple second results to obtain a second result vector; arrange the multiple third results to obtain a third result vector; Perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element quantity corresponding to the first result vector, a second element quantity corresponding to the second result vector, and a third element quantity corresponding to the third result vector; Detect the first element quantity, the second element quantity, and the third element quantity to obtain a detection result, and the detection result is used to indicate whether the hardware search meets the requirements; If the detection result indicates that the hardware search meets the requirements, then use the axis data as the target data, and the target data is the data ranked at a predetermined position when the numbers in the original data are sorted in ascending order; Among them, the step of selecting an element from the multiple elements in the ordered array as the axis data includes: Perform a bitwise AND operation on the first string and a pre-generated random vector to obtain a first vector; If the first vector is an all-zero vector, then select the element corresponding to the lowest bit that is 1 in the first string as the axis data, and generate a second vector, which is obtained by retaining the digit at the position corresponding to the axis data in the first string as 1 and setting the digits at the positions in the first string that do not correspond to the axis data to 0; If the first vector is a non-all-zero vector, then select the element corresponding to the lowest bit that is 1 in the first vector as the axis data, and generate a second vector, which is obtained by retaining the digit at the position corresponding to the axis data in the first vector as 1 and setting the digits at the positions in the first vector that do not correspond to the axis data to 0; Among them, the step of detecting the first element quantity, the second element quantity, and the third element quantity to obtain a detection result includes: If at least one of the following conditions is satisfied by the quantity of the first element, the quantity of the second element, and the quantity of the third element, the detection result is that the hardware lookup meets the requirements; The conditions include: The sum of the quantity of the first element and the quantity of the second element is equal to the quantity of the third element; The sum of the quantity of the first element and the quantity of the second element is not greater than 1; The sum of the quantity of the first element and 1 is equal to the value corresponding to the predetermined rank.

2. The hardware search method according to claim 1, wherein Comparing the elements in the ordered array with the axis data to obtain a plurality of first results, second results, and third results, including: For each element, comparing the element with the axis data; If the element is less than the axis data and the number corresponding to the element in the first string is 1, determining that the first result corresponding to the element is 1; otherwise, determining that the first result corresponding to the element is 0; If the element is not less than the axis data and the number corresponding to the element in the first string is 1, determining that the second result corresponding to the element is 1; otherwise, determining that the second result corresponding to the element is 0; If the element is equal to the axis data and the number corresponding to the element in the first string is 1, determining that the third result corresponding to the element is 1; otherwise, determining that the third result corresponding to the element is 0.

3. A hardware lookup method according to claim 1 or 2, characterized in that If the detection result indicates that the hardware lookup does not meet the requirements, the method further includes: Determining whether the value is less than the sum of the quantity of the first element and 1 to obtain a determination result; If the determination result indicates that the value is less than the sum of the quantity of the first element and 1, keeping the value unchanged and assigning the second result vector to the first string; Returning to the step of selecting an element from the multiple elements in the ordered array as the axis data.

4. The hardware search method according to claim 3, wherein If the determination result indicates that the value is not less than the sum of the quantity of the first element and 1, the method further includes: Subtracting the value from the quantity of the first element and 1 in sequence, and using the subtraction result as the updated value corresponding to the predetermined rank; Performing a NOT operation on the second vector to obtain a third vector; Performing an AND operation on the second result vector and the third vector to obtain a fourth vector; Assigning the fourth vector to the first string; Returning to the step of selecting an element from the multiple elements in the ordered array as the axis data.

5. A hardware lookup system, characterized in that, The system includes: A data input control unit configured to convert the input original data into an ordered array; A control unit, the control unit is connected to the data input control unit, the control unit is configured to receive the ordered array, and select one element from multiple elements in the ordered array as axis data; the control unit is configured to set a first string; wherein, the step of selecting one element from multiple elements in the ordered array as axis data includes: performing a bitwise AND operation on the first string and a pre-generated random vector to obtain a first vector; if the first vector is an all-zero vector, then select the element corresponding to the lowest bit that is 1 in the first string as the axis data, and generate a second vector, the second vector is obtained by retaining the digit at the position corresponding to the axis data in the first string as 1 and setting the digits at the positions in the first string that do not correspond to the axis data to 0; if the first vector is a non-all-zero vector, then select the element corresponding to the lowest bit that is 1 in the first vector as the axis data, and generate a second vector, the second vector is obtained by retaining the digit at the position corresponding to the axis data in the first vector as 1 and setting the digits at the positions in the first vector that do not correspond to the axis data to 0; A comparison unit, the comparison unit is respectively connected to the control unit and the data input control unit, the comparison unit is configured to receive the ordered array output by the data input control unit, as well as the axis data and the first string output by the control unit, and compare the elements in the ordered array with the axis data to obtain multiple first results, second results, and third results, wherein, the first result is determined according to the elements less than the axis data, the second result is determined according to the elements not less than the axis data, and the third result is determined according to the elements equal to the axis data; An aggregation unit, the aggregation unit is connected to the control unit and the comparison unit, the aggregation unit is configured to receive the multiple first results, second results, and third results output by the comparison unit, arrange the multiple first results to obtain a first result vector; arrange the multiple second results to obtain a second result vector; arrange the multiple third results to obtain a third result vector; and perform a bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element quantity corresponding to the first result vector, a second element quantity corresponding to the second result vector, and a third element quantity corresponding to the third result vector; The control unit is further configured to detect the first element quantity, the second element quantity, and the third element quantity to obtain a detection result, where the detection result is used to indicate whether the hardware search meets the requirements; and when the detection result indicates that the hardware search meets the requirements, output the axis data as target data, where the target data is the data ranked at a predetermined position when the numbers in the original data are sorted in ascending order; where, the detecting the first element quantity, the second element quantity, and the third element quantity to obtain a detection result includes: if the first element quantity, the second element quantity, and the third element quantity satisfy at least one of the following conditions, then the detection result is that the hardware search meets the requirements; the conditions include: the sum of the first element quantity and the second element quantity is equal to the third element quantity; the sum of the first element quantity and the second element quantity is not greater than 1; the sum of the first element quantity and 1 is equal to the value corresponding to the predetermined position.

6. The hardware search system according to claim 5, characterized in that, The system further includes: The comparison unit includes a comparator, and the comparator is configured to compare the elements in the ordered array with the axis data to obtain a plurality of first results, second results, and third results; The aggregation unit includes an adder and a register. The adder is configured to perform bitwise summation on the first result vector, the second result vector, and the third result vector respectively to obtain a first element quantity corresponding to the first result vector, a second element quantity corresponding to the second result vector, and a third element quantity corresponding to the third result vector, and the register is configured to store the first result vector, the second result vector, and the third result vector.

7. An electronic device, characterized in that, The electronic device includes a storage unit and a plurality of execution units. The storage unit is configured to store input data, and the storage unit is further configured to store calculation intermediate results. The execution unit executes the steps of a hardware search method according to any one of claims 1 to 4.

8. A computer-readable storage medium storing a computer program or circuit configuration information, characterized in that, When the computer program is executed by a processor, it implements a hardware search method according to any one of claims 1 to 4.

Images