A gate drive circuit

Abstract

The application discloses a gate drive circuit, relates to the technical field of integrated circuits, and aims to solve the problems of low tolerance capability of threshold voltage drift of a thin film transistor, small controllable range of output swing and slow response speed in the prior art. The gate drive circuit comprises six TFTs and a capacitor, and a previous-stage output signal is used as a next-stage input pulse signal, and the wiring structure is simple. The six TFTs comprise four switch TFTs and two drive TFTs; the two switch TFTs form an inverter, and the two drive TFTs form an output module; and the function of row-by-row scanning driving is realized based on an external control signal. The single-stage circuit is coupled by a capacitor, so that the output voltage has no threshold voltage loss, thereby reducing the sensitivity of the circuit to the threshold voltage. Moreover, the circuit fully considers the influence of the transistor size, maximizes the adaptive capability to the non-ideal characteristics of the device, supports a voltage regulation range of 2V-20V, a threshold voltage drift tolerance of 10V and a pulse width of less than 10us, and meets the requirements of 1k display / sensing matrix driving / reading.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a gate drive circuit. BACKGROUND

[0002] In recent years, thin film transistors (TFTs) have played an important role in display and sensing applications due to their low manufacturing cost and large-area preparation. One of the important functions of thin film transistors is to form a display / sensing matrix peripheral driving / reading circuit, i.e., a gate driver on array (GOA). It generates a pulse switching signal (row addressing) within a limited time, so that the display / sensing matrix can read / output signals. Compared with the traditional scheme (IC generates row addressing signal), the GOA circuit composed of TFTs can effectively reduce the cost and realize narrow frame.

[0003] The gate driver in the prior art has low tolerance to threshold voltage drift of thin film transistors, does not support swing regulation of a preset threshold voltage range (for example: 2V-20V), and has slow response speed.

[0004] Therefore, there is an urgent need to provide a more reliable gate drive circuit. SUMMARY

[0005] The present application aims to provide a gate drive circuit to solve the problem that the gate driver in the prior art has low tolerance to threshold voltage drift of thin film transistors, does not support swing regulation of a preset threshold voltage range (for example: 2V-20V), and has slow response speed.

[0006] In order to achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0007] The present application provides a gate drive circuit, which comprises:

[0008] six thin film transistors and one capacitor;

[0009] The six thin film transistors include four switching thin film transistors and two driving thin film transistors; two switching thin film transistors constitute an inverter, and two driving thin film transistors constitute an output module;

[0010] The gate drive circuit realizes row-by-row scanning driving function based on an external control signal; the external control signal includes a direct current level signal, an input pulse signal, and a clock signal.

[0011] Preferably, the thin film transistor is an N-type device; the direct current level signal comprises a first level signal and a second level signal, the first level signal corresponds to a higher level than the second level signal; the clock signal comprises a first clock signal and a second clock signal; the four switch thin film transistors comprise a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; the two drive thin film transistors comprise a first transistor and a second transistor; the fourth transistor and the sixth transistor constitute the inverter.

[0012] The row addressing signal generated by the gate drive circuit is connected to the gate of a display matrix or a sensing matrix.

[0013] Preferably, the voltage range of the first clock signal, the second clock signal and the input pulse signal is VGL-VGH, wherein VGH represents the level of the first level signal and VGL represents the level of the second level signal.

[0014] The first clock signal and the second clock signal of adjacent stages are connected alternately, and the row addressing signal generated by the gate drive circuit of the previous stage is also connected to the input end of the gate drive circuit of the next stage.

[0015] Preferably, in the preset stage, the input pulse signal and the first clock signal are both at the level of the first level signal, and the second clock signal is at the level of the second level signal, the third transistor and the fifth transistor are turned on, and at this time, the first node in the gate drive circuit is preset to high level.

[0016] The sixth transistor in the inverter is turned on, and the fourth transistor is turned off, at this time, the second node in the gate drive circuit is preset to high level, and the first transistor and the second transistor are both turned on, thereby realizing the presetting of the first node and the second node.

[0017] Preferably, in the capacitive coupling stage, the input pulse signal and the first clock signal are both at the level of the second level signal, and the second clock signal is at the level of the first level signal, and the third transistor and the fifth transistor are turned off.

[0018] The sixth transistor and the fourth transistor in the inverter are both turned on, at this time, the second node in the gate drive circuit is preset to low level; the second transistor is turned off, and the second clock signal jumps from low level to high level, and through capacitive coupling, the potential at the first node in the gate drive circuit is higher than the level of the first level signal, so as to compensate for the threshold voltage loss, and at this time, the generated row addressing signal is at the level of the first level signal.

[0019] Preferably, in the repositioning high level stage, the input pulse signal and the second clock signal are both the second level signal corresponding level, and the first clock signal is the second level signal corresponding level, the first node is set to low level, the second node is set to high level, and the final generated row addressing signal is the second level signal corresponding level, and the inverter is in the off stage.

[0020] Preferably, in the holding stage, the input pulse signal and the first clock signal are both the second level signal corresponding level, and the second clock signal is the first level signal corresponding level, the first node is set to low level, and the second node is set to high level.

[0021] The final generated row addressing signal outputs low level, the first node always maintains low potential, and the second node always maintains high potential until the next low level pulse of the input pulse signal is input.

[0022] Preferably, the thin film transistor is an amorphous silicon thin film transistor, an amorphous indium gallium zinc oxide thin film transistor or a low temperature polysilicon thin film transistor; the threshold voltage of the thin film transistor is about 0V, and the sub-threshold voltage swing is less than 250mV / dec.

[0023] Preferably, when the thin film transistor is a P-type device, the first level signal corresponding level is less than the second level signal corresponding level, VGH represents the level of the second level signal, VGL represents the first level signal corresponding level, and the clock signal is opposite to the N-type device.

[0024] Preferably, the gate drive circuit can generate an output signal with a voltage swing of 2-20V; and when the input pulse signal and the clock signal pulse width are less than a preset threshold, the gate drive circuit supports the driving and reading of 1k display matrix or sensing matrix.

[0025] Compared with the prior art, the gate drive circuit provided by the application comprises six thin film transistors and one capacitor; the six thin film transistors comprise four switching thin film transistors and two driving thin film transistors; two of the switching thin film transistors constitute an inverter, and the two driving thin film transistors constitute an output module; the gate drive circuit realizes a row-by-row scanning driving function based on external control signals; the external control signals comprise a direct current level signal, an input pulse signal and a clock signal. The circuit comprises only six TFTs and one capacitor, the interstage connection mode is simple, the output signal of the previous stage is used as the input pulse signal of the next stage, and the wiring structure is simple. The single-stage circuit realizes the output voltage through the capacitor coupling mode, so that the threshold voltage loss is reduced, thereby reducing the sensitivity of the circuit to the threshold voltage. Meanwhile, the circuit fully considers the influence of the transistor size, maximizes the adaptive ability to the non-ideal characteristics of the device, and therefore can support a voltage regulation range of 2V-20V, a threshold voltage drift tolerance of 10V and a pulse width of less than 10us, and meets the 1k display / sensor matrix driving / reading requirement. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0027] Figure 1 A structural schematic diagram of the gate drive circuit provided by the application;

[0028] Figure 2 A timing diagram of the gate drive circuit provided by the application;

[0029] Figure 3 A multi-stage circuit connection mode schematic diagram of the gate drive circuit provided by the application;

[0030] Figure 4 A simulation output waveform schematic diagram of the gate drive circuit provided by the application at different pulse widths;

[0031] Figure 5 A simulation output waveform schematic diagram of the gate drive circuit provided by the application at different voltage swings;

[0032] Figure 6 A simulation output waveform schematic diagram of the gate drive circuit provided by the application corresponding to a threshold voltage variation range of 10V. DETAILED DESCRIPTION

[0033] For the convenience of clearly describing the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms of "first", "second", etc. are used to distinguish the same or similar items with basically the same function and role. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and the order is not limited. Those skilled in the art can understand that the terms of "first", "second", etc. do not limit the quantity and execution order, and the terms of "first", "second", etc. also do not mean that they are necessarily different.

[0034] It should be noted that in the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are used to present the relevant concepts in a specific manner.

[0035] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be single or multiple.

[0036] Technical terms used in the specification are explained as follows:

[0037] TFT: Thin Film Transistor (TFT) is a kind of device. TFT display screen is the mainstream display device on various notebooks and desktop computers. Each liquid crystal pixel point on this kind of display screen is driven by a thin film transistor integrated behind the pixel point, so the TFT display screen is also a kind of active matrix liquid crystal display device. It is one of the best LCD color displays, and the TFT display has the advantages of high response, high brightness and high contrast, and its display effect is close to that of CRT display. TFT refers to the fact that each liquid crystal pixel point on the liquid crystal display is driven by a thin film transistor integrated behind it. Therefore, high-speed, high-brightness and high-contrast display screen information can be achieved. TFT-LCD (Thin Film Transistor Liquid Crystal Display) is a kind of liquid crystal display.

[0038] According to the different types of materials for making electronic circuits, almost all metals and most semiconductor materials can be made into TFT devices, and the commonly used main types include a-Si TFT (amorphous silicon), LTPS TFT (low-temperature polysilicon), HTPS TFT (high-temperature polysilicon), LTPO TFT (low-temperature polysilicon oxide), IGZO TFT (indium gallium zinc oxide-metal oxide), and the like.

[0039] GOA: the abbreviation of Gate Driven on Array, which means the integrated gate drive on array substrate, can realize the function of row-by-row scanning and driving of liquid crystal panel. In the traditional active matrix liquid crystal display, the row scanning signal is realized by external integrated circuit (G-COF), and by using GOA driving, the row scanning and driving circuit is made by the same process as the thin film transistor (TFT) on the basis of providing several control signals to the external circuit, so as to realize the function of row-by-row scanning and driving. Therefore, by using GOA driving, the integrated circuit related to scanning and driving is saved, and the manufacturing cost of the liquid crystal display is reduced.

[0040] At present, the design difficulty of the gate driver mainly lies in two aspects: one is that the stability of some thin film transistors is poor, and the threshold voltage drift range is large, for example, a-Si:H TFT (amorphous silicon thin film transistor) and a-IGZO TFT (amorphous indium gallium zinc oxide thin film transistor); the other is that the thin film transistors are mostly single N-type or P-type transistors, which increases the difficulty of circuit design.

[0041] The gate driver in the prior art has low tolerance ability to the threshold voltage drift of the thin film transistor, small controllable range of output swing, and slow response speed, and thus does not support the voltage regulation range of 2V-20V, the threshold voltage drift tolerance of 10V, and the 1k display / sensing matrix driving / reading.

[0042] Based on the defects in the prior art, the present application provides a high-tolerance and voltage-adjustable gate driving circuit, which is composed of only single-type TFT (N-type or P-type) that meets the preset conditions, which can effectively overcome the performance drift of TFT (10V tolerance to TFT threshold voltage drift under high voltage working condition). In addition, an output signal with a swing of 2-20V can be generated. In the case that the pulse width of the input pulse signal and the clock signal is small enough, the circuit can support 1k display / sensing matrix driving / reading.

[0043] Next, the scheme provided by the embodiments of the present application will be described in detail in combination with the drawings:

[0044] Figure 1 A schematic diagram of a gate driving circuit structure provided by the present application is shown in FIG. 1. Figure 1As shown, the circuit structure only contains six TFTs and one capacitor, and the peripheral driving signals include two direct current levels (VGH, VGL), one input pulse signal (OUT(0) or INPUT), and two clock signals (CLK1, CLK2). The six TFTs include four switch TFTs and two drive TFTs; two of the switch TFTs form an inverter, and the two drive TFTs form an output module.

[0045] The TFTs can be N-type devices or P-type devices.

[0046] Next, two types of devices are taken as examples for illustration. First, the TFTs are taken as N-type devices for illustration.

[0047] VGH represents the level of the first-level signal, and VGL represents the level corresponding to the second-level signal; the direct current level signals can include the first-level signal and the second-level signal, the level VGH corresponding to the first-level signal is greater than the level VGL corresponding to the second-level signal; the clock signals include a first clock signal CLK1 and a second clock signal CLK2.

[0048] The four switch TFTs include a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; the two drive TFTs include a first transistor T1 and a second transistor T2; the fourth transistor T4 and the sixth transistor T6 form the inverter; when the sixth transistor T6 is turned on, the inverter places the VGL voltage at the second node B, and at other times, the inverter is in an off state.

[0049] The third transistor T3 controls the voltage at the first node A in the gate drive circuit, and the fifth transistor T5 controls the voltage at the second node B in the gate drive circuit.

[0050] The row addressing signal OUT(N) generated by the gate drive circuit is finally connected to the gate of a display matrix or a sensing matrix.

[0051] The timing diagram corresponding to the external control signals is as shown in Figure 2 Figure 2 ​(A), (B), (C), (D) in FIG. 1 can represent four stages of the operation of the gate drive circuit, specifically, (A) is a stage of presetting A point and B point, (B) is a stage of capacitive coupling, (C) is a stage of resetting high level, and (D) is a stage of maintaining. The circuit needs two clock signals CLK1 and CLK2, one input pulse signal OUT(0), two direct current levels VGH and VGL (VGH > VGL), and the voltage range of the clock signal and the input pulse signal is VGH ~ VGL. In combination with Figure 2 The four stages of the operation of the gate drive circuit are described as follows:

[0052] (A): A stage of presetting A point and B point

[0053] In this stage, the input pulse signal and the first clock signal are both the level corresponding to the first level signal, and the second clock signal is the level corresponding to the second level signal, the third transistor and the fifth transistor are open, at this time, the first node is preset to high level;

[0054] The sixth transistor in the inverter is open, and the fourth transistor is closed, at this time, the second node is preset to high level, and the first transistor and the second transistor are both open, so as to preset the first node and the second node. Specifically, as shown in FIG. 2, in the stage (A), the state of all external drive signals is: OUT(N-1) = VGH, CLK1 = VGH, and CLK2 = VGL. For N-type TFT, T3 and T5 are open, so A point is preset to high level; Figure 2

[0055] In the inverter, T6 is open, and T4 is closed, so B point is preset to high level; T1 and T2 are both open, but CLK2 is low, so OUT(n) is low.

[0056] (B): A stage of capacitive coupling

[0057] In this stage, the input pulse signal and the first clock signal are both the level corresponding to the second level signal, and the second clock signal is the level corresponding to the first level signal, and the third transistor and the fifth transistor are closed;

[0058] The sixth transistor and the fourth transistor in the inverter are both open, at this time, the second node in the gate drive circuit is preset to low level; the second transistor is closed, the second clock signal jumps from low level to high level, and through capacitive coupling, the potential at the first node in the gate drive circuit is higher than the level corresponding to the first level signal, so as to make up for the threshold voltage loss, at this time, the finally generated row addressing signal is the level corresponding to the first level signal.

[0059] ​As shown in Figure 2 (B) stage, all the external driving signals are in the state: OUT(N-1)=VGL, CLK1=VGL, CLK2=VGH. For N-type TFT, T3, T5 are closed;

[0060] In the inverter, T4 / T6 are both open, so that B point is set low, T2 is closed; CLK2 jumps from low level to high level, through the capacitive coupling effect, the potential of A point is higher than VGH, which can effectively compensate the threshold voltage loss, at this time OUT(N)=VGH.

[0061] (C): reset high level stage

[0062] The input pulse signal and the second clock signal are both in the second level signal corresponding level, and the first clock signal is in the second level signal corresponding level, the first node is set to low level, and the second node is set to high level, and the finally generated row addressing signal is in the second level signal corresponding level, and the inverter is in the closed state, as shown in Figure 2 (C) stage, all the external driving signals are in the state: OUT(N-1)=VGL, CLK1=VGH, CLK2=VGL. A point is set low, B point is set high, and OUT(n)=VGL. Since A point is in low level, the inverter is in the closed stage.

[0063] (D): holding stage

[0064] The input pulse signal and the first clock signal are both in the second level signal corresponding level, and the second clock signal is in the first level signal corresponding level, the first node is set to low level, and the second node is set to high level;

[0065] The finally generated row addressing signal outputs low level, the first node always maintains low potential, and the second node always maintains high potential until the next low level pulse of the input pulse signal is input.

[0066] As shown in Figure 2 (D) stage, OUT(N-1)=VGL, CLK1=VGL, CLK2=VGH. The potentials of A point and B point are as shown in C stage. In the low level output stage of OUT(n), A point always maintains low potential, and B point always maintains high potential until the next low level pulse of OUT(n-1) is input. In addition, it can also be seen from Figure 2 that the potential of A point is higher than VGH.

[0067] In addition, the multi-stage connection mode is as shown in Figure 3As shown, by designing a single-stage gate drive circuit, non-overlapping GOA output signals can be achieved. According to the driving principle of the liquid crystal panel, the row scanning drive circuit actually has the function of a shift register, and under the action of the control signal of the external circuit, a shift pulse signal is generated, which not only drives the pixels of the current row to turn on the TFT, but also serves as the starting signal of the next row (the first row is triggered by the frame starting signal STV) and the end signal of the previous row.

[0068] As shown in the GOA unit and its cascade Figure 3 As shown in the GOA unit and its cascade Figure 3 As can be seen from the GOA unit, a GOA unit usually includes a pair of voltage phase-related CLK1 and CLK2 signals, an input pulse signal (OUT(0) or INPUT), a direct current level VGH, VGL and an output signal Out(n) of the current row; and Figure 3 As can be seen from the GOA unit, a GOA unit usually includes a pair of voltage phase-related CLK1 and CLK2 signals, an input pulse signal (OUT(0) or INPUT), a direct current level VGH, VGL and an output signal Out(n) of the current row; and

[0069] The adjacent stages CLK1 and CLK2 are alternately connected, and the output signal of the previous stage circuit is connected to the input of the next stage circuit in addition to being connected to the display / sensing matrix.

[0070] In the present scheme, devices made of different materials are used in cooperation with corresponding clock and power control signals, and the same function can also be achieved, such as a-Si:H TFT (amorphous silicon thin film transistor), a-IGZO TFT (amorphous indium gallium zinc oxide thin film transistor) and LTPS TFT (low temperature polysilicon thin film transistor).

[0071] More specifically, the thin film transistor used in the present application is a transistor that meets the preset conditions. In the present scheme, to ensure that the output swing of OUT(N) is 2V and the rising and falling edges of OUT(N) are within 50us, the threshold voltage of the thin film transistor should be set at about 0V, and the sub-threshold swing should be below 250mV / dec.

[0072] It should be noted that in the foregoing, the present application provides a solution in which the TFT can be N-type or P-type. The foregoing is mainly described by taking the N-type TFT as an example. Next, the N-type TFT can be replaced by the P-type or only part of it is changed, and the input waveform is also changed accordingly (including the DC level, the input pulse signal, the pulse signal) to realize the same signal control function. Specifically, when the thin film transistor is a P-type device, the level corresponding to the first level signal is less than the level corresponding to the second level signal, VGH represents the level of the second level signal, VGL represents the level corresponding to the first level signal, the clock signal is opposite to the N-type device, and the like.

[0073] Further, the simulation results of the gate drive circuit in the foregoing embodiments provided by the present application are as shown in Figure 4

[0074] Figure 4 The figure shows the corresponding output waveform under different clock frequencies. According to the order from top to bottom, the first subgraph represents the corresponding output waveform when the upper pulse width is 8us, the second subgraph represents the corresponding output waveform when the upper pulse width is 18us, and the third subgraph represents the corresponding output waveform when the upper pulse width is 38us. As can be seen from the three subgraphs of Figure 6 , when the period of the clock signal is 20us (the upper pulse width is 8us, and the lower pulse width is 12us), 40us (the upper pulse width is 18us, and the lower pulse width is 22us), and 80us (the upper pulse width is 38us, and the lower pulse width is 42us), the output signal can completely follow the change of the pulse width of the clock signal, as shown in Figure 4 , and the rising and falling edge time is short enough, so it can at least support the requirement of 1k display / sensor driving matrix under 60Hz.

[0075] Figure 5 The figure shows the corresponding output waveform when the voltage changes from 2V to 20V. According to the order from top to bottom, the first subgraph represents the corresponding output waveform when the output voltage swing is 2V, the second subgraph represents the corresponding output waveform when the output voltage swing is 10V, and the third subgraph represents the corresponding output waveform when the output voltage swing is 20V. As can be seen from the three subgraphs of Figure 5 , when the working voltage is lower, the rising and falling edges of the output signal become slower. As long as the input control signal pulse width is long enough, the circuit can have enough charging and discharging time. Therefore, the gate drive circuit provided by the present application can adapt to the voltage change from 2V to 20V.

[0076] As can be seen from the simulation waveform of Figure 6 , the gate drive circuit provided by the present application still maintains the normal output waveform under the threshold voltage change of 10V. Figure 6 ​In accordance with the order from top to bottom, the first subgraph represents the output waveform corresponding to the threshold voltage negative drift 1.5V, the second subgraph represents the output waveform corresponding to the threshold voltage in the initial state, and the third subgraph represents the output waveform corresponding to the threshold voltage positive drift 8.5V. From the three subgraphs, it can be seen that when the voltage parameter VGH-VGL of the gate drive circuit changes from 2V to 20V, the output voltage swing completely follows the change of the voltage and still maintains the normal output waveform in the case of a threshold voltage change of 10V. Figure 6 In combination with the simulation results in the foregoing embodiments and Figures 4-6 , it can be determined that the gate drive circuit provided by the application has the following technical effects:

[0077] (1) The gate drive circuit provided by the application only includes six TFTs and one capacitor, the inter-stage connection mode is simple, the output signal of the previous stage is used as the input pulse signal of the next stage, the wiring structure is simple, the circuit logic is simple, the transistor size can be adjusted to output an ideal waveform, the transistor size can be adjusted in a large range, and the robustness is good. The adjustable range of VGH and VGL is large, based on the requirements of different systems, the structure can support the swing control of the preset voltage range, in addition, under the condition of high voltage work, the circuit can still output a stable waveform under the condition of a threshold voltage drift of 10V.

[0078] (2) The non-overlapping GOA output signal can be realized by designing a single-stage gate drive circuit, the structure fully considers the influence of the transistor size, has a high threshold voltage drift tolerance, and can support a voltage control range of 2V-20V. In the case that the pulse width of the input pulse signal and the clock signal is small enough, the circuit can support 1k display / sensor matrix driving / reading.

[0079] Although the application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art by referring to the accompanying drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. Some measures are described in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0080] Although the present application has been described in connection with the preferred embodiments thereof with reference to the specific content thereof, it will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. Accordingly, it is intended that the present application cover all such modifications and changes as fall within the scope of the application, along with all equivalents thereof. It will be understood by those within the art that, in general, terms used herein, and especially to the immediately preceding description and claims attached hereto, are intended to be given their broadest interpretation consistent with the specification and the patent statutes.

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit comprises: six thin film transistors and a capacitor; four of the six thin film transistors are switch thin film transistors, and the other two are drive thin film transistors; the two switch thin film transistors constitute an inverter, and the two drive thin film transistors constitute an output module; the gate drive circuit realizes a row-by-row scanning driving function based on external control signals; the external control signals include a direct current level signal, an input pulse signal and a clock signal; the thin film transistors are N-type devices; the direct current level signal includes a first level signal and a second level signal, the level corresponding to the first level signal is higher than the level corresponding to the second level signal; the clock signal includes a first clock signal and a second clock signal; the four switch thin film transistors include a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; the two drive thin film transistors include a first transistor and a second transistor; the fourth transistor and the sixth transistor constitute the inverter; the third transistor controls the voltage at a first node in the gate drive circuit, and the fifth transistor controls the voltage at a second node in the gate drive circuit; the row addressing signal finally generated by the gate drive circuit is connected to the gate of a display matrix or a sensing matrix; in a preset stage, the input pulse signal and the first clock signal are both at the level corresponding to the first level signal, and the second clock signal is at the level corresponding to the second level signal; the third transistor and the fifth transistor are turned on, at this time, the first node is set to a high level; the sixth transistor in the inverter is turned on, and the fourth transistor is turned off, at this time, the second node is set to a high level, and the first transistor and the second transistor are both turned on, thereby realizing the preset of the first node and the second node; in a capacitor coupling stage, the input pulse signal and the first clock signal are both at the level corresponding to the second level signal, and the second clock signal is at the level corresponding to the first level signal; the third transistor and the fifth transistor are turned off; the sixth transistor and the fourth transistor in the inverter are both turned on, at this time, the second node in the gate drive circuit is set to a low level; the second transistor is turned off, the second clock signal jumps from a low level to a high level, and through the capacitor coupling effect, the potential at the first node in the gate drive circuit is higher than the level corresponding to the first level signal, so as to compensate for the threshold voltage loss, at this time, the row addressing signal finally generated is at the level corresponding to the first level signal.

2. The gate drive circuit according to claim 1, characterized by the voltage ranges of the first clock signal, the second clock signal and the input pulse signal are all VGL-VGH, wherein VGH represents the level of the first level signal, and VGL represents the level corresponding to the second level signal; when the sixth transistor is turned on, the inverter sets the VGL voltage to the second node, and the inverter is in an off state at other times. The first clock signal and the second clock signal of adjacent stages are alternately connected, and the row addressing signal finally generated by the gate drive circuit of the previous stage is also connected to the input end of the gate drive circuit of the next stage.

3. The gate drive circuit according to claim 1, characterized by In the high-level resetting stage, the input pulse signal and the second clock signal are both at the level corresponding to the second-level signal, the first clock signal is at the level corresponding to the second-level signal, the first node is set to low level, the second node is set to high level, the finally generated row addressing signal is at the level corresponding to the second-level signal, and the inverter is in the off state.

4. The gate drive circuit according to claim 1, characterized by In the holding stage, the input pulse signal and the first clock signal are both at the level corresponding to the second-level signal, and the second clock signal is at the level corresponding to the first-level signal, the first node is set to low level, and the second node is set to high level. The finally generated row addressing signal outputs low level, the first node always maintains low potential, and the second node always maintains high potential until the next low-level pulse of the input pulse signal is input.

5. The gate drive circuit according to claim 1, characterized by The thin film transistor is an amorphous silicon thin film transistor, an amorphous indium gallium zinc oxide thin film transistor or a low-temperature polysilicon thin film transistor; the threshold voltage of the thin film transistor is about 0V, and the sub-threshold voltage swing is less than 250mV / dec.

6. The gate drive circuit according to claim 1, characterized by When the thin film transistor is a P-type device, the level corresponding to the first-level signal is less than the level corresponding to the second-level signal, VGH represents the level of the second-level signal, VGL represents the level corresponding to the first-level signal, and the clock signal is opposite to the N-type device.

7. The gate drive circuit according to claim 1, wherein The gate drive circuit can generate an output signal with a voltage swing of 2-20V; and when the pulse width of the input pulse signal and the clock signal is less than a preset threshold, the gate drive circuit supports the driving and reading of a 1k display matrix or a sensing matrix.

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