Method of manufacturing a semiconductor device and corresponding semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device and a corresponding semiconductor device. A semiconductor chip or die is disposed on a first surface of a thermally conductive die pad of a substrate, such as a lead frame. A package of insulating material is molded onto the die pad with the semiconductor die disposed on the first surface. At a second surface of the die pad opposite the first surface, the package borders on the die pad at a boundary line surrounding the die pad. A recessed portion of the package is provided at the boundary line surrounding the die pad, for example by laser ablation. A thermally conductive material, such as a metallic material, is filled in the recessed portion of the package surrounding the die pad. The surface area of the thermally conductive die pad is increased by filling the thermally conductive material in the recessed portion of the package, thereby improving the thermal performance of the device.

Description

Methods for manufacturing semiconductor devices and corresponding semiconductor devices

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102022000008897, filed on May 3, 2022, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This specification relates to semiconductor devices.

[0004] One or more embodiments may be applied to, for example, power semiconductor devices, including gallium nitride (GaN) or silicon carbide (SiC) devices. Background Technology

[0005] For example, the trend toward miniaturization of semiconductor dies based on gallium nitride (GaN) or silicon carbide (SiC) devices has led to a search for improved heat dissipation performance in the packaging of small integrated circuit (IC) dies.

[0006] One way to achieve this performance improvement is to increase the size of the die pads at the leadframe design level.

[0007] This affects the lead frame size and the lead length in the lead bonding pattern.

[0008] Another solution relies on a lead frame that includes leads with overhanging die pads.

[0009] While conceptually appealing, this approach can be quite complex and expensive to implement.

[0010] There is a need in this field to help fully address the aforementioned problems. Summary of the Invention

[0011] One or more embodiments may relate to a method.

[0012] One or more embodiments may relate to corresponding semiconductor devices.

[0013] The examples presented in this article involve increasing (i.e., expanding) the back or bottom area of ​​the die pads without additionally affecting the die size and die-to-lead joint length.

[0014] For example, a laser beam can be used to form a groove around the periphery of the bottom surface of the die pad. A thermally conductive material (e.g., a metal such as copper) is filled (e.g., grown) in the groove to extend the die pad area on the bottom side of the package.

[0015] A seed layer of copper or the full desired thickness can be spray-printed, optionally followed by electroplating.

[0016] Laser direct forming (LDS) materials can be used as encapsulation molding materials, and thermally conductive materials (e.g., metals such as copper) can be grown in the groove using conventional methods in standard LDS processes (electro-free electroplating).

[0017] Thermally conductive materials (such as copper) can also be grown in the grooves using a laser-induced forward transfer (LIFT) process.

[0018] The thickness of the resulting die pad extension can be equal to or different from the thickness of the leadframe die pad.

[0019] One or more embodiments involve the use of molding materials compatible with laser direct forming (LDS).

[0020] This process can be used in conjunction with conventional molding equipment and known packaging. Due to the small amount of LDS material involved, the higher cost of LDS compounds has almost no impact on the total packaging cost and is advantageously less than any cost associated with possible package redesign.

[0021] The embodiments used in this specification can be identified, for example, by the different surface morphology of the basic die pad compared to the surrounding grown material, to increase the die pad size. Leads in the leadframe of an "overhanging" die pad can further indicate that the die pad has been enlarged by additional material grown around it after the leadframe is manufactured. Additionally, molding compound analysis can highlight the use of molding compounds compatible with laser direct forming (LDS) processes. Attached Figure Description

[0022] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0023] Figures 1A and 1B are exemplary partial cross-sectional views of a step or stage in the manufacture of a semiconductor device;

[0024] Figures 2A and 2B are partial cross-sectional views of another step or stage in the exemplary manufacture of a semiconductor device;

[0025] Figures 3A and 3B are partial cross-sectional views illustrating an example of another step or stage in the fabrication of a semiconductor device; and

[0026] Figures 4 and 5 are functional flowcharts comparing the conventional sequence of steps in semiconductor device manufacturing and the sequence of steps in semiconductor device manufacturing according to embodiments of this specification. Detailed Implementation

[0027] Unless otherwise specified, corresponding numbers and symbols in different figures usually refer to the corresponding parts.

[0028] The accompanying drawings are provided to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0029] The edges of features drawn in the attached figures do not necessarily indicate the end of the feature range.

[0030] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0031] References to "an embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment.

[0032] Furthermore, in one or more embodiments, specific conformations, structures, or features can be combined in any suitable manner.

[0033] The headings / references used herein are provided for convenience only and are not intended to limit the scope of protection or the scope of the embodiments.

[0034] For simplicity and ease of explanation, throughout this specification: the same parts or elements in each figure are indicated by the same reference numerals, and the corresponding descriptions are not repeated for each figure; and the manufacture of a single device will be described. It should also be understood that current manufacturing processes for semiconductor devices involve the simultaneous manufacture of multiple devices, which are separated into a single device in the final dicing.

[0035] Figures 1A-1B, 2A-2B, and 3A-3B are exemplary partial cross-sectional views of certain steps or stages in the manufacture of a semiconductor device 10 with a plastic package.

[0036] Specifically: the left figure (Figure 1A, Figure 2A and Figure 3A) is an example of an arrangement using wire bonding to provide electrical connections to a semiconductor chip or die; and the right figure (Figure 1B, Figure 2B and Figure 3B) is an example of an arrangement where electrical connections to a semiconductor chip or die are provided using laser direct forming (LDS) technology.

[0037] As is conventional in the prior art, device 10 includes a substrate (lead frame) on which one or more semiconductor chips or dies are disposed.

[0038] As used herein, the terms chip and die in relation to integrated circuits are considered synonymous.

[0039] Figures 1A-1B, 2A-2B and 3A-3B refer in an exemplary manner to a semiconductor device 10 including a die pad 12A in a lead frame, the lead frame also including an array of leads 12B surrounding the die pad 12A, the die pad 12A having, for example, a semiconductor integrated circuit (IC) chip or die 14 attached thereto via a die attachment film (DAF) 140.

[0040] The term “lead frame” (or “lead frame”) (see, for example, the USPC Combined Glossary of Terms) refers to a metal frame that provides support for an integrated circuit chip or die, and electrical leads that interconnect the integrated circuit in the chip or die to other components or contacts.

[0041] Essentially, the leadframe includes an array of conductive structures (or leads, e.g., 12B) extending inward from the outline location along the direction of the semiconductor chip or die (e.g., 14), thereby forming an array of conductive structures from die pads (e.g., 12A), which are configured to have at least one semiconductor integrated circuit chip or die attached thereto.

[0042] Some semiconductor devices may actually include multiple die pads and / or multiple dies or chips attached to the die pads or each die pad. For simplicity and ease of explanation, this specification relates to a device 10 including a single die pad 12A on which a single chip or die is attached (on the first surface, facing upward in the figure).

[0043] A conductive structure is provided to electrically couple the semiconductor chip 14 to a selected lead in the lead frame 12B.

[0044] As shown in Figures 1A, 2A, and 3A, these conductive structures may include a wire bonding pattern 16 for selecting leads that couple chip 14 to leads 12B. The wires in the wire bonding pattern 16 are coupled to die pads provided on the front or top surface of chip 141 (not visible due to scale).

[0045] An insulating encapsulation 20 (e.g., epoxy resin) is molded onto the above-formed assembly to complete the plastic body of the device 10.

[0046] Laser direct forming (LDS – also commonly known as direct copper interconnect (DCI) technology) is a laser-based processing technology now widely used in various sectors of the industrial and consumer electronics markets, such as for high-performance antenna integration, where antenna designs can be directly formed on molded plastic parts.

[0047] In an exemplary process, the molded part can be produced using a commercially available insulating resin that includes additives suitable for the LDS process; a wide range of resins, such as polymeric resins like PC, PC / ABS, ABS, and LCP, are currently available for this purpose.

[0048] In LDS, a laser beam can be used to transfer (“build”) a desired conductive pattern onto a plastic molded part, which can then be metallized to complete the desired conductive pattern.

[0049] Metallization may include electroless plating, followed by electrolytic plating.

[0050] Electroless plating, also known as chemical plating, is an industrial chemical process that produces a metal coating on various materials through the autocatalytic chemical reduction of metal cations in a liquid bath.

[0051] In electroplating, the electric field between the anode and the workpiece, which serves as the cathode, forces positively charged metal ions to move to the cathode, where they release their charge and deposit themselves as metal onto the surface of the workpiece.

[0052] References to U.S. Patent Application Publications Nos. 2018 / 342453A1, 2019 / 115287A1, 2020 / 203264A1, 2020 / 321274A1, 2021 / 050226A1, 2021 / 050299A1, 2021 / 183748A1, or 2021 / 305203A1 (all incorporated herein by reference) are examples of the possibility of applying LDS technology in the manufacture of semiconductor devices.

[0053] As shown in Figures 1B, 2B, and 3B, LDS technology facilitates the replacement of wires such as 16 with wires / through-holes produced by laser beam processes through LDS materials and subsequent metallization (e.g., growing metals such as copper through electroplating processes).

[0054] A conductive die to lead coupling structure (e.g., as discussed in the previously cited co-assigned application) can be provided in an insulating package 18 of LDS material (once cured, e.g., by thermosetting).

[0055] As shown in Figures 1B, 2B, and 3B, these die-to-lead coupling structures include: a first through-molding via (TMV) 181 extending through the LDS package 18 between the top (front) surface 18A of the LDS package 18 and a conductive pad (mentioned in conjunction with wire bonding pattern 16 and not visible for scale) on the front or top surface of the chip or die 14; a second through-molding via (TMV) 182 extending through the LDS package 18 between the top (front) surface 18A of the LDS package 18 and a corresponding lead 12B in the lead frame; and a conductive line or trace 183 extending at the front or top surface 18A of the LDS package 18 and electrically coupling a selected via in the first via 181 to a selected via in the second via 182 to provide a desired die-to-lead electrical connection (wiring) pattern between the chip or die 14 and the lead 12B.

[0056] Providing conductive dies to lead structures 181, 182, and 183 essentially includes (see Figures 2B and 3B): structuring these structures in the LDS material of package 18, for example, by applying laser beam energy to “activate” (and partially drill / ablate) the LDS material 18 at desired locations 181', 182', 183' for through holes 181, 182, and lines or traces 183; and growing conductive material (e.g., a metal such as copper) at the previously activated (structured) locations 181', 182', 183' via laser beam energy.

[0057] The growth of conductive materials can involve depositing metals such as copper through electroless / electrolytic metal growth to enhance the conductivity of structured structures.

[0058] Conductive materials can also be grown using a laser-induced forward transfer (LIFT) process, which includes a deposition process in which material is transferred from a donor strip or sheet to an acceptor substrate (here, an LDS material) by means of a laser pulse.

[0059] General information about the LIFT process can be found, for example, in P. Serra et al., “Laser-Induced Forward Transfer: Fundamentals and Applications”, Advanced Materials Technologies, Vol. 4, No. 1 (incorporated hereby by reference).

[0060] The semi-segmented arrangement of Figures 1A to 3A and Figures 1B to 3B is intended to emphasize the processes that can be applied as discussed below, resulting in an increase in the surface area of ​​die pad 12A (i.e., increasing its size by adding to or enlarging it to the die pad): i) for devices 10 including wire bonding patterns 16 such as those in Figures 1A, 2A, and 3A, where package 20 can be a conventional package (e.g., epoxy) that insulates the wire bonding patterns 16 (Figures 1A, 2A, and 3A); and ii) for devices 10 where package 18 is an LDS material, thus facilitating the provision of conductive structures 181, 182, and 183 therein (Figures 1B, 2B, and 3B).

[0061] Therefore, a device 10 is expected to adopt either scheme i) or ii) above, thus including: two (generally) mirror-symmetric parts, each as shown in FIG1A, FIG2A and FIG3A; or two (generally) mirror-symmetric parts, each as shown in FIG1B, FIG2B and FIG3B.

[0062] The term “roughly” is intended to take into account the fact that lead bonding patterns such as 16 (in the “wired” form of Figures 1A, 2A and 3A) and conductive structures such as 181, 182 and 183 (in the “laser-structured” form of Figures 1B, 2B and 3B) do not necessarily have wire / line wiring patterns that are strictly mirror-symmetrical with respect to any intermediate plane of device 10.

[0063] It should be understood that the examples discussed here primarily concern the packaged thermal performance of devices such as device 10, rather than the specific details of die-to-lead (or die-to-die) electrical coupling therein.

[0064] The package thermal performance of device 10 considered here is determined by package design and material selection, and can be modeled based on various parameters.

[0065] For example: Theta JA (θja) = junction-to-air thermal resistance; this is a measure of the device's ability to dissipate heat from the die surface to the surrounding environment through all possible paths; theta JC (θjc) = junction-to-case thermal resistance; this is a measure of the device's ability to dissipate heat from the die surface to the top or bottom surface of the package; theta Jb (θJb) = thermal resistance from the junction to the board on which the device is mounted; and psi JB (Ψjb) is a thermal characterization parameter of the junction to the board; this is a measure of the power flowing from the device through multiple thermal paths rather than a single direct path (such as thermal resistance).

[0066] The parameters introduced above are measured in °K / W.

[0067] As discussed in the introductory section of this specification, semiconductor (silicon) miniaturization leads to changes in package design. These involve reducing the size of the die pads (or heat sinks), which in itself will have a negative impact on thermal performance.

[0068] The current trend toward chip miniaturization demands improved (higher) package heat dissipation, and package designs are not always compatible with this specification: when accommodating smaller dies, die pad sizes are reduced to decrease connection lengths.

[0069] In practice, heat dissipation is improved in response to the increase in die pad size. New technologies (such as gallium nitride (GaN) or silicon carbide (SiC)) can specify more stringent heat dissipation specifications, thus leading to limitations in package selection.

[0070] Packaging redesign or packaging change can be seen as an option to solve this problem; however, packaging redesign involves higher development costs and may not meet customer requirements.

[0071] Other options may involve modifications to the materials, such as reducing the die thickness or improving the die attachment material. However, these measures are not as effective as redesigning the packaging.

[0072] Therefore, it is desirable to enhance the thermal properties of the package without adversely affecting lead connections and leadframe design (as well as the range of applicability and customization, thus enabling device flexibility).

[0073] The example presented here “enlarges” (increases) the back or bottom area of ​​die pad 12A (facing down in Figures 1A-1B to 3A-3B) without affecting the die size and die-to-lead joint length.

[0074] Figures 1A and 1B are examples of steps or stages in which at least one semiconductor chip 14 is arranged on the first surface (facing upward) of a thermally conductive (e.g., metal such as copper) die pad 12A in a substrate (lead frame).

[0075] The die pad 12A has a second surface (facing downwards in the figure) opposite to the first surface, and an insulating material package 18, 20 is molded onto the die pad 12A in a manner known to those skilled in the art. The die pad 12A has at least one semiconductor chip 14 disposed on the first surface.

[0076] As a result of molding, at the second surface of die pad 12A, packages 18 and 20 are attached to (and substantially flush with) the second surface of die pad 12A along the boundary line around die pad 12A (i.e., along the outer contour of the second surface of die pad 12A).

[0077] As illustrated in Figures 2A and 2B, a recess or groove (continuous / discontinuous) 120A can be formed around the periphery of the second (back or bottom) surface of the die pad 12A.

[0078] As shown in Figures 3A and 3B, a thermally conductive material (e.g., a metal such as copper) is grown (filled) in the groove 120A to increase the surface area of ​​the die pad region at the bottom side of the package (i.e., by increasing the surface area), as shown in 122A.

[0079] This concept refers to providing (continuous / discontinuous) recessed portions 120A of packages 18, 20 surrounding the second (back or bottom) surface of die pad 12A, for example, by removing insulating material from packages 18, 20 molded onto die pad 12A at the boundary line of the second surface of die pad 12A, to provide recessed portions 120A of packages 18, 20 surrounding die pad 12A, or otherwise (e.g., via molding); filling the recessed portions 120A of packages 18, 20 around die pad 12A with thermally conductive material 122A to increase the surface area of ​​thermally conductive die pad 12A by filling it with thermally conductive material 122A; and facilitating implementation in different ways: regardless of the specific implementation option, the thickness of the die pad extension indicated by reference numeral 122A may be different from or the same as the thickness of die pad 12A.

[0080] Forming the groove 120A may include, for example, selectively removing encapsulating material.

[0081] As illustrated at LB in Figures 2A and 2B, ablation by laser beam has been found to be advantageous due to its flexibility (e.g., an etching mask can be omitted).

[0082] The thermally conductive material 122A is grown (filled) in the groove 120A, as shown in MG in Figures 3A and 3B. This can also be achieved in different ways.

[0083] For example, a seed layer or the entire required thickness of material (e.g., copper) can be jet-printed into the groove 120A, which may then be electroplated.

[0084] Using a laser direct forming (LDS) material for package 18 represents an advantageous option in that the laser beam energy LB used to form recess 120A in package 18 at the rear or bottom surface of device 10 can be similarly used for through holes 181, 182 and lines or traces 183 (see 181', 182' and 183' in FIG. 2B) at the front or top surface 18A where the "structure" is "activated" (by "activating" the LDS material); and the same processes, such as electroplating (e.g., electroless electrolytic deposition) or LIFT processes, can be used to grow a conductive / thermal conductive material (e.g., a metal, such as copper) at recess 120A to extend the heat sink pad area at the bottom side of the package at 122A and promote conductivity of through holes 181, 182 and lines or traces 183 at the front or top surface of device 10 (see FIG. 2B).

[0085] Laser-direct forming (LDS) materials can also be used for the package 20 shown in Figures 1A, 2A and 3A, i.e. for the packaging of wire bonding patterns (e.g., wire bonding pattern 16) in the “wiring” form of the packaged device 10.

[0086] Similarly, in the latter case, the laser beam energy LB can be used to drill / ablate the LDS material of the package to form a recess 120A, for example, by electroplating (e.g., electroless electrolytic deposition), and a LIFT process (or jet printing) is used to grow a conductive / thermal conductive material at the recess 120A to extend the heat dissipation die pad area at the bottom side of the package at 122A.

[0087] It should be noted that the laser beam energy LB drills / ablates some LDS material (thus providing a forming effect or function), and in doing so, it also activates the LDS material (thus affecting the surface properties of the LDS molding compound).

[0088] Laser direct forming (LDS) can be used in conjunction with conventional mold-making equipment and known packaging.

[0089] The examples presented in this article facilitate the enlargement of the die pad area 12A without additional impact on the package design. The die pad enlargement is performed after molding and does not affect the leadframe design. Leadframe features (such as short connections from die to lead) can be maintained while improving thermal performance.

[0090] This is demonstrated by the functional flowcharts in Figures 4 and 5. These flowcharts respectively relate to the conventional sequence of steps in manufacturing a semiconductor device (Figure 4) and the sequence of steps in manufacturing a semiconductor device according to embodiments of this specification (Figure 5).

[0091] It should also be understood that the order of steps in Figures 4 and 5 is merely exemplary, provided that: one or more steps shown may be omitted, performed in a different manner (e.g., with other tools), and / or replaced by other steps; additional steps may be added; and one or more steps may be performed in an order different from that shown.

[0092] In Figures 4 and 5, box 100 collectively indicates those steps that produce the basic structure of a semiconductor device in a manner known to those skilled in the art (e.g., attaching one or more chips or dies 14 to die pads 12A, etc.) prior to molding an insulating package thereon.

[0093] This step (e.g., conventional encapsulation 20 of molded epoxy resin) is shown at 102 in Figure 4, followed by (tin) plating and “cropping”, as indicated by boxes 104 and 106 in Figure 4, respectively.

[0094] The resulting “standard” die pad 12A is shown at the bottom of Figure 4: this can be seen as a schematic diagram of the device 10 as viewed from the back or bottom of the device 10.

[0095] In the exemplary case shown in Figure 5, after box 100 is a sequence 102' of molding steps for encapsulating LDS material 18, followed by the LDS process at 102B.

[0096] As previously discussed in conjunction with Figures 2B and 3B, this process may involve applying laser beam energy LB to form a groove 120A on the back or bottom surface of the device 10 and to structure through-holes 181, 182 and lines or traces 183 on the front or top surface of the device 10.

[0097] In Figure 5, the plating at 104′ can represent copper plating + tin plating (e.g., electroless electrolytic deposition) or a LIFT process, which is used to grow a conductive / thermal conductive material (e.g., a metal, such as copper) at the recess 120A to extend the heat sink pad area at the bottom side of the package at 122A and to promote the conductivity of the through holes 181, 182 and the lines or traces 183 at the front or top surface of the device 10.

[0098] The bottom of Figure 5 shows the resulting standard die pad 12A with an “enlarged” surface area at 122A: this can be seen as a schematic diagram of the device 10 as viewed from the back or bottom of the device 10.

[0099] Although represented herein as a continuous and adjacent frame surrounding the original die pad 12A, in some embodiments, the augmentation portion 122A may be discontinuous (i.e., comprising multiple segments or dots in a dashed / dotted pattern) and / or not adjacent to the original die pad 12A (i.e., having a separation gap).

[0100] It should be understood that enlarging the die pad 12A at 122A (thus improving the heat dissipation of the device 10) occurs without increasing the overall size of the device 10, and more precisely, without increasing the length of the electrical connection path (e.g., wire 16 or “LDS structured” structure 181, 182, 183) between the semiconductor chip 14 and the lead 12B.

[0101] In fact, as can be seen in the examples presented in this article, lead 12B can protrude over the amplified portion 122A of die pad 12A (overhang).

[0102] The examples presented in this article can actually be applied to any leadframe-based plastic package.

[0103] The table below reports comparative data for PSSO36 packages with die dimensions in the μm range (X:Y:Z): 4182 vs. 3262 vs. 375, obtained through TRAC simulation. Wired version. Die attachment material: soft solder.

[0104]

[0105]

[0106] Without departing from the basic principles, details and embodiments may be changed, even significantly changed, relative to what has been described by example only, without departing from the scope of protection.

[0107] The scope of protection is determined by the appended claims.

[0108] The claims form an integral part of the technical teachings of the embodiments provided herein.

Claims

1. A method for manufacturing a semiconductor device, comprising: A semiconductor integrated circuit die is arranged on a first surface of a thermally conductive die pad on a substrate, the thermally conductive die pad having a second surface opposite to the first surface; An insulating material encapsulation is molded onto the thermally conductive die pad, wherein, at the second surface of the thermally conductive die pad, the encapsulation is adjacent to the thermally conductive die pad at a boundary line surrounding the thermally conductive die pad; a recessed portion of the encapsulation surrounding the thermally conductive die pad is provided at the boundary line surrounding the thermally conductive die pad; and a thermally conductive material is filled in the recessed portion of the encapsulation; wherein the surface area of ​​the thermally conductive die pad at the second surface is enlarged by the thermally conductive material in the recessed portion of the encapsulation.

2. The method according to claim 1, wherein filling the thermally conductive material comprises one of the following: spraying and printing the thermally conductive material at the recessed portion; plating the thermally conductive material at the recessed portion; or laser-induced positive transfer of the thermally conductive material at the recessed portion.

3. The method of claim 1, wherein providing the recessed portion includes removing insulating material from the package molded onto the thermal die pad at the boundary line surrounding the thermal die pad.

4. The method of claim 3, wherein removal comprises applying laser beam energy to the package.

5. The method of claim 3, wherein the insulating material of the package comprises laser-directly formed LDS material, and wherein removal includes applying laser forming to the LDS material of the package at the boundary line surrounding the thermal die pad.

6. The method of claim 5, wherein the encapsulated LDS material has a front surface opposite the thermal die pads, and further comprises: Structured through-holes extending from the front surface into the package are formed in the LDS material of the package; And a connecting line structured in the LDS material of the package, extending between selected perforations in the perforation above the front surface.

7. The method of claim 6, further comprising: Laser energy is applied to the LDS material of the package at candidate locations for the through-hole and the connecting wire; And after applying laser beam energy, a conductive material is filled at the candidate location to provide a conductive through-hole and connecting wire at the candidate location.

8. The method of claim 7, wherein the filling conductive material comprises: Electroplating of conductive material at the candidate location; Alternatively, laser-induced positive transfer of the thermally conductive material at the candidate location.

9. The method of claim 1, wherein the thermally conductive material filling the recessed portion of the package has a thickness different from the thickness of the thermally conductive die pad.

10. The method of claim 1, wherein the substrate comprises an array of conductive leads surrounding the thermally conductive die pad, and wherein the conductive leads protrude over the thermally conductive material filling the recessed portion of the package.

11. The method of claim 1, wherein the thermally conductive die pad is made of a conductive material, and wherein the thermally conductive material in the recessed portion of the encapsulation is made of a conductive material.

12. A semiconductor device, comprising: A semiconductor die, disposed on a first surface of a thermally conductive die pad on a substrate, the thermally conductive die pad having a second surface opposite to the first surface; An insulating material encapsulation is molded onto the thermally conductive die pad, the thermally conductive die pad having the semiconductor die disposed on the first surface; wherein, at the second surface of the thermally conductive die pad, the encapsulation has a recessed portion of the encapsulation surrounding the thermally conductive die pad; and a thermally conductive material is disposed in the recessed portion of the encapsulation; wherein the surface area of ​​the thermally conductive die pad at the second surface is enlarged by the thermally conductive material in the recessed portion of the encapsulation.

13. The semiconductor device of claim 12, wherein the thermally conductive material in the recessed portion of the package provides a continuous and / or adjacent framework around the thermally conductive die pad at the second surface of the thermally conductive die pad.

14. The semiconductor device of claim 12, wherein the thermally conductive material in the recessed portion of the package has a thickness equal to the thickness of the thermally conductive die pad.

15. The semiconductor device of claim 12, wherein the thermally conductive material filling the recessed portion of the package has a thickness different from the thickness of the thermally conductive die pad.

16. The semiconductor device of claim 12, further comprising an array of conductive leads surrounding the thermally conductive die pad, wherein the conductive leads in the conductive lead array protrude over the thermally conductive material filling the recessed portion of the package.

17. The semiconductor device of claim 12, wherein the thermally conductive die pad is made of a conductive material, and wherein the thermally conductive material in the recessed portion of the package is made of a conductive material.

Images