Power management chip based on aot fixed slope soft start buck circuit

Abstract

The application discloses a power management chip based on AOT fixed slope soft start Buck circuit, adds an error amplifier control loop on the basis of a traditional ripple AOT architecture, and opens a power tube when an output ripple falls to an error amplifier output; a PLL control loop is used to phase lock a switching frequency and an internal reference clock frequency to realize a pseudo constant frequency effect; an output voltage fixed proportional voltage division and an internal fixed slope rising reference source error amplifier are used to realize different output voltage fixed slope soft start power-on, and the soft start is ended after output power-on is completed to prevent a surge generated by inductance current stress at different output voltages; the application uses an inductance current ripple compensation and a direct current bias scheme to bias a direct current output of the error amplifier in a normal working state as a reference voltage, so that VC rises to a power supply to realize distinction when the system output is 100% duty cycle, and 100% duty cycle output control based on the ripple AOT is completed.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a power management chip based on an AOT fixed-slope soft-start Buck circuit. Background Technology

[0002] Power management chips manage the power supply to various modules in a system. Common power management chips can be divided into linear regulators and switching power supplies. Switching power supplies are widely used in AC / DC converters and DC / DC converters due to their high buck ratio, high efficiency, high precision, and low output ripple. Based on different topologies, they can be classified as buck converters, boost converters, flyback converters, forward converters, half-bridge converters, and full-bridge converters, as well as switched capacitors. Buck converters, as a common control method in DC / DC converters, include hysteresis, constant on-time, and PWM control. Based on different feedback signals, they can be classified as current-source, voltage-source, and output ripple-source. These different control and feedback methods have led to numerous control schemes.

[0003] The COT (Constant On Time) architecture is widely used in everyday applications due to its excellent transient response, simple architecture, and high conversion efficiency. Common COT architectures include inductor current-based and output ripple-based architectures. The output ripple-based architecture offers faster transient response. A typical system architecture is shown below. Figure 1 As shown, by connecting Rc and Cc in series across the inductor L, and then AC coupling through C1 to obtain the inductor current ripple, the DC bias is given to VFB through resistor Rb, and the output voltage ripple is sampled to obtain the signal V. DCR Through feedback voltage VFB and reference voltage error amplification and V DCR In comparison, the MP power transistor is turned on. In a traditional COT transistor, its on-time is constant, resulting in large variations in switching frequency under different voltages, leading to high system noise and instability. A conduction time control module is typically added to address frequency changes under different output voltages. This module dynamically adjusts the on-time based on the output voltage to achieve pseudo-constant frequency output, i.e., Adaptive On Time (AOT) control. Previously, constant frequency control was achieved by keeping the reference voltage Von constant during the on-time period, thus controlling the charging current during the on-time period to be inversely proportional to the input voltage and directly proportional to the output voltage. However, this control method results in an unstable switching frequency, significantly affected by circuit manufacturing errors and voltage deviations. Precise clock control requires multiple fabrication verifications, which is time-consuming and labor-intensive.

[0004] In traditional power management chips, the power-on process commonly used in the aforementioned system control schemes typically employs soft-start to prevent overshoot and overcurrent during power-on. Most soft-start schemes dynamically raise the reference voltage Vref at the inverting input of the error amplifier from zero to the required reference voltage during the soft-start phase using a fixed soft-start time. Figure 2 As shown, this is to achieve output voltage following a reference voltage rising from zero during soft start, controlling the power required for output during this stage and preventing overcurrent during power-up. Vref rise typically includes digitally controlled stepped rise and analog-controlled current-charge capacitor schemes. In the analog control scheme, the rise slope of the reference voltage is fixed by fixing the soft start time, but the rise slope of different output voltages is different. The required soft start time is the same, leading to inconsistent inductor current stress under different output voltages. The digitally controlled stepped rise scheme is widely used, but each step of Vref causes a sudden increase and then decrease in inductor current, forming an inductor current surge phenomenon, which seriously affects the chip's EMI characteristics and also has a certain impact on the inductor's lifespan. Summary of the Invention

[0005] In view of the above, the present invention provides a power management chip based on an AOT fixed-slope soft-start Buck circuit, which can achieve a fixed-slope soft-start of the output voltage under different input and output voltages, effectively avoiding inductor current surges during the soft-start process, and achieving 100% duty cycle output under the AOT architecture.

[0006] A power management chip based on an AOT fixed-slope soft-start Buck circuit is disclosed. The Buck circuit includes an inductor L, power transistors MP and MN, resistors Rc, Rp, and Rn, capacitor Cc, and capacitor C1. The source of power transistor MP is connected to the input voltage VIN. The drain of power transistor MP is connected to the drain of power transistor MN, one end of inductor L, and one end of resistor Rc, forming a SW node. The other end of resistor Rc is connected to one end of capacitor Cc and one end of capacitor C1. The other end of capacitor C1 generates a ripple signal V. DCR The other end of inductor L is connected to the other end of capacitor Cc and one end of resistor Rp to generate output voltage VOUT. The other end of resistor Rp is connected to one end of resistor Rn to generate feedback voltage V. FB The other end of resistor Rn is grounded, and the gates of power transistors MP and MN are connected to the drive signal provided by the chip; the power management chip includes:

[0007] Ripple sampling module, used to acquire ripple signal V DCR The output is then superimposed with a DC bias.

[0008] The reference circuit module, which is unaffected by the supply voltage, is used to provide the system with a reference voltage and a bias voltage.

[0009] The oscillator module generates a clock signal CLK through capacitor charging and discharging, providing a reference clock for system control;

[0010] The soft-start module detects the output voltage VOUT and the feedback voltage V. FB The system controls the input error amplifier based on the clock signal CLK, and then outputs the error amplification signal VC to achieve a fixed slope soft start under different output voltages.

[0011] The comparator module is used to process the ripple signal V with DC bias. DCR The turn-on control signal Sigon is obtained by comparing it with the error amplification signal VC. When Sigon is high, the power transistor MP is turned on.

[0012] The on-time control module generates an on-time control signal Von by comprehensively monitoring and judging the input voltage VIN, clock signal CLK, and drive signal PG_Ctl frequency. This control signal Von controls the on-time of the power transistor MP to stabilize its switching frequency as the input and output voltages change.

[0013] The zero-crossing detection shutdown module is used to monitor the voltage of the SW node. When the voltage of the SW node is detected to cross zero during the turn-on period of the power transistor MP, the output signal ZCD is high.

[0014] The current sampling module is used to sample the current flowing through the power transistor MP during its conduction period to obtain the signal Vsense;

[0015] The overcurrent protection module is used to determine the overcurrent of the signal Vsense and output the overcurrent protection signal OCP. When OCP is high, it triggers the system to enter the overcurrent protection mode.

[0016] The duty cycle control module generates a turn-off control signal Sigoff based on the error amplification signal VC and the conduction duration control signal Von to control the system duty cycle, so as to achieve a 100% duty cycle output of the system under the working requirement of VOUT=VIN;

[0017] The main control module performs logic processing based on the signal ZCD, the turn-on control signal Sigon, the turn-off control signal Sigoff, and the overcurrent protection signal OCP to generate the corresponding drive signals PG_Ctl and NG_Ctl for the power transistors MP and MN.

[0018] The driver module is used to amplify the power of the drive signals PG_Ctl and NG_Ctl and then drive the gates of the power transistors MP and MN to perform switching operations, respectively.

[0019] Furthermore, the power transistors MP and MN are integrated on-chip.

[0020] Furthermore, the ripple sampling module includes a resistor Rb and a buffer. One end of the resistor Rb is connected to the inverting input of the comparator module and is connected to the ripple signal V. DCR The other end of resistor Rb is connected to the output terminal of the buffer, and the input terminal of the buffer is connected to the feedback voltage V. FB Thus, the ripple signal V is obtained. DCR DC bias.

[0021] Furthermore, the soft-start module includes two PMOS transistors P1 and P2, four NMOS transistors N1 to N4, a capacitor C1, a hysteresis comparator Comp1, an 8-bit counter, two OR gates OR1 and OR2, an 8-input AND gate AND1, two 2-to-1 multiplexers mux1 and mux2, a D flip-flop, and an error amplifier. The source of PMOS transistor P1 is connected to the source of PMOS transistor P2 and connected to the power supply voltage VDD. The gate of PMOS transistor P2 is connected to the gate of PMOS transistor P1, the drain of PMOS transistor P1, and the drain of each NMOS transistor N1. The drain of PMOS transistor P2 is connected to the drain of NMOS transistor N3, and the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2. The gates of NMOS transistors N1 and N2 are connected to bias voltages VB1 and VB2, respectively. The gate of NMOS transistor N3 is connected to the signal SSOKN. The source of NMOS transistor N3 is connected to one end of capacitor C1, the drain of NMOS transistor N4, and the first input terminal of selector mux1. The other end of capacitor C1 is connected to the sources of NMOS transistors N2 and NMOS transistor N4. The non-inverting input terminal of hysteresis comparator Comp1 is connected to the feedback voltage V. FBThe inverting input of hysteresis comparator Comp1 is connected to a 0.59V reference voltage. The output of hysteresis comparator Comp1 is connected to the first input of OR gate OR1. The clock input of the 8-bit counter is connected to the clock signal CLK. The reset input of the 8-bit counter is connected to the system enable signal RDN (the system stops working when high). The 8 output ports of the 8-bit counter are connected to the 8 input ports of AND gate AND1. The output of AND gate AND1 is connected to the second input of OR gate OR1. The first input of OR gate OR2 is connected to the system enable signal RDN. The second input of OR gate OR2 is connected to the system exception signal Hiccup (the system is in an abnormal state). In its normal state (high level), the input of the D flip-flop is connected to the power supply voltage VDD. The clock input of the D flip-flop is connected to the output of the OR gate OR1. The reset input of the D flip-flop is connected to the output of the OR gate OR2. The output of the D flip-flop is connected to the gate of the NMOS transistor N4 and the selection ports of selectors mux1 and mux2, and outputs the signal SSOK. SSOKN is the inverted signal of SSOK. The second input of selector mux1 is connected to a 0.6V reference voltage. The first input of selector mux2 is connected to VOUT / 2 (obtained by voltage division of the output voltage VOUT through resistors). The second input of selector mux2 is connected to the feedback voltage V. FB The output of selector mux1 is connected to the non-inverting input of the error amplifier, and the output of selector mux2 is connected to the inverting input of the error amplifier. The output of the error amplifier generates the error amplification signal VC. During the soft-start phase, the soft-start module connects VOUT to the input of the error amplifier via a fixed-ratio voltage divider and a reference voltage. At this time, the reference voltage is a ramp signal with a fixed slope. After the soft-start ends, the module switches from the fixed-ratio voltage divider to the feedback voltage V. FB and a 0.6V reference voltage.

[0022] Furthermore, the zero-crossing detection module is configured by an external PFM signal. When the PFM signal is low, the system enters FCCM (Force Continuous Conduction Mode) under light load mode, and the output signal ZCD remains low. When the PFM signal is high, the system enters DCM (Discontinuous Conduction Mode) under light load mode, and the conduction time of the power transistor MP remains fixed. At this time, when the voltage of the SW node is detected to cross zero during the turn-on period of the power transistor MP, the output signal ZCD is high.

[0023] Furthermore, the duty cycle control module includes a PMOS transistor P17, a resistor R8, a hysteresis comparator Comp2, a comparator Comp3, a NAND gate NAND1, a pulse generator, and an AND gate AND2. The source of the PMOS transistor P17 is connected to the power supply voltage VDD. One end of the resistor R8 is connected to the drain and gate of the PMOS transistor P17 and the non-inverting input of the hysteresis comparator Comp2. The other end of the resistor R8 is grounded. The inverting input of the hysteresis comparator Comp2 is connected to the error amplification signal VC. The non-inverting input of the comparator Comp3 is connected to... The on-time control signal Von is used. The inverting input of comparator Comp3 is connected to the charging ramp signal Vramp. The output of hysteresis comparator Comp2 is connected to the first input of NAND gate NAND1 and the first input of AND gate AND2. The output of comparator Comp3 is connected to the second input of NAND gate NAND1. The output of NAND gate NAND1 is connected to the input of the pulse generator. The output of the pulse generator is connected to the second input of AND gate AND2. The output of AND gate AND2 outputs the turn-off control signal Sigoff. During normal system operation, the DC bias of VC is near the reference voltage of 0.6V. At 100% duty cycle output, the DC bias of VC is the power supply voltage. This control method distinguishes between the two.

[0024] Furthermore, the conduction duration control module includes a PLL modulation loop. The PLL modulation loop dynamically adjusts the MP conduction time flip threshold, Von, by detecting the phase difference between the power transistor MP's turn-on frequency and the clock signal CLK, and generates a charging ramp signal Vramp by charging the capacitor with a fixed current. When Vramp reaches Von, the duty cycle control module outputs a high-level turn-off control signal Sigoff to turn off the power transistor MP, and simultaneously resets Vramp to zero.

[0025] This invention adds an error amplifier control loop to the traditional ripple-based AOT architecture. When the output ripple falls to the error amplifier output, power transistor MP is turned on, followed by power transistor MN. This invention uses a PLL control loop to phase-lock the switching frequency and the internal reference clock frequency to achieve a pseudo-constant frequency effect. This invention utilizes a fixed-ratio voltage divider for the output voltage and an internal reference source error amplifier with a fixed-slope rise to achieve a fixed-slope soft-start power-on for different output voltages. After the output power-on is complete, the soft-start ends to prevent different inductor current stresses under different output voltages or surges generated during the soft-start phase. This invention uses an external RC inductor current ripple compensation and DC bias scheme to bias the error amplifier output DC to the reference voltage of 0.6V under normal operating conditions, so that when the system outputs 100% duty cycle, VC rises to the power supply to distinguish between the two, completing 100% duty cycle output control based on ripple-based AOT. Therefore, this invention has the following beneficial technical effects:

[0026] 1. The fixed-slope soft-start scheme of this invention can achieve fixed-slope soft-start under different input and output circuits, avoiding different current stresses or surges during the soft-start phase under different output voltages of the inductor. Specifically, the capacitor is charged to reach the reference voltage at a fixed slope, thereby achieving a fixed-slope rise of the reference voltage. Then, the error between the output voltage and the fixed-slope reference voltage is amplified by a fixed-ratio voltage divider. When VOUT reaches the set value, the soft start ends. Thus, the time required for soft start varies for different output voltages, but it can effectively avoid the inductor current surge problem in the traditional soft-start process, reduce EMI electromagnetic noise during system startup, and ensure the stability of system operation.

[0027] 2. The duty cycle control module in the power management chip of this invention enables the system to have a 100% duty cycle output function, and can realize the output configuration of VOUT=VIN. While adopting the AOT architecture to achieve fast response, it uses PLL loop modulation to improve the stability of the system operating frequency and effectively reduce the noise during system operation. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the control of a Buck system based on a traditional COT architecture.

[0029] Figure 2 This is a schematic diagram of the traditional digital soft-start process.

[0030] Figure 3 This is a schematic diagram of the power management chip structure based on the AOT fixed slope soft-start Buck circuit of the present invention.

[0031] Figure 4 This is a schematic diagram of the soft-start process of the present invention.

[0032] Figure 5 This is a schematic diagram of the soft-start module of the present invention.

[0033] Figure 6 This is a schematic diagram of the timing of key signals in the Buck circuit system of this invention.

[0034] Figure 7 This is a schematic diagram of the duty cycle control module of the present invention. Detailed Implementation

[0035] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] This invention proposes a fixed-slope soft-start scheme that can be applied to AOT-modulated Buck systems based on ripple and inductor current compensation control. Figure 3The diagram shows the Buck system and its power management chip structure of the present invention, which includes an input voltage VIN, an output voltage VOUT, a shared SW pin for two power transistors, a ground pin GND, and a feedback voltage V. FB ripple sampling signal V DCR The chip has six pins and internal components including a reference voltage and current module, a ripple sampling module 202, a soft-start control module 101, an error amplifier EA, a driver module, a zero-crossing detection module, a power transistor MP current sampling module, an overcurrent protection module, a clock oscillator module, a conduction duration control module, a duty cycle control module 201, a main logic control module, and on-chip PMOS power transistor MP and NMOS power transistor MN.

[0037] The power input pin VIN and the ground pin GND are connected to various modules inside the chip. The source of the power transistor MP is connected to the input voltage VIN, and the drain of MP is connected to pin SW. The drain of the MN pin is connected to pin SW, and the source of MN is connected to the GND pin. The gate of MP is connected to the output signal PG of the driver module, which is turned on when it is low. The gate of MN is connected to the output signal NG of the driver module, which is turned on when it is high. The output voltage is fed through the feedback voltage pin V. FB Feedback is sent internally; through series connection of Rc and Cc and isolation via capacitor C1, and DC bias provided by resistor Rb, a superimposed inductor current ripple compensation is obtained to address the subharmonic oscillation problem caused by the low ESR of current MLCCs (ceramic capacitors). Under normal operating conditions, the feedback voltage V... FB The reference voltage and the error amplifier EA are respectively connected to the two ends of the error amplifier EA to obtain the error amplification signal VC, while the ripple signal V DCR The error signal VC is connected to the comparator input, and the generated turn-on signal is connected to the main control module; the current sampling module samples the current signal on the power transistor MP to the overcurrent protection module, and the output overcurrent protection signal is input to the main control module; the reference clock signal CLK generated by the oscillator and the MP drive signal PG_Ctl output by the main control module are input to the turn-on duration control module, which controls the MP turn-on time together with the internal PLL modulation loop, and the output signal is connected to the main control module after passing through the duty cycle control module.

[0038] The process by which the chip of this invention operates under normal load, causing the system control to operate in CCM (Continuous On-Mode) state, is as follows: Figure 6 As shown, when power transistor MP is off and power transistor MN is on, the inductor current is in the decreasing phase. At this time, the output voltage ripple is mainly caused by the inductor current flowing into the low ESR regulating capacitor Co. The inductor current ripple sampled by resistor Rc and capacitor Cc compensates for this output ripple to obtain the signal V. DCR At this time, the ripple signal V DCR The AC signal on the voltage is proportional to the current signal IL, which begins to decrease when V... DCR Trigger feedback voltage VFB When the signal VC is amplified from the reference voltage difference, the Sigon signal generates a positive pulse, power transistor MP turns on while power transistor MN turns off. At this time, the inductor current IL rises. As mentioned above, V... DCR The AC signal still rises proportionally to the inductor current IL. The conduction duration of the power transistor MP is controlled by the conduction duration control module. When the internal signal Vslope of the conduction duration control module touches the VON signal, the Sigoff signal generates a high pulse. At this time, the power transistor MP is turned off and the power transistor MN is turned on. Vslope is obtained by charging the capacitor C2, whose initial voltage is zero, with the current IL, which is proportional to VIN. The relationship is as follows:

[0039]

[0040] The system's on-time is then:

[0041]

[0042] Therefore, the system's operating frequency is:

[0043]

[0044] In traditional COT control schemes, most methods use a ratio of Ton to (VIN-VOUT) to achieve constant frequency. However, this method is greatly affected by process deviations. The chip of this invention uses a PLL modulation loop to monitor the phase difference between the clock signal CLK and the MP control signal PG_Ctl and control the signal VON, thereby fixing the system switching frequency and making the system operation more stable.

[0045] The fixed-slope soft-start circuit designed in this invention is as follows: Figure 5 As shown, this invention uses a fixed-slope soft-start scheme by amplifying the error through a fixed-ramp signal Vref and a fixed-ramp voltage divider, effectively avoiding the difference in inductor current stress during the soft-start phase under different output voltage requirements. The module's input signals VB1 and VB2 are reference current bias voltages. When the system is first powered on, RDN is high, resetting the D flip-flop SSOKN to high and SSOK to low, thus resetting Vref to ground potential. When the system input voltage is fully powered on and RDN = 0, a fixed current begins charging C1, resulting in a fixed-slope ramp signal Vref on the upper plate of C1. The slope of Vref is as follows, thus achieving a fixed power-on slope of 2*Slope for the output voltage.

[0046]

[0047] When the system is operating normally in a non-100% duty cycle mode, when V FBWhen the voltage reaches 0.59V, it is determined that the soft start is completed. At this time, the OR gate or1 outputs a high level, so that SSOK is set to a high level, and the data selectors mux1 and mux2 are switched to output the signal source. Since the bandwidth of the error amplifier is relatively lower than the switching frequency, as long as the switching rate is fast enough and the input signal has a certain driving capability, the output voltage fluctuation during the switching process can be reduced. Meanwhile, using 0.59V instead of 0.6V can to a certain extent avoid the output voltage oscillation caused by the V0D6 signal fluctuation during the switching of mux1 and mux2 when SSOK=1, which leads to the oscillation of VC.

[0048] When the system is in the 100% duty cycle output mode, as shown in Figure 4 , at this time V FB cannot reach 0.59V under heavy load, and additional control is required to end the soft start mode. The soft start scheme of the present invention uses the system clock signal CLK for counting as shown in Figure 5 , and when the count reaches 2 8 CLK cycles, the AND gate and1 outputs a high level, so that the OR gate or1 outputs a high level to force SSOK=1, thus ending the soft start mode. When the system enters an abnormal operation mode, such as output short circuit, input overvoltage or undervoltage, and over-temperature protection, the abnormal mode signal Hiccup will continuously force the SSOK signal to zero, and restart soft start only after the abnormal mode exits.

[0049] The duty cycle control module of the present invention is as shown in Figure 7 , when the system configured output duty cycle is not 100%, the power transistor MP is turned on by comparing the output signal VC of the error amplifier with V DCR , V DCR has a DC bias provided by V FB at 0.6V. The DC value of VC in the steady state of normal system operation is 0.6V. At this time Figure 7 , VC is less than VBA so that Comp2 outputs a high level. During normal operation of the system, whenever the power transistor MP is turned on, the capacitor is charged to generate a Vramp ramp signal. When this ramp signal touches Von, nand1 outputs a high level to generate the pulse Sigoff. Since Comp2 outputs a high level, Sigoff' is consistent with Sigoff. According to Figure 6 the system control operation timing shown, the power transistor MP is turned off at this time. When the system configuration output is VOUT=VIN, VOUT<VIN holds due to the influence of the on-resistance of the power transistor and the loop parasitic parameters. At this time, the output VC of the error amplifier reaches its maximum swing which is the power supply voltage, that is, VC=VDD>VBA, so that Comp2 outputs a low level, triggering the duty cycle control module to act, shielding the turn-off signal Sigoff of the power transistor MP to keep it continuously conductive, so as to achieve 100% duty cycle output.

[0050] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A power management chip based on an AOT fixed-slope soft-start Buck circuit, wherein the Buck circuit includes an inductor L, power transistors MP and MN, resistors Rc, Rp, and Rn, capacitor Cc, and capacitor C1, wherein the source of power transistor MP is connected to the input voltage VIN, the drain of power transistor MP is connected to the drain of power transistor MN, one end of inductor L, and one end of resistor Rc to form a SW node, the other end of resistor Rc is connected to one end of capacitor Cc and one end of capacitor C1, and the other end of capacitor C1 generates a ripple signal V. DCR The other end of inductor L is connected to the other end of capacitor Cc and one end of resistor Rp to generate output voltage VOUT. The other end of resistor Rp is connected to one end of resistor Rn to generate feedback voltage V. FB The other end of resistor Rn is grounded, and the gates of power transistors MP and MN are connected to the drive signal provided by the chip; its characteristic is that... The power management chip includes: Ripple sampling module, used to acquire ripple signal V DCR The output is then superimposed with a DC bias. The reference circuit module, which is unaffected by the supply voltage, is used to provide the system with a reference voltage and a bias voltage. The oscillator module generates a clock signal CLK through capacitor charging and discharging, providing a reference clock for system control; The soft-start module detects the output voltage VOUT and the feedback voltage V. FB The system controls the input error amplifier based on the clock signal CLK, and then outputs the error amplification signal VC to achieve a fixed slope soft start under different output voltages. The comparator module is used to process the ripple signal V with DC bias. DCR The turn-on control signal Sigon is obtained by comparing it with the error amplification signal VC. When Sigon is high, the power transistor MP is turned on. The on-time control module generates an on-time control signal Von by comprehensively monitoring and judging the input voltage VIN, clock signal CLK, and drive signal PG_Ctl frequency. This control signal Von controls the on-time of the power transistor MP to stabilize its switching frequency as the input and output voltages change. The zero-crossing detection shutdown module is used to monitor the voltage of the SW node. When the voltage of the SW node is detected to cross zero during the turn-on period of the power transistor MP, the output signal ZCD is high. The current sampling module is used to sample the current flowing through the power transistor MP during its conduction period to obtain the signal Vsense; The overcurrent protection module is used to determine the overcurrent of the signal Vsense and output the overcurrent protection signal OCP. When OCP is high, it triggers the system to enter the overcurrent protection mode. The duty cycle control module generates a turn-off control signal Sigoff based on the error amplification signal VC and the conduction duration control signal Von to control the system duty cycle, so as to achieve a 100% duty cycle output of the system under the working requirement of VOUT=VIN; The main control module performs logic processing based on the signal ZCD, the turn-on control signal Sigon, the turn-off control signal Sigoff, and the overcurrent protection signal OCP to generate the corresponding drive signals PG_Ctl and NG_Ctl for the power transistors MP and MN. The driver module is used to amplify the power of the drive signals PG_Ctl and NG_Ctl and then drive the gates of the power transistors MP and MN to perform switching operations, respectively.

2. The power management chip according to claim 1, characterized in that: The power transistors MP and MN are integrated on-chip.

3. The power management chip according to claim 1, characterized in that: The ripple sampling module includes a resistor Rb and a buffer. One end of the resistor Rb is connected to the inverting input of the comparator module and is connected to the ripple signal V. DCR The other end of resistor Rb is connected to the output terminal of the buffer, and the input terminal of the buffer is connected to the feedback voltage V. FB Thus, the ripple signal V is obtained. DCR DC bias.

4. The power management chip according to claim 1, characterized in that: The soft-start module includes two PMOS transistors P1 and P2, four NMOS transistors N1 to N4, a capacitor C1, a hysteresis comparator Comp1, an 8-bit counter, two OR gates OR1 and OR2, an 8-input AND gate AND1, two 2-to-1 multiplexers mux1 and mux2, a D flip-flop, and an error amplifier. The source of PMOS transistor P1 is connected to the source of PMOS transistor P2 and connected to the power supply voltage VDD. The gate of PMOS transistor P2 is connected to the gate of PMOS transistor P1, the drain of PMOS transistor P1, and the drain of each NMOS transistor N1. The drain of PMOS transistor P2 is connected to the drain of NMOS transistor N3, and the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2. The gates of NMOS transistors N1 and N2 are connected to bias voltages VB1 and VB2, respectively. The gate of NMOS transistor N3 is connected to the signal SSOKN. The source of NMOS transistor N3 is connected to one end of capacitor C1, the drain of NMOS transistor N4, and the first input terminal of selector mux1. The other end of capacitor C1 is connected to the sources of NMOS transistors N2 and NMOS transistor N4. The non-inverting input terminal of hysteresis comparator Comp1 is connected to the feedback voltage V. FB The inverting input of hysteresis comparator Comp1 is connected to a 0.59V reference voltage. The output of hysteresis comparator Comp1 is connected to the first input of OR gate OR1. The clock input of the 8-bit counter is connected to the clock signal CLK, and the reset input of the 8-bit counter is connected to the system enable signal RDN. The 8 output ports of the 8-bit counter are respectively connected to the 8 input ports of AND gate AND1. The output of AND gate AND1 is connected to the second input of OR gate OR1. The first input of OR gate OR2 is connected to the system enable signal RDN, and the second input of OR gate OR2 is connected to the system error signal. In the Hiccup, the input of the D flip-flop is connected to the power supply voltage VDD. The clock input of the D flip-flop is connected to the output of OR gate OR1. The reset input of the D flip-flop is connected to the output of OR gate OR2. The output of the D flip-flop is connected to the gate of NMOS transistor N4 and the selection ports of selectors mux1 and mux2, outputting the signal SSOK. SSOKN is the inverted signal of SSOK. The second input of selector mux1 is connected to a 0.6V reference voltage. The first input of selector mux2 is connected to VOUT / 2. The second input of selector mux2 is connected to the feedback voltage V. FB The output of selector mux1 is connected to the non-inverting input of the error amplifier, and the output of selector mux2 is connected to the inverting input of the error amplifier. The output of the error amplifier generates the error amplification signal VC.

5. The power management chip according to claim 1, characterized in that: The zero-crossing detection shutdown module is configured by an external PFM signal. When the PFM signal is low, the system enters FCCM mode under light load mode, and the output signal ZCD remains low. When the PFM signal is high, the system enters DCM mode under light load mode, and the conduction time of the power transistor MP remains fixed. At this time, when the voltage of the SW node is detected to cross zero during the power transistor MP is turned on, the output signal ZCD is high.

6. The power management chip according to claim 1, characterized in that: The duty cycle control module includes a PMOS transistor P17, a resistor R8, a hysteresis comparator Comp2, a comparator Comp3, a NAND gate NAND1, a pulse generator, and an AND gate AND2. The source of PMOS transistor P17 is connected to the power supply voltage VDD. One end of resistor R8 is connected to the drain and gate of PMOS transistor P17 and the non-inverting input of hysteresis comparator Comp2, while the other end of resistor R8 is grounded. The inverting input of hysteresis comparator Comp2 is connected to the error amplification signal VC. The non-inverting input of comparator Comp3 is connected to the on-time control signal Von, and the inverting input of comparator Comp3 is connected to the charging ramp signal Vramp. The output of hysteresis comparator Comp2 is connected to the first input of NAND gate NAND1 and the first input of AND gate AND2. The output of comparator Comp3 is connected to the second input of NAND gate NAND1. The output of NAND gate NAND1 is connected to the input of the pulse generator. The output of the pulse generator is connected to the second input of AND gate AND2. The output of AND gate AND2 outputs a turn-off control signal Sigoff.

7. The power management chip according to claim 1, characterized in that: The conduction duration control module includes a PLL modulation loop. The PLL modulation loop dynamically adjusts the MP conduction time flip threshold, Von, by detecting the phase difference between the power transistor MP's turn-on frequency and the clock signal CLK, and generates a charging ramp signal Vramp by charging the capacitor with a fixed current. When Vramp reaches Von, the duty cycle control module outputs a high-level turn-off control signal Sigoff to turn off the power transistor MP, and simultaneously resets Vramp to zero.

8. The power management chip according to claim 1, characterized in that: This chip adds an error amplifier control loop to the traditional ripple-based AOT architecture. When the output ripple falls to the output of the error amplifier, the power transistor MP is turned on, followed by the power transistor MN. At the same time, a PLL control loop is used to phase-lock the switching frequency and the internal reference clock frequency to achieve a pseudo-constant frequency effect. The chip uses a fixed-ratio voltage divider of the output voltage and an internal reference source error amplifier with a fixed-slope rise to achieve soft-start power-on with a fixed slope for different output voltages. After the output is powered on, the soft-start ends to prevent different inductor current stresses under different output voltages or surges generated during the soft-start phase. By using an external RC inductor current ripple compensation and DC bias scheme, the error amplifier output under normal operating conditions is biased DC to a reference voltage of 0.6V, so that when the system outputs 100% duty cycle, VC rises to the power supply to achieve differentiation, thus completing the 100% duty cycle output control based on ripple AOT.

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