Semiconductor device layout generation method and semiconductor device

Abstract

An embodiment of the present application provides a layout generation method for a semiconductor device and a semiconductor device, wherein the layout generation method for a semiconductor device includes a plurality of stacked chips, and the layout generation method includes: obtaining first attribute information of the chip; the first attribute information includes the connection relationship of the chip's power supply, power interface size parameters, and spacing parameters; obtaining second attribute information of the chip; the second attribute information includes the connection relationship of the chip's signals, communication port size parameters, and spacing parameters; based on the first attribute information and the second attribute information, synchronously planning the layout of the chip's communication port and the chip's power network.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a layout generation method for a semiconductor device and a semiconductor device. Background Art

[0002] For stacked chips in three-dimensional integrated circuits (3DICs), where at least one chip is stacked on top of another, whether face-to-face or face-to-back, the planning and arrangement of communication ports between the two chips (for example, the top and bottom chips) is particularly important. Maximizing the number of communication ports between chips to improve chip performance is a pressing technical challenge. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a layout generation method for a semiconductor device and a semiconductor device to solve at least one technical problem existing in the prior art.

[0004] According to a first aspect of an embodiment of the present application, a layout generation method for a semiconductor device is provided, wherein the semiconductor device includes a plurality of stacked chips, and the layout generation method includes: obtaining first attribute information of the chip; the first attribute information includes the connection relationship of the power supply of the chip, the power interface size parameters and the spacing parameters; obtaining second attribute information of the chip; the second attribute information includes the connection relationship of the signal of the chip, the communication port size parameters and the spacing parameters; based on the first attribute information and the second attribute information, synchronously planning the layout of the communication port of the chip and the power network of the chip.

[0005] In the above scheme, the layout of the communication port of the chip and the power network of the chip are synchronously planned, including: generating a first number of multiple power bumps; generating a second number of multiple signal bumps; based on the first size parameter of the signal bump and the second size parameter of the power bump, calculating the third size parameter of the signal bump and the fourth size parameter of the power bump according to the first rule; based on the third size parameter and the fourth size parameter, calculating the distribution of the signal bumps and the power bumps according to the second rule; wherein the distribution of the signal bumps and the power bumps includes a third number of power bumps and a fourth number of signal bumps, the third number is greater than or equal to the first number, and the fourth number is greater than the second number.

[0006] In the above solution, in some embodiments, the first rule includes: a constraint relationship between size parameters of the signal bump and size parameters of the power bump; the constraint relationship includes a minimum spacing between the signal bump and the power bump.

[0007] In the above scheme, the first size parameter includes the first length and the first spacing of the signal bump; the second size parameter includes the second length and the second width of the power bump; the third size parameter includes the first length, the second spacing and the third spacing of the signal bump; the fourth size parameter includes the fourth width, the fourth spacing and the fifth spacing of the power bump; the third size parameter of the signal bump and the fourth size parameter of the power bump are calculated according to the first rule, including: obtaining the second spacing based on the first length and the first spacing, obtaining the third spacing based on the second number and the first spacing; and, obtaining the fourth width based on the second number and the first spacing, obtaining the fourth spacing based on the second length and the second width, and obtaining the fifth spacing based on the third spacing, the fourth width and the second spacing.

[0008] In the above scheme, the second spacing includes the sum of the first length and the first spacing, and the third spacing includes the product of the second number and the first spacing; and the fourth width includes the product of the second number and the first spacing, and the fourth spacing includes the sum of the second length and the second width; the fifth spacing includes the result of the third spacing plus half of the fourth width minus half of the second spacing.

[0009] In the above scheme, the distribution of signal bumps and power bumps is calculated according to the second rule, including: maximizing the first number to obtain the third number and the gap area outside the outer contour of the power network; placing the signal bumps in the gap area; based on the first length, the second spacing and the third spacing, maximizing the second number to obtain the fourth number.

[0010] In the above scheme, the distribution of signal bumps and power bumps includes multiple first power wirings located on the top layer of the chip and multiple second power wirings located on the second top layer of the chip, and the extension direction of the multiple first power wirings is orthogonal to the extension direction of the multiple second power wirings; maximizing the first quantity includes: reducing the characteristic size and spacing of the multiple first power wirings and reducing the characteristic size and spacing of the multiple second power wirings, maximizing the area outside the outer contours of the multiple first power wirings and the multiple second power wirings, and obtaining the third quantity and gap area.

[0011] In the above scheme, the distribution of signal bumps and power bumps includes multiple signal bumps surrounded by the outer contours of multiple first power wirings and the outer contours of multiple second power wirings; maximizing the second number includes: based on the first length, the second spacing and the third spacing, setting the maximum number of signal bumps in the gap area, the maximum number being the fourth number.

[0012] According to a second aspect of an embodiment of the present application, a semiconductor device is provided, comprising a plurality of stacked chips; the power supply network of the chip comprises a plurality of first power supply wirings located on a top layer of the chip and a plurality of second power supply wirings located on a second top layer of the chip; the extension direction of the plurality of first power supply wirings is orthogonal to the extension direction of the plurality of second power supply wirings; the communication port of the chip is surrounded by the outer contours of the plurality of first power supply wirings and the outer contours of the plurality of second power supply wirings.

[0013] In the above scheme, the multiple signal bumps include multiple signal units arranged in an array, each signal unit includes multiple signal bumps arranged in an array; the multiple first power wirings and the multiple second power wirings are connected through interlayer conductive vias; the conductive vias are located in the overlapping area of ​​the outer contour of the multiple first power wirings and the outer contour of the multiple second power wirings.

[0014] The layout generation method for semiconductor devices proposed in the embodiments of the present application simultaneously performs layout of communication ports and power supply networks (i.e., power supply network planning and communication port planning are performed simultaneously), and generates power bumps to simulate the power supply network and signal bumps to simulate the communication ports, which can prevent chip communication ports and power supply networks from generating design rule check violations, optimize design rationality, and shorten the design cycle; after simultaneously performing power supply network planning and communication port planning, the layout of communication ports and power supply networks obtained can maximize the number of communication ports between chips without affecting the robustness of the power supply, thereby improving the chip performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A A schematic flow chart of a method for generating a layout of a semiconductor device provided in an embodiment of the present application;

[0016] Figure 1B for Figure 1A A flowchart of some steps of

[0017] Figure 2 A schematic cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0018] Figure 3 A schematic top-down perspective view of a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application and the accompanying drawings. The described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. It is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all the features of the actual embodiments are not described here, and the well-known functions and structures are not described in detail.

[0020] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0021] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0022] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0023] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0024] For stacked 3DIC chips, whether in a face-to-face or front-to-back stacking configuration, the planning and arrangement of communication ports between the two chips (e.g., the top and bottom chips) is particularly important. This is because the number of communication ports between the chips affects the communication bandwidth between the top and bottom chips and is a key parameter in measuring the performance of stacked 3DIC chips.

[0025] The 3DIC stacked chip includes multiple chips stacked on a substrate. The multiple chips may be multiple memory chips or multiple logic chips.

[0026] When stacking multiple chips on the back end, for example, in the 3DIC design process, when converting the register transfer level (RTL) description code into a graphic design system (GDS) file while meeting the functional, speed, and area constraints of the designed circuit, the planning and arrangement of the communication ports between chips have not been deeply and meticulously optimized. For example, the number of communication ports between chips cannot be further increased. After the layout design file is handed over to the chip foundry for tape-out, the performance of the 3DIC stacked chip cannot be improved or is difficult to improve.

[0027] The current approach for planning communication ports on logic-stacked chips is to evenly distribute the communication ports in the gaps between the power meshes after the power mesh is planned (for example, using hybrid bonding packaging technology). Finally, wiring is performed for these communication ports during the wiring stage.

[0028] The above-mentioned related processes and technical methods have the following defects:

[0029] 1. In the back-end implementation of 3DIC stacked chips, because the communication ports will occupy the top-level routing resources without considering the communication ports during power network planning, the power network is planned to be as large as possible without considering the gap area. This results in a small number of plannable communication ports and poor performance of the 3DIC stacked chip.

[0030] 2. In the back-end implementation of 3DIC stacked chips, the top-level power metal clearances are not planned in advance during communication port planning, while physical checks such as the spacing pitch between top-level power metal traces must be adhered to. As a result, the area utilization of communication ports within a given space is low.

[0031] 3. In the back-end implementation of 3DIC stacked chips, all power networks are deleted during communication port planning before the communication ports are placed. This can cause overlap or insufficient spacing between the communication ports and the top-level power networks, resulting in Design Rule Checking (DRC) violations such as short circuits.

[0032] 4. In order to solve the above-mentioned errors or defects, it is necessary to increase the number of iterations, thereby extending the 3DIC stacked chip design cycle.

[0033] In short, the current planning of communication ports in the back-end implementation of 3DIC stacked chips may lead to insufficient performance of 3DIC stacked chips or increase the design time of 3DIC stacked chips, which is time-consuming and labor-intensive.

[0034] In view of this, embodiments of the present application provide a layout generation method for a semiconductor device and a semiconductor device to solve at least one technical problem existing in the prior art.

[0035] Figure 1A A schematic diagram of a flow chart of a method for generating a layout of a semiconductor device provided in an embodiment of the present application. Figure 1A According to a first aspect of an embodiment of the present application, a layout generation method for a semiconductor device is provided. The semiconductor device includes a plurality of stacked chips. The layout generation method includes the following steps:

[0036] S101, obtaining first attribute information of a chip; the first attribute information includes a connection relationship of a power supply of the chip, size parameters of a power supply interface, and spacing parameters;

[0037] S102, obtaining second attribute information of the chip; the second attribute information includes the connection relationship of the chip's signals, communication port size parameters, and spacing parameters;

[0038] S103 : Based on the first attribute information and the second attribute information, synchronously plan the layout of the communication port of the chip and the power supply network of the chip.

[0039] It should be understood that Figure 1A The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 1AThe steps shown in the figure can be adjusted in sequence according to actual needs.

[0040] It should be noted that the description of obtaining the first attribute information of the chip and obtaining the second attribute information of the chip in two steps does not mean that step S101 and step S102 are performed separately. For example, step S101 can be performed first, then step S102, or step S102 can be performed first, then step S101. Steps S101 and S102 can also be performed simultaneously. The following description uses the simultaneous performance of steps S101 and S102 as an example.

[0041] Execute step S101 and step S102 to synchronously obtain the first attribute information of the chip and the second attribute information of the chip.

[0042] In the 3DIC design process, the register transfer level description code is converted into a gate-level netlist while meeting the constraints of the design circuit's function, speed, and area. For example, the connection relationship between the chip's power supply and the chip's signals can be obtained.

[0043] In the library definition of the 3DIC electronic design automation (EDA) tool, for example, in the hybrid bonding library definition, in the 3DIC rule file and the logic chip rule file, the chip's power interface size parameters and spacing parameters, as well as the chip's communication port size parameters and spacing parameters can be obtained.

[0044] Figure 1B for Figure 1A Flow chart of some steps (step S103). Figure 1B , executing step S103, in some embodiments, synchronously planning the layout of the chip's communication ports and the chip's power supply network includes the following steps:

[0045] S1031, generating a first number of power bumps;

[0046] S1032, generating a second number of signal bumps;

[0047] S1033, based on the first size parameter of the signal bump and the second size parameter of the power bump, calculate the third size parameter of the signal bump and the fourth size parameter of the power bump according to the first rule;

[0048] S1034. Calculate the distribution of the signal bumps and the power bumps according to the second rule based on the third size parameter and the fourth size parameter.

[0049] The distribution of the signal bumps and the power bumps includes a third number of power bumps and a fourth number of signal bumps, the third number is greater than or equal to the first number, and the fourth number is greater than the second number.

[0050] It should be understood that Figure 1B The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 1B The steps shown in the figure can be adjusted in sequence according to actual needs.

[0051] In some embodiments, the chips may be memory chips or logic chips. In some embodiments, the chips may all be memory chips of the same type.

[0052] In some embodiments, the number of stacked chips in the semiconductor device may be two, three, or more chips (eg, ten chips).

[0053] It should be noted that, for ease of description, the following separate descriptions of generating multiple power bumps and generating multiple signal bumps do not imply that step S1031 and step S1032 are performed separately. For example, step S1031 may be performed first, followed by step S1032, or step S1032 may be performed first, followed by step S1031. Steps S1031 and S1032 may also be performed simultaneously.

[0054] Execute step S1031 to generate a plurality of power bumps.

[0055] In some embodiments, the first number is greater than or equal to a first preset value, satisfying the robustness of the power network.

[0056] The power supply network (power wiring) of a semiconductor device is formed by arranging the metal wiring layers of the upper layers (e.g., the top and second-top layers) in a mesh pattern. Furthermore, the power wiring layers serve as power connection strips on the upper portions of the chiplets (e.g., the top and second-top layers of the chip). The power supply network of the semiconductor device is connected to the power wiring of the entire semiconductor device via conductive vias, thereby providing power.

[0057] Here, the magnitude of the first number can represent the degree of power robustness. For example, a larger first number indicates greater power robustness per unit area. The initial distribution of the power network can be understood as the distribution of the power network when the first number is a first preset value. It is desirable to arrange the power network with a higher density as much as possible without compromising power robustness, thereby leaving a larger gap between the power networks.

[0058] Execute step S1032 to generate a plurality of signal bumps.

[0059] In some embodiments, the second number is greater than or equal to a second preset value, meeting basic communication requirements of the communication port.

[0060] The communication port (signal wiring) of the semiconductor device needs to pass through the gap between the power wiring layers.

[0061] Here, the second number can represent the inter-chip communication capability of the semiconductor device. For example, a larger second number indicates a stronger inter-chip communication capability of the semiconductor device. The initial distribution of the power network can be understood as the number of communication ports when the second number is the second preset number. It is desirable to arrange as many communication ports of the semiconductor devices as possible within the gaps reserved between the power networks without compromising the robustness of the power supply.

[0062] Execute step S1033 to obtain a third size parameter and a fourth size parameter based on the first size parameter and the second size parameter.

[0063] For the convenience of explanation, the multiple power bumps of the power network of the analog chip and the multiple signal bumps of the communication port of the analog chip are referred to as power bump and signal bump respectively in the following text.

[0064] The first size parameter of the signal bump involved in the implementation of this application is explained as follows:

[0065] signal bump x: the length of the signal bump on the x-axis, and the width defined by the hybrid bonding library;

[0066] signal bump y: the length of the signal bump on the y-axis, and the height defined by the hybrid bonding library;

[0067] Signal bump min pitch x: The minimum pitch of the signal bump on the x-axis, obtained from the 3DIC rule file and the logic chip rule file;

[0068] Signal bump min pitch y: The minimum pitch of the signal bump on the y-axis, obtained from the 3DIC rule file and the logic chip rule file;

[0069] Signal bump offset x: the distance between the signal bump and the chip edge in the x-axis direction;

[0070] Signal bump offset y: The distance between the signal bump and the chip edge in the y-axis direction.

[0071] The second size parameter of the power bump involved in the implementation of this application is explained as follows:

[0072] Power bump x: The length of the power bump in the x-axis direction, which is consistent with the chip size;

[0073] Power bump y: The length of the power bump in the y-axis direction, which is consistent with the chip size;

[0074] Power bump x width: width of the power bump in the x-axis direction;

[0075] Power bump y width: the width of the power bump in the y-axis direction;

[0076] Power bump pitch x: the spacing of the power bump on the x-axis;

[0077] Power bump pitch y: the y-axis spacing of the power bumps;

[0078] Power bump offset x: the distance between the power bump and the chip edge in the x-axis direction;

[0079] Power bump offset y: The distance between the power bump and the chip edge in the y-axis direction.

[0080] The third size parameter of the signal bump and the fourth size parameter of the power bump involved in the implementation of this application, as well as the explanation of the related algorithm (including the first rule) are as follows:

[0081] signal bump min pitch x=signal bump min pitch x+signal bump x;

[0082] signal bump min pitch y=signal bump min pitch y+signal bump y;

[0083] signal bump offset x=n1*signal bump min pitch x;

[0084] signal bump offset y=n2*signal bump min pitch y;

[0085] power bump x width=n3*signal bump min pitch x;

[0086] power bump y width=n4*signal bump min pitch y;

[0087] power bump pitch x=power bump x width+power bump x;

[0088] power bump pitch y=power bump y width+power bump y;

[0089] power bump offset x=signal bump offset x+power bump x width / 2–signalbump min pitch x / 2;

[0090] power bump offset y = signal bump offset y + power bump y width / 2 – signal bump min pitch y / 2; In the above formula, n1, n2, n3, and n4 are all positive integers.

[0091] In some embodiments, the first rule includes: a constraint relationship between size parameters of the signal bump and size parameters of the power bump, wherein the constraint relationship includes a minimum spacing between the signal bump and the power bump.

[0092] Illustratively, the above formulas: power bump offset x = signal bump offset x + power bump x width / 2 – signal bump min pitch x / 2; and power bump offset y = signal bump offset y + power bump y width / 2 – signal bump min pitch y / 2, may represent the constraint relationship between the size parameters of the signal bump and the size parameters of the power bump.

[0093] In some embodiments,

[0094] The first size parameter includes a first length and a first spacing of the signal bumps;

[0095] The second size parameter includes a second length and a second width of the power bump;

[0096] The third size parameter includes a first length, a second spacing, and a third spacing of the signal bumps;

[0097] The fourth size parameters include a fourth width, a fourth spacing, and a fifth spacing of the power bumps;

[0098] The third size parameter of the signal bump and the fourth size parameter of the power bump are calculated according to the first rule, including:

[0099] A second spacing is obtained based on the first length and the first spacing, and a third spacing is obtained based on the second number and the first spacing; and

[0100] A fourth width is obtained based on the second number and the first interval, a fourth interval is obtained based on the second length and the second width, and a fifth interval is obtained based on the third interval, the fourth width, and the second interval.

[0101] Illustratively, in the first size parameter: the first length of the signal bump is abbreviated as signal bump x and signal bump y; the first pitch of the signal bump is abbreviated as signal bump min pitch x and signal bump min pitch y.

[0102] Illustratively, in the second size parameters, the second length of the power bump is abbreviated as power bump x and power bump y; the second width of the power bump is abbreviated as power bump x width and power bump y width.

[0103] A second spacing is obtained based on the first length and the first spacing, a third spacing is obtained based on the second number and the first spacing; and a fourth width is obtained based on the second number and the first spacing, a fourth spacing is obtained based on the second length and the second width, and a fifth spacing is obtained based on the third spacing, the fourth width and the second spacing.

[0104] Illustratively, in the third size parameter: the first length of the signal bump is abbreviated as signal bump x and signal bump y; the second pitch of the signal bump is abbreviated as signal bump min pitch x and signal bump min pitch y; and the third pitch of the signal bump is abbreviated as signal bump offset x and signal bump offset y.

[0105] Illustratively, in the fourth size parameter: the fourth width of the power bump is abbreviated as power bump x width and power bump y width; the fourth pitch of the power bump is abbreviated as power bump pitch x and power bump pitch y; and the fifth pitch of the power bump is abbreviated as power bump offset x and power bump offset y.

[0106] In some embodiments,

[0107] The second spacing includes the sum of the first length and the first spacing, and the third spacing includes the product of the second number and the first spacing; and

[0108] The fourth width includes the product of the second number and the first spacing, the fourth spacing includes the sum of the second length and the second width; the fifth spacing includes the third spacing plus half of the fourth width minus half of the second spacing.

[0109] Exemplarily, the second distance includes the sum of the first length and the first distance:

[0110] signal bump min pitch x=signal bump min pitch x+signal bump x;

[0111] signal bump min pitch y=signal bump min pitch y+signal bump y.

[0112] Exemplarily, the third spacing comprises the product of the second number and the first spacing:

[0113] signal bump offset x=n1*signal bump min pitch x;

[0114] signal bump offset y=n2*signal bump min pitch y.

[0115] Exemplarily, the fourth width includes the product of the second number and the first spacing:

[0116] power bump x width=n3*signal bump min pitch x;

[0117] power bump y width=n4*signal bump min pitch y.

[0118] Exemplarily, the fourth distance includes the sum of the second length and the second width:

[0119] power bump pitch x=power bump x width+power bump x;

[0120] power bump pitch y=power bump y width+power bump y.

[0121] Illustratively, the fifth spacing comprises the third spacing plus half of the fourth width minus half of the second spacing:

[0122] power bump offset x=signal bump offset x+power bump x width / 2–signalbump min pitch x / 2;

[0123] power bump offset y=signal bump offset y+power bump y width / 2–signal bump min pitch y / 2.

[0124] Wherein, n1, n2, n3, and n4 in the above formulas are all positive integers.

[0125] Step S1034 is executed to obtain a layout of the simulated communication port and the power network based on the third size parameter and the fourth size parameter.

[0126] In some embodiments, calculating the distribution of signal bumps and power bumps according to the second rule includes:

[0127] Maximizing the first quantity to obtain a third quantity and a clearance area outside the outer contour of the power network;

[0128] Place the signal bump in the gap area;

[0129] Based on the first length, the second interval, and the third interval, the second number is maximized to obtain a fourth number.

[0130] In some embodiments, the distribution of the signal bumps and the power bumps includes a plurality of first power wirings located on a top layer of the chip and a plurality of second power wirings located on a second top layer of the chip, and an extension direction of the plurality of first power wirings is orthogonal to an extension direction of the plurality of second power wirings;

[0131] Maximize the first quantity, including:

[0132] The characteristic size and spacing of the plurality of first power wirings and the characteristic size and spacing of the plurality of second power wirings are reduced, and the area outside the outer contours of the plurality of first power wirings and the plurality of second power wirings is maximized to obtain a third number and gap area.

[0133] In some embodiments, the distribution of the signal bumps and the power bumps includes a plurality of signal bumps surrounded by outer contours of the plurality of first power wirings and outer contours of the plurality of second power wirings;

[0134] Maximize the second quantity, including:

[0135] Based on the first length, the second spacing, and the third spacing, a maximum number of signal bumps is set in the gap area, and the maximum number is a fourth number.

[0136] Here, before starting the power network planning and communication port planning, an initial distribution of signal bumps and power bumps (or reference distribution) is randomly generated. The second rule can be understood as after the power network planning and communication port planning are performed simultaneously, the layout density of the power network is higher than the initial distribution of the signal bumps and power bumps, and a larger gap is left between the power networks of the semiconductor devices as much as possible. The larger gap is used to arrange a larger number of communication ports of the semiconductor devices.

[0137] Step S1034 may be performed using a 3DIC electronic design automation (EDA) tool, for example, a Cadence 3DIC EDA tool.

[0138] In each embodiment of the present application, it can be understood to include the following steps. For example, the first step is to import data through the 3DIC EDA tool, such as the size parameters defined by the hybrid bonding library, the chip size parameters, the minimum spacing parameters in the rule file, etc.; the second step is to perform algorithm calculations to obtain the parameters required for power network planning and the parameters required for communication port planning; the third step is to set the parameters and input them into the 3DIC EDA tool; the fourth step is to generate the size parameters of the power network rule and input them into the 3DIC EDA tool; the fifth step is to simultaneously perform power network planning and communication port planning.

[0139] In each embodiment of the present application, the layout of the communication port and the power network is performed simultaneously (i.e., the power network planning and the communication port planning are performed simultaneously), and power bumps are generated to simulate the power network, and signal bumps are generated to simulate the communication port. This can reduce or prevent design rule check violations between the chip communication port and the power network, optimize design rationality, and shorten the design cycle.

[0140] In each embodiment of the present application, after simultaneously planning the power supply network and the communication port, the layout of the communication ports and the power supply network is obtained to ensure that the layout density of the power supply network is higher, and a larger gap is left between the power supply networks of the semiconductor devices as much as possible. The larger gap is used to arrange a larger number of communication ports of the semiconductor devices. In this way, while ensuring the normal layout of the power supply network of the semiconductor device, the layout density of the power supply network is higher, and a larger gap is left between the power supply networks of the semiconductor devices. A larger number of communication ports of the semiconductor devices are arranged in the larger gap, thereby improving the chip performance of the semiconductor device. In other words, without affecting the robustness of the power supply, the number of communication ports between chips can be maximized, thereby improving the chip performance of the semiconductor device.

[0141] Figure 2 A schematic cross-sectional view of a semiconductor device provided in an embodiment of the present application; Figure 3 A schematic top-down perspective view of a semiconductor device provided in an embodiment of the present application.

[0142] refer to Figure 2 and Figure 3 According to a second aspect of an embodiment of the present application, there is provided a semiconductor device, comprising: a plurality of stacked chips;

[0143] The power supply network of the chip includes a plurality of first power supply wirings 301 located on the top layer of the chip and a plurality of second power supply wirings 302 located on the second top layer of the chip; the extension direction of the plurality of first power supply wirings 301 is orthogonal to the extension direction of the plurality of second power supply wirings 302;

[0144] The communication port of the chip is surrounded by the outer contours of the plurality of first power supply wirings 301 and the outer contours of the plurality of second power supply wirings 302 .

[0145] Here and below, the first and second directions are orthogonal directions parallel to the top surface of the substrate. The third direction is a direction parallel to the thickness of the substrate, which can also be understood as the direction in which the chips are stacked. For example, the first direction is the X direction in the drawings; the second direction is the Y direction in the drawings; and the third direction is the Z direction in the drawings.

[0146] It should be noted that, in order to clearly show the relative position relationship between the power wiring of different layers and the power wiring and the communication ports, the power wiring of different layers and the communication ports are all perspectively placed in the same plane, such as Figure 3 As shown, a plurality of first power supply wirings, a plurality of second power supply wirings, and a communication port of the chip are shown in perspective on the same XY plane.

[0147] In some embodiments, the semiconductor device includes a plurality of chips 211 - 214 stacked on a substrate 201 .

[0148] In some embodiments, substrate 201 may be a package substrate or a printed circuit board, for example, a stacked substrate formed as a stack of multiple thin layers (or stacks) of a polymer material such as bismaleimide triazine (BT), FR-4, ABF, etc. However, any other suitable substrate may be utilized, such as a silicon interposer, a silicon substrate, an organic substrate, a ceramic substrate, etc.

[0149] In some embodiments, substrate 201 may further include other components, such as a buried oxide layer and / or an epitaxial layer. Furthermore, the substrate may be a semiconductor on an insulator, such as silicon on an insulator. In other embodiments, substrate 201 may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer overlying other different types of semiconductor layers, such as a silicon layer over a silicon germanium layer. In other examples, substrate 201 may include a multilayer compound semiconductor structure. Substrate 201 may further include isolation structures and active regions, such as shallow trench isolation components or selective oxidation of silicon (LOCOS) components formed in the substrate, for isolating the active region from other regions of the substrate; the active region may be configured as an NMOS device or a PMOS device. Substrate 201 may further include a dummy gate and / or gate structure overlying the substrate, which may be formed from various metal layers and by various etching and / or patterning techniques on various regions of the substrate.

[0150] In some embodiments, the chips may be memory chips or logic chips. In some embodiments, the chips may all be memory chips of the same type. In other embodiments, some of the chips may be memory chips while others may be logic chips.

[0151] The memory chip may be a volatile memory chip, such as a dynamic random access memory (DRAM) chip and a static random access memory (SRAM) chip, or may be a non-volatile memory chip, such as a NAND memory, a phase change random access memory chip, a magnetoresistive random access memory chip, a ferroelectric random access memory chip, and a resistive random access memory chip. In some example embodiments, the chip may be a high-bandwidth memory (HBM) DRAM.

[0152] Logic chips may include control chips (such as a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application specific integrated circuit (ASIC), etc.).

[0153] Although the number of stacked chips is shown as four (first chip 211, second chip 212, third chip 213, fourth chip 214) in this exemplary embodiment, the number of chips that can be stacked in the memory is not limited thereto. For example, the number of stacked chips in the semiconductor device can be two, three, or more chips (e.g., ten chips).

[0154] Here, the semiconductor device's power network (power wiring layer) is formed by arranging a top metal wiring layer (multiple first power wirings) and a second-top metal wiring layer (multiple second power wirings) in a mesh pattern. Furthermore, the power wiring layer serves as a power connection strip on the upper portion of the chiplet (e.g., the top and second-top layers of the chip). The semiconductor device's power network is connected to the power wiring throughout the entire semiconductor device via conductive vias, providing power.

[0155] In some embodiments, the communication port of the chip includes a plurality of signal units 320 arranged in an array, and each signal unit includes a plurality of signal ports 3201 arranged in an array;

[0156] The first power wirings 301 and the second power wirings 302 are connected via interlayer conductive vias 322 . The conductive vias 322 are located in an overlapping area OLA between the outer contours of the first power wirings 301 and the outer contours of the second power wirings 302 .

[0157] Exemplarily, each signal unit includes 12 signal ports 3201 arranged in an array.

[0158] In each embodiment of the present application, after simultaneously planning the power supply network and the communication port, the layout of the communication ports and the power supply network is obtained, ensuring that the density of the layout of the power supply network is higher, leaving a larger gap between the power supply networks of the semiconductor devices as much as possible, and the larger gap is used to arrange the communication ports of a larger number of semiconductor devices. In this way, while ensuring the normal layout of the power supply network of the semiconductor device, the density of the layout of the power supply network is higher, leaving a larger gap between the power supply networks of the semiconductor devices, and arranging a larger number of communication ports of the semiconductor devices in the larger gap, thereby improving the chip performance of the semiconductor device. In other words, without affecting the robustness of the power supply, the number of communication ports between chips can be maximized, or, while enhancing the robustness of the power supply, the number of communication ports between chips can be maximized, thereby improving the chip performance of the semiconductor device.

[0159] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0160] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for generating a layout of a semiconductor device, characterized in that: The semiconductor device includes a plurality of stacked chips, and the layout generation method includes: Acquire first attribute information of the chip; the first attribute information includes a connection relationship of a power supply of the chip, size parameters of a power supply interface, and spacing parameters; Acquiring second attribute information of the chip; the second attribute information includes a connection relationship of signals of the chip, a size parameter of a communication port, and a spacing parameter; Based on the first attribute information and the second attribute information, synchronously planning the layout of the communication port of the chip and the power network of the chip; The synchronous planning of the layout of the communication port of the chip and the power supply network of the chip includes: Generating a first number of power bumps; the first number satisfies the robustness of the power network; Generating a second number of multiple signal bumps; the second number meets the basic communication requirements of the communication port; Maximizing the first number yields a third number and maximizing the second number yields a fourth number; the distribution of the signal bumps and the power bumps includes the third number of the power bumps and the fourth number of the signal bumps.

2. The layout generation method according to claim 1, wherein: The synchronous planning of the layout of the communication port of the chip and the power supply network of the chip includes: Based on the first size parameter of the signal bump and the second size parameter of the power bump, calculating the third size parameter of the signal bump and the fourth size parameter of the power bump according to the first rule; Based on the third size parameter and the fourth size parameter, the distribution of the signal bumps and the power bumps is calculated according to a second rule.

3. The layout generation method according to claim 2, wherein: The first rule includes: a constraint relationship between the size parameters of the signal bump and the size parameters of the power bump; the constraint relationship includes a minimum spacing between the signal bump and the power bump.

4. The layout generation method according to claim 3, wherein: The first size parameter includes a first length and a first spacing of the signal bumps; The second size parameter includes a second length and a second width of the power bump; The third size parameter includes the first length, the second spacing and the third spacing of the signal bumps; The fourth size parameter includes a fourth width, a fourth spacing, and a fifth spacing of the power bumps; The calculating the third size parameter of the signal bump and the fourth size parameter of the power bump according to the first rule includes: The second distance is obtained based on the first length and the first distance, and the third distance is obtained based on the second number and the first distance; as well as, The fourth width is obtained based on the second number and the first interval, the fourth interval is obtained based on the second length and the second width, and the fifth interval is obtained based on the third interval, the fourth width, and the second interval.

5. The layout generation method according to claim 4, characterized in that: The second distance includes the sum of the first length and the first distance, and the third distance includes the product of the second number and the first distance; as well as, The fourth width includes the product of the second number and the first spacing, the fourth spacing includes the sum of the second length and the second width; and the fifth spacing includes the third spacing plus half of the fourth width minus half of the second spacing.

6. The layout generation method according to claim 4, characterized in that: The calculating the distribution of the signal bumps and the power bumps according to the second rule includes: Maximizing the first quantity to obtain the third quantity and a gap area outside the outer contour of the power network; placing the signal bump in the gap area; The fourth number is obtained by maximizing the second number based on the first length, the second interval, and the third interval.

7. The layout generation method according to claim 6, characterized in that: The distribution of the signal bumps and the power bumps includes a plurality of first power wirings located on the top layer of the chip and a plurality of second power wirings located on the second top layer of the chip, wherein the extension direction of the plurality of first power wirings is orthogonal to the extension direction of the plurality of second power wirings; The maximizing the first quantity includes: The characteristic size and spacing of the plurality of first power wirings and the characteristic size and spacing of the plurality of second power wirings are reduced, and the area outside the outer contours of the plurality of first power wirings and the plurality of second power wirings is maximized to obtain the third number and the gap area.

8. The layout generation method according to claim 7, wherein: The distribution of the signal bumps and the power bumps includes the plurality of signal bumps surrounded by outer contours of the plurality of first power wirings and outer contours of the plurality of second power wirings; The maximizing the second quantity includes: Based on the first length, the second spacing, and the third spacing, a maximum number of the signal bumps is set in the gap area, and the maximum number is the fourth number.

9. A semiconductor device, characterized in that: The semiconductor device is obtained by the method according to any one of claims 1 to 8, comprising a plurality of stacked chips; The power supply network of the chip includes a plurality of first power supply wirings located on a top layer of the chip and a plurality of second power supply wirings located on a second top layer of the chip; An extending direction of the plurality of first power supply wires is orthogonal to an extending direction of the plurality of second power supply wires; The power interface of the chip is located in an overlapping area between the outer contours of the plurality of first power wirings and the outer contours of the plurality of second power wirings; The power interface includes a third number of power bumps; The communication port of the chip is surrounded by outer contours of the plurality of first power wirings and outer contours of the plurality of second power wirings; the communication port includes a fourth number of signal bumps.

10. The semiconductor device according to claim 9, wherein The communication port includes a plurality of signal units arranged in an array, and each of the signal units includes a plurality of signal bumps arranged in an array; The plurality of first power wirings and the plurality of second power wirings are connected by interlayer conductive vias; The conductive via is located in an overlapping area between outer contours of the plurality of first power wirings and outer contours of the plurality of second power wirings.

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