Display panel and display device

Abstract

This invention discloses a display panel and display device, relating to the field of display technology. The display area includes N sub-display areas arranged along a second direction, and the non-display area includes N gate driving modules corresponding to the sub-display areas. In each gate driving module, the gate driving unit at the first stage is connected to different start-up trigger signal lines. The first frequency display frame of the display panel includes a data write frame and a data hold frame. The display panel includes a light-emitting control module and a light-emitting control signal provided to the light-emitting control module. The light-emitting control signal includes a first-level signal and a second-level signal. The light-emitting control module is turned on under the control of the first-level signal. In the data hold frame, the first-level signal and the second-level signal are alternately set, and the effective level signal of the start-up trigger signal sent by each start-up trigger signal line is located within the time period corresponding to the first second-level signal in the data hold frame. This helps to improve the low-frequency flicker problem of display products.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the widespread use of electronic devices (such as mobile phones, tablets, etc.), electronic devices can support more and more applications and have more and more powerful functions. Electronic devices are developing in a diversified and personalized direction, becoming indispensable electronic products in users' lives.

[0003] Current display devices typically drive panels or devices containing electroluminescent devices such as organic light-emitting diodes (OLEDs) and miniature diodes at different driving frequencies. In other words, the display panel can display images at different refresh rates. Specifically, when high-speed driving is required, the refresh rate is increased to drive the pixels; when power consumption must be reduced or low-speed driving is required, the refresh rate is decreased to drive the pixels.

[0004] In related technologies, when reducing the refresh rate to drive pixels, display devices are prone to low-frequency flickering, which affects the display effect. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a display device to improve the problem of low-frequency flicker and enhance the display effect.

[0006] In a first aspect, this application provides a display panel, including a display area and a non-display area surrounding the display area;

[0007] The display area includes multiple first scan lines extending along a first direction and arranged along a second direction, the first direction intersecting the second direction; the display area includes N sub-display areas arranged along the second direction, where N≥2 and is an integer;

[0008] The non-display area includes N gate driving modules corresponding to the sub-display area. Each gate driving module includes multiple cascaded gate driving units, which are electrically connected to the first scan line. In each gate driving module, the gate driving unit located in the first stage is connected to different start-up trigger signal lines. The start-up trigger signal lines are used to transmit start-up trigger signals to the gate driving unit located in the first stage connected to them.

[0009] The display panel includes a first frequency display frame, which includes a data write frame and a data hold frame. The display panel includes a light emission control module and a light emission control signal provided to the light emission control module. The light emission control signal includes a first level signal and a second level signal. The light emission control module is turned on under the control of the first level signal and turned off under the control of the second level signal. In the data hold frame, the first level signal and the second level signal are alternately set, and the effective level signal of the start trigger signal sent by each of the start trigger signal lines is located within the time period corresponding to the first second level signal in the data hold frame.

[0010] Secondly, this application provides a display device, the display device including the display panel provided in the first aspect.

[0011] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0012] In the display panel and display device provided in this application, during the data holding frame, the effective level signals of the start-up trigger signals sent by each start-up trigger signal line are all located within the time period corresponding to the first second level signal in the data holding frame. That is, the bias state of the driving transistor is adjusted when the light-emitting control module is in the off state. In particular, this invention limits the effective level signals of the start-up trigger signals sent by each start-up trigger signal line to be located within the time period corresponding to the first second level signal in the data holding frame. That is, during the time period corresponding to the first second level signal in the data holding frame, the gate driving unit located in the first stage of each driving module adjusts the bias state of the driving transistor corresponding to the sub-pixel in the first row of each sub-display area. The starting time of the bias adjustment in different sub-display areas is all located within the time period corresponding to the first second level signal. The state of the driving transistor in each display area can be adjusted in half a frame or even less, effectively saving the bias adjustment time. Therefore, it is beneficial to avoid the problem that the bias adjustment signal may be transmitted to the data writing frame due to the excessive bias adjustment time, thus avoiding the problem of low-frequency flicker caused by the above problem, and thus improving the low-frequency display effect of the display panel.

[0013] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0014] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0016] Figure 1 The diagram shown illustrates a driving cycle for low-frequency display frames in related technologies.

[0017] Figure 2 The figure shown is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention;

[0018] Figure 3 yes Figure 2 A schematic diagram of an electrical connection structure for a neutron pixel;

[0019] Figure 4 The diagram shown is a schematic diagram of a driving cycle for a display panel displaying a frame at a first frequency, provided in an embodiment of the present invention.

[0020] Figure 5 The diagram shown is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0021] Figure 6 The diagram shown is a schematic diagram of a driving cycle for a display panel displaying a frame at a second frequency, provided in an embodiment of the present invention.

[0022] Figure 7 The diagram shown is a schematic diagram of another driving cycle of the display panel displaying the frame at the first frequency according to an embodiment of the present invention.

[0023] Figure 8 The diagram shows a light-emitting element and a pixel circuit connected to the light-emitting element.

[0024] Figure 9 The diagram shown is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0025] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0026] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0027] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0028] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0029] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0030] In existing technologies, during the driving process of a variable frequency display panel, if the display frame is downclocked from the base frequency to a low frequency display frame, the low frequency display frame includes a data writing period and a data holding period. During the data holding period, the bias state of the driving transistor can be adjusted to improve the low frequency display effect. Downclocking can generally be achieved in two forms: Frameskip and Long-V. Both Frameskip and Long-V downclocking are implemented through frame interpolation. For Frameskip, downclocking is performed by inserting entire frames. Assuming the base frequency is 120Hz, when using Frameskip for downclocking, the frequency can only be reduced to 60Hz, 30Hz, etc., but not to 80Hz. For Long-V, frequency reduction can be achieved without inserting full frames. Assuming a base frequency of 120Hz, inserting half a frame reduces it to 120Hz ÷ 1.5 = 80Hz, and inserting 0.25 frames reduces it to 120Hz ÷ 1.25 = 96Hz. This allows frequencies that cannot be achieved using frame skipping for frequency reduction. Therefore, Long-V offers greater flexibility and wider applicability. However, when frequency reduction is not performed by inserting full frames, signals that would normally belong to the data holding period (such as signals adjusting the bias state of the driving transistors) may appear during the data writing period. For example, please refer to [reference needed]. Figure 1 , Figure 1 The pulse signal that should have been in the data hold period (keep) but actually appeared in the data write period (active) is represented in bold. This causes data crosstalk during the data write period (active), resulting in noticeable flickering. Figure 1 The diagram shows a driving cycle for a low-frequency display frame in related technologies.

[0031] To address these issues, the present invention provides a display panel. Figure 2 The figure shown is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention. Figure 3 yes Figure 2 A schematic diagram of an electrical connection structure for a neutron pixel. Figure 4 The diagram shown is a schematic diagram of a driving cycle for a display panel displaying a frame at a first frequency, provided in an embodiment of the present invention. Please refer to the diagram for details. Figures 2 to 4 The display panel 100 includes a display area A and a non-display area NA surrounding the display area A;

[0032] Display area A includes multiple first scan lines S01 extending along a first direction D1 and arranged along a second direction D2, where the first direction D1 and the second direction D2 intersect; display area A includes N sub-display areas A0 arranged along the second direction D2, where N≥2 and are integers;

[0033] The non-display area NA includes N gate driving modules VSR corresponding to the sub-display area A0. Each gate driving module VSR includes multiple cascaded gate driving units 10, which are electrically connected to the first scan line S01. In each gate driving module VSR, the gate driving unit 10 located in the first stage is connected to different start-up trigger signal lines STV. The start-up trigger signal lines STV are used to transmit start-up trigger signals to the gate driving unit 10 located in the first stage connected to them.

[0034] The display panel includes a first frequency display frame, which includes a data write frame (active) and a data hold frame (keep). The display panel includes a light emission control module 30 and a light emission control signal EM provided to the light emission control module 30. The light emission control signal EM includes a first level signal V1 and a second level signal V2. The light emission control module 30 is turned on under the control of the first level signal V1 and turned off under the control of the second level signal V2. In the data hold frame (keep), the first level signal V1 and the second level signal V2 are alternately set, and the effective level signal of the start trigger signal sent by each start trigger signal line STV is located within the time period corresponding to the first second level signal V2 in the data hold frame (keep).

[0035] Specifically, the display panel provided in this embodiment is an organic light-emitting diode (OLED) display panel or a display panel including electroluminescent devices such as micro-light-emitting diodes. If the display panel is an OLED display panel, it may include multiple sub-pixels P. Optionally, the multiple sub-pixels P may include various different colors, such as at least red, green, and blue sub-pixels, and may also include white sub-pixels, etc., which is not limited in this embodiment. Optionally, the multiple sub-pixels P may be arranged in an array on the display panel, or may be arranged in other ways. Figure 2 This example only uses the arrangement of multiple sub-pixel P arrays as an example for illustration. It can be understood that this embodiment... Figure 2 The example uses a strip shape as an example of the orthogonal projection of a subpixel P onto the light-emitting surface of the display panel. In actual implementation, the shape of the subpixel P includes, but is not limited to, this shape. For example, it can also be designed as a circle or a polygon, etc. The specific design can be based on actual needs.

[0036] Continue to refer to Figures 2 to 4 The display panel provided by the present invention includes a display area A comprising multiple first scan lines S01 extending along a first direction D1 and arranged along a second direction D2, and the display area A comprising N sub-display areas A0 arranged along the second direction D2. Figure 2 This explanation uses the example of display area A comprising two sub-display areas A0 (the first sub-display area A01 and the second sub-display area A02) as an example, but does not limit the actual number of sub-display areas A0 contained in display area A. Figure 2 In the illustrated embodiment, the gate driving modules corresponding to the two sub-display areas are a first gate driving module VSR1 and a second gate driving module VSR2, respectively. The gate driving unit 10 in the first stage of the first gate driving module VSR1 is connected to the first start-up trigger signal line STV1, and the gate driving unit 10 in the first stage of the second gate driving module VSR2 is connected to the second start-up trigger signal line STV2. In some other embodiments of the present invention, the number of sub-display areas A0 may be three or more, for example, please refer to... Figure 5 , Figure 5 The diagram shown is a schematic representation of another planar structure of the display panel provided in an embodiment of the present invention. Figure 2 The difference lies in the number of sub-display areas A0 contained in display area A, and the number of gate drive modules VSR contained in non-display area A. Figure 5 In the illustrated embodiment, a display area A is provided, comprising three sub-display areas A0: a first sub-display area A01, a second sub-display area A02, and a third sub-display area A03. Each of the three sub-display areas A0 corresponds to an independent gate driving module VSR. The corresponding gate driving modules VSR1, VSR2, and VSR3 are respectively the first gate driving module VSR1, the second gate driving module VSR2, and the third gate driving module VSR3. The start-up trigger signal lines corresponding to the three gate driving modules are the first start-up trigger signal line STV1, the second start-up trigger signal line STV2, and the third start-up trigger signal line STV3.

[0037] It should be noted that each sub-display area A0 is equipped with multiple first scan lines S01. Figure 2 The first scan line S01 shown is for illustration only and does not limit the actual number of first scan lines S01 contained in the display panel or the actual number of first scan lines S01 contained in each sub-display area A0, nor does it limit the number of sub-pixels P connected to the first scan line S01.

[0038] N gate drive modules (VSRs) are provided in the non-display area A of the display panel. Each sub-display area A0 has a corresponding gate drive module (VSR). Each gate drive module (VSR) includes a cascaded gate drive unit 10. The gate drive unit 10 is electrically connected to the first scan line S01 in the corresponding sub-display area A0 and is used to transmit scan control signals to the first scan line S01. In each gate drive module VSR, the gate drive unit 10 in the first stage is connected to different start trigger signal lines STV. The start trigger signal line STV is used to transmit a start trigger signal to the gate drive unit 10 in the first stage connected to it. The start trigger signal is transmitted to the input terminal of the gate drive unit 10 in the first stage as an input signal. After the gate drive unit 10 in the first stage is shifted, the above signal is output to the first scan line S01 of the same stage as an output signal of the gate drive unit 10 in the first stage. It is used as a scan control signal or bias control signal transmitted to the first scan line S01 to control the conduction state of the transistor connected to the first scan line S01. At the same time, the output signal of the first gate drive unit 10 in the first stage is also input to the input terminal of the first gate drive unit 10 in the next stage. After the first gate drive unit 10 in the next stage is shifted, it outputs the signal to the first scan line connected to it.

[0039] The display panel provided by this invention includes a first frequency display frame. Optionally, the first frequency display frame is a low-frequency display frame, which can be understood as a display frame at a low refresh rate after the display panel has undergone frequency reduction operation. This first frequency display frame includes a data write frame (active) and a data hold frame (keep). In the data write frame (active), the gate driving unit 10 cooperates with the sub-pixels in the display panel to complete the scanning of all sub-pixels in the display panel, realizing the normal display function of the display panel. Each sub-pixel includes a pixel circuit and a light-emitting element 20, with the pixel circuit driving the light-emitting element 20 to emit light. In the data hold frame (keep), the bias state of the driving transistor DT in the pixel circuit can be adjusted, reducing the degree of ion polarization inside the driving transistor DT and lowering the threshold voltage offset of the driving transistor. This can improve the display effect by mitigating the hysteresis effect of the driving transistor in the display panel.

[0040] Please combine Figures 2 to 4The display panel provided by this invention includes a light-emitting control module 30 and a light-emitting control signal EM provided to the light-emitting control module 30. The light-emitting control signal EM includes a first level signal V1 and a second level signal V2. The light-emitting control module 30 can be turned on under the control of the first level signal V1 and turned off under the control of the second level signal V2. The start-up trigger signal transmitted by the start-up trigger signal line STV connected to the gate driving unit 10 in the first stage includes an effective level signal and an ineffective level signal. The effective level signal is a signal that can control the transistor connected to the first scan line to turn on after being output to the corresponding first scan line. The ineffective level signal is a signal that cannot control the transistor connected to the first scan line to turn on. During the data hold frame keep, the first level signal V1 and the second level signal V2 are alternately set. Since the light-emitting control module 30 is turned on under the control of the first level signal V1 and turned off under the control of the second level signal V2, when the bias operation is performed during the data hold frame keep, the time for each start-up trigger signal line STV to send the effective level signal must be set within the time period corresponding to the second level signal V2. That is, the bias operation is performed when the light-emitting control module 30 is turned off.

[0041] In this embodiment of the invention, during the data hold frame keep, the effective level signals of the start trigger signals sent by each start trigger signal line STV are all located within the time period corresponding to the first second level signal V2 in the data hold frame keep. That is, the bias state of the driving transistor is adjusted when the light emission control module 30 is in the off state. In particular, this invention limits the effective level signal of the start-up trigger signal sent by each start-up trigger signal line STV to be within the time period corresponding to the first second level signal V2 in the data holding frame keep. That is, within the time period corresponding to the first second level signal V2 in the data holding frame keep, the bias state of the driving transistor corresponding to the sub-pixel in the first row of each sub-display area A0 is adjusted. The starting time of the bias adjustment of the driving transistor in the first row of the sub-pixel in different sub-display areas A0 is within the time period corresponding to the first second level signal V2. The state of the driving transistor in each display area A can be adjusted in half a frame or even less, which effectively saves the bias adjustment time. Therefore, it is beneficial to avoid the problem that the bias adjustment signal may be transmitted to the data writing frame due to the excessive bias adjustment time. Thus, it is beneficial to avoid the problem of low-frequency flicker caused by the above problem, and thus it is beneficial to improve the low-frequency display effect of the display panel.

[0042] Figure 6 The diagram shown is a schematic diagram of a driving cycle of a display panel in a second frequency display frame according to an embodiment of the present invention. Please refer to it. Figure 6In an optional embodiment of the present invention, the display panel further includes a second frequency display frame, the second frequency being greater than the first frequency, and the second frequency display frame only includes the data writing frame active.

[0043] Specifically, the second frequency display frame mentioned in this embodiment of the invention can be understood as the display frame corresponding to the basic refresh rate when the display panel is not downclocked, and the first frequency display frame can be understood as the display frame at a low refresh rate after the display panel has undergone downclocking. This embodiment of the invention does not specifically limit the refresh rate of the first and second frequency display frames, only requiring that the refresh rate of the second frequency display frame is greater than the refresh rate of the first frequency display frame. Figure 6 As shown, in the second frequency display frame, only the data write frame "active" is included. This means that the display panel does not undergo frequency downgrading and still uses a higher refresh rate for display, thus satisfying the normal frequency display requirements of the display panel. By simultaneously introducing the first and second frequency display frames into the display panel, both the normal frequency display requirements and the frequency downgrading display requirements are met, effectively saving power consumption of the display product.

[0044] Please refer to Figure 4 In an optional embodiment of the present invention, in a single first frequency display frame, the duration of the data keeping frame keep is T1, and the duration of the data writing frame active is T2, where T1 / T2 = X, and X is a non-integer.

[0045] Please continue to refer to this. Figure 3 When the ratio of the duration of the data hold frame (keep) to the duration of the data write frame (active) is not an integer, it means that the frequency reduction of the display panel is not performed in whole frames. In related technologies, when the frequency reduction of the display panel is not performed in whole frames, if the gate driving unit 10 adjusts the bias state of the driving transistors row by row from the first row to the last row of the display panel during the data hold frame (keep), the bias state adjustment time is too long. It is difficult to complete the adjustment of the bias state of all driving transistors during the data hold frame (keep), and some bias state adjustment control signals will be transmitted to the data write frame (active), causing signal crosstalk and resulting in a more obvious flickering problem. In response to the issue that the frequency reduction of the display panel is not performed in whole frames, this embodiment of the invention ensures that the effective level signals in the start-up trigger signals sent to each gate driving unit 10 in the first stage during the first frequency display frame are all located within the time period corresponding to the first second level signal V2. This ensures that at least some of the driving transistors in different sub-display areas A0 are biased and adjusted within the same time period, saving bias adjustment time. This helps to avoid signal crosstalk and flickering problems caused by the frequency reduction of the display panel not being performed in whole frames, thus improving the overall display effect of the display panel.

[0046] Continue to refer to Figures 2 to 4 In an optional embodiment of the present invention, during the data holding frame keep, each start trigger signal line STV simultaneously sends an effective level signal of the start trigger signal to the corresponding gate drive unit 10.

[0047] Specifically, Figure 4 The illustrated embodiment shows that the start times of each valid level signal in the start-up trigger signal line STV corresponding to different gate drive modules VSR are at the same time. That is, each start-up trigger signal line STV simultaneously sends the valid level signal of the start-up trigger signal to the gate drive unit 10 connected to it. At this time, the drive transistors in the first pixel row of different sub-display areas A0 simultaneously adjust their bias states. In each sub-display area A0, after the bias state adjustment of the drive transistors in the first pixel row is completed, the bias state adjustment of the drive transistors in subsequent pixel rows is performed sequentially. It can be seen that at least part of the process of adjusting the bias state of the drive transistors in different sub-display areas A0 is performed synchronously, which shortens the bias state adjustment time by at least half compared to related technologies, and avoids the signal corresponding to the bias state adjustment from entering the active data write frame, thus helping to improve the low-frequency flicker problem.

[0048] Furthermore, the method of simultaneously sending effective level signals of the start-up trigger signal to the corresponding gate drive unit 10 during the data hold frame keep also helps to simplify the control timing of the entire display panel and reduce the design complexity of the control chip.

[0049] Please continue to refer to this. Figures 2 to 4 In an optional embodiment of the present invention, during the data holding frame keep, the gate driving unit 10 is used to transmit a bias adjustment control signal to the first scan line S01, and the duty cycle of the bias adjustment control signal transmitted by the gate driving unit 10 in each gate driving module VSR is the same.

[0050] Continue to refer to Figure 4The bias adjustment control signal transmitted by the gate driving unit 10 includes an active level signal and an inactive level signal. The same duty cycle means that the durations of different active level signals and different inactive level signals in each gate driving unit 10 are the same. When the duty cycle of the bias adjustment control signal transmitted by the gate driving unit 10 in each gate driving module VSR is set to the same, and during the data hold frame keep, each start trigger signal line STV simultaneously sends an active level signal of the start trigger signal to the corresponding gate driving unit 10, when the bias state of the driving transistor is adjusted during the data hold frame keep, the driving transistors corresponding to the sub-pixels in the nth row of different sub-display areas A0 will simultaneously undergo bias state adjustment, where n≥1. For example, the driving transistors in the sub-pixels in the first row of different sub-display areas A0 simultaneously undergo bias state adjustment, then the driving transistors in the sub-pixels in the second row of different sub-display areas A0 simultaneously undergo bias state adjustment, until the bias state adjustment of the driving transistors in each sub-display area A0 is completed. In this configuration, the bias adjustment control signals provided to the driving transistors in different sub-display areas A0 are high and low level signals with the same duty cycle. Therefore, it is beneficial to reduce the types of bias adjustment control signals, simplify the control complexity of the display panel, and reduce the design complexity of the control chip.

[0051] The above embodiments illustrate a scheme where the start times of the effective levels of the start-trigger signals transmitted by each start-trigger signal line (STV) are the same. In some other embodiments of the present invention, the start times of the effective levels of the start-trigger signals transmitted by different start-trigger signal lines (STV) may be slightly offset. For example, please refer to... Figure 7 , Figure 7 The diagram shown illustrates another driving cycle of the display panel in the first frequency display frame according to an embodiment of the present invention. Please refer to [the diagram]. Figure 7 In an optional embodiment of the present invention, during the data hold frame keep, the start time of the effective level signal of the start trigger signal sent by at least two start trigger signal lines STV has a first interval, the duration of the first interval t0 > 0.

[0052] Specifically, please combine Figure 2 , Figure 3 and Figure 7When the effective level signals of the start trigger signals sent by each start trigger signal are all located within the time period corresponding to the first second level signal V2 in the data holding frame keep, the start times of the effective level signals of different start trigger signals may be slightly misaligned, i.e., there is a certain first interval. At least two different start trigger signals are not sent to the corresponding gate drive unit 10 at the same time. At this time, at least one sub-display area A0 corresponding to the first level gate drive unit 10 is turned on first, and the other sub-display area A0 corresponding to the first level gate drive unit 10 is turned on later. However, both are turned on within the time period corresponding to the first second level signal V2 in the data holding frame keep. The interval between the times when all the corresponding drive transistors in each sub-display area A0 are adjusted is also small. Different sub-display areas A0 will also adjust the bias voltage of each drive transistor within the same short time period. This can also avoid the phenomenon of the bias adjustment control signal being transmitted to the data write frame active. Therefore, it is also beneficial to improve the problem of display panel flickering during low-frequency display and also beneficial to improve the display effect of the display panel.

[0053] Please refer to Figure 7 In an optional embodiment of the present invention, the duration of the first second level signal V2 in the data hold frame keep is t1, and the duration of the effective level of a single start trigger signal is t2. In the data hold frame keep, the duration of the first interval between the start times of at least two start trigger signal lines STV transmitting the effective level signals of the start trigger signals is t0≤t1-t2.

[0054] Specifically, when the start times of the effective levels of the start-trigger signals sent by at least two start-trigger signal lines STV are misaligned and have a first interval, in order to ensure that the effective levels of the start-trigger signals are all within the time period corresponding to the first second-level signal V2 in the data hold frame keep, one extreme case is that the start time of the effective level sent by one of the start-trigger signal lines STV1 is the same as the start time of the first second-level signal V2 in the data hold frame keep, and the end time of the effective level sent by the other start-trigger signal line STV2 is the same as the start time of the first second-level signal V2 in the aforementioned data hold frame keep. The cutoff times of V2 are the same. Assuming that the duration of a single effective level corresponding to different start trigger signals is the same, the duration of the first interval between the start times of the effective levels of the two start trigger signals is t1-t2. For other misalignment cases, the duration of the first interval is less than t1-t2. Therefore, when the duration of the first interval is set to t0≤t1-t2 in this embodiment of the invention, it can still be guaranteed that the effective level signals of the start trigger signals received by the gate drive unit 10 located in the first stage in different gate drive modules VSR are all within the time period corresponding to the first second level signal V2 in the data holding frame keep.

[0055] Please combine Figures 2 to 4 ,as well as Figure 7 In an optional embodiment of the present invention, in the first frequency display frame, within a data write frame active, the light emission control signal includes M first level signals V1, where N≤M.

[0056] Specifically, this embodiment establishes a correspondence between the number M of effective levels of the light emission control signal within each data write frame active corresponding to the first frequency display frame and the number N of sub-display areas A0 that can be divided by the display area A. Considering that the number of first-level signals V1 and second-level signals V2 of the light emission control signal are consistent within the first data write frame active, and that the bias adjustment control signal sent by the gate driving unit 10 in the gate driving module VSR is located within the time period of the second-level signal V2 of the light emission control signal in the data holding frame keep, and that the number of sub-display areas A0 corresponds to the gate driving module VSR, setting the number N of sub-display areas A0 to be less than or equal to the number M of first-level signals V1 included in the light emission control signal within a data write frame active in the first frequency display frame enables the gate driving unit 10 in each gate driving module VSR to complete the transmission of the bias adjustment control signal in the data holding frame keep, thereby completing the bias state adjustment of the driving transistors in each sub-display area A0 in the data holding frame keep.

[0057] Please refer to Figure 2 and Figure 5In an optional embodiment of the present invention, the number of first scan lines S01 contained in each sub-display area A0 is the same. This is equivalent to dividing the display area A of the display panel into N equal sub-display areas A0, and the number of gate driving units 10 corresponding to each sub-display area A0 will also be the same. During the data hold frame (keep), the time required for different sub-display areas A0 to complete the bias state adjustment of the driving transistors is the same. When the start time of the effective level signal of the start trigger signal line STV sending the start trigger signal to the corresponding first-stage gate driving unit 10 in the gate driving module VSR corresponding to different sub-display areas A0 is the same, the scheme of having the same number of first scan lines S01 contained in each sub-display area A0 allows different sub-display areas A0 to complete the bias state adjustment of all driving transistors at the same time. Thus, the bias adjustment process of different sub-display areas A0 will be completed within the same time period, effectively shortening the time required for bias adjustment. Therefore, it is more beneficial to avoid the phenomenon of the bias adjustment control signal being transmitted to the data write frame (active), and it is more beneficial to improve the problem of low-frequency flicker.

[0058] Please continue to refer to this. Figure 2 and Figure 4 In an optional embodiment of the present invention, the gate driving modules VSRs corresponding to two adjacent sub-display areas A0 along the second direction D2 are respectively the first gate driving module VSR1 and the second gate driving module VSR2. When the data write frame is active, the effective level signal of the start trigger signal received by the gate driving unit 10 located in the first stage of the first gate driving module VSR1 is S1, and the effective level signal of the start trigger signal received by the gate driving unit 10 located in the first stage of the second gate driving module VSR2 is S2. Wherein, S2-S1=p*t, where t is the time for scanning the sub-pixels in display area A connected to the same first scan line S01, and p is the number of first scan lines S01 connected to the first gate driving module VSR.

[0059] Specifically, this embodiment describes the operation of the gate driving module VSR when the data write frame is active. In the active data write frame, the gate driving modules VSR corresponding to the two adjacent sub-display areas A0 along the second direction D2 are respectively the first gate driving module VSR1 and the second gate driving module VSR2. Optionally, the gate driving unit 10 in the first stage of the first gate driving module VSR1 is electrically connected to the first first scan line S01 in the upper sub-display area A0, and the gate driving unit 10 in the first stage of the second gate driving module VSR2 is electrically connected to the first first scan line S01 in the lower sub-display area A0. Optionally, in the active data write frame, when the data write frame is active, the gate driving unit 10 in the first stage of the second gate driving module VSR2 is electrically connected to the first first scan line S01 in the lower sub-display area A0. When scanning from top to bottom, in the upper sub-display area (assuming it is the first sub-display area A01), the cascaded gate driving unit 10 sends scan control signals line by line to the first scan line S01 in the first sub-display area A01 to scan the corresponding sub-pixels line by line. After the first sub-display area A01 is scanned, the gate driving unit 10 in the first stage of the lower sub-display area (assuming it is the second sub-display area A02) adjacent to the first sub-display area A01 then sends scan control signals to the corresponding first scan line. In the second sub-display area A02, the cascaded gate driving unit 10 sends scan control signals line by line to the first scan line S01 in the second sub-display area A02 to scan the corresponding sub-pixels line by line. In other words, in this embodiment, S2-S1 = p*t is defined so that after the scanning of one sub-display area A0 is completed in the data writing frame active, the scanning of the next sub-display area A0 is then performed. That is, in the data writing frame active, the gate driving units 10 located in the first stage in different gate driving modules VSR do not transmit scanning control signals simultaneously. The scanning of all first scan lines S01 in the display area A is performed line by line from top to bottom or from bottom to top.

[0060] In this embodiment of the invention, different gate driving modules (VSRs) are set for different sub-display areas A0. During the data write frame (active), the gate driving units 10 in the different gate driving modules (VSRs) can be controlled to transmit scan control signals line by line to the connected first scan lines S01. During the data hold frame (keep), the gate driving units 10 in the first stage of the different gate driving modules (VSRs) can be controlled to simultaneously transmit bias control signals to the corresponding first scan lines S01. This reduces the time required to adjust the bias voltage of the driving transistors in display area A, avoiding signal crosstalk caused by the bias adjustment control signal entering the data write frame (active) due to the bias voltage adjustment time. This helps improve the low-frequency display problem of the display panel. Therefore, setting different gate driving modules (VSRs) for different sub-display areas A0 can satisfy both the display requirements of the data write frame (active) and the bias voltage adjustment requirements of the data hold frame (keep), effectively improving the control flexibility of the display panel.

[0061] Please combine Figure 2 and Figure 4 In an optional embodiment of the present invention, when the data writing frame of the first frequency display frame is active, the duty cycle of the scan control signal output by the gate driving unit 10 in each gate driving module VSR is the same.

[0062] Specifically, when the data writing frame of the first frequency display frame is active, the gate driving unit 10 in the first stage of the gate driving module VSR corresponding to different sub-display areas A0 does not transmit the scan control signal simultaneously. Instead, it performs the scan of the next sub-display area A0 after completing the scan of one sub-display area A0. At this time, when the duty cycle of the scan control signal output by the gate driving unit 10 in each gate driving module VSR is set to the same, the scanning frequency of the corresponding sub-display area A0 by different gate driving modules VSR is consistent. This is beneficial to achieve uniform scanning of the entire display area A line by line from top to bottom or from bottom to top, and improve the display effect of the display panel in low frequency display mode.

[0063] In addition, when the duty cycle of the scan control signal output by each gate drive unit 10 is set to be the same during the active data write frame, the type of signal output by the gate drive unit 10 during the active data write frame can be simplified, which in turn helps to simplify the control timing of the display panel during the active data write frame and reduce the design difficulty of the control chip.

[0064] Figure 8 The diagram shows a light-emitting element and a pixel circuit connected to the light-emitting element. Figure 8The overall structure can be viewed as the connection relationship of a sub-pixel within the display panel. It should be noted that... Figure 8 This explanation uses only some P-type transistors and some N-type transistors as examples, without limiting the types of transistors. Specifically, the gate of a P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal; the gate of an N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal.

[0065] Please combine Figure 3 and Figure 8 In an optional embodiment of the present invention, the display panel includes a plurality of light-emitting elements and a pixel circuit connected to the light-emitting elements. The pixel circuit includes a driving transistor DT, a data writing module 40, a compensation module 50, a first light-emitting control module 31 and a second light-emitting control module 32. The gate of the driving transistor DT is connected to a first node N1, the first electrode of the driving transistor DT is connected to a second node N2, and the second electrode of the driving transistor DT is connected to a third node N3.

[0066] The input terminal of the data writing module 40 is connected to the first signal terminal (corresponding to signal Vdata), and the control terminal is connected as follows: Figure 2 or Figure 5 The first scan line S01 shown corresponds to the data write control signal or bias adjustment signal SP1, and the second end is connected to the second node N2; the first end of the compensation module 50 is connected to the third node N3, the second end is connected to the first node N1, the control end is connected to the second scan line, and the transmitted signal is the control signal Scan2.

[0067] The first terminal of the first light-emitting control module 31 is connected to the first power supply terminal, and the corresponding signal is the first power supply signal Vpvdd. The second terminal is connected to the second node N2, and the control terminal is connected to the light-emitting control signal terminal, and the corresponding signal is the light-emitting control signal EM. The first terminal of the second light-emitting control module 32 is connected to the third node N3, the second terminal is connected to the first electrode of the light-emitting element 20, the control terminal is connected to the light-emitting control signal terminal, and the corresponding signal is the light-emitting control signal EM. The second electrode of the light-emitting element 20 is connected to the second power supply terminal, and the corresponding signal is the second power supply signal Vpvee.

[0068] Please combine Figure 4 and Figure 8 During the bias phase of the data hold frame, the data writing module 40 is turned on, and the first signal terminal transmits the bias signal to the second node N2.

[0069] like Figure 3 and Figure 8As shown, a sub-pixel P of the display panel includes an electrically connected pixel circuit and a light-emitting element, which can be an organic light-emitting diode (OLED). The pixel circuit included in sub-pixel P is used to drive signal lines (such as scan lines, data lines, power signal lines, light-emitting control signal lines, reset signal lines, etc.) on the display panel. Figure 8 (Not shown in the image) Under the action of a signal, the light-emitting driving current is transmitted to the light-emitting element, providing driving current to the light-emitting element so that it emits light.

[0070] Specifically, this embodiment uses a pixel circuit comprising 7 transistors and 1 capacitor for illustration. The first light-emitting control module 31 includes a first transistor T1, the second light-emitting control module 32 includes a sixth transistor T6, and the data writing module 40 is multiplexed as a bias adjustment module. The bias adjustment module, i.e., the data writing module 40, includes a second transistor T2. The pixel circuit also includes a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, and a storage capacitor Cst. The gate of the driving transistor DT is connected to the first terminal of the fifth transistor T5, the second terminal of the fifth transistor T5 is connected to the first reset signal Vref1, and the gate of the fifth transistor T5 is connected to the first scan control signal Scan1. The first terminal of the driving transistor DT is connected to the first terminal of the first transistor T1, the second terminal of the first transistor T1 is connected to the first power supply signal Vpvdd, and the gate of the first transistor T1 is connected to the light-emitting control signal EM. The first terminal of the driving transistor DT is also connected to the first terminal of the second transistor T2, the second terminal of the second transistor T2 is connected to the voltage signal Vdata, and the gate of the second transistor T2 is connected to the data writing control signal or the bias adjustment signal SP1.

[0071] The second terminal of the driving transistor DT is connected to the first terminal of the sixth transistor T6. The second terminal of the sixth transistor T6 is connected to the anode of the light-emitting element 20. The cathode of the light-emitting element 20 is connected to the second power supply signal Vpvee. The gate of the sixth transistor T6 is also connected to the light-emitting control signal EM. That is, when the gate of the first transistor T1 and the gate of the sixth transistor T6 respond together to the effective level signal of the light-emitting control signal EM, the first transistor T1 and the sixth transistor T6 are in the conducting state.

[0072] Optionally, the first terminal of the seventh transistor T7 is connected to the second reset signal Vref2, the second terminal of the seventh transistor T7 is connected to the anode of the light-emitting element 20, and the gate of the seventh transistor T7 is connected to the first scan control signal Scan1. That is, when the gates of the fifth transistor T5 and the seventh transistor T7 jointly respond to the effective level signal of the first scan control signal Scan1, the fifth transistor T5 and the seventh transistor T7 are in the on state. Optionally, the second reset signal Vref2 and the first reset signal Vref1 can be different reset voltage signals or the same reset voltage signal. The figure in this embodiment is only used as an example to illustrate that the second reset signal Vref2 and the first reset signal Vref1 are different reset voltage signals and are provided by different signal lines.

[0073] The first terminal of the fourth transistor T4 is connected to the gate of the driving transistor DT, and the second terminal of the fourth transistor T4 is connected to the second terminal of the driving transistor DT. The gate of the fourth transistor T4 is connected to the second scan control signal Scan2. That is, when the gate of the fourth transistor T4 can respond to the effective level signal of the second scan control signal Scan2, the fourth transistor T4 is in the on state. Optionally, the second scan control signal Scan2 and the gate of the second transistor T2 are connected to the data write control signal or the bias adjustment signal SP1, which may be the same signal or different signals. This invention does not limit this.

[0074] One end of the storage capacitor Cst is connected to the first power supply signal Vpvdd, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor DT. The storage capacitor Cst is used to stabilize the gate potential of the driving transistor DT, which helps the driving transistor DT to remain on.

[0075] This embodiment explains the circuit connection structure that a pixel circuit in a display panel may include. The pixel circuit includes multiple transistors and a storage capacitor Cst, wherein one transistor is a driving transistor DT, and the remaining transistors are switching transistors. (This embodiment...) Figure 8 Taking the schematic diagram of the pixel circuit and the structure of the light-emitting element electrically connected as an example, the gate of the driving transistor DT represents the first node N1, the first electrode of the driving transistor DT represents the second node N2, the second electrode of the driving transistor DT represents the third node N3, and the anode of the light-emitting element 20 is taken as the fourth node N4. The working principle of this pixel circuit is as follows:

[0076] During the initial reset phase, the fifth transistor T5 and the seventh transistor T7 are turned on, while the remaining transistors are turned off. The potential of the first node N1 is the first reset signal Vref1, and the potential of the fourth node N4 is the second reset signal Vref2, thus completing the reset of the gate of the driving transistor DT and the anode of the light-emitting element 20.

[0077] During the data writing and threshold capture phase, the second transistor T2, the fourth transistor T4, and the driving transistor DT are turned on, while the other transistors are turned off. The potential of the second node N2 is the data voltage signal Vdata, and the potentials of the first node N1 and the third node N3 are Vdata-|Vth|, where Vth is the threshold voltage of the driving transistor DT.

[0078] During the light-emitting phase, the first transistor T1, the sixth transistor T6, and the driving transistor DT are turned on, while the remaining transistors are turned off. The first power supply signal Vpvdd is transmitted to the driving transistor DT, which generates a driving current to drive the light-emitting element 20 to emit light. The potential of the second node N2 is the first power supply signal Vpvdd, the potential of the first node N1 is Vdata - |Vth|, and the potential of the third node N3 is Vpvee + Voled, where Voled is the corresponding voltage on the light-emitting element 20. Therefore, the light-emitting current Id = k(Vgs - |Vth|). 2 = k(Vpvdd-Vdata-|Vth|) 2 ; where the constant k is related to the performance of the driving transistor DT itself.

[0079] This embodiment explains that the data writing module 40 in the pixel circuit can be reused as a bias adjustment module. Specifically, during the bias voltage phase of the data holding frame (keep), when the bias adjustment signal SP1 controls the first and second terminals of the bias adjustment module to conduct, the bias signal VD at the first signal terminal is transmitted to the second node N2 to adjust the bias voltage of the driving transistor DT. This reduces the degree of ion polarization inside the driving transistor DT, lowers the threshold voltage of the driving transistor DT, and mitigates the impact of the hysteresis effect of the driving transistor DT on the display effect, thereby improving the display quality. Since the data writing module 40 is reused as a bias adjustment module, it helps reduce the number of transistors in the pixel circuit, which in turn helps increase the aperture ratio of sub-pixels in the panel, saving panel layout space.

[0080] Please combine Figure 4 , Figure 7 and Figure 8 In one optional embodiment of the present invention, in the data write frame active, the signal at the first signal terminal is the data signal Vdata; in the data hold frame keep, the signal at the first signal terminal is the bias signal VD, which is different from the data signal.

[0081] It should be noted that when the data writing module is multiplexed to the bias adjustment module, during the data writing phase corresponding to the data writing frame, the signal at the first signal terminal connected to the data writing module is a data signal; during the bias phase corresponding to the data holding frame, the signal at the first signal terminal connected to the data writing module is a bias signal. In other words, the signal provided by the first signal terminal is different during the normal display phase and the bias phase. This allows for targeted provision of corresponding bias signals to the driving transistor according to its bias adjustment requirements, thereby improving the bias state adjustment effect of the driving transistor.

[0082] Figure 9 The diagram shown is a schematic representation of a display device provided in an embodiment of this application. Please refer to it. Figure 9 Based on the same inventive concept, this application also provides a display device 200, which includes a display panel 100. The display panel is any of the display panels 100 provided in this application.

[0083] It should be noted that the embodiments of the display device provided in this application can refer to the embodiments of the display panel described above, and will not be repeated here. The display device provided in this application can be any product and component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, vehicle display screen, or navigator. The display device provided in this embodiment of the invention has the beneficial effects of the display panel provided in the above embodiments of the invention. For details, please refer to the specific descriptions of the display panel in the above embodiments, which will not be repeated here.

[0084] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0085] In the display panel and display device provided in this application, during the data holding frame, the effective level signals of the start-up trigger signals sent by each start-up trigger signal line are all located within the time period corresponding to the first second level signal in the data holding frame. That is, the bias state of the driving transistor is adjusted when the light-emitting control module is in the off state. In particular, this invention limits the effective level signals of the start-up trigger signals sent by each start-up trigger signal line to be located within the time period corresponding to the first second level signal in the data holding frame. That is, during the time period corresponding to the first second level signal in the data holding frame, the gate driving unit located in the first stage of each driving module adjusts the bias state of the driving transistor corresponding to the first row of sub-pixels in each sub-display area. The starting time of the bias adjustment in different sub-display areas is all located within the time period corresponding to the first second level signal. The state of the driving transistor in each display area can be adjusted within at least half a frame or even less, effectively saving the bias adjustment time. Therefore, it is beneficial to avoid the problem that the bias adjustment signal may be transmitted to the data writing frame due to excessive bias adjustment time, thus avoiding the problem of low-frequency flicker caused by the above-mentioned problem, and thus improving the low-frequency display effect of the display panel.

[0086] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area surrounding the display area; The display area includes multiple first scan lines extending along a first direction and arranged along a second direction, the first direction intersecting the second direction; the display area includes N sub-display areas arranged along the second direction, where N≥2 and is an integer; The non-display area includes N gate driving modules corresponding to the sub-display area. Each gate driving module includes multiple cascaded gate driving units, which are electrically connected to the first scan line. In each gate driving module, the gate driving unit located in the first stage is connected to different start-up trigger signal lines. The start-up trigger signal lines are used to transmit start-up trigger signals to the gate driving unit located in the first stage connected to them. The display panel includes a first frequency display frame, which includes a data write frame and a data hold frame. The display panel includes a light emission control module and a light emission control signal provided to the light emission control module. The light emission control signal includes a first level signal and a second level signal. The light emission control module is turned on under the control of the first level signal and turned off under the control of the second level signal. In the data hold frame, the first level signal and the second level signal are alternately set, and the effective level signal of the start trigger signal sent by each of the start trigger signal lines is located within the time period corresponding to the first second level signal in the data hold frame.

2. The display panel according to claim 1, characterized in that, The display panel also includes a second frequency display frame, the second frequency being greater than the first frequency, and the second frequency display frame only includes data write frames.

3. The display panel according to claim 1, characterized in that, In a single first frequency display frame, the duration of the data holding frame is T1, and the duration of the data writing frame is T2, where T1 / T2 = X, and X is a non-integer.

4. The display panel according to claim 1, characterized in that, During the data holding frame, each of the start-up trigger signal lines simultaneously sends a valid level signal of the start-up trigger signal to the corresponding gate drive unit.

5. The display panel according to claim 4, characterized in that, In the data holding frame, the gate driving unit is used to transmit a bias adjustment control signal to the first scan line, and the duty cycle of the bias adjustment control signal transmitted by the gate driving unit in each gate driving module is the same.

6. The display panel according to claim 1, characterized in that, In the data holding frame, the start times of the effective level signals of the start trigger signals sent by at least two of the start trigger signal lines have a first interval, the duration of the first interval being t0 > 0.

7. The display panel according to claim 6, characterized in that, The duration of the first second-level signal in the data holding frame is t1, and the duration of the effective level of a single start trigger signal is t2, wherein the duration of the first interval is t0 ≤ t1 - t2.

8. The display panel according to claim 1, characterized in that, In the first frequency display frame, within one of the data writing frames, the light emission control signal includes M of the first level signals, where N≤M.

9. The display panel according to claim 1, characterized in that, The number of first scan lines contained in each of the sub-display areas is the same.

10. The display panel according to claim 1, characterized in that, The gate driving modules corresponding to the two adjacent sub-display areas along the second direction are the first gate driving module and the second gate driving module, respectively. In the data writing frame, the effective level signal of the start trigger signal received by the gate driving unit located in the first stage of the first gate driving module is S1, and the effective level signal of the start trigger signal received by the gate driving unit located in the first stage of the second gate driving module is S2, where S2-S1=p*t, where t is the time for scanning the sub-pixels connected to the same first scan line in the display area, and p is the number of the first scan lines connected to the first gate driving module.

11. The display panel according to claim 10, characterized in that, In the data writing frame of the first frequency display frame, the duty cycle of the scan control signal output by the gate driving unit in each gate driving module is the same.

12. The display panel according to claim 1, characterized in that, The display panel includes multiple light-emitting elements and pixel circuits connected to the light-emitting elements. The pixel circuits include a driving transistor, a data writing module, a compensation module, a first light-emitting control module, and a second light-emitting control module. The gate of the driving transistor is connected to a first node, the first electrode is connected to a second node, and the second electrode is connected to a third node. The input terminal of the data writing module is connected to the first signal terminal, the control terminal is connected to the first scan line, and the second terminal is connected to the second node; the first terminal of the compensation module is connected to the third node, the second terminal is connected to the first node, and the control terminal is connected to the second scan line. The first end of the first light-emitting control module is connected to the first power supply terminal, the second end is connected to the second node, and the control terminal is connected to the light-emitting control signal terminal; the first end of the second light-emitting control module is connected to the third node, the second end is connected to the first electrode of the light-emitting element, the control terminal is connected to the light-emitting control signal terminal, and the second electrode of the light-emitting element is connected to the second power supply terminal. During the bias phase of the data holding frame, the data writing module is turned on, and the first signal terminal transmits the bias signal to the second node.

13. The display panel according to claim 12, characterized in that, In the data write frame, the signal at the first signal terminal is a data signal; in the data hold frame, the signal at the first signal terminal is the bias signal, which is different from the data signal.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-13.

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