FPGA-based liquid crystal display control device and control method

Abstract

The application discloses a kind of based on FPGA's liquid crystal display control device and control method, a kind of based on FPGA's liquid crystal display control device includes: MCU, FPGA control system, HyperRAM and LCD display;The FPGA control system includes analysis module, arbitration module, cache module, HyperRAM control module, adjustment module and output control module;The MCU is electrically connected with the analysis module, the analysis module is respectively electrically connected with the arbitration module with the cache module, the arbitration module is respectively electrically connected with the adjustment module and the cache module, the cache module is respectively electrically connected with the HyperRAM control module and the output control module;The HyperRAM control module is electrically connected with the HyperRAM, and the output control module is electrically connected with the LCD display.The application can improve the refreshing speed of LCD display, improve the flexibility of display, facilitate image processing, meet the basic development needs of large display screen.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, in particular to a liquid crystal display control device and control method based on FPGA. BACKGROUND

[0002] As a relatively active research field in computer science, digital image processing is accompanied by the improvement of social information level and the leapfrog development of information technology, and the demand for digital image information gradually expands in human production and life. Digital image processing is widely used in security monitoring, biological medicine, military guidance, film and television media and other industries. Field programmable logic array (FPGA) is widely used in communication, image processing and other fields due to its high flexibility, short development cycle, strong processing performance (parallel) and other characteristics. Therefore, image processing based on FPGA has become a popular research topic.

[0003] The standard term of MCU-LCD interface is 8080 bus (I80) standard proposed by Intel, so I80 is often used to refer to MCU-LCD screen. The advantages of MCU-LCD interface are: simple and convenient control, no clock and synchronization signal is needed; the disadvantages are: it consumes GRAM and it is difficult to achieve large screen (3.8 or more). In addition, the display data of MCU-LCD interface is written into DDRAM, which is often used for static picture display. The advantages and disadvantages of RGB-LCD interface are just the opposite of MCU-LCD mode. Its display data is not written into DDRAM, but directly written into the screen, which is fast and often used for displaying video or animation.

[0004] In order to meet the connection requirements of the RGB interface of the display, the common LCD controller in the prior art can convert the MCU interface into the RGB interface. However, when applied in a special field, only converting the MCU interface into the RGB interface cannot meet the requirements, and sometimes some data processing is also needed. Therefore, FPGA processing is introduced to convert the MCU interface into the RGB interface and to perform data processing at the same time, thereby improving the flexibility. SUMMARY

[0005] The purpose of the present application is to provide a liquid crystal display control device and control method based on FPGA. In the present application, the control of MCU is retained, FPGA processing is added, the I80 signal of MCU is analyzed as RGB signal, the refresh speed of LCD screen and the flexibility of display are improved, image processing is facilitated, and the basic development requirements of large display screen are met.

[0006] To solve the above technical problems, the present application provides a liquid crystal display control device based on FPGA, which comprises an MCU, an FPGA control system, a HyperRAM and an LCD display.

[0007] The FPGA control system comprises an analysis module, an arbitration module, a cache module, a HyperRAM control module, an adjustment module and an output control module.

[0008] The MCU is electrically connected with the analysis module, the analysis module is electrically connected with the arbitration module and the cache module respectively, the arbitration module is electrically connected with the adjustment module and the cache module respectively, and the cache module is electrically connected with the HyperRAM control module and the output control module respectively.

[0009] The HyperRAM control module is electrically connected with the HyperRAM, and the output control module is electrically connected with the LCD display.

[0010] To solve the above technical problems, the application provides a liquid crystal display control method based on FPGA, which is applied to the liquid crystal display control device based on FPGA, and the control method comprises the following steps.

[0011] The analysis module is controlled to analyze the control instruction of the MCU and realize mutual conversion of I80 signals and RGB signals.

[0012] The cache module is controlled to temporarily store the RGB signals, the control instruction and data addresses.

[0013] After the arbitration module completes a read or write operation, the I80 bus is kept in an idle state.

[0014] The display parameter adjustment instruction issued by the MCU is received and transmitted to the arbitration module.

[0015] The arbitration module is controlled to adjust the data format of the RGB signals after receiving the display parameter adjustment instruction and send an instruction signal to the adjustment module.

[0016] The adjustment module is controlled to obtain the data of the RGB signals from the cache module and adjust the display parameters according to the instruction signal of the arbitration module.

[0017] The RGB signals after the display parameters are adjusted are output to the LCD display through the output control module.

[0018] Preferably, the control of the analysis module to analyze the control instruction of the MCU and realize mutual conversion of I80 signals and RGB signals comprises the following steps.

[0019] When the control instruction is a write signal, the I80 signal is analyzed as the RGB signal and written into the cache module.

[0020] reading the RGB signal from the cache module when the control instruction is a read signal;

[0021] converting the RGB signal into the I80 signal and sending the I80 signal to the MCU.

[0022] Preferably, the step of controlling the arbitration module to complete a read or write operation and keeping the I80 bus in an idle state comprises:

[0023] when the arbitration module receives a write instruction;

[0024] if the write instruction is followed by a read instruction, the arbitration module instructs the HyperRAM control module to read data from a position to be written;

[0025] storing the data from the position to be written into the cache module and writing the data to be written into a corresponding address;

[0026] writing the read data into a mirror address and reading the data from the mirror address when a read instruction is received.

[0027] Preferably, if no read instruction is received after the write instruction, the data is directly written into the corresponding address to complete a write operation.

[0028] Preferably, the step of controlling the arbitration module to complete a read or write operation and keeping the I80 bus in an idle state further comprises:

[0029] when the arbitration module receives a read instruction;

[0030] if the read instruction is preceded by the write instruction, the arbitration module instructs the HyperRAM control module to read data from a mirror address;

[0031] setting a flag when a read or write operation is performed, setting the flag to 0 when a write instruction is received and setting the flag to 1 when a read instruction is received;

[0032] detecting the flag to determine a working state before a read or write operation.

[0033] Preferably, if no write instruction is received before the read instruction, the required data is directly read from a corresponding address to complete a read operation; the read data is output to the parsing module and parsed into the I80 signal which is output to the MCU.

[0034] Preferably, the display parameter adjustment instruction comprises a contrast adjustment instruction.

[0035] Preferably, the display parameter adjustment instruction further comprises a brightness adjustment instruction.

[0036] The application discloses a liquid crystal display control device based on FPGA, which has the following beneficial effects: the liquid crystal display control device based on FPGA comprises an MCU, an FPGA control system, a HyperRAM and an LCD display; the FPGA control system comprises an analysis module, an arbitration module, a cache module, a HyperRAM control module, an adjustment module and an output control module; the MCU is electrically connected with the analysis module; the analysis module is electrically connected with the arbitration module and the cache module respectively; the arbitration module is electrically connected with the adjustment module and the cache module respectively; the cache module is electrically connected with the HyperRAM control module and the output control module respectively; the HyperRAM control module is electrically connected with the HyperRAM; and the output control module is electrically connected with the LCD display. The application reserves the control of the MCU, adds FPGA processing, and analyzes the I80 signal of the MCU into an RGB signal. Therefore, the application can improve the refreshing speed of the LCD display, improve the flexibility of display, facilitate image processing, and meet the basic development requirements of a large display screen. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the present application will be further described below with reference to the drawings and embodiments. The drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings:

[0038] Figure 1 is a structure schematic view of a liquid crystal display control device based on FPGA according to the preferred embodiment of the present application;

[0039] Figure 2 is a flow schematic view of a liquid crystal display control method based on FPGA according to the preferred embodiment of the present application;

[0040] Figure 3 is a flow schematic view of the analysis module 21 analyzing the control instruction of the MCU 1 and realizing the mutual conversion of the I80 signal and the RGB signal according to the preferred embodiment of the present application;

[0041] Figure 4 is a write timing schematic view of the mutual conversion of the I80 signal and the RGB signal according to the preferred embodiment of the present application;

[0042] Figure 5 is a read timing schematic view of the mutual conversion of the I80 signal and the RGB signal according to the preferred embodiment of the present application. DETAILED DESCRIPTION

[0043] The core of the present application is to provide a kind of FPGA-based liquid crystal display control device and control method, in the present application, the control of MCU is reserved, FPGA processing is added, I80 signal of MCU is parsed as RGB signal, the refreshing speed of LCD screen is improved and the flexibility of display is improved, image processing is facilitated, and the basic development needs of large display screen are met.

[0044] To make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the scope of protection of the present application.

[0045] Please refer to Figure 1 , Figure 1 A structure schematic diagram of a FPGA-based liquid crystal display control device provided by the present application, comprising MCU 1, FPGA control system 2, HyperRAM 3 and LCD display 4;

[0046] The FPGA control system 2 comprises a parsing module 21, an arbitration module 22, a cache module 23, a HyperRAM control module 24, an adjustment module 25 and an output control module 26;

[0047] The MCU 1 is electrically connected with the parsing module 21, the parsing module 21 is electrically connected with the arbitration module 22 and the cache module 23 respectively, the arbitration module 22 is electrically connected with the adjustment module 25 and the cache module 23 respectively, and the cache module 23 is electrically connected with the HyperRAM control module 24 and the output control module 26 respectively;

[0048] The HyperRAM control module 24 is electrically connected with the HyperRAM, and the output control module 26 is electrically connected with the LCD display 4.

[0049] In the prior art, a common LCD controller can convert MCU interface into RGB interface. However, when applied in a special field, only converting MCU interface into RGB interface cannot meet the requirements.

[0050] In view of the above shortcomings, the MCU 1, the FPGA control system 2, the HyperRAM and the LCD display 4 are cooperated in the present application to improve the refreshing speed of the LCD display 4 and the flexibility of display.

[0051] Specifically, in the embodiment, the parsing module 21 is used for parsing the control instruction of the MCU and realizing mutual conversion of the I80 signal and the RGB signal; the cache module 23 is used for temporarily storing the RGB signal, the control instruction and a data address; the arbitration module 22 is used for keeping the I80 bus in an idle state after completing a read or write operation; the MCU 1 is used for sending a display parameter adjustment instruction and transmitting the display parameter adjustment instruction to the arbitration module 22; the arbitration module 22 is used for adjusting the data format of the RGB signal after receiving the display parameter adjustment instruction and sending an instruction signal to the adjustment module 25; the adjustment module is used for obtaining the data of the RGB signal from the cache module 23 and adjusting the display parameter according to the instruction signal of the arbitration module 22; and the output control module 26 is used for outputting the RGB signal after the display parameter is adjusted to the LCD display. Therefore, the application can realize conversion of the I80 signal and the RGB signal, directly write the RGB signal into the LCD display screen after the data of the RGB signal is processed, and improve the refreshing speed of the LCD screen and the display flexibility.

[0052] In conclusion, the application provides a liquid crystal display control device based on FPGA, in which an MCU 1, an FPGA control system 2, a HyperRAM and an LCD display 4 are provided; the FPGA control system 2 comprises a parsing module 21, an arbitration module 22, a cache module 23, a HyperRAM control module 24, an adjustment module 25 and an output control module 26; the MCU 1 is electrically connected with the parsing module 21; the parsing module 21 is electrically connected with the arbitration module 22 and the cache module 23 respectively; the arbitration module 22 is electrically connected with the adjustment module 25 and the cache module 23 respectively; the cache module 23 is electrically connected with the HyperRAM control module 24 and the output control module 26 respectively; the HyperRAM control module 24 is electrically connected with the HyperRAM; and the output control module 26 is electrically connected with the LCD display 4. Therefore, the application can improve the refreshing speed of the LCD display 4, improve the display flexibility, facilitate image processing and meet the basic development requirements of large display screens.

[0053] On the basis of the above embodiment:

[0054] Please refer to Figure 2 , Figure 2 a flowchart of a liquid crystal display control method based on FPGA provided by the application.

[0055] The application further provides a liquid crystal display control method based on FPGA, which is applied to the liquid crystal display control device based on FPGA and comprises the following steps:

[0056] S1, control the parsing module 21 to parse the MCU1 control instruction, and realize the mutual conversion of I 80 signal and RGB signal;

[0057] S2, control the cache module 23 to temporarily store the RGB signal, the control instruction and data address;

[0058] S3, control the arbitration module 22 to complete a read or write operation, so that the I 80 bus remains idle state;

[0059] S4, receiving the MCU1 issued display parameter adjustment instruction, and transmitting to the arbitration module 22;

[0060] S5, control the arbitration module 22 to receive the display parameter adjustment instruction to adjust the data format of the RGB signal, and send an indication signal to the adjustment module 25;

[0061] S6, control the adjustment module 25 to obtain the data of the RGB signal from the cache module 23, and adjust the display parameter according to the indication signal of the arbitration module 22;

[0062] S7, through the output control module 26, output the RGB signal after adjusting the display parameter to the LCD display 4.

[0063] Please refer to Figure 3 , Figure 3 A control method for parsing the MCU1 control instruction and realizing the mutual conversion of I 80 signal and RGB signal is provided for the application.

[0064] As a preferred embodiment, the control method for parsing the MCU1 control instruction and realizing the mutual conversion of I 80 signal and RGB signal comprises:

[0065] S11, when the control instruction is write signal, the I 80 signal is parsed into the RGB signal and written into the cache module 23;

[0066] S12, when the control instruction is read signal, the RGB signal is read out from the cache module 23;

[0067] S13, the RGB signal is converted into the I 80 signal and sent to the MCU1.

[0068] Please refer to Figure 4 , Figure 4 A write timing diagram for the mutual conversion of I 80 signal and RGB signal is provided for the application.

[0069] Please refer toFigure 5 , Figure 5 A read timing for converting I 80 signal and RGB signal is provided.

[0070] Specifically, in the embodiment, when parsing I 80 signal, according to I 80 bus standard proposed by Intel, data is transmitted to FPGA receiver by four control pins and eight data pins, as shown in Figure 4 , the four control pins are CS (chip select signal), RS (D / C data / instruction selection line, set to 1 for writing data, set to 0 for writing command), WR (0 indicates writing data), and RD (0 indicates reading data), and the eight data pins are D0-D7.

[0071] Specifically, in the embodiment, FPGA receives four control signals and eight data signals from MCU, when the chip select signal is low, it indicates that the signal starts to be received, when RS is 0 and WR is 0, it indicates that the write command is received, at this time, eight data is received, and the content of the write data is determined according to the different values of the eight data, and the specific data format is shown in Table 1:

[0072]

[0073] Table 1

[0074] In Table 1, CS is a chip select signal; RS is a port selection signal, connected to an address line; WR is a write signal; RD is a read signal; DATA[7:0] is a data line; wherein RS is used to select the port number, RS equal to 0 selects the command port, and RS equal to 1 selects the data port.

[0075] Specifically, when RS is 1 and WR is 0, it indicates that the data is written, at this time, the eight data received is in RGB232 format, when RS is 1 and RD is 0, it indicates that the data in the register starts to be read out and returned to MCU, and the read-write timing is as shown in Figure 4 and Figure 5 , thereby completing the conversion of I 80 signal to RGB signal.

[0076] As a preferred embodiment, the control of the arbitration module 22 to complete a read or write operation, so that the I 80 bus remains idle state includes:

[0077] When the arbitration module 22 receives a write instruction;

[0078] If the write instruction is followed by a read instruction, the arbitration module 22 instructs the HyperRAM control module 24 to read the data at the position to be written;

[0079] The data of the position to be written is stored in the cache module 23, and the written data is written to the corresponding address;

[0080] The read data is written in the mirror address, and the data in the mirror address is read when a read instruction comes.

[0081] As a preferred embodiment, if no read instruction follows the write instruction, the data is directly written to the corresponding address, completing a write operation.

[0082] As a preferred embodiment, the control of the arbitration module 22 to complete a read or write operation, so that the I80 bus remains idle, also includes:

[0083] When the arbitration module 22 receives a read instruction;

[0084] If the read instruction is preceded by the write instruction, the arbitration module 22 instructs the HyperRAM control module 24 to read data from the mirror address;

[0085] A flag bit is set when reading and writing, the flag bit is 0 when receiving a write instruction, and the flag bit is 1 when receiving a read instruction;

[0086] The working state before reading and writing is determined by detecting the flag bit.

[0087] As a preferred embodiment, if no write instruction is received before the read instruction, the required data is directly read from the corresponding address, completing a read operation; the read data is output to the parsing module 21 and parsed into the I80 signal output to the MCU1.

[0088] As a preferred embodiment, the display parameter adjustment instruction includes a contrast adjustment instruction.

[0089] As a preferred embodiment, the display parameter adjustment instruction also includes a brightness adjustment instruction.

[0090] Specifically, in this embodiment, when the arbitration module 22 receives a contrast adjustment instruction, the RGB 232 format is first converted to the RBG 888 format, and the data format is agreed as follows: D7(R2, high bit of red), D6(R1), D5(R0, low bit of red), D4(G2, high bit of green), D3(G1), D2(G0, low bit of green), D1(B1, high bit of blue), D1(B0, low bit of blue); The arbitration module 22 will send a signal to the adjustment module 25, and the adjustment module 25 will obtain the RGB data from the cache module 23 and adjust the contrast gradient value according to the instruction of the arbitration module 22.

[0091] Specifically, the gradient value is set to 64 levels, the contrast range is -31-31, the parameter setting range in programming is 0-63, wherein 0-31 represents negative numbers, 32-63 represents positive numbers, the initialization level is 32 levels, which is the best contrast, and the specific level is determined by the instruction input by the front-end MCU. The gradient value is processed on the RGB data through the contrast adjustment algorithm, and the specific algorithm is as follows:

[0092] Referring to the Photoshop contrast algorithm. When the contrast range is set to -255-255, the following formula is used to represent:

[0093] nRGB=RGB+(RGB-Threshold)*Contrast / 255; (1)

[0094] In the formula, nRGB represents the new R, G, and B components of the image pixel, RGB represents the R, G, and B components of the image pixel, Threshold is a given threshold, and Contrast is the processed contrast increment. The Photoshop contrast increment is processed according to the positive and negative of the given value respectively:

[0095] When the increment is equal to -255, it is the lower limit of the image contrast, at this time, the RGB components of the image are equal to the threshold, the image is all gray, and there is only one line on the gray scale image, which is the threshold gray scale;

[0096] When the increment is greater than -255 and less than 0, the image pixel components are calculated directly using the above formula;

[0097] When the increment is equal to 255, it is the upper limit of the image contrast, which is equal to setting the image threshold, and the image is composed of up to eight colors, and there are up to 8 lines on the gray scale image, which are red, yellow, green, cyan, blue, purple, and black and white;

[0098] When the increment is greater than 0 and less than 255, then the increment is processed according to the following formula (2) first, and then the contrast is calculated according to the above formula (1):

[0099] nContrast=255*255 / (255-Contrast)-255; (2)

[0100] In the formula, nContrast is the processed contrast increment, and Contrast is the given contrast increment.

[0101] The present application refers to the above algorithm, sets the contrast range to -31-31, applies the above algorithm to calculate and process the RGB signal, and outputs the processed RGB data to the output control module 26 for output.

[0102] Specifically, in the embodiment, when the arbitration module 22 receives the brightness adjustment instruction, the arbitration module 22 will send a signal to the adjustment module 25 to adjust the duty cycle of the PWM according to the brightness gradient value.

[0103] Specifically, the brightness gradient value is set to 8 levels, and level 1 is the darkest and level 8 is the brightest. A 50MHz crystal clock is input externally to the FPGA, and the Gowin software internal IP core rPLL is called to divide the frequency of the crystal clock to generate a 30KHz clock. A counter is set, and there are a total of 1000 counts at a frequency of 30KHz. The PWM is initialized to 1. When the brightness is level 1, the counter counts from 0 to 125, and the PWM is 0. The counter counts from 125 to 1000, and the PWM is 1. Thus, a PWM signal with a duty cycle of 12.5% is formed. By changing the proportion of high and low levels in a period, the brightness of the LED lamp is controlled, and then output to the output control module 26.

[0104] Specifically, the output control module 26 generates Vsync, Hsync and DE signals, converts 8-bit RGB data to 24-bit RGB data, and uses the Gowin software internal IP core FIFO (First-In First-Out queue) to input the data into the FIFO for caching. The DE signal is used as the enable signal for reading data from the FIFO, and the cached data in the FIFO is read out when the DE signal is detected. Thus, the data timing is adjusted to align with the synchronization signal, and then output to the LCD display 4. At the same time, the PWM signal is output to the LCD display 4 to adjust the brightness of the backlight. It can be understood that in the embodiment, the PWM signal is output to the LCD screen through the pin LED_PWM. In a period, the greater the proportion of low level of the PWM, the brighter the luminous intensity.

[0105] For the liquid crystal display control device based on FPGA provided in the application, please refer to the above embodiment, which will not be described here.

[0106] It should be noted that in the present specification, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or equipment comprising the element.

[0107] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and that the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A liquid crystal display control device based on FPGA, characterized in that, This includes an MCU, an FPGA control system, HyperRAM, and an LCD display. The FPGA control system includes a parsing module, an arbitration module, a cache module, a HyperRAM control module, an adjustment module, and an output control module. The MCU is electrically connected to the parsing module, the parsing module is electrically connected to the arbitration module and the cache module respectively, the arbitration module is electrically connected to the adjustment module and the cache module respectively, and the cache module is electrically connected to the HyperRAM control module and the output control module respectively. The HyperRAM control module is electrically connected to the HyperRAM, and the output control module is electrically connected to the LCD display. The parsing module is used to parse the control commands of the MCU and to convert between I80 signals and RGB signals, including: When the control command is a write signal, the I80 signal is parsed into the RGB signal and written into the cache module; When the control command is a read signal, the RGB signal is read from the cache module; The RGB signal is converted into the I80 signal and sent to the MCU; The arbitration module is used to keep the I80 bus idle after completing a read or write operation, including: When the arbitration module receives a write command; If a write instruction is immediately followed by a read instruction, the arbitration module instructs the HyperRAM control module to read the data at the location to be written. The data to be written is stored in the cache module, and then the data to be written is written to the corresponding address; The read data is written into the mirror address, and the data in the mirror address is read out when the read instruction arrives. The adjustment module is used to obtain the RGB signal data from the cache module and adjust the display parameters according to the indication signal of the arbitration module; The output control module outputs an RGB signal with adjusted display parameters to the LCD display.

2. The FPGA-based liquid crystal display control device according to claim 1, characterized in that, If no read instruction follows the write instruction, data is written directly to the corresponding address to complete one write operation.

3. The FPGA-based liquid crystal display control device according to claim 2, characterized in that, The step of controlling the arbitration module to keep the I80 bus idle after completing a read or write operation also includes: When the arbitration module receives a read command; If the read instruction was previously received by the write instruction, the arbitration module instructs the HyperRAM control module to read data from the mirror address; A flag is set during read and write operations. When a write command is received, the flag is set to 0, and when a read command is received, the flag is set to 1. The working state before reading and writing is determined by detecting the flag bits.

4. The FPGA-based liquid crystal display control device according to claim 3, characterized in that, If no write instruction has been received before the read instruction, the required data is read directly from the corresponding address to complete a read operation; the read data is output to the parsing module and parsed into the I80 signal, which is then output to the MCU.

5. The FPGA-based liquid crystal display control device according to claim 1, characterized in that, The display parameter adjustment commands include contrast adjustment commands.

6. The FPGA-based liquid crystal display control device according to claim 1, characterized in that, The display parameter adjustment commands also include brightness adjustment commands.

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