A composite field-limiting ring circular layout lateral power device and a preparation method thereof

Abstract

The application discloses a kind of composite field limiting ring circular layout lateral power devices and preparation method, including substrate, buried oxygen layer, active layer, composite field limiting ring, source metal, gate metal and drain metal;The cross section of lateral power device is circular or oval, and the active layer includes semiconductor drain region, drift region and semiconductor well region arranged coaxially from inside to outside;Composite field limiting ring has at least two, with the center of semiconductor drain region as the center, and is embedded in the top surface of drift region equidistantly;Each composite field limiting ring includes P-type region and dielectric region;P-type region surrounds the two sides and bottom surface of dielectric region.The high-K dielectric material of composite field limiting ring in the application can effectively modulate surface electric field to avoid the influence of surface charge on field limiting ring, thereby improving breakdown voltage;Meanwhile, the doping concentration of drift region is improved, and the on-resistance of device is reduced.In addition, gate dielectric, field dielectric and the dielectric in composite field limiting ring use the same dielectric material, which reduces the process difficulty.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor power devices, in particular to a composite field limiting ring circular layout lateral power device and a preparation method thereof. BACKGROUND

[0002] As an important component of power integrated circuits, lateral power devices are widely used in the fields of communication electronics, automotive electronics, smart furniture, etc. due to their small size, easy integration, high breakdown voltage, low on-resistance, superior conversion performance, and good process compatibility. One of the goals of device design is to reduce the on-resistance and other electrical characteristics of lateral power devices. The field limiting ring termination technology has achieved remarkable results in reducing the specific on-resistance by deforming the field limiting ring of the termination structure. The basic principle is that under the action of the reverse bias voltage of the main junction, the depletion region of the main junction will meet and overlap with the depletion region of the field limiting ring before the voltage reaches the breakdown voltage of the main junction. At this time, the two are in a punch-through state, which raises the field limiting ring point. In this case, the field limiting ring acts as a voltage divider when the voltage of the main junction is increased, thereby achieving the purpose of increasing the breakdown voltage.

[0003] However, the traditional field limiting ring structure needs to gradually reduce the width of the field limiting ring from the main junction outward and gradually increase the spacing. Moreover, the field limiting ring structure is very sensitive to surface charge effects, especially the field limiting ring structure of a shallow planar junction, which can cause the breakdown voltage of the device to decrease and even cause the device to fail due to the influence of the surface electric field.

[0004] In addition, in order to keep the field limiting ring at a certain distance from the surface of the drift region, the implantation depth of impurities needs to be controlled by ion implantation, which not only causes damage to the area between the field limiting ring and the surface of the drift region, but also poses a challenge in controlling the distribution of impurities. SUMMARY

[0005] The technical problem to be solved by the present application is to overcome the shortcomings of the prior art. The composite field limiting ring circular layout lateral power device and the preparation method thereof can improve the doping concentration of the drift region, reduce the on-resistance of the device, and improve the breakdown voltage. At the same time, the influence of surface charge effects on the field limiting ring is overcome by high-k dielectric, and the influence of the electric field concentration effect of the main junction on the breakdown voltage is solved by the composite field limiting ring.

[0006] To solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0007] A composite field limiting ring circular layout lateral power device comprises a substrate, a buried oxygen layer, an active layer, a composite field limiting ring, a source metal, a gate metal, and a drain metal.

[0008] The cross section of the lateral power device is circular or elliptical, and the substrate, the buried oxygen layer and the active layer are sequentially arranged from bottom to top.

[0009] The active layer comprises a semiconductor drain region, a drift region and a semiconductor well region which are coaxially arranged from inside to outside.

[0010] The semiconductor drain region is arranged at the top center of the active layer and is in a cylindrical shape, and the drain metal is arranged at the top center of the semiconductor drain region.

[0011] The source metal is arranged at the top outer edge of the semiconductor well region.

[0012] The gate metal is arranged on the top surface of the active layer adjacent to the source metal through the gate dielectric layer.

[0013] The composite field limiting ring has M composite field limiting rings which are embedded in the top surface of the drift region at equal distances with the center of the semiconductor drain region as the center.

[0014] Each composite field limiting ring comprises a P-type region and a dielectric region; the P-type region is arranged on both sides and the bottom surface of the dielectric region.

[0015] The depth of the P-type region in the composite field limiting ring is 0.1-1 microns; when the thickness of the active layer is less than 2 microns, the depth of the P-type region is half of the thickness of the active layer.

[0016] The semiconductor well region comprises a semiconductor contact region and a semiconductor source region; the semiconductor contact region is located directly below the source metal and is in a ring shape, and the ring width of the semiconductor contact region is less than the ring width of the source metal; the semiconductor source region is in a ring shape and is in contact with the inner wall of the semiconductor contact region.

[0017] The number M of the composite field limiting rings is selected according to the width of the drift region, and M≥2; when the width of the drift region increases by 4-5 microns, one composite field limiting ring needs to be added.

[0018] The ring width of the P-type region and the ring width of the dielectric region in each composite field limiting ring change synchronously.

[0019] The ring width of the dielectric region in each composite field limiting ring is equal, or the ring width of the dielectric region in each composite field limiting ring gradually increases from the source metal to the drain metal.

[0020] The top surface of the active region between the source metal and the drain metal is provided with a field dielectric layer, wherein the field dielectric layer located directly below the gate metal is formed as the gate dielectric layer; the field dielectric layer, the gate dielectric layer and the dielectric region in each composite field limiting ring are the same high-K dielectric.

[0021] A preparation method of a composite field limiting ring circular layout lateral power device, comprising the following steps.

[0022] Step 1, making an active layer: sequentially arranging a buried oxygen layer and an active layer on a substrate; wherein the buried oxygen layer is used for electrical isolation between the active layer and the substrate;

[0023] Step 2, etching a ring-shaped groove: etching M concentric and equidistant ring-shaped grooves on the top surface of the active layer;

[0024] Step 3, making a P-type region: using photoresist as a mask, boron ions are implanted in each ring-shaped groove by an ion implantation process to form a P-type region with a concave cross-section.

[0025] Step 4, making a semiconductor well region: using photoresist as a mask, low-concentration P-type semiconductor impurities are implanted on the top surface of the active layer outside the outermost P-type region by an ion implantation process to form a semiconductor well region in communication with the buried oxygen layer.

[0026] Step 5, making a semiconductor contact region: using photoresist as a mask, high-doped P-type semiconductor impurities are implanted on the top surface of the outer edge of the semiconductor well region by an ion implantation process to form a semiconductor contact region.

[0027] Step 6, making a semiconductor source region and a semiconductor drain region: using photoresist as a mask, high-doped phosphorus ions are implanted in the middle ring-shaped region on the top surface of the semiconductor well region and the center of the top surface of the active layer by an ion implantation process to form a semiconductor source region and a semiconductor drain region.

[0028] Step 7, annealing to promote diffusion to form a predetermined impurity distribution;

[0029] Step 8, depositing dielectric material: depositing dielectric material in each P-type region and on the top surface of the active layer formed in step 3, wherein the dielectric material deposited in each P-type region forms a dielectric region; the dielectric region and the corresponding P-type region together form a composite field limiting ring; the dielectric material deposited on the top surface of the active layer forms a field dielectric layer.

[0030] Step 9, etching source and drain contact holes: the source and drain contact holes include source contact holes and drain metal holes; the source contact holes are etched on the outer edge of the field dielectric layer, and the drain metal holes are etched in the field dielectric layer directly above the semiconductor drain region.

[0031] Step 10, depositing source metal, drain metal and gate metal: depositing source metal in the source contact hole, depositing drain metal in the drain metal hole, and depositing gate metal on the top surface of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the drift region; wherein the field dielectric below the gate metal forms a gate dielectric layer.

[0032] The ring-shaped groove in step 2 is etched by a dry etching process.

[0033] The number of annular grooves in step 2 is selected according to the width of the drift region, and is not less than 2; when the width of the drift region increases by 4-5 microns, one annular groove is added.

[0034] The present application has the following beneficial effects:

[0035] 1. The present application can improve the doping concentration of the drift region, reduce the on-resistance of the device, and improve the breakdown voltage.

[0036] 2. In the present application, the P-type region of the composite field limiting ring can be depleted with the N-type drift region to improve the drift region concentration, and the high-k dielectric can further assist in depleting the drift region to modulate the surface electric field to solve the adverse effects of surface charge on the field limiting ring, thereby reducing the on-resistance of the device and improving the breakdown voltage of the device.

[0037] 3. The composite field limiting ring in the present application can greatly reduce the difficulty of process design when using equal spacing and equal width, and can be realized by only conventional processes such as grooving, ion implantation, and dielectric deposition.

[0038] 4. In the present application, the same dielectric material is used for the gate dielectric, the field dielectric, and the dielectric in the composite field limiting ring, which reduces the process difficulty. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A structure diagram of a composite field limiting ring circular layout lateral power device of the present application is shown.

[0040] Figure 2 A structure diagram of an active layer prepared in step 1 of the present application is shown.

[0041] Figure 3 A structure diagram of an annular groove after etching in step 2 of the present application is shown.

[0042] Figure 4 A structure diagram of a P-type region prepared in step 3 of the present application is shown.

[0043] Figure 5 A structure diagram of a semiconductor well region prepared in step 4 of the present application is shown.

[0044] Figure 6 A structure diagram of a semiconductor contact region prepared in step 5 of the present application is shown.

[0045] Figure 7 A structure diagram of a semiconductor source region and a semiconductor drain region prepared in step 6 of the present application is shown.

[0046] Figure 8 An A-A' cross-sectional view of the step 7 of depositing dielectric material in the present application is shown.

[0047] Figure 9 Figure 1 shows a schematic view of the cross-section of the composite field-limiting-ring circular layout lateral power device according to the present application.

[0048] Figure 10 Figure 2 shows a comparison of the breakdown voltage and specific on-resistance of the composite field-limiting-ring circular layout lateral power device according to the present application and the conventional lateral power device as a function of the drift region doping concentration.

[0049] Figure 11 Figure 3 shows a simulated potential distribution diagram of the composite field-limiting-ring circular layout lateral power device according to the present application.

[0050] Figure 1 shows a schematic view of the composite field-limiting-ring circular layout lateral power device according to the present application, which comprises: 1, a substrate; 2, a buried oxygen layer; 3, an active layer; 4, a ring-shaped groove; 5, a semiconductor contact region; 6, a semiconductor source region; 7, a semiconductor well region; 8, a semiconductor drain region; 9, a P-type region; 10, a gate electrode; 11, a gate dielectric layer; 12, a source metal; 13, a drain metal; and 14, a gate metal.

[0051] 101-104, high-k dielectric,

[0052] 11, a gate dielectric layer; 12, a source metal; 13, a drain metal; and 14, a gate metal. DETAILED DESCRIPTION

[0053] The present application will be further described below in conjunction with the drawings and specific preferred embodiments.

[0054] In the description of the present application, it should be understood that the terms "left side", "right side", "upper part", "lower part", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and "first", "second", and the like do not represent the importance of the parts, and therefore cannot be understood as limiting the present application. The specific dimensions used in the embodiments are only for the purpose of illustrating the technical solutions and do not limit the protection scope of the present application.

[0055] As shown in Figures 1 and 2, a composite field-limiting-ring circular layout lateral power device comprises a substrate 1, a buried oxygen layer 2, an active layer 3, a composite field-limiting ring, a source metal 12, a gate metal 14, and a drain metal 13. Figure 1 and Figure 9 As shown in Figures 1 and 2, a composite field-limiting-ring circular layout lateral power device comprises a substrate 1, a buried oxygen layer 2, an active layer 3, a composite field-limiting ring, a source metal 12, a gate metal 14, and a drain metal 13.

[0056] The cross-section of the lateral power device is circular or elliptical, and the substrate, the buried oxygen layer, and the active layer are arranged in order from bottom to top.

[0057] The active layer comprises a semiconductor drain region 8, a drift region, and a semiconductor well region 7 arranged coaxially from inside to outside.

[0058] The semiconductor drain region is arranged at the center of the top of the active layer and has a cylindrical shape. A drain metal is arranged at the center of the top of the semiconductor drain region. The radius of the semiconductor drain region is preferably greater than the radius of the drain metal.

[0059] The source metal is arranged at the outer edge of the top of the semiconductor well region. The gate metal is arranged on the top surface of the active layer adjacent to the source metal through the gate dielectric layer 11.

[0060] The semiconductor well region includes a semiconductor contact region 5 and a semiconductor source region 6.

[0061] The semiconductor contact region is arranged directly below the source metal and has a ring shape. The ring width of the semiconductor contact region is smaller than the ring width of the source metal. The semiconductor source region is in contact with the inner wall of the semiconductor contact region and has a ring shape. The semiconductor source region is partially arranged below the source metal.

[0062] The semiconductor contact region is used to eliminate the parasitic transistor effect. The semiconductor source region is used to collect the electrons flowing from the channel formed below the gate dielectric. The gate metal is below the gate dielectric layer and covers the semiconductor well region formed by double diffusion. When the gate voltage is greater than the threshold voltage, a channel is formed on the surface of the semiconductor well region, and the device is turned on. The drain metal electrode is below the highly doped N-type semiconductor region, also known as the semiconductor drain region. The semiconductor drain region and the semiconductor well region are separated by an N-type drift region.

[0063] The composite field limiting ring has M rings with the center of the semiconductor drain region as the center and is embedded in the top surface of the drift region at equal distances. The number M of the composite field limiting ring is selected according to the width of the drift region, and M≥2. When the width of the drift region increases by 4-5 microns, one composite field limiting ring needs to be added.

[0064] Each composite field limiting ring includes a P-type region 9 and a dielectric region 101-104. The P-type region surrounds the two sides and the bottom surface of the dielectric region and is symmetric about the dielectric region.

[0065] The depth of the P-type region in the composite field limiting ring is preferably 0.1-1 microns. If the depth of the P-type region is too shallow, ion implantation is not easy to control. If the depth of the P-type region is too deep, the groove etching and filling process is difficult to implement. Therefore, when the thickness of the active layer is less than 2 microns, the depth of the P-type region is preferably half of the thickness of the active layer.

[0066] The ring width of the P-type region and the ring width of the dielectric region in each composite field limiting ring can change synchronously.

[0067] When the ring width of the dielectric region in each composite field limiting ring is equal, the ring width of the P-type region in each composite field limiting ring is also equal.

[0068] As the ring width of the dielectric region in each composite field limiting ring gradually increases from the source metal to the drain metal, the ring width of the P-type region in each composite field limiting ring will also change synchronously with the ring width of the corresponding P-type region.

[0069] Furthermore, a field dielectric layer is disposed on the top surface of the active region between the source metal and the drain metal, wherein the field dielectric layer located directly below the gate metal is formed as the gate dielectric layer; the field dielectric layer, the gate dielectric layer, and the dielectric region in each composite field limiting ring are all the same high-k dielectric. Here, high-k dielectric refers to a dielectric material with a higher dielectric constant than silicon dioxide, preferably a dielectric constant greater than 20.

[0070] A method for fabricating a circular layout lateral power device with a composite field-limiting ring includes the following steps.

[0071] Step 1: Create the active layer: such as Figure 2 As shown, a buried oxide layer and an active layer are sequentially disposed on the substrate; wherein, the buried oxide layer is used for electrical isolation between the active layer and the substrate.

[0072] The active layer described above is a substrate with a low concentration of boron ions. The substrate material can also be a wide bandgap semiconductor material such as silicon, silicon carbide, gallium nitride, or gallium oxide.

[0073] Step 2: Etching annular grooves: M concentric and equally spaced annular grooves are preferably etched on the top surface of the active layer using a dry etching process. The etching depth of each annular groove is preferably half the thickness of the active layer, and the spacing between each groove is controlled to be the same. The structure after forming the annular grooves is as follows. Figure 3 As shown. The dry etching process is used because of its high processing precision, easier control of etching depth compared to wet etching, and better etching anisotropy.

[0074] Furthermore, the number of the aforementioned annular grooves is selected based on the width of the drift region, and shall not be less than two; when the width of the drift region increases by 4-5 micrometers, one additional annular groove is required.

[0075] Step 3: Fabrication of the P-type region: Using photoresist as a mask, boron ions are implanted into each annular groove using an ion implantation process to form a P-type region 9 with a concave cross-section, as shown in the figure below. Figure 4 As shown. The concentration in the P-type region is 1 × 10⁻⁶. 15 cm -3 Up to 5×10 17 cm -3 .

[0076] Step 4: Fabrication of the semiconductor well region: Using ion implantation technology and photoresist as a mask, a low concentration of P-type semiconductor impurities is implanted onto the top surface of the active layer outside the outermost P-type region to form a semiconductor well region connected to the buried oxide layer. Specifically, as shown below... Figure 5as shown.

[0077] Step 5, making semiconductor contact region: using photoresist as mask, high-doped P-type semiconductor impurity is implanted into the top surface of the outer edge of the semiconductor well region by ion implantation process to form semiconductor contact region, as shown in 6; wherein the concentration of P-type semiconductor impurity is not less than 1x1019cm-3. 19 cm -3 .

[0078] Step 6, making semiconductor source region and semiconductor drain region: using photoresist as mask, high-doped phosphorus ions are implanted into the top surface of the middle annular region of the semiconductor well region and the center of the active layer top surface by ion implantation process to form semiconductor source region and semiconductor drain region; wherein the concentration of phosphorus ions is not less than 1x1019cm-3. 20 cm -3 .

[0079] Step 7, annealing: using annealing process to repair ion implantation damage, and only one annealing process is used to promote ion diffusion to form the established impurity distribution, as shown in Figure 7 .

[0080] Step 8, depositing dielectric material: in each P-type region and the top surface of the active layer made in step 2, dielectric material is deposited by RF magnetron sputtering deposition process, wherein the dielectric material deposited in the groove of each P-type region forms dielectric region; the dielectric region and the corresponding P-type region jointly constitute a composite field limiting ring; the dielectric material deposited on the top surface of the active layer forms gate dielectric layer, as shown in Figure 8 .

[0081] The above high-K dielectric material can be silicon dioxide but is not limited thereto, which can modulate the surface electric field to solve the adverse effects of surface charge effect on the composite field limiting ring, thereby improving the breakdown voltage and reducing the on-resistance of the device.

[0082] The gate dielectric material of the traditional device adopts silicon dioxide because it can form a very ideal silicon interface with the silicon substrate. In the present embodiment, a part of the high-k dielectric retained after magnetron deposition is selected as the dielectric layer, without generating a silicon dioxide gate dielectric layer, thereby saving process steps.

[0083] Step 9, etching source and drain contact holes: the source and drain contact holes include source contact hole and drain metal hole; the source contact hole is etched in the outer edge of the field dielectric layer, and the drain metal hole is etched in the field dielectric layer directly above the semiconductor drain region.

[0084] Step 10, depositing source metal, drain metal and gate metal: depositing source metal in the source contact hole, depositing drain metal in the drain metal hole, and depositing gate metal on the top surface of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the drift region, as shown in Figure 9As shown; wherein, the field dielectric below the gate metal is formed as a gate dielectric layer.

[0085] Figure 10 This diagram shows a comparison of the breakdown voltage as a function of drift region doping concentration for a circularly patterned lateral power device with a composite field-limiting ring (composite field-limiting ring device), a conventional lateral power device without a field-limiting ring (conventional device), and a lateral power device with only a P-type field-limiting ring (conventional field-limiting ring device). The P-type region concentration for both the composite field-limiting ring device and the conventional field-limiting ring device is 8 × 10⁻⁶. 16 cm -3 The dielectric constant of the dielectric in the composite field-limiting ring is 200, while other structural parameters remain consistent across the three devices. Figure 10 It can be seen that the maximum breakdown voltage (BV) of the composite field-limiting device is 26% higher than that of the other two devices. Furthermore, the drift region concentration corresponding to the maximum breakdown voltage is also the highest, thus exhibiting a lower on-resistance (R0). on,sp When the device reaches its maximum breakdown voltage, the figure of merit (FOM) of the composite field limiting ring device provided by this invention can be improved by more than double.

[0086] Figure 11 The figure shows the simulated potential line distribution of the circular layout lateral power device with composite field-limiting ring provided by this invention. As can be seen from the figure, the electric field strength of the device is strongest near the drain region and semiconductor well region, and weakest at the composite field-limiting ring. This indicates that the device can effectively exhaust the electric field in the drift region, optimize the surface electric field, prevent premature breakdown, thereby optimizing the device's breakdown voltage and improving its breakdown voltage. Figure 11 In the diagram, the horizontal axis represents the horizontal distance, and the vertical axis represents the vertical distance.

[0087] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A composite field-limiting-ring circular-geometry lateral power device, characterized by: The lateral power device comprises a substrate, a buried oxygen layer, an active layer, a composite field limiting ring, a source metal, a gate metal and a drain metal; The cross section of the lateral power device is circular or elliptical, and the substrate, the buried oxygen layer and the active layer are sequentially arranged from bottom to top; The active layer comprises a semiconductor drain region, a drift region and a semiconductor well region which are coaxially arranged from inside to outside; The semiconductor drain region is arranged at the top center of the active layer and is in a cylindrical shape, and the drain metal is arranged at the top center of the semiconductor drain region; The source metal is arranged at the top outer edge of the semiconductor well region; The gate metal is arranged on the top surface of the active layer adjacent to the source metal through a gate dielectric layer; The composite field limiting ring has M composite field limiting rings which are inlaid in the top surface of the drift region at equal intervals with the center of the semiconductor drain region as the center; Each composite field limiting ring comprises a P-type region and a dielectric region; the P-type region is arranged on both sides and the bottom surface of the dielectric region; the dielectric region is high-K dielectric, and the dielectric constant of the high-K dielectric is 200; The depth of the P-type region in the composite field limiting ring is 0.1-1 microns; when the thickness of the active layer is less than 2 microns, the depth of the P-type region is half of the thickness of the active layer; The number M of the composite field limiting ring is selected according to the width of the drift region, and M≥2; when the width of the drift region increases by 4-5 microns, one composite field limiting ring needs to be added; The annular width of the dielectric region in each composite field limiting ring is equal, or the annular width of the dielectric region in each composite field limiting ring gradually increases from the source metal to the drain metal; The top surface of the active region between the source metal and the drain metal is provided with a field dielectric layer, wherein the field dielectric layer directly below the gate metal is formed as the gate dielectric layer; the field dielectric layer, the gate dielectric layer and the dielectric region in each composite field limiting ring are the same high-K dielectric; The high-K dielectric can better assist in depleting the drift region and modulating the surface electric field of the drift region to solve the adverse effects of the surface charge effect on the field limiting ring, thereby reducing the on-resistance of the device and improving the breakdown voltage of the device.

2. The compound field-limit-ring circular layout lateral power device of claim 1, wherein: The semiconductor well region comprises a semiconductor contact region and a semiconductor source region; the semiconductor contact region is annular and located directly below the source metal; the annular width of the semiconductor contact region is smaller than the annular width of the source metal; The semiconductor source region is annular and in contact with the inner wall of the semiconductor contact region.

3. The composite field-limiting-ring circular layout lateral power device according to claim 1, wherein: The annular width of the P-type region and the annular width of the dielectric region in each composite field limiting ring change synchronously.

4. A method of manufacturing a composite field limit ring circular layout lateral power device according to any one of claims 1-3, characterized in that: The method comprises the following steps: Step 1: manufacturing the active layer: sequentially arranging the buried oxygen layer and the active layer on the substrate; wherein the buried oxygen layer is used for electrical isolation between the active layer and the substrate; Step 2: etching annular grooves: etching M concentric and equidistant annular grooves on the top surface of the active layer; Step 3: manufacturing the P-type region: using photoresist as a mask, boron ions are injected into each annular groove by using an ion implantation process to form a P-type region with a longitudinal section in the shape of a concave letter; Step 4: manufacturing the semiconductor well region: using photoresist as a mask, low-concentration P-type semiconductor impurities are injected into the top surface of the active layer outside the outermost P-type region by using an ion implantation process to form a semiconductor well region in communication with the buried oxygen layer; Step 5: manufacturing the semiconductor contact region: using photoresist as a mask, high-doped P-type semiconductor impurities are injected into the top surface of the outer edge of the semiconductor well region by using an ion implantation process to form a semiconductor contact region. Step 6, making semiconductor source region and semiconductor drain region: using ion implantation process, high-doped phosphorus ions are implanted in the middle annular region of the top surface of the semiconductor well region and the center of the top surface of the active layer, thereby forming the semiconductor source region and the semiconductor drain region; Step 7, annealing, promoting diffusion to form a predetermined impurity distribution; Step 8, depositing dielectric material: depositing dielectric material in each P-type region and on the top surface of the active layer, wherein the dielectric material deposited in each P-type region forms a dielectric region; the dielectric region and the corresponding P-type region jointly constitute a composite field limiting ring; the dielectric material deposited on the top surface of the active layer forms a field dielectric layer; Step 9, etching source-drain contact holes: the source-drain contact holes include source contact holes and drain metal holes; the source contact holes are etched in the outer edge of the field dielectric layer, and the drain metal holes are etched in the field dielectric layer directly above the semiconductor drain region; Step 10, depositing source metal, drain metal and gate metal: depositing source metal in the source contact holes, depositing drain metal in the drain metal holes, and depositing gate metal on the top surface of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the drift region; wherein the field dielectric layer below the gate metal forms a gate dielectric layer.

5. The method of claim 4, wherein: The annular grooves in step 2 are etched by a dry etching process.

6. The method of claim 4, wherein: The number of annular grooves in step 2 is selected according to the width of the drift region, and is not less than 2; when the width of the drift region increases by 4-5 microns, one annular groove needs to be added.

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