Display panel and display device

Abstract

A display panel and a display device are disclosed, which belong to the technical field of display and are used for shielding the pixel driving circuit. The display panel comprises a substrate and a plurality of first pixel units. The plurality of first pixel units are arranged in multiple rows and multiple columns. Each first pixel unit comprises a plurality of sub-pixels, each sub-pixel comprising a pixel driving circuit and a light emitting device. The light emitting device is located on the side of the pixel driving circuit away from the substrate and is electrically connected to the pixel driving circuit. The pixel driving circuit comprises a first reset transistor. The plurality of sub-pixels comprise a first sub-pixel, a second sub-pixel and a third sub-pixel. The area of the light emitting device of the first sub-pixel is greater than the area of the light emitting device of the second sub-pixel and greater than the area of the light emitting device of the third sub-pixel. The orthographic projection of the first reset transistor in the second sub-pixel and / or the orthographic projection of the first reset transistor in the third sub-pixel on the substrate is located within the orthographic projection of the light emitting device of the first sub-pixel on the substrate. The display panel is used in a display device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] At present, OLED (organic light-emitting diode) display devices are widely used due to their self-luminous, fast response, wide viewing angle and flexible substrate making characteristics. The OLED display device includes a plurality of sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The light-emitting device is driven by the pixel driving circuit to emit light, thereby realizing display. SUMMARY

[0003] The purpose of the present disclosure is to provide a display panel and a display device to shield the pixel driving circuit.

[0004] To achieve the above purpose, the present disclosure provides the following technical solutions:

[0005] In one aspect, a display panel is provided. The display panel includes a substrate and a plurality of first pixel units. The plurality of first pixel units are located on one side of the substrate and arranged in multiple rows and multiple columns. Each of the first pixel units includes a plurality of sub-pixels, and each of the sub-pixels includes a pixel driving circuit and a light-emitting device. The light-emitting device is located on a side of the pixel driving circuit away from the substrate and is electrically connected to the pixel driving circuit. The pixel driving circuit includes a first reset transistor.

[0006] The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The area of the light-emitting device of the first sub-pixel is greater than the area of the light-emitting device of the second sub-pixel and greater than the area of the light-emitting device of the third sub-pixel.

[0007] The first reset transistor in the second sub-pixel and / or the first reset transistor in the third sub-pixel has a normal projection on the substrate, which is located within the normal projection of the light-emitting device of the first sub-pixel on the substrate.

[0008] In some embodiments, the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are all located within the normal projection of the light-emitting device of the first sub-pixel on the substrate.

[0009] In some embodiments, at least two of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are the same transistor.

[0010] In some embodiments, the pixel driving circuit further comprises a second reset transistor; the second reset transistor of the first sub-pixel, the second reset transistor of the second sub-pixel and the second reset transistor of the third sub-pixel are the same transistor; the orthographic projection of the second reset transistor on the substrate is located within the orthographic projection of the light emitting device of the first sub-pixel on the substrate; the second reset transistor is in series with any of the first reset transistors.

[0011] The display panel further comprises a reset signal line and an initialization signal line; the control electrode of each of the first reset transistors and the control electrode of the second reset transistor are electrically connected to the reset signal line; the first electrode of the second reset transistor is electrically connected to the initialization signal line, and the second electrode of the second reset transistor is electrically connected to the first electrode of each of the first reset transistors.

[0012] The pixel driving circuit further comprises a driving transistor; the control electrode of the driving transistor of each of the pixel driving circuits is electrically connected to the second electrode of each of the first reset transistors.

[0013] In some embodiments, the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel are arranged at intervals along the column direction; the light emitting device of the first sub-pixel is located in the adjacent column of the column in which the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel are located; and the light emitting device of the first sub-pixel crosses the gap region between the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel.

[0014] The pixel driving circuit further comprises a circuit body; the orthographic projection of the circuit body of the first sub-pixel on the substrate is located within the orthographic projection of the light emitting device of the first sub-pixel on the substrate, the orthographic projection of the circuit body of the second sub-pixel on the substrate is located within the orthographic projection of the light emitting device of the second sub-pixel on the substrate, and the orthographic projection of the circuit body of the third sub-pixel on the substrate is located within the orthographic projection of the light emitting device of the third sub-pixel on the substrate.

[0015] In some embodiments, the second reset transistor, the first reset transistor of the third sub-pixel and the first reset transistor of the second sub-pixel are located on the side of the first reset transistor of the first sub-pixel close to the circuit body of the third sub-pixel, and are sequentially away from the circuit body of the third sub-pixel.

[0016] In some embodiments, the reset signal line extends in a row direction, and one of the reset signal lines is electrically connected to the control electrode of the second reset transistor and the control electrode of each of the first reset transistors in a row of the first pixel units.

[0017] The second reset transistor and each of the first reset transistors are located between the orthogonal projection of the initialization signal line on the substrate to which the second reset transistor is electrically connected and the orthogonal projection of the circuit body of the third sub-pixel on the substrate; and the orthogonal projection of the reset signal line on the substrate is located between the orthogonal projection of the initialization signal line on the substrate and the orthogonal projection of the circuit body of the third sub-pixel on the substrate.

[0018] In some embodiments, the substrate includes a first display area, and the plurality of first pixel units are located in the first display area.

[0019] The display panel further includes a plurality of signal lines located between the substrate and the light-emitting device; at least one of the signal lines includes metal traces and transparent connection traces that are electrically connected to each other at a location in the first display area; and at least part of the metal traces is located within the orthogonal projection of the light-emitting device on the substrate.

[0020] In some embodiments, the display panel includes a first gate metal layer and a first transparent trace layer, both of which are located between the substrate and the light-emitting device, and the first transparent trace layer is located on a side of the first gate metal layer away from the substrate.

[0021] The at least one signal line includes a reset signal line, and the reset signal line extends in a row direction, and one of the reset signal lines is electrically connected to the control electrode of the second reset transistor and the control electrode of each of the first reset transistors in a row of the first pixel units.

[0022] The metal traces of the reset signal line are located in the first gate metal layer, at least part of the orthogonal projection of the metal traces of the reset signal line on the substrate is located within the orthogonal projection of the light-emitting device of the first sub-pixel on the substrate; the transparent connection traces of the reset signal line are located in the first transparent trace layer; the orthogonal projection of the transparent connection traces of the reset signal line on the substrate is located outside the orthogonal projection of the light-emitting device of the second sub-pixel on the substrate and outside the orthogonal projection of the light-emitting device of the third sub-pixel on the substrate; and the transparent connection traces of the reset signal line are connected to the metal traces of the reset signal line through a via.

[0023] In some embodiments, the circuit body of the pixel driving circuit comprises a write transistor, a compensation transistor and a third reset transistor; the at least one signal line further comprises a scan signal line, one of the scan signal lines is electrically connected to the control electrode of the write transistor, the control electrode of the compensation transistor and the control electrode of the third reset transistor of all the sub-pixels in one row of the first pixel units.

[0024] The metal trace of the scan signal line is located on the first gate metal layer, and at least part of the orthographic projection of the metal trace of the scan signal line on the substrate is located within the orthographic projection of the light emitting device on the substrate; the transparent connection trace of the scan signal line is located on the first transparent trace layer, and the transparent connection trace of the scan signal line is connected to the metal trace of the scan signal line through a via.

[0025] In some embodiments, the circuit body of the pixel driving circuit further comprises a first light emitting control transistor and a second light emitting control transistor; the at least one signal line further comprises a light emitting control signal line, one of the light emitting control signal lines is electrically connected to the control electrode of the first light emitting control transistor and the control electrode of the second light emitting control transistor of all the sub-pixels in one row of the first pixel units.

[0026] The metal trace of the light emitting control signal line is located on the first gate metal layer, and at least part of the orthographic projection of the metal trace of the light emitting control signal line on the substrate is located within the orthographic projection of the light emitting device on the substrate; the transparent connection trace of the light emitting control signal line is located on the first transparent trace layer, and the transparent connection trace of the light emitting control signal line is connected to the metal trace of the light emitting control signal line through a via.

[0027] In some embodiments, the display panel comprises: a first source-drain metal layer and a first transparent trace layer, both of which are located between the substrate and the light emitting device, and the first transparent trace layer is located on the side of the first source-drain metal layer away from the substrate.

[0028] The at least one signal line further comprises an initialization signal line, one of the initialization signal lines is electrically connected to the first electrode of the second reset transistor in one row of the first pixel units; the metal trace of the initialization signal line is located on the first source-drain metal layer, and at least part of the orthogonal projection of the metal trace of the initialization signal line on the substrate is located within the orthogonal projection of the light-emitting device of the first sub-pixel on the substrate; the transparent connection trace of the initialization signal line is located on the first transparent trace layer; the orthogonal projection of the transparent connection trace of the initialization signal line on the substrate is located outside the orthogonal projection of the light-emitting device of the second sub-pixel on the substrate and outside the orthogonal projection of the light-emitting device of the third sub-pixel on the substrate; and the transparent connection trace of the initialization signal line is connected to the metal trace of the initialization signal line through a via.

[0029] In some embodiments, the display panel comprises a second gate metal layer, a second source-drain metal layer and a second transparent trace layer located between the substrate and the light-emitting device, the second source-drain metal layer is located on the side of the second gate metal layer away from the substrate, and the second transparent trace layer is located on the side of the second source-drain metal layer away from the second gate metal layer. The circuit body of the pixel driving circuit further comprises a capacitor, and the first electrode plate of the capacitor is located on the second gate metal layer.

[0030] The at least one signal line further comprises a first power signal line, the first power signal line extends along the column direction, and one of the first power signal lines is electrically connected to the first electrode plate of the capacitor of the second sub-pixel and the first electrode plate of the capacitor of the third sub-pixel in one column of the first pixel units.

[0031] The metal trace of the first power signal line is located on the second source-drain metal layer, and at least part of the orthogonal projection of the metal trace of the first power signal line on the substrate is located within the orthogonal projection of the light-emitting device of the second sub-pixel and the light-emitting device of the third sub-pixel on the substrate; the transparent connection trace of the first power signal line is located on the second transparent trace layer, and the transparent connection trace of the first power signal line is connected to the metal trace of the first power signal line through a via.

[0032] In some embodiments, the at least one signal line further comprises a second power signal line, the second power signal line extends along the column direction, and one of the second power signal lines is electrically connected to the first electrode plate of the capacitor of the first sub-pixel in one column of the first pixel units.

[0033] The metal trace of the second power signal line is located on the second source-drain metal layer, and a projection of the metal trace of the second power signal line on the substrate is at least partially located within a projection of the light-emitting device of the first sub-pixel on the substrate; the transparent connection trace of the second power signal line is located on the second transparent trace layer, and the transparent connection trace of the second power signal line is connected to the metal trace of the second power signal line through a via.

[0034] In some embodiments, the display panel further comprises a plurality of data lines extending along the column direction, and a projection of a portion of the plurality of data lines located in the first display area on the substrate is located outside a projection of the light-emitting device of any of the sub-pixels on the substrate, and at least one data line is located at a portion of the first display area on the second transparent trace layer.

[0035] The circuit body of the pixel driving circuit comprises a write transistor; in one of the first pixel units, the first electrode of the write transistor of the first sub-pixel, the first electrode of the write transistor of the second sub-pixel, and the first electrode of the write transistor of the third sub-pixel are respectively connected to different data lines.

[0036] In some embodiments, the portion of the at least one data line located in the first display area is a transparent trace segment.

[0037] In the same column of the first pixel units, a projection of the transparent trace segment of the data line electrically connected to the write transistor in the first sub-pixel on the substrate is located on a side of a projection of the circuit body of the first sub-pixel on the substrate away from a projection of the circuit body of the second sub-pixel on the substrate; a projection of the light-emitting device of the second sub-pixel on the substrate and a projection of the light-emitting device of the third sub-pixel on the substrate are located between a projection of the transparent trace segment of the data line electrically connected to the write transistor of the second sub-pixel on the substrate and a projection of the transparent trace segment of the data line electrically connected to the write transistor of the third sub-pixel on the substrate.

[0038] In some embodiments, the circuit body of the pixel driving circuit further comprises a compensation transistor and a third reset transistor.

[0039] In one of the first pixel units, the write transistor, the compensation transistor, and the third reset transistor in the first sub-pixel are sequentially away from the circuit body of the second sub-pixel; the write transistor, the compensation transistor, and the third reset transistor in the second sub-pixel are sequentially arranged along a first set direction; and the write transistor, the compensation transistor, and the third reset transistor in the third sub-pixel are sequentially arranged along a direction opposite to the first set direction.

[0040] In some embodiments, the light emitting device comprises an anode, a light emitting layer and a cathode, the anode is electrically connected with the pixel driving circuit, the light emitting layer is located on the side of the anode away from the substrate, and the cathode is located on the side of the light emitting layer away from the substrate. The first reset transistor in the second sub-pixel and / or the first reset transistor in the third sub-pixel has a projection on the substrate, which is located within the projection of the anode of the first sub-pixel on the substrate.

[0041] In some embodiments, the first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel.

[0042] In some embodiments, the display panel comprises a first display area and a second display area. The first display area is provided with the first pixel unit; the second display area is provided with a plurality of second pixel units arranged in multiple rows and multiple columns; the second pixel unit comprises a plurality of sub-pixels; the sub-pixel density of the first display area is equal to the sub-pixel density of the second display area; and the area of the light emitting device of a sub-pixel in the first display area is 0.4-0.6 times the area of the light emitting device of a sub-pixel of the same color in the second display area.

[0043] In another aspect, a display device is provided. The display device comprises the display panel according to any one of the above embodiments.

[0044] The display panel and the display device provided by the present disclosure have the following beneficial effects:

[0045] In the display panel provided by the present disclosure, the area of the light emitting device of the first sub-pixel is the largest, and the areas of the light emitting devices of the second sub-pixel and the third sub-pixel are relatively small. By hiding the first reset transistor of the pixel driving circuit in the second sub-pixel and / or the first reset transistor of the pixel driving circuit in the third sub-pixel under the light emitting device of the first sub-pixel, the first reset transistor in the second sub-pixel and / or the first reset transistor in the third sub-pixel can be shielded, and because the area of the light emitting device of the first sub-pixel is large, the structure of the pixel driving circuit under the light emitting device of the first sub-pixel will not be too compact, and the space under the light emitting device of the first sub-pixel is reasonably utilized.

[0046] The display device provided by the present disclosure has the same beneficial effects as the display panel provided by the above technical solution, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description only represent some of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the product involved in the embodiments of the present disclosure.

[0048] FIG. 1A Structure diagram of a display device according to some embodiments;

[0049] FIG. 1B Structure diagram of a display device according to some embodiments;

[0050] FIG. 2A Structure diagram of a display device according to some embodiments;

[0051] FIG. 2B Structure diagram of a display panel according to some embodiments;

[0052] FIG. 3A Structure diagram of a display panel according to some embodiments;

[0053] FIG. 3B Structure diagram of a display panel according to some embodiments;

[0054] FIG. 4A Structure diagram of a pixel driving unit according to some embodiments;

[0055] FIG. 4B Timing diagram of a pixel driving circuit according to some embodiments;

[0056] FIG. 4C Structure diagram of a pixel driving unit according to some embodiments;

[0057] FIG. 4D Structure diagram of a pixel driving unit according to some embodiments;

[0058] FIG. 4E Structure diagram of a pixel driving unit according to some embodiments;

[0059] FIG. 4F Structure diagram of a pixel driving unit according to some embodiments;

[0060] FIG. 5A Structure diagram of a display panel according to some embodiments;

[0061] FIG. 5B Structure diagram of a display panel according to some embodiments;

[0062] FIG. 5C A structural diagram of a display panel according to some embodiments;

[0063] FIG. 5D A structural diagram of a display panel according to some embodiments;

[0064] FIG. 6A A structural diagram of a display panel according to some embodiments;

[0065] FIG. 6B A structural diagram of a display panel according to some embodiments;

[0066] FIG. 7A A structural diagram of a display panel according to some embodiments;

[0067] FIG. 7B A structural diagram of a display panel according to some embodiments;

[0068] FIG. 7C A structural diagram of a display panel according to some embodiments;

[0069] FIG. 8A A structural diagram of a display panel according to some embodiments;

[0070] FIG. 8B A structural diagram of a display panel according to some embodiments;

[0071] FIG. 9A A structural diagram of a display panel according to some embodiments;

[0072] FIG. 9B A structural diagram of a display panel according to some embodiments;

[0073] FIG. 9C A structural diagram of a display panel according to some embodiments;

[0074] FIG. 10A A structural diagram of a display panel according to some embodiments;

[0075] FIG. 10B A structural diagram of a display panel according to some embodiments;

[0076] FIG. 11A A structural diagram of a display panel according to some embodiments;

[0077] FIG. 11B A structural diagram of a display panel according to some embodiments;

[0078] FIG. 11C A structural diagram of a display panel according to some embodiments;

[0079] FIG. 11D A structural diagram of a display panel according to some embodiments;

[0080] FIG. 11E Structure diagram of a display panel according to some embodiments;

[0081] FIG. 12A Structure diagram of a display panel according to some embodiments;

[0082] FIG. 12B Structure diagram of a display panel according to some embodiments;

[0083] FIG. 12C Structure diagram of a display panel according to some embodiments;

[0084] FIG. 13A Structure diagram of a display panel according to some embodiments;

[0085] FIG. 13B Structure diagram of a display panel according to some embodiments;

[0086] FIG. 14 Structure diagram of a display panel according to some embodiments. DETAILED DESCRIPTION

[0087] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0088] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, and other forms of the term “comprise”, are used in an open, inclusive sense, i.e., “including, but not limited to”, throughout the specification and claims. In the description of the specification, the terms “some embodiments”, “example” or “some examples” and the like are intended to indicate that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any suitable way in one or more embodiments or examples.

[0089] The terms "first", "second", etc. are used herein only to describe one implementation, and do not imply or connote relative importance or a listing of multiple structures (for example, a "first" structure can be synonymous with a "second" structure where there are no recitations of quantities, expressions such as "at least one of A and B" and "between A and B" are inclusive of A and / or B.

[0090] In describing some embodiments, the use of "coupled" or relative terms such as "connected", "engaged", and the like, can be used herein to indicate either direct physical or electrical contact between elements or indirect physical or electrical contact between elements via one or more intermediate elements.

[0091] "A and / or B" includes the following three combinations: A alone, B alone, and a combination of A and B.

[0092] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while", depending on the context.

[0093] The use of "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0094] Additionally, the use of "based on" means open and inclusive, as the process, step, calculation, or other action that is based on one or more recited conditions or values can in practice be based on additional conditions or values beyond those that are recited.

[0095] In describing some embodiments, the use of "a structure disposed under the anode" or

[0096] "under the anode" or "hidden under the anode" means that the positive projection of the structure onto the substrate is within the positive projection of the anode onto the substrate.

[0097] In describing some embodiments, the use of "an area of a structure" means the area of the positive projection of the structure onto the substrate.

[0098] As used herein, "substantially" or "approximately" means an average value of the recited quantity, as well as values within an acceptable range of deviation from the recited quantity, as determined by one of ordinary skill in the art considering the measurement at issue and the error in measurement associated with the particular quantity being measured (i.e., the limitations of the measurement system).

[0099] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions that are approximately the recited condition, the range of which is within an acceptable deviation range, as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, where the acceptable deviation range for approximately perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximately equal can be, for example, a difference between the two that is less than or equal to 5% of either.

[0100] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0101] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layers of components of the devices are included in illustrative drawings. Thus, the thickness of layers and regions can be exaggerated in order to show such features more clearly. It will also be appreciated that, for example, manufacturing techniques can result in deviations from the shapes of the regions shown in the figures. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated in the figures, which are schematic, but include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have curved or jagged features. The regions illustrated in the figures are schematic, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0102] Some embodiments of the present disclosure provide a display device. FIG. 1A and FIG. 1B is a structural diagram of a display device according to some embodiments. Please refer to FIG. 1A and FIG. 1B The display device 100 is a product having an image (including a still image or a dynamic image, where the dynamic image can be a video) display function. For example, the display device 100 can be any one of a watch, a display, a television, a billboard, a digital photo frame, a laser printer having a display function, a telephone, a cell phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information inquiry device (such as a business inquiry device of an electronic government, a bank, a hospital, a power company, etc.), a monitor, and the like.

[0103] wherein please refer toFIG. 2A The display device 100 includes a display panel 200 and a sensor 300.

[0104] Some embodiments of the present disclosure provide a display panel 200, FIG. 2B is a structural diagram of the display panel according to some embodiments. Please refer to FIG. 2B The display panel 200 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA. The display area AA is used for displaying a picture. In some examples, the peripheral area BB can be disposed on one or more sides of the display area AA. In other examples, the peripheral area BB is disposed around the display area AA.

[0105] The display panel 200 can be an OLED (organic light-emitting diode) display panel. The OLED display panel has the advantages of wide viewing angle, high contrast, fast response, low power consumption, foldable, flexible, etc.

[0106] Please refer to FIG. 2B The display panel 200 includes a substrate 210 and a plurality of first pixel units 220 disposed on one side of the substrate 210 and arranged in multiple rows and columns. The first pixel unit 220 includes a plurality of sub-pixels 230. The sub-pixel 230 is the smallest unit for displaying a picture by the display panel 200. Each sub-pixel 230 can display a single color, such as red, green, or blue. By adjusting the brightness (gray scale) of different color sub-pixels, color combination and superposition can realize the display of multiple colors, thereby realizing the full-color display of the display panel 200.

[0107] In some embodiments, please refer to FIG. 2B The display area AA includes a first display area A1, and the plurality of first pixel units 220 are disposed in the first display area A1. Please refer to FIG. 2A The display panel 200 includes a backlight side 201 and a display side 202 disposed opposite to each other, wherein the display side 202 is used for displaying a picture. The sensor 300 is disposed on the backlight side 201 of the display panel 200 and located in the first display area A1 of the display panel 200.

[0108] The sensor 300 is, for example, an image sensor or an infrared sensor, etc. The sensor 300 is configured to receive light from the display side 202 of the display panel 200, so as to perform image shooting, distance sensing, light intensity sensing, etc. These light can pass through the first display area A1 and then irradiate on the sensor 300, so as to be sensed by the sensor 300.

[0109] By disposing the sensor 300 at the first display area A1 of the display panel 200 and on the backlight side 201 of the display panel, a hole can be avoided in the display screen, the screen-to-body ratio can be improved, and better visual experience can be achieved.

[0110] FIG. 3A FIG. 1 is a structural diagram of a display panel according to some embodiments. FIG. 3A The sub-pixel 230 includes a pixel driving circuit 231 and a light emitting device 232. The light emitting device 232 is located on a side of the pixel driving circuit 231 away from the substrate 210 and is electrically connected to the pixel driving circuit 231. The pixel driving circuit 231 is configured to drive the light emitting device 232 to emit light.

[0111] FIG. 3B FIG. 2 is a structural diagram of a display panel according to some embodiments. FIG. 3B FIG. 3 shows the structure of a sub-pixel. FIG. 3B The light emitting device 232 includes an anode AND1, a light emitting layer EL, and a cathode CTD1. The anode AND1 is located on a side of the pixel driving circuit 231 away from the substrate 210 and is electrically connected to the pixel driving circuit 231. The light emitting layer EL is located on a side of the anode AND1 away from the substrate 210. The cathode CTD1 is located on a side of the light emitting layer EL away from the substrate 210. In some examples, the light emitting device 232 further includes one or more of an election transporting layer (ETL), an election injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0112] In some examples, the orthographic projection of the anode AND1 on the substrate 210, the orthographic projection of the light emitting layer EL on the substrate 210, and the orthographic projection of the cathode CTD1 on the substrate 210 at least partially overlap.

[0113] FIG. 4 shows the structure of a first pixel unit 220. FIG. 3A The plurality of sub-pixels 230 in the first pixel unit 220 includes a first sub-pixel 230B, a second sub-pixel 230G, and a third sub-pixel 230R.

[0114] In the first pixel unit 220, the area of the light emitting device 232 of the first sub-pixel 230B is greater than the area of the light emitting device 232 of the second sub-pixel 230G and greater than the area of the light emitting device 232 of the third sub-pixel 230R. Correspondingly, FIG. 5 shows the structure of a first pixel unit 220. FIG. 3AIn a first pixel unit 220, the area of the anode AND-B of the first sub-pixel 230B is greater than the area of the anode AND-G of the second sub-pixel 230G, and greater than the area of the anode AND-R of the third sub-pixel 230R. Correspondingly, in a first pixel unit 220, the area of the light-emitting layer EL of the first sub-pixel 230B is greater than the area of the light-emitting layer EL of the second sub-pixel 230G, and greater than the area of the light-emitting layer EL of the third sub-pixel 230R. Correspondingly, in a first pixel unit 220, the area of the cathode CTD1 of the first sub-pixel 230B is greater than the area of the cathode CTD1 of the second sub-pixel 230G, and greater than the area of the cathode CTD1 of the third sub-pixel 230R.

[0115] The anode AND1 is in a block shape, and the anodes AND1 of different sub-pixels 230 are separated from each other. The light-emitting layer EL is in a block shape, and the light-emitting layers EL of different sub-pixels 230 are separated from each other.

[0116] In some examples, the cathodes CTD1 of the plurality of sub-pixels 230 in the display panel 200 are connected to each other, and the cathodes CTD1 of the plurality of sub-pixels 230 are in a whole-layer structure. In these examples, the area of the cathode CTD1 of a sub-pixel 230 is equal to the area of the light-emitting layer EL or the area of the anode AND1. In addition, in these examples, the area of the larger one of the light-emitting layer EL and the anode AND1 is the area of the light-emitting device 232. For example, if the area of the orthographic projection of the anode AND1 on the substrate 210 is greater than the area of the orthographic projection of the light-emitting layer EL on the substrate 210, then the area of the light-emitting device 232 is the area of the anode AND1. For example, if the area of the orthographic projection of the light-emitting layer EL on the substrate 210 is greater than the area of the orthographic projection of the anode AND1 on the substrate 210, then the area of the light-emitting device 232 is the area of the light-emitting layer EL.

[0117] In other examples, the cathode CTD1 is in a block shape, and the cathodes CTD1 of the plurality of sub-pixels 230 in the display panel 200 are separated from each other. In this case, the area of the largest one of the cathode CTD1, the light-emitting layer EL, and the anode AND1 is the area of the light-emitting device 232. For example, among the cathode CTD1, the light-emitting layer EL, and the anode AND1 of a sub-pixel 230, if the area of the cathode CTD1 is the largest, then the area of the light-emitting device 232 is the area of the cathode CTD1. If the area of the anode AND1 is the largest, then the area of the light-emitting device 232 is the area of the anode AND1. If the area of the light-emitting layer EL is the largest, then the area of the light-emitting device 232 is the area of the light-emitting layer EL.

[0118] For example, in the first pixel unit 220, the first sub-pixel 230B is a blue sub-pixel, the second sub-pixel 230G is a green sub-pixel, and the third sub-pixel 230R is a red sub-pixel.

[0119] The light-emitting layer EL includes an effective light-emitting area. In some examples, in a first pixel unit 220, the area of the light-emitting device 232 of the first sub-pixel 230B is greater than the area of the light-emitting device 232 of the second sub-pixel 230G, and greater than the area of the light-emitting device 232 of the third sub-pixel 230R. Correspondingly, the area of the effective light-emitting area of the first sub-pixel 230B is greater than the area of the effective light-emitting area of the second sub-pixel 230G, and greater than the area of the effective light-emitting area of the third sub-pixel 230R. The light-emitting layer EL in the light-emitting device 232 includes a light-emitting material, and the efficiency of the light-emitting material of the blue sub-pixel is relatively low. By maximizing the effective light-emitting area of the blue sub-pixel, the color deviation problem caused by the different light-emitting efficiencies of the red, green, and blue sub-pixels can be reduced.

[0120] In an implementation manner, by reducing the area of the light-emitting device 232 of the sub-pixel 230, and hiding the pixel driving circuit 231 under the light-emitting device 232, the area of the sub-pixel 230 in the display panel 200 can be reduced, and thus the area of the light-transmitting region can be increased, and the light transmittance of the first display area A1 can be improved. It should be noted that the area of the light-emitting device 232 refers to the area covered by the orthographic projection of the light-emitting device 232 on the substrate 210. The pixel driving circuit 231 being hidden under the light-emitting device 232 means that the pixel driving circuit 231 is located on the side of the light-emitting device 232 close to the substrate 210, and the orthographic projection of the pixel driving circuit 231 on the substrate 210 is located within the orthographic projection of the light-emitting device 232 on the substrate 210.

[0121] However, since the area of the light-emitting device 232 of the second sub-pixel 230G and the area of the light-emitting device 232 of the third sub-pixel 230R are relatively small, it is difficult to hide the pixel driving circuit 231-G of the second sub-pixel 230G under the light-emitting device 232 of the second sub-pixel 230G, and it is difficult to hide the pixel driving circuit 231-R of the third sub-pixel 230R under the light-emitting device 232 of the third sub-pixel 230R. If the pixel driving circuit 231 is exposed outside the light-emitting device 232, the light transmittance of the first display area A1 will be reduced, and diffraction will be increased, which is not conducive to imaging.

[0122] Based on this, the present disclosure provides a pixel driving unit 400, please refer to FIG. 4A The pixel driving unit 400 includes a plurality of pixel driving circuits 231.

[0123] In some embodiments, the structure of the pixel driving circuit in the present disclosure includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit 231 can include "6T1C", "7T1C", "6T2C", or "7T2C", etc. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C. The following is described taking the pixel driving circuit in the 7T1C mode as an example.

[0124] Referring to FIG. 4A , the pixel driving circuit 231 includes a driving transistor T3 and a second reset transistor T12, the second reset transistor T12 is electrically connected with a reset signal terminal Rst, an initialization signal terminal Vin and a control electrode of the driving transistor T3, and the second reset transistor T12 is configured to transmit an initialization signal received at the initialization signal terminal Vin to the control electrode of the driving transistor T3 to reset the control electrode of the driving transistor T3 in response to a reset signal received at the reset signal terminal Rst.

[0125] For example, the control electrode of the second reset transistor T12 is electrically connected with the reset signal terminal Rst, the first electrode is electrically connected with the initialization signal terminal Vin, and the second electrode is electrically connected with the control electrode of the driving transistor T3.

[0126] Referring to FIG. 4A , in addition to the second reset transistor T12 and the driving transistor T3, the pixel driving circuit 231 further includes a compensation transistor T2, a writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a third reset transistor T7 and a capacitor Cst.

[0127] The control electrode of the compensation transistor T2 is electrically connected with a scanning signal terminal Gt, the first electrode of the compensation transistor T2 is electrically connected with the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is electrically connected with the control electrode of the driving transistor T3.

[0128] The control electrode of the writing transistor T4 is electrically connected with the scanning signal terminal Gt, the first electrode of the writing transistor T4 is electrically connected with a data signal terminal Dt, and the second electrode of the writing transistor T4 is electrically connected with the first electrode of the driving transistor T3.

[0129] The control electrode of the first light-emitting control transistor T5 is electrically connected with a light-emitting control signal terminal Em, the first electrode of the first light-emitting control transistor T5 is electrically connected with a first type power signal terminal Vdd, and the second electrode of the first light-emitting control transistor T5 is electrically connected with the first electrode of the driving transistor T3.

[0130] The control electrode of the second light emitting control transistor T6 is electrically connected with the light emitting control signal terminal Em, the first electrode of the second light emitting control transistor T6 is electrically connected with the second electrode of the driving transistor T3, and the second electrode of the second light emitting control transistor T6 is electrically connected with the anode of the light emitting device 232. The cathode of the light emitting device 232 is electrically connected with the second type power signal terminal Vss. The voltage of the first type power signal received at the first type power signal terminal Vdd is greater than the voltage of the second type power signal received at the second type power signal terminal Vss.

[0131] The control electrode of the third reset transistor T7 is electrically connected with the scanning signal terminal Gt, the first electrode of the third reset transistor T7 is electrically connected with the initialization signal terminal Vin, and the second electrode of the third reset transistor T7 is electrically connected with the anode of the light emitting device 232.

[0132] The first electrode plate of the capacitor Cst is electrically connected with the first type power signal terminal Vdd, and the second electrode plate of the capacitor Cst is electrically connected with the control electrode of the driving transistor T3.

[0133] In some examples, the second reset transistor T12, the compensation transistor T2, the driving transistor T3, the write transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6 and the third reset transistor T7 can all be P-type transistors or N-type transistors. The N-type transistor is turned on when a high voltage signal is received at the gate, while the P-type transistor is turned on when a low voltage signal is received at the gate. It should be noted that the above-mentioned "high voltage signal" and "low voltage signal" are colloquial expressions. Generally, the turn-on condition of the N-type transistor is that the gate-source voltage difference is greater than the threshold voltage, i.e. the gate voltage of the N-type transistor is greater than the sum of the source voltage and the threshold voltage of the N-type transistor. The threshold voltage of the N-type transistor is positive, so the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turn-on condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than the threshold voltage, and the threshold voltage of the P-type transistor is negative, i.e. the gate voltage of the P-type transistor is less than the sum of the source voltage and the threshold voltage of the P-type transistor. The gate voltage signal that turns on the P-type transistor is called a low voltage signal. The high and low in "high voltage signal" and "low voltage signal" are relative to the voltage of the source.

[0134] In some examples, referring to FIG. 4A , the second reset transistor T12, the compensation transistor T2, the driving transistor T3, the write transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6 and the third reset transistor T7 can all be P-type transistors. At this time, the timing diagram of the pixel driving circuit 231 is as shown in FIG. 4B .

[0135] The following describes the driving process of the pixel driving circuit 231 based on the transistors in the pixel driving circuit 231 being P-type transistors.

[0136] The driving process of the pixel driving circuit 231 is as follows: one frame period includes a reset stage t1, a data refresh and compensation stage t2, and an emission stage t3.

[0137] In the reset stage t1, the reset signal is at a low voltage, at which time the second reset transistor T12 is turned on, the second reset transistor T12 transmits the initialization signal to the control electrode of the driving transistor T3, thereby resetting the control electrode of the driving transistor T3 and turning on the driving transistor T3. The compensation transistor T2, the write transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 are all in an off state, and the light emitting device 232 does not emit light.

[0138] In the data refresh and compensation stage t2, the reset signal received at the reset signal end Rst is at a high voltage, and the second reset transistor T12 is turned off. The scan signal received at the scan signal end Gt is at a low voltage, so the third reset transistor T7 is turned on under the control of the scan signal, and the initialization signal received at the initialization signal end Vin is written to the anode of the light emitting device 232, thereby resetting the anode of the light emitting device 232.

[0139] At the same time, under the control of the scan signal, the write transistor T4 and the compensation transistor T2 are turned on, and the driving transistor T3 maintains the on state in the reset stage t1, so the data signal received at the data signal end Dt can be transmitted to the control electrode of the driving transistor T3 through the write transistor T4, the driving transistor T3, and the compensation transistor T2 in sequence, so that the voltage of the control electrode of the driving transistor T3 changes until the voltage of the control electrode of the driving transistor T3 reaches the sum of the threshold voltage of the driving transistor T3 and the voltage of the data signal, so that the driving transistor T3 is turned off.

[0140] In the data refresh and compensation stage t2, the threshold voltage of the driving transistor T3 can be written to the control electrode of the driving transistor T3 to compensate for the threshold voltage drift of the driving transistor T3, thereby reducing the impact on the luminous intensity of the light emitting device 232. In this stage, the first emission control transistor T5 and the second emission control transistor T6 are in an off state under the control of the emission control signal.

[0141] In the light emitting stage t3, the second reset transistor T12, the compensation transistor T2, the write transistor T4 and the third reset transistor T7 are turned off. The capacitor Cst fixes the voltage of the control electrode of the driving transistor T3, so that the control electrode of the driving transistor T3 is maintained at the voltage in the data refreshing and compensation stage t2. At this time, the light emitting control signal is low voltage, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal, and then the first power signal received at the first power signal terminal Vdd is written to the first electrode of the driving transistor T3, so that the driving transistor T3 is turned on, thereby forming a path between the first power signal terminal and the light emitting device 232, so that the light emitting device 232 emits light.

[0142] In the pixel driving unit 400 provided by some embodiments of the present disclosure, referring to FIG. 4A , the second reset transistors T12 of the at least two pixel driving circuits 231 are the same transistor, thereby reducing the area of the pixel driving unit 400 and facilitating hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light emitting device 232.

[0143] In some examples, the second reset transistors T12 of all the pixel driving circuits 231 in one pixel driving unit 400 are the same transistor.

[0144] In some examples, in one pixel driving unit 400, the plurality of pixel driving circuits 231 include a first pixel driving circuit 231B, a second pixel driving circuit 231G and a third pixel driving circuit 231R. Among them, the second reset transistor T12 of the first pixel driving circuit 231B, the second reset transistor T12 of the second pixel driving circuit 231G and the second reset transistor T12 of the third pixel driving circuit 231R are the same transistor.

[0145] Among them, the first pixel driving circuit 231B, the second pixel driving circuit 231G and the third pixel driving circuit 231R share the second reset transistor T12, and one second reset transistor T12 can reset the control electrodes of the driving transistors T3 in the pixel driving circuits 231B, 231G and 231R at the same time.

[0146] By sharing the second reset transistor T12, the number of transistors in one pixel driving unit 400 can be reduced, and therefore the area of the pixel driving unit 400 can be reduced, facilitating hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light emitting device 232.

[0147] In some examples, referring to FIG. 3AThe first sub-pixel 230B includes a first pixel driving circuit 231B and an anode AND-B, and the first pixel driving circuit 231B and the anode AND-B are electrically connected. The second sub-pixel 230G includes a second pixel driving circuit 231G and an anode AND-G, and the second pixel driving circuit 231G and the anode AND-G are electrically connected. The third sub-pixel 230R includes a third pixel driving circuit 231R and an anode AND-R, and the third pixel driving circuit 231R and the anode AND-R are electrically connected.

[0148] In some embodiments, referring to FIG. 4A The pixel driving circuit 231 further includes a first reset transistor T11. In the same pixel driving circuit 231, the first reset transistor T11 is connected in series between the second reset transistor T12 and the control electrode of the driving transistor T3.

[0149] The control electrode of the first reset transistor T11 is electrically connected to a reset signal terminal Rst, and the first reset transistor T11 and the second reset transistor T12 jointly reset the control electrode of the driving transistor T3, thereby preventing leakage.

[0150] In some examples, referring to FIG. 4C-F In one pixel driving unit 400, the first reset transistors T11 of the at least two pixel driving circuits 231 are the same transistor.

[0151] Based on the above embodiment in which the plurality of pixel driving circuits 231 include the first pixel driving circuit 231B, the second pixel driving circuit 231G, and the third pixel driving circuit 231R. In some embodiments, referring to FIG. 4C-F At least two of the first reset transistor T11-B of the first pixel driving circuit 231B, the first reset transistor T11-G of the second pixel driving circuit 231G, and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

[0152] In some examples, referring to FIG. 4C The first reset transistor T11-B of the first pixel driving circuit 231B and the first reset transistor T11-G of the second pixel driving circuit 231G are the same transistor.

[0153] In some examples, referring to FIG. 4D The first reset transistor T11-B of the first pixel driving circuit 231B and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

[0154] In some examples, referring to FIG. 4EThe first reset transistor T11-G of the second pixel driving circuit 231G and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

[0155] In some examples, referring to FIG. 4F In some examples, referring to

[0156] By making at least two of the plurality of pixel driving circuits 231 in one pixel driving unit 400 share the first reset transistor T11, the number of transistors in one pixel driving unit 400 can be reduced, and the area of the pixel driving circuit 231 in the pixel driving unit 400 can be reduced, which is conducive to hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light emitting device 232.

[0157] In addition, in some other examples, referring to FIG. 4A In some examples, referring to

[0158] By providing each pixel driving circuit 231 with a first reset transistor T11, the control electrode of the driving transistor T3 is reset by different first reset transistors T11 in different pixel driving circuits 231, which can ensure the reset effect of the control electrode of the driving transistor T3.

[0159] The display device 100 provided by some embodiments of the present disclosure includes the pixel driving unit 400 provided by any of the above embodiments. Therefore, the display device 100 provided by some embodiments of the present disclosure has all the beneficial effects of the pixel driving unit 400 provided by any of the above embodiments, which will not be repeated here.

[0160] Some embodiments of the present disclosure also provide a display panel 200, referring to FIG. 5AIn the display panel 200, the orthographic projection of the first reset transistor T11-G in the second sub-pixel 230G and / or the orthographic projection of the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0161] It should be noted that, in the case where the area of the light emitting device 232 is the area of the anode AND1, the orthographic projection of the light emitting device 232 on the substrate 210 coincides with the orthographic projection of the anode AND1 on the substrate 210. In the case where the area of the light emitting device 232 is the area of the light emitting layer EL, the orthographic projection of the light emitting device 232 on the substrate 210 coincides with the orthographic projection of the light emitting layer EL on the substrate 210. In the case where the area of the light emitting device 232 is the area of the cathode CTD1, the orthographic projection of the light emitting device 232 on the substrate 210 coincides with the orthographic projection of the cathode CTD1 on the substrate 210.

[0162] In some examples, in a first pixel unit 220, the area of the light emitting device 232 of the first sub-pixel 230B is the largest, and the area of the light emitting device 232 of the second sub-pixel 230G and the area of the light emitting device 232 of the third sub-pixel 230R are relatively small. By hiding the first reset transistor T11-G in the second sub-pixel 230G and / or the first reset transistor T11-R in the third sub-pixel 230R under the light emitting device 232 of the first sub-pixel 230B, not only can the first reset transistor T11-G in the second sub-pixel 230G and / or the first reset transistor T11-R in the third sub-pixel 230R be shielded, but also because the area of the light emitting device 232 of the first sub-pixel 230B is large, the structure of the pixel driving circuit 231 under the light emitting device 232 of the first sub-pixel 230B will not be too compact, and the space under the light emitting device 232 of the first sub-pixel 230B will be reasonably utilized.

[0163] In some examples, only the first reset transistor T11-G in the second sub-pixel 230G can be made to have a footprint on the substrate 210 within the footprint of the light emitting device 232 of the first sub-pixel 230B on the substrate 210. In one first pixel unit 220, the light emitting device 232 of the second sub-pixel 230G has a smaller area, and by arranging the first reset transistor T11-G in the second sub-pixel 230G under the light emitting device 232 of the first sub-pixel 230B, the number of transistors in the pixel driving circuit 231 under the light emitting device 232 of the second sub-pixel 230G can be reduced, and the area of the pixel driving circuit 231 under the light emitting device 232 of the second sub-pixel 230G can be reduced, which is conducive to the light emitting device 232 of the second sub-pixel 230G shielding the pixel driving circuit 231 thereunder.

[0164] In other examples, only the first reset transistor T11-R in the third sub-pixel 230R can be made to have a footprint on the substrate 210 within the footprint of the light emitting device 232 of the first sub-pixel 230B on the substrate 210. By arranging the first reset transistor T11-R in the third sub-pixel 230R under the light emitting device 232 of the first sub-pixel 230B, the number of transistors in the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R can be reduced, and the area of the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R can be reduced, which is conducive to the light emitting device 232 of the third sub-pixel 230R shielding the pixel driving circuit 231 thereunder.

[0165] In other embodiments, referring to FIG. 5A , the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R are all within the footprint of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0166] The first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G and the first reset transistor T11-R of the third sub-pixel 230R are all arranged below the light emitting device 232 of the first sub-pixel 230B, which not only reduces the area of the pixel driving circuit 231 below the light emitting device 232 of the second sub-pixel 230G, but also reduces the area of the pixel driving circuit 231 below the light emitting device 232 of the third sub-pixel 230R, which is conducive to shielding the pixel driving circuit 231 in the second sub-pixel 230G and the pixel driving circuit 231 in the third sub-pixel 230R, and reduces the diffraction phenomenon. Moreover, the first reset transistor T11-B of the first sub-pixel 230B is arranged below the light emitting device 232 of the first sub-pixel 230B, which avoids occupying other space by the first reset transistor T11-B, thereby improving the light transmittance.

[0167] In some embodiments, referring to FIG. 4C-F , at least two of the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G and the first reset transistor T11-R of the third sub-pixel 230R are the same transistor.

[0168] In one first pixel unit 220, the first reset transistors T11 of at least two sub-pixels 230 are the same transistor, which can reduce the number of first reset transistors T11 in the first pixel unit 220. When the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G and the first reset transistor T11-R of the third sub-pixel 230R are all arranged below the light emitting device 232 of the first sub-pixel 230B, the number of first reset transistors T11 is reduced, which can reduce the area of the pixel driving circuit 231 below the light emitting device 232 of the first sub-pixel 230B, and further can reduce the area of the light emitting device 232 of the first sub-pixel 230B, thereby improving the light transmittance of the first display area A1.

[0169] In some examples, the material of the anode AND1 includes a transparent conductive oxide material and a metal material, where the transparent conductive oxide material is, for example, ITO or IZO, and the metal material is, for example, Au, Ag, Ni or Pt. For example, the anode layer AND can include a laminated composite structure of a layer of transparent conductive oxide, a layer of metal and a layer of transparent conductive oxide, which can be denoted as transparent conductive oxide / metal / transparent conductive oxide, for example, the structure of an anode layer AND is ITO / Ag / ITO. The anode AND1 has poor light transmittance or is not light-transmissive.

[0170] In some embodiments, referring to FIG. 5AThe normal projection of the first reset transistor T11-B in the first sub-pixel 230B, the first reset transistor T11-G in the second sub-pixel 230G, and / or the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 is located within the normal projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. It should be noted that the area of the light-emitting device 232 and the anode AND1 can be equal or not equal at this time, and it can also be understood that the normal projection of the light-emitting device 232 on the substrate 210 can be completely or partially overlapped with the normal projection of the anode AND1 on the substrate 210.

[0171] The anode AND1 is poor in light transmittance or non-transparent, and thus the anode AND1 can shield the pixel driving circuit 231 and the signal line and the like located below the anode AND1, thereby reducing the exposure of the pixel driving circuit 231 and the signal line, so as to reduce the diffraction when the sensor 300 takes a picture through the first display area A1, and at the same time increase the light transmittance of the first display area A1.

[0172] In some examples, the normal projection of the first reset transistor T11-B in the first sub-pixel 230B, the first reset transistor T11-G in the second sub-pixel 230G, and / or the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 is located within the normal projection of the anode AND-B of the first sub-pixel 230B on the substrate 210.

[0173] In some embodiments, referring to FIG. 5A and FIG. 5B , the display panel 200 further includes a reset signal line RST and an initialization signal line VIN.

[0174] Referring to FIG. 5A , the pixel driving circuit 231 further includes a second reset transistor T12, and the second reset transistor T12 is connected in series with any first reset transistor T11. As shown in FIG. 5B , the control electrode of each first reset transistor T11 and the control electrode of the second reset transistor T12 are electrically connected with the reset signal line RST; the first electrode of the second reset transistor T12 is electrically connected with the initialization signal line VIN, and the second electrode of the second reset transistor T12 is electrically connected with the first electrode of each first reset transistor T11. The pixel driving circuit 231 further includes a driving transistor T3, and the control electrode of the driving transistor T3 of each pixel driving circuit 231 is electrically connected with the second electrode of each first reset transistor T11.

[0175] The reset signal line RST is used for transmitting a reset signal, and the initialization signal line VIN is used for transmitting an initialization signal. In the case where the first reset transistor T11 and the second reset transistor T12 are both P-type transistors, when the reset signal is a low-voltage signal, the first reset transistor T11 and the second reset transistor T12 are turned on, and the first reset transistor T11 and the second reset transistor T12 can transmit the initialization signal to the control electrode of the driving transistor T3, thereby resetting the control electrode of the driving transistor T3. Through the two transistors, the control electrode of the driving transistor T3 is reset, which can prevent leakage.

[0176] In some embodiments, referring to FIG. 5A , the second reset transistor T12 of the first sub-pixel 230B, the second reset transistor T12 of the second sub-pixel 230G, and the second reset transistor T12 of the third sub-pixel 230R are the same transistor, and the orthogonal projection of the second reset transistor T12 on the substrate 210 is located within the orthogonal projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0177] As shown in FIG. 5A , the second reset transistor T12 of the first sub-pixel 230B, the second reset transistor T12 of the second sub-pixel 230G, and the second reset transistor T12 of the third sub-pixel 230R are the same transistor, which can reduce the number of transistors under the light-emitting device 232 of the first sub-pixel 230B, thereby reducing the area of the pixel driving circuit 231 under the light-emitting device 232 of the first sub-pixel 230B, and facilitating the light-emitting device 232 of the first sub-pixel 230B to shield the pixel driving circuit 231 located thereunder, avoiding the pixel driving circuit 231 from being exposed, thereby reducing the diffraction phenomenon.

[0178] Meanwhile, in the case where the number of transistors under the light-emitting device 232 of the first sub-pixel 230B is small, the area of the light-emitting device 232 of the first sub-pixel 230B can be reduced, and the light transmittance can be increased.

[0179] In some other examples, referring to FIG. 5A , the orthogonal projection of the second reset transistor T12 on the substrate 210 is located within the orthogonal projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. Among them, the anode AND-B of the first sub-pixel 230B is not transparent, and its shielding effect on the second reset transistor T12 is good, thereby reducing the diffraction phenomenon when the sensor 300 takes a picture through the first display area A1.

[0180] In some embodiments, referring to FIG. 5C, the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R are arranged along the column direction Y. The direction indicated by the arrow Y is the column direction Y. The light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R are arranged in sequence along the column direction Y, so that the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R in a column of first pixel units 220 can be arranged in a column. The light emitting device 232 of the first sub-pixel 230B in a column of first pixel units 220 can be arranged in a column. Please refer to FIG. 5B and FIG. 5C , the light emitting device 232 of the first sub-pixel 230B is located in the adjacent column of the column in which the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R are located; and the light emitting device 232 of the first sub-pixel 230B spans the gap region between the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R.

[0181] It should be noted that please refer to FIG. 5B and FIG. 5C , the direction indicated by the arrow X is the row direction X, which is perpendicular to the column direction Y in some examples. The light emitting device 232 of the third sub-pixel 230R in a row of first pixel units 220 can be arranged in a row. The light emitting device 232 of the second sub-pixel 230G in a row of first pixel units 220 can be arranged in a row. The light emitting device 232 of the first sub-pixel 230B in a row of first pixel units 220 can be arranged in a row. The gap region between the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R refers to the gap region between the light emitting device 232 of the third sub-pixel 230R in an adjacent row and the light emitting device 232 of the second sub-pixel 230G in a row.

[0182] The light emitting device 232 of the first sub-pixel 230B spans the gap region between the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R can also be understood as that the projection of the light emitting device 232 of the first sub-pixel 230B in the row direction X overlaps with the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R.

[0183] The arrangement of the sub-pixel 230 disclosed in some of the above embodiments can be referred to as "REAL pixel arrangement". By using the REAL pixel arrangement, the graininess can be reduced and the display effect can be improved in the case that the PPI (pixels per inch) of the display panel 200 is low (for example, lower than 400). The above display panel 200 can be applied to a watch device.

[0184] In some embodiments, referring to FIG. 5A , the pixel driving circuit 231 further comprises a circuit body 2311. For example, the circuit body 2311 of each sub-pixel 230 comprises a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a third reset transistor T7, and a capacitor Cst.

[0185] The normal projection of the circuit body 2311-B of the first sub-pixel 230B on the substrate 210 is within the normal projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210, the normal projection of the circuit body 2311-G of the second sub-pixel 230G on the substrate 210 is within the normal projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210, and the normal projection of the circuit body 2311-R of the third sub-pixel 230R on the substrate 210 is within the normal projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210.

[0186] In one sub-pixel 230, the light-emitting device 232 shields the circuit body 2311 to which it is electrically connected, so as to avoid the exposure of the circuit body 2311 to the light-emitting device 232 and reduce the diffraction phenomenon. At the same time, the light transmittance of the first display area A1 can be improved.

[0187] In other examples, referring to FIG. 5A , the normal projection of the circuit body 231 of each sub-pixel 230 on the substrate 210 is within the normal projection of the anode AND1 of the sub-pixel 230B on the substrate 210. For example, the normal projection of the circuit body 2311-B of the first sub-pixel 230B on the substrate 210 is within the normal projection of the anode AND-B of the first sub-pixel 230B on the substrate 210, the normal projection of the circuit body 2311-G of the second sub-pixel 230G on the substrate 210 is within the normal projection of the anode AND-G of the second sub-pixel 230G on the substrate 210, and the normal projection of the circuit body 2311-R of the third sub-pixel 230R on the substrate 210 is within the normal projection of the anode AND-R of the third sub-pixel 230R on the substrate 210. The anode AND1 of the sub-pixel 230B is not light-transmissive, and the shielding effect of each circuit body 23112 is good, thereby reducing the diffraction phenomenon when the sensor 300 takes a photo through the first display area A1.

[0188] In some examples, referring to FIG. 5A , the direction of the second sub-pixel 230G to the third sub-pixel 230 is the second specified direction C2, and the direction indicated by the arrow C2 is the second specified direction C2. The second specified direction C2 is parallel to the column direction Y.

[0189] In some embodiments, referring to FIG. 5D In a row of first pixel units 220, the second reset transistor T12 and the plurality of first reset transistors T11 are located on the side of the circuit body 2311-R of the third sub-pixel 230R away from the light emitting device 232 of the second sub-pixel 230G, and at this time, the direction of the circuit body 2311-R of the third sub-pixel 230R pointing to the second reset transistor T12 and the plurality of first reset transistors T11 is the second specified direction C2.

[0190] In some embodiments, referring to FIG. 5D The second reset transistor T12, the first reset transistor T11-R of the third sub-pixel 230R, and the first reset transistor T11-G of the second sub-pixel 230G are located on the side of the first reset transistor T11-B of the first sub-pixel 230B close to the circuit body 2311-R of the third sub-pixel 230R, and sequentially away from the circuit body 2311-R of the third sub-pixel 230R.

[0191] In some examples, in a first pixel unit 220, the direction of the third sub-pixel 230R pointing to the first sub-pixel 230B is the first specified direction C1, the direction indicated by the arrow C1 is the first specified direction C1, and the first specified direction C1 is parallel to the row direction X.

[0192] The second reset transistor T12, the first reset transistor T11-R of the third sub-pixel 230R, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-B of the first sub-pixel 230B are sequentially arranged along the first specified direction C1, so as to facilitate the electrical connection between the first reset transistor T11-R of the third sub-pixel 230R and the driving transistor T3 of the third sub-pixel 230R, and facilitate the electrical connection between the first reset transistor T11-G of the second sub-pixel 230G and the driving transistor T3 of the second sub-pixel 230G.

[0193] In some embodiments, referring to FIG. 5B and FIG. 5C The reset signal line RST extends along the row direction X, and one reset signal line RST is electrically connected to the control electrode of the second reset transistor T12 and the control electrode of each first reset transistor T11 in a row of first pixel units 220. Among them, FIG. 5B and FIG. 5C The second reset transistor T12 is not shown in FIG. 5A .

[0194] The pattern of the reset signal line RST can be a straight line pattern or an approximately straight line pattern. The "extending along the row direction X" of the reset signal line RST means that the main pattern of the reset signal line RST extends along a certain row direction X.

[0195] The second reset transistor T12 in the row of first pixel units 220, the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R receive the same reset signal. Therefore, the control electrodes of the driving transistors T3 in each sub-pixel 230 in the row of first pixel units 220 are reset at the same time.

[0196] Referring to FIG. 5B , the initialization signal line VIN extends along the row direction X. One initialization signal line VIN is electrically connected to the first electrode of the second reset transistor T12 in the row of first pixel units 220. FIG. 5B The second reset transistor T12 is not shown in FIG. 5A .

[0197] The pattern of the initialization signal line VIN can be a straight line pattern or an approximately straight line pattern. The "extending along the row direction X" of the initialization signal line VIN means that the main pattern of the initialization signal line VIN extends along a certain row direction X.

[0198] The initialization signal line VIN is used to transmit an initialization signal. The initialization signal is transmitted to each first reset transistor T11 through the second reset transistor T12, and then transmitted to the control electrode of the driving transistor T3 of each sub-pixel 230, so as to reset the control electrode of the driving transistor T3.

[0199] Referring to FIG. 5A , the orthographic projection of the second reset transistor T12 and each first reset transistor T11 on the substrate 210 is located between the orthographic projection of the initialization signal line VIN to which the second reset transistor T12 is electrically connected on the substrate 210 and the orthographic projection of the circuit main body 2311-R of the third sub-pixel 230R on the substrate 210. The orthographic projection of the reset signal line RST on the substrate 210 is located between the orthographic projection of the initialization signal line VIN on the substrate 210 and the orthographic projection of the circuit main body 2311-G of the third sub-pixel 230R on the substrate 210.

[0200] For the convenience of description, the second reset transistor T12 and each first reset transistor T11 are defined as the first type of reset transistor.

[0201] Referring to FIG. 5AThe circuit body 2311-R of the third sub-pixel 230R, the first type reset transistor, and the initialization signal line VIN are sequentially arranged along a second designated direction C2.

[0202] In a row of the first pixel units 220, the control electrodes of the second reset transistor T12 and each first reset transistor T11 are located on the reset signal line RST.

[0203] The position of the control electrode of the first reset transistor T11 in combination with the plurality of film layers in the display panel 200 is described below.

[0204] In some examples, referring to FIG. 5D The display panel 200 includes an active film layer 240 and a first gate metal layer Gate1 arranged on one side of the substrate 210, and the active film layer 240 and the first gate metal layer Gate1 are both located between the substrate 210 and the light-emitting device 232, and the first gate metal layer Gate1 is located on the side of the active film layer 240 away from the substrate 210. In some examples, a first gate insulating layer is arranged between the active film layer 240 and the first gate metal layer Gate1.

[0205] The active film layer 240 includes an active layer of each transistor in the pixel driving circuit 231, wherein the active layer of the transistor includes a first electrode region, a second electrode region, and a channel region connecting the first electrode region and the second electrode region.

[0206] For example, referring to FIG. 6A The active film layer 240 includes an active layer T12-P of the second reset transistor T12 and an active layer T11-P of each first reset transistor T11.

[0207] For example, referring to FIG. 6A The active layer T12-P of the second reset transistor T12 extends along the row direction X, and the active layer T11-P of each first reset transistor T11 extends along the column direction Y. One end of the active layer T12-P of the second reset transistor T12 away from the circuit body 2311-R of the third sub-pixel 230R is connected to one end of the active layer T11-P of each first reset transistor T11 away from the circuit body 2311-B of the first sub-pixel 230B.

[0208] The active layer T11-RP of the first reset transistor T11-R of the third sub-pixel 230R, the active layer T11-GP of the first reset transistor T11-G of the second sub-pixel 230G, and the active layer T11-BP of the first reset transistor T11-B of the first sub-pixel 230B are sequentially arranged along the first designated direction C1.

[0209] For example, referring to FIG. 6BThe first gate metal layer, Gate1, includes a reset signal line, RST. The reset signal line RST is located on the side of the active film layer 240 away from the substrate 210. (See also...) FIG. 5D The portion of the reset signal line RST that overlaps with the active layer T12-P of the second reset transistor T12 and the active layer T11-P of each first reset transistor T11 is multiplexed as the control electrode of the second reset transistor T12 and the control electrode of each first reset transistor T11.

[0210] In some embodiments, please refer to FIG. 2B The substrate 210 includes a first display area A1, and a plurality of first pixel units 220 are located within the first display area A1. The display panel 200 also includes a plurality of signal lines located between the substrate 210 and the light-emitting device 232. It should be noted that the first display area A1 in the substrate 210 and the first display area A1 in the display panel 200 are the same region. FIG. 2B The light-emitting device 232 is not shown in the figure; please refer to [reference needed]. FIG. 3A , FIG. 5A and FIG. 5B wait.

[0211] Please see FIG. 5B At least one signal line located within the first display area A1 includes a metal trace 250 and a transparent connection trace 260 electrically connected to each other. At least a portion of the metal trace 250's orthogonal projection onto the substrate 210 lies within the orthogonal projection of the light-emitting device 232 onto the substrate 210. For an example, please refer to... FIG. 5C The display panel 200 includes multiple signal lines such as reset signal line RST, scan signal line GT, light emission control signal line EM, initialization signal line VIN, first power signal line VDD1, and second power signal line VDD2.

[0212] In some examples, the orthographic projection of all metal traces 250 onto substrate 210 lies within the orthographic projection of light-emitting device 232 onto substrate 210.

[0213] In other examples, please refer to FIG. 5B The orthogonal projection of a portion of the metal traces 250 onto the substrate 210 lies within the orthogonal projection of the light-emitting device 232 onto the substrate 210, while the orthogonal projections of the remaining metal traces 250 onto the substrate 210 lie outside the orthogonal projection of the light-emitting device 232 onto the substrate 210.

[0214] For example, please refer to FIG. 5A and FIG. 5B The end of the metal trace 250 is provided with a metal connector 2501. (See also...) FIG. 5BThe end of the transparent connection wire 260 is provided with a transparent connection part 2601, and the orthogonal projection of the metal connection part 2501 on the substrate 210 at least partially overlaps the orthogonal projection of the transparent connection part 2601 on the substrate 210. In some examples, the orthogonal projection of the metal connection part 2501 on the substrate 210 is at least partially located within the orthogonal projection of the light emitting device 232 on the substrate 210. In other examples, the orthogonal projection of the metal connection part 2501 on the substrate 210 is entirely located outside the orthogonal projection of the light emitting device 232 on the substrate 210.

[0215] The metal wire 250 in the signal line can be connected through the transparent connection wire 260, and at least part of the transparent connection wire 260 is exposed outside the light emitting device 232, and the transparent connection wire 260 is a transparent wire and can transmit light. Therefore, by connecting the metal wire 250 through the transparent connection wire 260, the light transmittance of the first display area A1 can be improved.

[0216] In other examples, please refer to FIG. 5B At least part of the orthogonal projection of the metal wire 250 on the substrate 210 is located within the orthogonal projection of the anode AND1 of the sub-pixel 230 on the substrate 210.

[0217] The reset signal line RST, the scan signal line GT, the light emitting control signal line EM, the initialization signal line VIN, the first power signal line VDD1 and the second power signal line VDD2 will be introduced in turn below.

[0218] In some embodiments, please refer to FIG. 7A The display panel 200 includes a first transparent wire layer 271, the first transparent wire layer 271 is located between the substrate 210 and the light emitting device 232, and the first transparent wire layer 271 is located on the side of the first gate metal layer Gate1 away from the substrate 210.

[0219] In some examples, the material of the first gate metal layer Gate1 is metal, such as Al, Ag, Cu, Cr, etc. The material of the first transparent wire layer 271 is transparent conductive oxide material, such as ITO, IZO, etc.

[0220] Please refer to FIG. 7B The reset signal line RST includes a metal wire 251 and a transparent connection wire 261. The metal wire 251 of the reset signal line RST is located on the first gate metal layer Gate1, and at least part of the orthogonal projection of the metal wire 251 of the reset signal line RST on the substrate 210 is located within the orthogonal projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210. In some examples, the metal wire 251 of the reset signal line RST is located on the first gate metal layer Gate1, and the orthogonal projection of the metal wire 251 of the reset signal line RST on the substrate 210 is entirely located within the orthogonal projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210. FIG. 7B The light emitting device 232 of the first sub-pixel 230B is not shown in the aboveFIG. 5B .

[0221] The reset signal line RST includes a plurality of metal wires 251, and at least part of a metal wire 251 is located below the light emitting device 232 of the first sub-pixel 230B. In some examples, all of the metal wires 251 are located below the light emitting device 232 of a first sub-pixel 230B. In other examples, part of the metal wire 251 is located below the light emitting device 232 of a first sub-pixel 230B.

[0222] Referring to FIG. 6B , the metal wire 251 in the reset signal line RST includes a main wire segment 2511 and a connection wire segment 2512. The main wire segment 2511 extends in the row direction X and overlaps the active layer T11-P of each first reset transistor T11, and the control electrode of the first reset transistor T11 is located on the main wire segment 2511. The connection wire segment 2512 extends in the column direction Y and overlaps the active layer T12-P of the second reset transistor T12. The part of the connection wire segment 2512 that overlaps the active layer T12-P of the second reset transistor T12 is the control electrode of the second reset transistor T12, i.e. the control electrode of the second reset transistor T12 is located on the connection wire segment 2512. Wherein, FIG. 6B The active layer T12-P of the second reset transistor T12 is not shown in FIG. 5D and FIG. 6A .

[0223] Referring to FIG. 7B , the transparent connection wire 261 of the reset signal line RST is located in the first transparent wire layer 271, and the transparent connection wire 261 of the reset signal line RST is connected to the metal wire 251 of the reset signal line RST through a via.

[0224] Wherein, the orthogonal projection of the transparent connection wire 261 of the reset signal line RST on the substrate 210 is located outside the orthogonal projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210, and is located outside the orthogonal projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210. Therefore, the transparent connection wire 261 of the reset signal line RST does not occupy the space below the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R, thereby increasing the area of the pixel driving circuit 231 below the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R, and avoiding the structure of the pixel driving circuit 231 below the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R from being too compact and coupling. Wherein, FIG. 7BThe light emitting device 232 of the third sub-pixel 230R is not shown in FIG. 2A, and please refer to FIG. 5A and FIG. 5B. FIG. 5B .

[0225] In some examples, please refer to FIG. 2A and FIG. 2B, FIG. 7B at least part of the orthogonal projection of the metal trace 251 of the reset signal line RST on the substrate 210 is within the orthogonal projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. The orthogonal projection of the transparent connection trace 261 of the reset signal line RST on the substrate 210 is outside the orthogonal projection of the anode AND-G of the second sub-pixel 230G on the substrate 210, and outside the orthogonal projection of the anode AND-R of the third sub-pixel 230R on the substrate 210. Wherein, FIG. 7B The anode AND1 of each sub-pixel 230 is not shown in FIG. 2A, and please refer to FIG. 5A and FIG. 5B. FIG. 5B .

[0226] In some examples, please refer to FIG. 2A and FIG. 2B, FIG. 5D The main body 2311 of the pixel driving circuit 231 includes a write transistor T4, a compensation transistor T2, and a third reset transistor T7.

[0227] The at least one signal line further includes a scan signal line GT. One scan signal line GT is electrically connected to the control electrodes of the write transistors T4, the control electrodes of the compensation transistors T2, and the control electrodes of the third reset transistors T7 of all the sub-pixels 230 in one row of the first pixel units 220.

[0228] The scan signal line GT is used for transmitting a scan signal. All the sub-pixels 230 in one row of the first pixel units 220 receive the same scan signal. The write transistors T4, the compensation transistors T2, and the third reset transistors T7 in one row of the first pixel units 220 are turned on at the same time.

[0229] Please refer to FIG. 2A and FIG. 2B, FIG. 7B The metal trace 252 of the scan signal line GT is located in the first gate metal layer Gate1. At least part of the orthogonal projection of the metal trace 252 of the scan signal line GT on the substrate 210 is within the orthogonal projection of the light emitting device 232 on the substrate 210. The transparent connection trace 262 of the scan signal line GT is located in the first transparent trace layer 271. The transparent connection trace 262 of the scan signal line GT is connected to the metal trace 252 of the scan signal line GT through a via.

[0230] Please refer to FIG. 2A and FIG. 2B, FIG. 7BThe scan signal line GT includes a plurality of metal traces 252. A normal projection of one of the metal traces 252 on the substrate 210 is at least partially within a normal projection of one of the light emitting devices 232 on the substrate 210. In some examples, all of the metal traces 252 are disposed under the light emitting devices 232. In other examples, some of the metal traces 252 are disposed under the light emitting devices 232.

[0231] In some examples, referring to FIG. 7B A normal projection of the metal traces 252 of the scan signal line GT on the substrate 210 is at least partially within a normal projection of the anode AND1 of the sub-pixel 230 on the substrate 210.

[0232] In some examples, referring to FIG. 5D One of the metal traces 252 of the scan signal line GT is electrically connected to the control electrode of the write transistor T4, the control electrode of the compensation transistor T2 and the control electrode of the third reset transistor T7 in one of the sub-pixels 230.

[0233] In some examples, referring to FIG. 6A The active film layer 240 includes the active layer T4-P of the write transistor T4, the active layer T2-P of the compensation transistor T2 and the active layer T7-P of the third reset transistor T7.

[0234] In some examples, referring to FIG. 5D The overlapping part of one of the metal traces 252 and the active layer T4-P of the write transistor T4 is multiplexed as the control electrode of the write transistor T4. The overlapping part of one of the metal traces 252 and the active layer T2-P of the compensation transistor T2 is multiplexed as the control electrode of the compensation transistor T2. The overlapping part of one of the metal traces 252 and the active layer T7-P of the third reset transistor T7 is multiplexed as the control electrode of the third reset transistor T7. That is, the control electrode of the write transistor T4, the control electrode of the compensation transistor T2 and the control electrode of the third reset transistor T7 in one of the sub-pixels 230 are located on one of the metal traces 252.

[0235] In some examples, referring to FIG. 4A and FIG. 5D The compensation transistor T2 of each of the sub-pixels 230 includes a first compensation transistor T21 and a second compensation transistor T22. The first compensation transistor T21 and the second compensation transistor T22 are connected in series.

[0236] The control electrode of the first compensation transistor T21 is electrically connected to the scan signal line GT. The first electrode of the first compensation transistor T21 is electrically connected to the second electrode of the drive transistor T3 and the first electrode of the second light emitting control transistor T6. The second electrode of the first compensation transistor T21 is electrically connected to the first electrode of the second compensation transistor T22.

[0237] The control electrode of the second compensation transistor T22 is electrically connected with the scan signal line GT, and the second electrode of the second compensation transistor T22 is electrically connected with the second electrode of the first reset transistor T11 and the control electrode of the driving transistor T3.

[0238] By setting the compensation transistor T2 as the first compensation transistor T21 and the second compensation transistor T22 in series, the effect of preventing leakage current can be achieved.

[0239] Based on the example that the compensation transistor T2 includes the first compensation transistor T21 and the second compensation transistor T22, please refer to FIG. 6B The metal trace 252 of the scan signal line GT includes a main trace segment 2521 and a connection trace segment 2522. The main trace segment 2521 extends along the row direction X, and the connection trace segment 2522 extends along the column direction and is connected with the main trace segment 2521 at one end. The overlapping part of the connection trace segment 2522 and the active layer T2-P of the compensation transistor T2 is multiplexed as the control electrode of the second compensation transistor T22. The overlapping parts of the main trace segment 2521 and the active layers T4-P of the write transistor T4, T2-P of the compensation transistor T2, and T7-P of the third reset transistor T7 are multiplexed as the control electrode of the write transistor T4, the control electrode of the first compensation transistor T21, and the control electrode of the third reset transistor T7, respectively. In FIG. 6B , the active layers of the various transistors are not shown, please refer to FIG. 5D and FIG. 6A .

[0240] In some examples, please refer to FIG. 7C The scan signal line GT includes multiple metal trace segments 252 and multiple transparent connection trace segments 262. The multiple metal trace segments 252 include a first metal trace segment 252A, a second metal trace segment 252B, and a third metal trace segment 252C. In FIG. 7C , the metal trace segments 252 and the multiple transparent connection trace segments 262 are not shown, please refer to FIG. 7B .

[0241] The orthographic projection of the first metal trace segment 252A on the substrate 210 is at least partially within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0242] The orthographic projection of the second metal trace segment 252B on the substrate 210 is at least partially within the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210.

[0243] The third segment metal trace 252C is in the orthographic projection of the substrate 210 at least partially within the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210.

[0244] In some examples, referring to FIG. 7C The display panel 200 further includes a second transparent trace layer 272. The second transparent trace layer 272 is located on the side of the first transparent trace layer 271 away from the substrate 210, or on the side of the first transparent trace layer 271 toward the substrate 210.

[0245] The plurality of segment transparent connection traces 262 in a scan signal line GT includes a first segment transparent connection trace 262A, a second segment transparent connection trace 262B, a third segment transparent connection trace 262C, and a fourth segment transparent connection trace 262D. Among them, the first segment transparent connection trace 262A, the second segment transparent connection trace 262B, and the third segment transparent connection trace 262C are located in the first transparent trace layer 271. And the fourth segment transparent connection trace 262D is located in the second transparent trace layer 272.

[0246] Among them, the first segment metal trace 252A electrically connected to the first sub-pixel 230B in each first pixel unit 220 and the third segment metal trace 252C electrically connected to the third sub-pixel 230R are electrically connected through the first segment transparent connection trace 262A.

[0247] The first segment metal trace 252A electrically connected to the first sub-pixel 230B in a first pixel unit 220 and the third segment metal trace 252C electrically connected to the third sub-pixel 230R in the first pixel unit 220 adjacent in the row direction X are electrically connected through the second segment transparent connection trace 262B.

[0248] One end of the third segment transparent connection trace 262C is electrically connected to the end of the second segment metal trace 252B away from the first sub-pixel 230B, and the other end is electrically connected to the fourth segment transparent connection trace 262D. The end of the fourth segment transparent connection trace 262D away from the third segment transparent connection trace 262C is electrically connected to the second segment transparent connection trace 262B.

[0249] In some embodiments, referring to FIG. 5D The circuit body 2311 of the pixel driving circuit 231 further includes a first light emitting control transistor T5 and a second light emitting control transistor T6. The at least one signal line further includes a light emitting control signal line EM. One light emitting control signal line EM is electrically connected to the control electrode of the first light emitting control transistor T5 and the control electrode of the second light emitting control transistor T6 of all sub-pixels 230 in a row of first pixel units 220.

[0250] The light emitting control signal line EM is used to transmit a light emitting control signal, and all the sub-pixels 230 in a row of the first pixel units 220 receive the same light emitting control signal. The first light emitting control transistor T5 and the second light emitting control transistor T6 in a row of the first pixel units 220 are turned on at the same time.

[0251] Please refer to FIG. 7B and FIG. 7C , the metal wire 253 of the light emitting control signal line EM is located in the first gate metal layer Gate1. At least part of the orthogonal projection of the metal wire 253 of the light emitting control signal line EM on the substrate 210 is located within the orthogonal projection of the light emitting device 232 on the substrate 210. The transparent connection wire 263 of the light emitting control signal line EM is located in the first transparent wire layer 271, and the transparent connection wire 263 of the light emitting control signal line EM is connected with the metal wire 253 of the light emitting control signal line EM through a via. Among them, FIG. 7B and FIG. 7C , the light emitting device 232 is not shown in FIG. 5A .

[0252] In other examples, please refer to FIG. 5A , at least part of the orthogonal projection of the metal wire 253 of the light emitting control signal line EM on the substrate 210 is located within the orthogonal projection of the anode AND1 of the sub-pixel 230 on the substrate 210.

[0253] Please refer to FIG. 7B and FIG. 7C , the light emitting control signal line EM includes a plurality of metal wires 253, and the orthogonal projection of one of the metal wires 253 on the substrate 210 is at least partially located within the orthogonal projection of one of the light emitting devices 232 on the substrate 210. In some examples, all of each metal wire 253 is disposed under the light emitting device 232. In other examples, part of each metal wire 253 is disposed under the light emitting device 232.

[0254] In some examples, please refer to FIG. 5A , one of the metal wires 253 in the light emitting control signal line EM is electrically connected with the control electrode of the first light emitting control transistor T5 and the control electrode of the second light emitting control transistor T6 in one of the sub-pixels 230.

[0255] In some examples, please refer to FIG. 6A , the active film layer 240 includes the active layer T5-P of the first light emitting control transistor T5 and the active layer T6-P of the second light emitting control transistor T6.

[0256] Among them, please refer to FIG. 5DThe overlapping part of the metal wire 253 and the active layer T5-P of the first light emitting control transistor T5 is reused as the control electrode of the first light emitting control transistor T5. The overlapping part of the metal wire 253 and the active layer T6-P of the second light emitting control transistor T6 is reused as the control electrode of the second light emitting control transistor T6. That is, the control electrode of the first light emitting control transistor T5 and the control electrode of the second light emitting control transistor T6 in one sub-pixel 230 are located on the metal wire 252.

[0257] In some examples, referring to FIG. 6A The active film layer 240 further includes the active layer T3-P of the driving transistor T3, referring to FIG. 6B The second plate Cst2 of the capacitor Cst is further included in the first gate metal layer Gate1, referring to FIG. 5D The orthographic projection of the second plate Cst2 on the substrate 210 partially overlaps with the orthographic projection of the active layer T3-P of the driving transistor T3 on the substrate 210, wherein the overlapping part of the second plate Cst2 and the active layer T3-P of the driving transistor T3 is reused as the control electrode of the driving transistor T3.

[0258] In some examples, referring to FIG. 7C The light emitting control signal line EM includes a plurality of metal wires 253 and a plurality of transparent connection wires 263. The plurality of metal wires 253 includes a fourth metal wire 253D, a fifth metal wire 253E and a sixth metal wire 253F. The fourth metal wire 253D is located on the first transparent wire layer 271, the fifth metal wire 253E is located on the second transparent wire layer 272, and the sixth metal wire 253F is located on the third transparent wire layer 273. FIG. 7C The light emitting control signal line EM, the metal wire 253 and the transparent connection wire 263 are not shown in FIG. 7B .

[0259] The orthographic projection of the fourth metal wire 253D on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0260] The orthographic projection of the fifth metal wire 253E on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210.

[0261] The orthographic projection of the sixth metal wire 253F on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210.

[0262] Referring to FIG. 7B The plurality of transparent connection wires 263 in the light emitting control signal line EM includes a fifth transparent connection wire 263E, a sixth transparent connection wire 263F and a seventh transparent connection wire 263G, and they are all located on the first transparent wire layer 271.

[0263] Referring to FIG. 7B The fourth metal trace 253D electrically connected to the first sub-pixel 230B in the first pixel unit 220 and the sixth metal trace 253F electrically connected to the third sub-pixel 230R are electrically connected through the fifth transparent connection trace 263E.

[0264] The fourth metal trace 253D electrically connected to the first sub-pixel 230B in the first pixel unit 220 and the sixth metal trace 253F electrically connected to the third sub-pixel 230R in the first pixel unit 220 adjacent to the first pixel unit 220 in the first specified direction C1 are electrically connected through the sixth transparent connection trace 263F.

[0265] One end of the seventh transparent connection trace 263G is electrically connected to the fifth metal trace 253E electrically connected to the second sub-pixel 230G away from the first sub-pixel 230B, and the other end is electrically connected to the sixth transparent connection trace 263F.

[0266] In addition to the first gate metal layer Gate1, in some embodiments, referring to FIG. 8A and FIG. 8B The display panel 200 further comprises a second gate metal layer Gate2 between the active film layer 240 and the light emitting device 232.

[0267] In some examples, the material of the second gate metal layer Gate2 is metal, such as Al, Ag, Cu, Cr, etc.

[0268] Referring to FIG. 8A and FIG. 8B The circuit body 2311 of the pixel driving circuit 231 further comprises a capacitor Cst, and a first plate Cst1 of the capacitor Cst is located at the second gate metal layer Gate2.

[0269] In some examples, referring to FIG. 8B The second gate metal layer Gate2 is located on the side of the first gate metal layer Gate1 away from the substrate 210. Wherein, the first plate Cst1 of the capacitor Cst, and the orthographic projection of the first plate Cst1 on the substrate 210 and the orthographic projection of the second plate Cst2 on the substrate 210 at least partially overlap.

[0270] In some embodiments, referring to FIG. 9A and FIG. 9BThe display panel 200 comprises a first source-drain metal layer SD1, the first source-drain metal layer SD1 is located between the substrate 210 and the light emitting device 232, the first source-drain metal layer SD1 is located on a side of the second gate metal layer Gate1 away from the substrate 210, the first transparent wiring layer 271 is located on a side of the first source-drain metal layer SD1 away from the substrate 210, and the first transparent wiring layer 271 is located between the first source-drain metal layer SD1 and the light emitting device 232. Wherein, please refer to FIG. 9C The second gate metal layer Gate1 and the first source-drain metal layer SD1 are provided with an interlayer dielectric layer ILD, and a plurality of vias ILDO are provided in the interlayer dielectric layer ILD, wherein the positions of the plurality of vias in the interlayer dielectric layer ILD are as shown in FIG. FIG. 9C .

[0271] In some examples, the material of the first source-drain metal layer SD1 is metal, such as Al, Ag, Cu, Cr, etc.

[0272] Please refer to FIG. 7B and FIG. 7C The at least one signal line further comprises an initialization signal line VIN, and one initialization signal line VIN is electrically connected to the first electrode of the second reset transistor T12 in one row of the first pixel units 220. Wherein, the metal wiring 254 of the initialization signal line VIN is located in the first source-drain metal layer SD1. Please refer to FIG. 5A At least part of the orthographic projection of the metal wiring 254 of the initialization signal line VIN on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0273] In some examples, one initialization signal line VIN comprises a plurality of metal wirings 254, and one metal wiring 254 overlaps with the light emitting device 232 of one first sub-pixel 230B.

[0274] In some examples, one metal wiring 254 of the initialization signal line VIN is entirely arranged under the light emitting device 232 of the first sub-pixel 230B.

[0275] In another example, part of one metal wiring 254 of the initialization signal line VIN is arranged under the light emitting device 232 of the first sub-pixel 230B. At this time, the transparent connection wiring 264 of the initialization signal line VIN is partially located under the light emitting device 232 of the first sub-pixel 230B.

[0276] Please refer to FIG. 7BThe transparent connection wire 264 of the initialization signal line VIN is located on the first transparent wire layer 271; the transparent connection wire 264 of the initialization signal line VIN is connected with the metal wire 254 of the initialization signal line VIN through the via. The orthographic projection of the transparent connection wire 264 of the initialization signal line VIN on the substrate 210 is located outside the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210 and outside the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210. Therefore, the transparent connection wire 264 of the initialization signal line VIN does not occupy the space below the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R, thereby increasing the area of the pixel driving circuit 231 below the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R, so as to avoid the structure of the pixel driving circuit 231 below the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R being too compact to be coupled. Wherein, FIG. 7B The light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R are not shown in the FIG. 5B .

[0277] In other examples, please refer to FIG. 5A The orthographic projection of the metal wire 254 of the initialization signal line VIN on the substrate 210 is at least partially located within the orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. The orthographic projection of the transparent connection wire 264 of the initialization signal line VIN on the substrate 210 is located outside the orthographic projection of the anode AND-G of the second sub-pixel 230G on the substrate 210 and outside the orthographic projection of the anode AND-R of the third sub-pixel 230R on the substrate 210.

[0278] In some examples, please refer to FIG. 5A and FIG. 9A The metal wire 254 of the initialization signal line VIN includes a main wire segment 2541 and a connection wire segment 2542, wherein the main wire segment 2541 extends along the row direction X, and the connection wire segment 2542 extends along the column direction Y, and one end of the main wire segment 2541 close to the third sub-pixel 230R is connected with the connection wire segment 2542.

[0279] Please refer to FIG. 5A One end of the connection wire segment 2542 away from the main wire segment 2541 is connected with the active layer T7-P of the third reset transistor T7 in the first sub-pixel 230B through the via.

[0280] In some examples, referring to FIG. 7B The display panel 200 further includes a first transparent connecting line 281 located in the first transparent trace layer 271, one end of the first transparent connecting line 281 being electrically connected to the end of the connecting trace segment 2542 away from the main body trace segment 2541, and the other end being electrically connected to the active layer T7-P of the third reset transistor T7 in the third sub-pixel 230R.

[0281] In some examples, referring to FIG. 7C The display panel 200 further includes a second transparent connecting line 282 and a third transparent connecting line 283, wherein the second transparent connecting line 282 is located in the first transparent trace layer 271, and the third transparent connecting line 283 is located in the second transparent trace layer 272. One end of the second transparent connecting line 282 is electrically connected to the active layer T7-P of the third reset transistor T7 in the second sub-pixel 230G, and the other end is electrically connected to the third transparent connecting line 283, and the third transparent connecting line 283 is connected to the one end of the connecting trace segment 2542 through a via.

[0282] Referring to FIG. 7B The display panel 200 further includes a fourth transparent connecting line 284 and a fifth transparent connecting line 285, wherein the fourth transparent connecting line 284 and the fifth transparent connecting line 285 are both located in the first transparent trace layer 271.

[0283] One end of the fifth transparent connecting line 285 is electrically connected to the active layer T11-GP of the first reset transistor T11-G in the second sub-pixel 230G, and the other end is electrically connected to the control electrode of the driving transistor T3 in the second sub-pixel 230G, that is, the second plate Cst2 of the capacitor Cst.

[0284] One end of the fourth transparent connecting line 284 is electrically connected to the active layer T11-RP of the first reset transistor T11-R in the third sub-pixel 230R, and the other end is electrically connected to the control electrode of the driving transistor T3 in the third sub-pixel 230R, that is, the second plate Cst2 of the capacitor Cst.

[0285] In addition to the metal trace 254 in the initialization signal line VIN, the first source-drain metal layer SD1 further includes a plurality of bridge patterns, which are connected to the active film layer 240, the first gate metal layer Gate1 and the second gate metal layer Gate2 through vias.

[0286] In some examples, referring to FIG. 9A and FIG. 9BThe first bridge pattern 510 is connected to the active layer T6-P of the second light-emitting control transistor T6 at one end and connected to the active layer T7-P of the third reset transistor T7 at the other end.

[0287] In some examples, referring to FIG. 9A and FIG. 9B The second bridge pattern 520 is connected to the control electrode of the driving transistor T3, i.e., the second plate Cst2 of the capacitor Cst, at one end and connected to the active layer T2-P of the compensation transistor T2 at the other end.

[0288] In some examples, referring to FIG. 9A and FIG. 9B The third bridge pattern 530 is connected to the first plate Cst1 of the capacitor Cst at one end and connected to the active layer T5-P of the first light-emitting control transistor T5 at the other end.

[0289] In some other examples, the orthographic projection of the plurality of bridge patterns on the substrate 210 is also located within the orthographic projection of the anode AND1 on the substrate 210.

[0290] In some embodiments, referring to FIG. 10A and FIG. 10B The display panel 200 comprises a second source-drain metal layer SD2, which is located between the substrate 210 and the light-emitting device 232 and is located on the side of the second gate metal layer Gate2 away from the substrate 210.

[0291] Referring to FIG. 11A and FIG. 11B The display panel 200 further comprises a second transparent wiring layer 272, which is located between the substrate 210 and the light-emitting device 232 and is located on the side of the second source-drain metal layer SD2 away from the second gate metal layer Gate2.

[0292] In some examples, the second source-drain metal layer SD2 is located on the side of the first source-drain metal layer SD1 away from the substrate 210. The material of the second source-drain metal layer SD2 is metal, such as Al, Ag, Cu, Cr, etc. The material of the second transparent wiring layer 272 is transparent conductive oxide material, such as ITO, IZO, etc.

[0293] In the case that the first source-drain metal layer SD1 and the first transparent trace layer 271 are further included in the display panel 200, in some examples, the first source-drain metal layer SD1, the second source-drain metal layer SD2, the first transparent trace layer 271 and the second transparent trace layer 272 are sequentially arranged on the side of the second gate metal layer Gate2 away from the substrate 210.

[0294] In other examples, the first source-drain metal layer SD1, the first transparent trace layer 271, the second source-drain metal layer SD2 and the second transparent trace layer 272 are sequentially arranged on the side of the second gate metal layer Gate2 away from the substrate 210. Please refer to FIG. 11C A passivation layer PVX is arranged between the first source-drain metal layer SD1 and the first transparent trace layer 271, and a plurality of via holes PVXO are arranged in the passivation layer PVX. Please refer to FIG. 11D A first planarization layer PLN1 is arranged between the first transparent trace layer 271 and the second source-drain metal layer SD2, and a plurality of via holes PLNO1 are arranged in the first planarization layer PLN1. Please refer to FIG. 11E A second planarization layer PLN2 is arranged between the second source-drain metal layer SD2 and the second transparent trace layer 272, and a plurality of via holes PLNO2 are arranged in the second planarization layer PLN2.

[0295] Please refer to FIG. 11B The at least one signal line further includes a first power signal line VDD1, the first power signal line VDD1 extends along the column direction Y, and one first power signal line VDD1 is electrically connected with the first plate Cst1 of the capacitor Cst of the second sub-pixel 230G and the first plate Cst1 of the capacitor Cst of the third sub-pixel 230R in one column of the first pixel units 220.

[0296] The first power signal line VDD1 extends along the column direction Y means that the main pattern of the first power signal line VDD1 tends to extend along a certain column direction Y. The pattern of the first power signal line VDD1 can be a straight line pattern or an approximately straight line pattern.

[0297] The first power signal line VDD1 is used for transmitting a first type of power signal. The first power signal line VDD1 is electrically connected with the first plate Cst1 of the capacitor Cst, so as to transmit the first type of power signal to the first plate Cst1.

[0298] Please refer to FIG. 11BThe metal trace 255 of the first power signal line VDD1 is located on the second source-drain metal layer SD2, and at least part of the orthogonal projection of the metal trace 255 of the first power signal line VDD1 on the substrate 210 is located within the orthogonal projection of the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R on the substrate 210. The transparent connection trace 265 of the first power signal line VDD1 is located on the second transparent trace layer 272, and the transparent connection trace 265 of the first power signal line VDD1 is connected to the metal trace 255 of the first power signal line VDD1 through a via. Among them, FIG. 11B The light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R are not shown in FIG. 8, and can be referred to in FIG. 5C .

[0299] In some other examples, please refer to FIG. 11B At least part of the orthogonal projection of the metal trace 255 of the first power signal line VDD1 on the substrate 210 is located within the orthogonal projection of the anode AND-G of the second sub-pixel 230G and the anode AND-R of the third sub-pixel 230R on the substrate 210. FIG. 11B The anode AND-G of the second sub-pixel 230G and the anode AND-R of the third sub-pixel 230R are not shown in FIG. 8, and can be referred to in FIG. 5C .

[0300] In some examples, please refer to FIG. 11B The first power signal line VDD1 includes a plurality of metal traces 255, wherein the plurality of metal traces 255 of the first power signal line VDD1 includes a seventh metal trace 255G and an eighth metal trace 255H.

[0301] In some examples, the orthogonal projection of the seventh metal trace 255G on the substrate 210 is entirely located within the orthogonal projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210. The orthogonal projection of the eighth metal trace 255H on the substrate 210 is entirely located within the orthogonal projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210. At this time, the seventh metal trace 255G and the eighth metal trace 255H are electrically connected through the transparent connection trace 265, and the transparent connection trace 265 extends below the light-emitting device 232 of the third sub-pixel 230R and below the light-emitting device 232 of the second sub-pixel 230G.

[0302] In other examples, a portion of the seventh segment metal trace 255G that is within the footprint of the light emitting device 232 of the second sub-pixel 230G on the substrate 210, and a remaining portion of the seventh segment metal trace 255G that is outside the footprint of the light emitting device 232 of the second sub-pixel 230G on the substrate 210. A portion of the eighth segment metal trace 255H that is within the footprint of the light emitting device 232 of the third sub-pixel 230R on the substrate 210, and a remaining portion of the eighth segment metal trace 255H that is outside the footprint of the light emitting device 232 of the third sub-pixel 230R on the substrate 210.

[0303] In some examples, referring to FIG. 11B , the first power signal line VDD1 includes a plurality of segment transparent connection traces 265, and the plurality of segment transparent connection traces 265 includes an eighth segment transparent connection trace 265H and a ninth segment transparent connection trace 265I.

[0304] In a first pixel unit 220, the seventh segment metal trace 255G electrically connected to the second sub-pixel 230G is electrically connected to the eighth segment metal trace 255H electrically connected to the third sub-pixel 230R through the eighth segment transparent connection trace 265H.

[0305] In a first pixel unit 220, the eighth segment metal trace 255H electrically connected to the third sub-pixel 230R is electrically connected to the seventh segment metal trace 255G electrically connected to the second sub-pixel 230G in the first pixel unit 220 adjacent to the first pixel unit 220 in the second specified direction C2 through the ninth segment transparent connection trace 265I.

[0306] In some examples, referring to FIG. 12A , the seventh segment metal trace 255G of the first power signal line VDD1 is connected to the third bridge pattern 530 under the light emitting device 232 of the second sub-pixel 230G through a via, so as to transmit the first type of power signal line to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light emitting control transistor T5 in the second sub-pixel 230G through the third bridge pattern 530.

[0307] In some examples, referring to FIG. 12B , the eighth segment metal trace 255H of the first power signal line VDD1 is connected to the third bridge pattern 530 under the light emitting device 232 of the third sub-pixel 230R through a via, so as to transmit the first type of power signal line to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light emitting control transistor T5 in the third sub-pixel 230R through the third bridge pattern 530.

[0308] In some embodiments, referring to FIG. 11BThe at least one signal line further includes a second power signal line VDD2 extending along the column direction Y, and one second power signal line VDD2 is electrically connected with the first plate Cst1 of the capacitor Cst of the first sub-pixel 230B in one column of the first pixel units 220.

[0309] The second power signal line VDD2 extends along the column direction Y, which means that the main pattern of the second power signal line VDD2 has a trend of extending along the column direction Y. The pattern of the second power signal line VDD2 can be a straight line pattern or an approximately straight line pattern.

[0310] The second power signal line VDD2 is used for transmitting the first type of power signal. The second power signal line VDD2 is electrically connected with the first plate Cst1 of the capacitor Cst of the first sub-pixel 230B, so as to transmit the first type of power signal to the first plate Cst1 of the first sub-pixel 230B.

[0311] Please refer to FIG. 11B The metal trace 256 of the second power signal line VDD2 is located in the second source-drain metal layer SD2, and the orthogonal projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is at least partially located within the orthogonal projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210; the transparent connection trace 266 of the second power signal line VDD2 is located in the second transparent trace layer 272, and the transparent connection trace 266 of the second power signal line VDD2 is connected with the metal trace 256 of the second power signal line VDD2 through a via. Among them, FIG. 11B The light-emitting device 232 of the first sub-pixel 230B is not shown in FIG. 5C .

[0312] In some examples, the orthogonal projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is entirely located within the orthogonal projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210. At this time, the orthogonal projection of the transparent connection trace 266 of the second power signal line VDD2 on the substrate 210 partially overlaps with the orthogonal projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0313] In other examples, the orthogonal projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is partially located within the orthogonal projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210.

[0314] In other examples, the orthogonal projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is at least partially located within the orthogonal projection of the AND-B of the first sub-pixel 230B on the substrate 210.

[0315] In some examples, referring to FIG. 12C The metal trace 256 of the second power signal line VDD2 is connected to the third bridge pattern 530 under the light emitting device 232 of the first sub-pixel 230B through a via, so as to transmit the first type of power signal to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light emitting control transistor T5 in the first sub-pixel 230B through the third bridge pattern 530.

[0316] The reset signal line RST, the scan signal line GT, the light emitting control signal line EM, the first power signal line VDD1 and the second power signal line VDD2 in the display panel 200 are introduced above. In addition to the above-mentioned signal lines, the display panel 200 also includes a data line DT. In some embodiments, referring to FIG. 11B The display panel 200 further includes: a plurality of data lines DT, the plurality of data lines DT extending along the column direction Y.

[0317] Wherein, the data line DT extends along the column direction Y, which means that the main pattern of the data line DT has a trend of extending along a certain column direction Y. The data line DT pattern can be a straight line pattern, or an approximately straight line pattern.

[0318] Referring to FIG. 11B The orthographic projection of the part of the plurality of data lines DT in the first display area A1 on the substrate 210 is located outside the orthographic projection of the light emitting device 232 of any sub-pixel 230 on the substrate 210.

[0319] Therefore, the data line DT does not occupy the space under the light emitting device 232, thereby increasing the space occupied by the pixel driving circuit 231 under the light emitting device 232, and avoiding the structure of the pixel driving circuit 231 under the light emitting device 232 being too compact.

[0320] Wherein, the part of the at least one data line DT in the first display area A1 is located on the second transparent trace layer 272. Wherein, the part of the data line DT in the first display area A1 is arranged on the second transparent trace layer 272, and the part of the data line DT in the first display area A1 will not block light, thereby improving the light transmittance of the first display area A1 in the display panel 200.

[0321] Referring to FIG. 7C The circuit main body 2311 of the pixel driving circuit 231 includes: a write transistor T4. In a first pixel unit 220, the first electrode of the write transistor T4 of the first sub-pixel 230B, the first electrode of the write transistor T4 of the second sub-pixel 230G and the first electrode of the write transistor T4 of the third sub-pixel 230R are respectively connected to different data lines DT. Wherein, FIG. 7CThe write transistor T4 of the first sub-pixel 230B, the first electrode of the write transistor T4 of the second sub-pixel 230G, and the write transistor T4 of the third sub-pixel 230R are not shown in FIG. 2, and can be referred to in the description of FIG. 3. FIG. 5D .

[0322] The data line DT is used to transmit a data signal. In each sub-pixel 230, the first electrode of the write transistor T4 is electrically connected to the data line DT, so that the data signal can be transmitted to the first electrode of the write transistor T4. In one first pixel unit 220, the plurality of sub-pixels 230 are respectively connected to different data lines DT, and the voltages of the data signals in different data lines DT can be different, so that the light emitting devices 232 in different sub-pixels 230 can have different gray scales.

[0323] In addition, in some embodiments described above, in one first pixel unit 220, the first reset transistor T11 and the second reset transistor T12 in the plurality of sub-pixels 230 are simultaneously turned on, so that the pixel driving circuits 231 in the plurality of sub-pixels 230 are simultaneously in the reset stage. The compensation transistor T2, the write transistor T4, and the third reset transistor T7 are simultaneously turned on, so that the pixel driving circuits 231 in the plurality of sub-pixels 230 are simultaneously in the data refresh and compensation stage t2. In the data refresh and compensation stage t2, the data signal is written into the control electrode of the driving transistor T3 through the write transistor T4 and the compensation transistor T2, so that the data signal is simultaneously written into the pixel driving circuits 231 in one first pixel unit 220. The first light emitting control transistor T5 and the second light emitting control transistor T6 are simultaneously turned on, so that the pixel driving circuits 231 in the plurality of sub-pixels 230 are simultaneously in the light emitting stage t3. In summary, in one first pixel unit 220, the plurality of sub-pixels 230 emit light simultaneously.

[0324] In some embodiments, referring to FIG. 7C At least one data line DT in the first display area A1 is a transparent wiring segment 27.

[0325] The transparent wiring segment 27 is located in the second transparent wiring layer 272. In addition to the transparent wiring segment 27, the second transparent wiring layer 272 also includes a transparent connection pattern 2701. The transparent connection pattern 2701 extends substantially along the row direction X. One end of the transparent connection pattern 2701 is connected to the transparent wiring segment 27, and the other end is electrically connected to the active layer T4-P of the write transistor T4.

[0326] In some examples, referring to FIG. 9AThe fourth bridge pattern 540 is further included in the first source-drain metal layer SD1. The switching pattern is arranged in the first transparent wiring layer 271 and the second source-drain metal layer SD2. The transparent connection pattern 2701 is connected to the switching pattern in the second source-drain metal layer SD2 through a via, and the switching pattern in the second source-drain metal layer SD2 is connected to the switching pattern in the first transparent wiring layer 271 through a via, and the switching pattern in the first transparent wiring layer 271 is connected to the fourth bridge pattern 540 through a via, and the fourth bridge pattern 540 is connected to the active layer T4-P of the write transistor T4 through a via, so that the data signal is transmitted to the first electrode of the write transistor T4. In some examples of the present disclosure, the fourth bridge pattern 540 and the switching patterns are arranged between the transparent connection pattern 2701 and the active layer T4-P of the write transistor T4, so that the via depth can be reduced. Since the deeper the via is, the greater the impedance is, in some examples of the present disclosure, the impedance can be reduced.

[0327] In some examples, each data line DT is located in the second transparent wiring layer 272 in the first display area A1, that is, each data line DT includes the transparent wiring segment 27.

[0328] Please refer to FIG. 11B In the same column of the first pixel unit 220, the orthogonal projection of the transparent wiring segment 27-B of the data line DT-B electrically connected to the write transistor T4 in the first sub-pixel 230B on the substrate 210 is located on the side away from the orthogonal projection of the circuit body 2311-G of the second sub-pixel 230G on the substrate 210.

[0329] The orthogonal projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210 and the orthogonal projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210 are located between the orthogonal projection of the transparent wiring segment 27-G of the data line DT-G electrically connected to the write transistor T4 of the second sub-pixel 230G on the substrate 210 and the orthogonal projection of the transparent wiring segment 27-R of the data line DT-R electrically connected to the write transistor T4 of the third sub-pixel 230G on the substrate 210.

[0330] The transparent wiring segment 27-G electrically connected to the second sub-pixel 230G and the transparent wiring segment 27-R electrically connected to the third sub-pixel 230G are arranged on the two sides of the column where the second sub-pixel 230G and the third sub-pixel 230G are located, respectively.

[0331] In some examples, please refer to FIG. 11A and FIG. 11B The transparent wiring segment 27-R, the transparent wiring segment 27-G, and the transparent wiring segment 27-B are arranged in the first specified direction C1 in sequence.

[0332] In some examples, the transparent trace segment 27-G, the transparent trace segment 27-R, and the transparent trace segment 27-B are sequentially arranged along the first specified direction C1.

[0333] In some embodiments, referring to FIG. 5D In a first pixel unit 220, the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the first sub-pixel 230B are sequentially away from the circuit body 2311-G of the second sub-pixel 230G. That is, the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the first sub-pixel 230B are sequentially away from the column where the second sub-pixel 230G and the third sub-pixel 230R are located, so that the transparent trace segment 27-B electrically connected to the first sub-pixel 230B is located on the side of the first sub-pixel 230B away from the column where the second sub-pixel 230G and the third sub-pixel 230R are located.

[0334] In some embodiments, referring to FIG. 5D In a first pixel unit 220, the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the second sub-pixel 230G are sequentially arranged along the first specified direction; and the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the third sub-pixel 230R are sequentially arranged along the opposite direction of the first specified direction.

[0335] In some embodiments, referring to FIG. 11B and in combination with FIG. 5D The transparent trace segment 27 is electrically connected to the active layer T4-P of the write transistor T4. In one of the second sub-pixel 230G and the third sub-pixel 230R, the write transistor T4 is located on the side of the compensation transistor T2 away from the first sub-pixel 230B. In the other sub-pixel 230, the write transistor T4 is located on the side of the compensation transistor T2 close to the first sub-pixel 230B. Therefore, the transparent trace segment 27-G electrically connected to the second sub-pixel 230G and the transparent trace segment 27-R of the third sub-pixel 230R are respectively arranged on both sides of the column where the second sub-pixel 230G and the third sub-pixel 230R are located, and the transparent trace segment 27-R can be conveniently connected to the write transistor T4 of the third sub-pixel 230R, and the transparent trace segment 27-G can be conveniently connected to the write transistor T4 of the second sub-pixel 230G.

[0336] In some examples, referring to FIG. 11B The first specified direction C1 is opposite to the first specified direction D, and at this time, the transparent trace segment 27-R electrically connected to the third sub-pixel 230R, the transparent trace segment 27-G electrically connected to the second sub-pixel 230G, and the data line 27-B electrically connected to the first sub-pixel 230B are sequentially arranged along the first specified direction C1.

[0337] In some examples, the first set direction D is the same as the first specified direction C1, and the transparent wire segment 27-G to which the second sub-pixel 230G is electrically connected, the transparent wire segment 27-R to which the third sub-pixel 230R is electrically connected, and the data line 27-B to which the first sub-pixel 230B is electrically connected are sequentially arranged along the first specified direction C1.

[0338] Referring to FIG. 13A and FIG. 13B , the display panel 200 further includes an anode layer AND, and the anode layer AND includes a plurality of anodes AND1, such as an anode AND-B of the first sub-pixel 230B, an anode AND-G of the second sub-pixel 230G, and an anode AND-R of the third sub-pixel 230R.

[0339] In some embodiments, referring to FIG. 2B , in addition to the first display area A1, the display panel 200 further includes a second display area A2, and the first display area A1 is provided with the first pixel unit 220. The second display area A2 is provided with a plurality of second pixel units 290, and the plurality of second pixel units 290 are arranged in multiple rows and multiple columns; the second pixel unit 290 includes a plurality of sub-pixels 291. The plurality of sub-pixels 291 include a first sub-pixel 291B, a second sub-pixel 291G, and a third sub-pixel 291R,

[0340] The second display area A2 is located at least one side of the first display area A1. In some examples, the second display area A2 can be arranged on one or more sides of the first display area A1. In other examples, the second display area A2 can be arranged around the first display area A1. It should be noted that in FIG. 2B , the area enclosed by the smaller dashed box is the first display area A1, and the larger dashed box is located outside the smaller dashed box. The area between the smaller dashed box and the larger dashed box is the second display area A2, and the first display area A1 and the second display area A2 together constitute the display area AA.

[0341] Referring to FIG. 14 , the sub-pixel 291 of the second pixel unit 290 includes a light-emitting device 232, and the area of the light-emitting device 232 of the first sub-pixel 291B of the second pixel unit 290 is greater than the area of the light-emitting device 232 of the second sub-pixel 291G of the second pixel unit 290, and greater than the area of the light-emitting device 232 of the third sub-pixel 291R of the second pixel unit 290.

[0342] The light emitting device 232 includes an anode AND1. In some examples, the area of the anode AND1 of the first sub-pixel 230B of the first pixel unit 220 is greater than the area of the anode AND1 of the second sub-pixel 230G of the first pixel unit 220, and greater than the area of the anode AND1 of the third sub-pixel 230R of the first pixel unit 220.

[0343] In some embodiments, the area of the light emitting device 232 of the sub-pixel 230 in the first display area A1 is 0.4-0.6 times the area of the light emitting device 232 of the sub-pixel 291 of the same color in the second display area A2.

[0344] In some examples, in the second display area A2, the first sub-pixel 291B of the second pixel unit 290 can be a blue sub-pixel, the second sub-pixel 291G can be a green sub-pixel, and the third sub-pixel 291R can be a red sub-pixel.

[0345] As described above, in some examples, in the first display area A1, the first sub-pixel 230B of the first pixel unit 220 is a blue sub-pixel, the second sub-pixel 230G is a green sub-pixel, and the third sub-pixel 230R is a red sub-pixel.

[0346] In some examples, the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.4-0.6 times the area of the light emitting device 232 of the first sub-pixel 291B of the second pixel unit 290. In this way, it can be avoided that the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too large (for example, greater than 0.6 times the area of the light emitting device 232 of the first sub-pixel 291B), resulting in a low light transmittance of the first display area A1. At the same time, it can also be avoided that the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too small (for example, less than 0.4 times the area of the light emitting device 232 of the first sub-pixel 291B), resulting in a small area of the pixel driving circuit 231 located under the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220, so that the structure in the pixel driving circuit 231 of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too compact, causing coupling between structures.

[0347] For example, the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.5 times the area of the light emitting device 232 of the first sub-pixel 291B of the second pixel unit 290.

[0348] For example, the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.5 times the area of the light emitting device 232 of the first sub-pixel 291B of the second pixel unit 290. FIG. 14The area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.4-0.6 times the area of the light-emitting device 232 of the second sub-pixel 291G of the second pixel unit 290. In this way, the area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 can be prevented from being too large (e.g., greater than 0.6 times the area of the light-emitting device 232 of the second sub-pixel 291G), which can result in a low light transmittance of the first display area A1. Meanwhile, the area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 can also be prevented from being too small (e.g., less than 0.4 times the area of the light-emitting device 232 of the second sub-pixel 291G), which can result in a small area of the circuit body 2311-G of the second sub-pixel 230G under the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220, and the structures in the circuit body 2311-G of the second sub-pixel 230G of the first pixel unit 220 can be too compact, which can cause coupling between the structures.

[0349] For example, the area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.5 times the area of the light-emitting device 232 of the second sub-pixel 291G of the second pixel unit 290.

[0350] For example, the area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.5 times the area of the light-emitting device 232 of the second sub-pixel 291G of the second pixel unit 290. FIG. 14 The area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.4-0.6 times the area of the light-emitting device 232 of the third sub-pixel 291R of the second pixel unit 290. In this way, the area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 can be prevented from being too large (e.g., greater than 0.6 times the area of the light-emitting device 232 of the third sub-pixel 291R), which can result in a low light transmittance of the first display area A1. Meanwhile, the area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 can also be prevented from being too small (e.g., less than 0.4 times the area of the light-emitting device 232 of the third sub-pixel 291R), which can result in a small area of the circuit body 2311-R of the third sub-pixel 230R under the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220, and the structures in the circuit body 2311-R of the third sub-pixel 230R of the first pixel unit 220 can be too compact, which can cause coupling between the structures.

[0351] For example, the area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.5 times the area of the light-emitting device 232 of the third sub-pixel 291R of the second pixel unit 290.

[0352] In some examples, the sub-pixel density of the first display area A1 is equal to the sub-pixel density of the second display area A2. It should be noted that the sub-pixel density of the first display area A1 refers to the number of sub-pixels 230 per unit area in the first display area A1. The sub-pixel density of the second display area A2 refers to the number of sub-pixels 291 per unit area in the second display area A2.

[0353] Although the area of the light-emitting device 232 of the sub-pixel 291 in the second display area A2 is larger than the area of the light-emitting device 232 of the sub-pixel 230 with the same color in the first display area A1, the sub-pixel density of the first display area A1 is equal to the sub-pixel density of the second display area A2, so that the display difference between the first display area A1 and the second display area A2 can be reduced.

[0354] In addition, the light transmittance of the first display area A1 is greater than the light transmittance of the second display area A2, so that the sensor 300 can sense sufficient light.

[0355] The structure of the light-emitting device 232 of the sub-pixel 291 is the same as that of the light-emitting device 232 of the sub-pixel 230, which will not be described herein. It can be understood that, among the cathode CTD1, the light-emitting layer EL and the anode AND1 of one sub-pixel 291, if the area of the cathode CTD1 is the largest, then the area of the light-emitting device 232 of the sub-pixel 291 is the area of the cathode CTD1. If the area of the anode AND1 is the largest, then the area of the light-emitting device 232 of the sub-pixel 291 is the area of the anode AND1. If the area of the light-emitting layer EL is the largest, then the area of the light-emitting device 232 of the sub-pixel 291 is the area of the light-emitting layer EL.

[0356] The display device 100 provided by some embodiments of the present disclosure includes the display panel 200 provided by any of the above embodiments. Therefore, the display device 100 provided by some embodiments of the present disclosure has all the beneficial effects of the display panel 200 provided by any of the above embodiments, which will not be described herein.

[0357] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that, include: Substrate; Multiple first pixel units are located on one side of the substrate and arranged in multiple rows and columns; wherein, each first pixel unit includes multiple sub-pixels, and each sub-pixel includes a pixel driving circuit and a light-emitting device; the light-emitting device is located on the side of the pixel driving circuit away from the substrate and is electrically connected to the pixel driving circuit; the pixel driving circuit includes a first reset transistor; The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the area of ​​the light-emitting device of the first sub-pixel is greater than the area of ​​the light-emitting device of the second sub-pixel and greater than the area of ​​the light-emitting device of the third sub-pixel. The orthogonal projection of the first reset transistor in the second sub-pixel and / or the first reset transistor in the third sub-pixel onto the substrate is located within the orthogonal projection of the light-emitting device of the first sub-pixel onto the substrate; The area of ​​the anode of the first sub-pixel is greater than the area of ​​the anode of the second sub-pixel, and also greater than the area of ​​the anode of the third sub-pixel.

2. The display panel according to claim 1, characterized in that, The first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are all located within the orthogonal projection of the light-emitting device of the first sub-pixel onto the substrate.

3. The display panel according to claim 1, characterized in that, At least two of the first reset transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel are the same transistor.

4. The display panel according to any one of claims 1 to 3, characterized in that, The pixel driving circuit further includes a second reset transistor; the second reset transistor of the first sub-pixel, the second reset transistor of the second sub-pixel, and the second reset transistor of the third sub-pixel are the same transistor; the orthogonal projection of the second reset transistor on the substrate is located within the orthogonal projection of the light-emitting device of the first sub-pixel on the substrate; The second reset transistor is connected in series with any one of the first reset transistors; The display panel further includes a reset signal line and an initialization signal line; the control electrode of each of the first reset transistors and the control electrode of the second reset transistors are both electrically connected to the reset signal line; the first electrode of the second reset transistor is electrically connected to the initialization signal line, and the second electrode of the second reset transistor is electrically connected to the first electrode of each of the first reset transistors. The pixel driving circuit further includes a driving transistor, wherein the control electrode of each driving transistor of the pixel driving circuit is electrically connected to the second electrode of each of the first reset transistors.

5. The display panel according to claim 4, characterized in that, The light-emitting devices of the second sub-pixel and the third sub-pixel are spaced apart along the column direction; the light-emitting device of the first sub-pixel is located in an adjacent column of the columns where the light-emitting devices of the second sub-pixel and the third sub-pixel are located; and the light-emitting device of the first sub-pixel spans the gap region between the light-emitting devices of the second sub-pixel and the third sub-pixel. The pixel driving circuit also includes a circuit body; the orthographic projection of the circuit body of the first sub-pixel on the substrate is located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate, the orthographic projection of the circuit body of the second sub-pixel on the substrate is located within the orthographic projection of the light-emitting device of the second sub-pixel on the substrate, and the orthographic projection of the circuit body of the third sub-pixel on the substrate is located within the orthographic projection of the light-emitting device of the third sub-pixel on the substrate. The second reset transistor, the first reset transistor of the third sub-pixel, and the first reset transistor of the second sub-pixel are located on the side of the first reset transistor of the first sub-pixel closer to the circuit body of the third sub-pixel, and sequentially further away from the circuit body of the third sub-pixel.

6. The display panel according to claim 5, characterized in that, The reset signal line extends along the row direction, and one of the reset signal lines is electrically connected to the control electrode of the second reset transistor in the first pixel unit of a row and the control electrode of each first reset transistor. The initialization signal line extends along the row direction, and one of the initialization signal lines is electrically connected to the first electrode of the second reset crystal in the first pixel unit of a row. The orthographic projections of the second reset transistor and each of the first reset transistors on the substrate are located between the orthographic projection of the initialization signal line electrically connected to the second reset transistor on the substrate and the orthographic projection of the circuit body of the third sub-pixel on the substrate. The orthographic projection of the reset signal line on the substrate is located between the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the circuit body of the third sub-pixel on the substrate.

7. The display panel according to claim 5 or 6, characterized in that, The substrate includes a first display area, and the plurality of first pixel units are located within the first display area; The display panel further includes: multiple signal lines located between the substrate and the light-emitting device; The portion of at least one signal line located within the first display area includes metal traces and transparent connection traces electrically connected to each other; at least a portion of the metal traces' orthogonal projection onto the substrate lies within the orthogonal projection of the light-emitting device onto the substrate.

8. The display panel according to claim 7, characterized in that, include: Both the first gate metal layer and the first transparent wiring layer are located between the substrate and the light-emitting device, with the first transparent wiring layer located on the side of the first gate metal layer facing away from the substrate. The at least one signal line includes a reset signal line, the reset signal line extends along the row direction, and one of the reset signal lines is electrically connected to the control electrode of the second reset transistor in the row of the first pixel unit and the control electrode of each first reset transistor. The metal trace of the reset signal line is located in the first gate metal layer, and at least a portion of the orthographic projection of the metal trace of the reset signal line on the substrate is located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate. The transparent connection trace of the reset signal line is located in the first transparent trace layer; the orthographic projection of the transparent connection trace of the reset signal line on the substrate is outside the orthographic projection of the light-emitting device of the second sub-pixel on the substrate, and outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate. The transparent connection trace of the reset signal line is connected to the metal trace of the reset signal line through a via.

9. The display panel according to claim 8, characterized in that, The main circuit of the pixel driving circuit includes a write transistor, a compensation transistor, and a third reset transistor. The at least one signal line further includes a scan signal line, wherein one of the scan signal lines is electrically connected to the control electrode of the write transistor, the control electrode of the compensation transistor, and the control electrode of the third reset transistor of all the sub-pixels in a row of the first pixel unit; The metal trace of the scan signal line is located in the first gate metal layer, and at least a portion of the orthogonal projection of the metal trace of the scan signal line on the substrate is located within the orthogonal projection of the light-emitting device on the substrate; The transparent connection trace of the scan signal line is located in the first transparent trace layer, and the transparent connection trace of the scan signal line is connected to the metal trace of the scan signal line through vias.

10. The display panel according to claim 8 or 9, characterized in that, The main circuit of the pixel driving circuit also includes a first light-emitting control transistor and a second light-emitting control transistor. The at least one signal line further includes a light emission control signal line, and one of the light emission control signal lines is electrically connected to the control electrode of the first light emission control transistor and the control electrode of the second light emission control transistor of all the sub-pixels in a row of the first pixel unit. The metal trace of the light-emitting control signal line is located in the first gate metal layer, and at least a portion of the orthogonal projection of the metal trace of the light-emitting control signal line on the substrate is located within the orthogonal projection of the light-emitting device on the substrate; The transparent connection trace of the light emission control signal line is located in the first transparent trace layer, and the transparent connection trace of the light emission control signal line is connected to the metal trace of the light emission control signal line through a via.

11. The display panel according to claim 7, characterized in that, include: The first source / drain metal layer and the first transparent wiring layer are both located between the substrate and the light-emitting device, and the first transparent wiring layer is located on the side of the first source / drain metal layer away from the substrate. The at least one signal line further includes: an initialization signal line, wherein one of the initialization signal lines is electrically connected to the first electrode of the second reset crystal in a row of the first pixel unit; The metal trace of the initialization signal line is located in the first source / drain metal layer, and at least a portion of the orthographic projection of the metal trace of the initialization signal line on the substrate is located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate. The transparent connection trace of the initialization signal line is located in the first transparent trace layer; the orthographic projection of the transparent connection trace of the initialization signal line on the substrate is outside the orthographic projection of the light-emitting device of the second sub-pixel on the substrate, and outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate; the transparent connection trace of the initialization signal line is connected to the metal trace of the initialization signal line through a via.

12. The display panel according to claim 7, characterized in that, include: A second gate metal layer, a second source / drain metal layer, and a second transparent wiring layer are located between the substrate and the light-emitting device. The second source / drain metal layer is located on the side of the second gate metal layer that is away from the substrate, and the second transparent wiring layer is located on the side of the second source / drain metal layer that is away from the second gate metal layer. The main body of the pixel driving circuit also includes a capacitor, wherein the first plate of the capacitor is located in the second gate metal layer; The at least one signal line further includes a first power signal line, which extends along the column direction and is electrically connected to the first plate of the capacitor of the second sub-pixel and the first plate of the capacitor of the third sub-pixel in the first pixel unit of a column. The metal trace of the first power signal line is located in the second source / drain metal layer, and at least a portion of the orthographic projection of the metal trace of the first power signal line on the substrate is located within the orthographic projection of the light-emitting device of the second sub-pixel and the light-emitting device of the third sub-pixel on the substrate. The transparent connection trace of the first power signal line is located in the second transparent trace layer, and the transparent connection trace of the first power signal line is connected to the metal trace of the first power signal line through a via.

13. The display panel according to claim 12, characterized in that, The at least one signal line further includes a second power signal line, which extends along the column direction and is electrically connected to the first plate of the capacitor of the first sub-pixel in the first pixel unit of a column. The metal trace of the second power signal line is located in the second source / drain metal layer, and the orthographic projection of the metal trace of the second power signal line on the substrate is at least partially located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate. The transparent connection trace of the second power signal line is located in the second transparent trace layer, and the transparent connection trace of the second power signal line is connected to the metal trace of the second power signal line through a via.

14. The display panel according to claim 12 or 13, characterized in that, Also includes: Multiple data lines extend along the column direction, and the orthographic projection of the portion of the multiple data lines located in the first display area on the substrate is located outside the orthographic projection of the light-emitting device of any of the sub-pixels on the substrate, and at least one data line located in the first display area is located in the second transparent trace layer. The main circuit of the pixel driving circuit includes: a write transistor; In a first pixel unit, the first electrode of the write transistor of the first sub-pixel, the first electrode of the write transistor of the second sub-pixel, and the first electrode of the write transistor of the third sub-pixel are respectively connected to different data lines.

15. The display panel according to claim 14, characterized in that, The portion of the at least one data line located in the first display area is a transparent trace segment; Within the first pixel unit in the same column, the orthographic projection of the transparent trace segment of the data line electrically connected to the write transistor in the first sub-pixel on the substrate is located on the side of the orthographic projection of the circuit body of the first sub-pixel on the substrate that is far from the orthographic projection of the circuit body of the second sub-pixel on the substrate; the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and the orthographic projection of the light-emitting device of the third sub-pixel on the substrate are located between the orthographic projection of the transparent trace segment of the data line electrically connected to the write transistor of the second sub-pixel on the substrate and the orthographic projection of the transparent trace segment of the data line electrically connected to the write transistor of the third sub-pixel on the substrate.

16. The display panel according to claim 15, characterized in that, The main circuit of the pixel driving circuit also includes a compensation transistor and a third reset transistor. Within a first pixel unit, the third reset transistor, compensation transistor, and write transistor in the first sub-pixel are sequentially moved away from the circuit body of the second sub-pixel; the third reset transistor, compensation transistor, and write transistor in the second sub-pixel are sequentially arranged along a first predetermined direction; the third reset transistor, compensation transistor, and write transistor in the third sub-pixel are sequentially arranged in the opposite direction to the first predetermined direction.

17. The display panel according to any one of claims 1 to 3, characterized in that, The light-emitting device includes an anode, a light-emitting layer, and a cathode. The anode is electrically connected to the pixel driving circuit. The light-emitting layer is located on the side of the anode facing away from the substrate, and the cathode is located on the side of the light-emitting layer facing away from the substrate. The orthographic projection of the first reset transistor in the second sub-pixel and / or the first reset transistor in the third sub-pixel onto the substrate is located within the orthographic projection of the anode of the first sub-pixel onto the substrate.

18. The display panel according to any one of claims 1 to 3, characterized in that, The first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel.

19. The display panel according to any one of claims 1 to 3, characterized in that, include: A first display area and a second display area, wherein the first display area is provided with the first pixel unit; The second display area is provided with a plurality of second pixel units, which are arranged in multiple rows and columns; the second pixel unit includes a plurality of sub-pixels, and the sub-pixel density of the first display area is equal to the sub-pixel density of the second display area; The area of ​​the light-emitting device of the sub-pixel in the first display area is 0.4 to 0.6 times the area of ​​the light-emitting device of the sub-pixel of the same color in the second display area.

20. A display device, characterized in that, include: The display panel according to any one of claims 1 to 19.

Images