Voltage conversion circuit

Abstract

The application provides a voltage conversion circuit, comprising: a voltage dividing circuit for dividing a first floating voltage to generate a second floating voltage; a voltage offset circuit for offsetting the second floating voltage to generate a third floating voltage; the voltage offset circuit comprises a voltage offset unit, which comprises a current source for generating a constant current, a part of the constant current flows through a first branch to form a first branch current, and another part of the constant current flows through a second branch to form a second branch current; the first branch comprises a first field effect transistor and a first load, and the second branch comprises a second field effect transistor and a second load; the source of the first field effect transistor and the second field effect transistor are connected; the width-length ratio of the conductive channel of the first field effect transistor and the second field effect transistor is different; the gate of the first field effect transistor inputs the second floating voltage; and the gate of the second field effect transistor is connected with the third floating voltage. The voltage conversion circuit can convert a large floating power supply voltage into a driving voltage of an integrated switching element, and has low process sensitivity.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to voltage conversion circuits. Background Technology

[0002] In the modern semiconductor industry, CMOS (Complementary Metal-Oxide-Semiconductor) technology has become the mainstream technology in integrated circuit (IC) design today due to its near-zero static power consumption of logic circuits and the scale-down capability of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0003] In analog integrated circuit design, circuits with digital logic switching functions are often involved. The driving voltage range of switching elements is limited by both the element's threshold voltage and its withstand voltage. As the feature size of MOSFETs continues to shrink, and modern CMOS advanced processes enter the deep submicron and even subnanometer era, the withstand voltages between each pair of the drain, source, gate, and substrate of a MOSFET are constantly decreasing. Therefore, the permissible driving voltage range is becoming increasingly smaller.

[0004] In some cases, the power supply voltage used to generate the driving voltage fluctuates significantly. For example, the lower limit of the power supply voltage is lower than the maximum withstand voltage of the switching element, but the upper limit of the power supply voltage is much higher than the maximum withstand voltage of the switching element, which further increases the design difficulty of the voltage conversion circuit.

[0005] Existing voltage conversion circuits generally use a relatively stable power supply voltage to generate the required driving voltage. When the power supply voltage itself fluctuates significantly, some of these existing voltage conversion circuits cannot theoretically obtain the required driving voltage, and the output voltage is greatly affected by semiconductor process fluctuations, making it difficult to meet the design requirements of integrated circuits. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a voltage conversion circuit for converting a large fluctuation in power supply voltage into a drive voltage for integrated switching elements, and with low process sensitivity.

[0007] In a first aspect, this application provides a voltage conversion circuit, the voltage conversion circuit including a voltage divider circuit and a voltage offset circuit connected to the voltage divider circuit, the voltage divider circuit divides a first floating voltage to generate a second floating voltage, the voltage offset circuit offsets the second floating voltage to generate a third floating voltage, the voltage offset circuit includes at least one voltage offset unit, the voltage offset unit including a current source, a first branch and a second branch, the current source being used to generate a constant current, a portion of the constant current flowing through the first branch to form a first branch current, and another portion of the constant current flowing through the second branch to form a second branch current, the first branch including a first field-effect transistor and a first load connected in series, the second branch including a second field-effect transistor and a second load connected in series, the source of the first field-effect transistor and the source of the second field-effect transistor being connected, the conductive channel width-to-length ratio of the first field-effect transistor and the second field-effect transistor being different to form a current difference between the first branch current and the second branch current, the gate of the first field-effect transistor receiving the second floating voltage, and the gate of the second field-effect transistor being connected to the third floating voltage.

[0008] In one implementation of the first aspect, the first field-effect transistor and the second field-effect transistor are PMOS transistors, and the width-to-length ratio of the conductive channel of the second field-effect transistor is q times the width-to-length ratio of the conductive channel of the first field-effect transistor, where 1.5 ≤ q ≤ 30.

[0009] In one implementation of the first aspect, the impedance of the second load is k times the impedance of the first load, where 1.5 ≤ k ≤ 30.

[0010] In one implementation of the first aspect, the first load and the second load are NMOS transistors, and the aspect ratio of the conductive channel of the first load is k times the aspect ratio of the conductive channel of the second load, where 1.5 ≤ k ≤ 30.

[0011] In one implementation of the first aspect, the second field-effect transistor includes a plurality of PMOS device units connected in parallel, each PMOS device unit being arranged around the first field-effect transistor, and the position center of each PMOS device unit coinciding with the position center of the first field-effect transistor.

[0012] The first load includes multiple NMOS device units connected in parallel, each NMOS device unit is arranged around the second load, and the center of each NMOS device unit coincides with the center of the second load.

[0013] In one implementation of the first aspect, the first field-effect transistor and the second field-effect transistor are NMOS transistors, and the width-to-length ratio of the conductive channel of the first field-effect transistor is q times the width-to-length ratio of the conductive channel of the second field-effect transistor, where 1.5 ≤ q ≤ 30.

[0014] In one implementation of the first aspect, the impedance of the first load is k times the impedance of the second load, where 1.5 ≤ k ≤ 30.

[0015] In one implementation of the first aspect, the first load and the second load are PMOS transistors, and the aspect ratio of the conductive channel of the second load is k times the aspect ratio of the conductive channel of the first load, where 1.5 ≤ k ≤ 30.

[0016] In one implementation of the first aspect, the first field-effect transistor includes a plurality of NMOS device units connected in parallel, each of the NMOS device units being arranged around the second field-effect transistor, and the position center of each of the NMOS device units coinciding with the position center of the second field-effect transistor;

[0017] The second load includes a plurality of PMOS device units connected in parallel, each PMOS device unit being arranged around the first load, and the center of position of each PMOS device unit coinciding with the center of position of the first load.

[0018] In one implementation of the first aspect, the sources of the first field-effect transistor and the second field-effect transistor are connected to the current source; the gate and drain of the second field-effect transistor are connected; and the gates of the first load and the second load are connected to the drain of the first field-effect transistor.

[0019] As described above, the voltage conversion circuit of this application can convert large fluctuations in power supply voltage into drive voltage for integrated switching elements, and has low process sensitivity. Attached Figure Description

[0020] Figure 1 This diagram illustrates an application scenario of the voltage conversion circuit described in one embodiment of this application.

[0021] Figure 2 The diagram shown is a circuit diagram of a voltage conversion circuit as described in an embodiment of the prior art.

[0022] Figure 3 The diagram shown is a structural block diagram of a voltage conversion circuit described in one embodiment of this application.

[0023] Figure 4 The diagram shown is a structural block diagram of a voltage offset circuit described in one embodiment of this application.

[0024] Figure 5The diagram shown is a circuit diagram of a voltage conversion circuit described in one embodiment of this application.

[0025] Figure 6 The diagram shown is a circuit diagram of a voltage conversion circuit as described in another embodiment of this application.

[0026] Figure 7 The diagram shown is a circuit diagram of a voltage conversion circuit as described in another embodiment of this application.

[0027] Figure 8 The diagram shown is a circuit diagram of a voltage conversion circuit as described in another embodiment of this application.

[0028] Component designation explanation

[0029] 100, Voltage divider circuit; 200, Current source; 300, First branch; 310, First field-effect transistor; 320, First load; 400, Second branch; 410, Second field-effect transistor; 420, Second load; 500, Buffer; 600, Voltage offset circuit; 610, First stage voltage offset unit; 620, Last stage voltage offset unit. Detailed Implementation

[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0031] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] Figure 1This application scenario illustrates an embodiment of the present application. The scenario involves a transmission gate circuit, including a first resistor R1, a second resistor R2, a first switch Q1, a second switch Q2, and a first inverter NOT1. The first resistor R1 and the second resistor R2 divide the power supply voltage VDD to obtain a first voltage VA. The first switch Q1 is an NMOS transistor, and the second switch Q2 is a PMOS transistor. The source of the first switch Q1 is connected to the midpoint between the first resistor R1 and the second resistor R2, and the drain of the second switch Q2 is also connected to the midpoint between the first resistor R1 and the second resistor R2. The drain of the first switch Q1 and the source of the second switch Q2 are interconnected, outputting a second voltage VB. On one hand, the transmission gate control voltage V... EN It acts directly on the gate of the first switching transistor Q1, controlling the on / off state of Q1. On the other hand, the transmission gate control voltage V... EN After being inverted by the first inverter NOT1, it acts on the gate of the second switch Q2, controlling the on / off state of the second switch Q2.

[0033] To ensure reliable transmission from the transmission gate, the control voltage V of the transmission gate must first be guaranteed. EN To ensure that at least one of the second switch Q2 and the first switch Q1 is reliably turned on, it is also necessary to ensure that the voltage across any two terminals of all MOSFETs does not exceed the withstand voltage value.

[0034] Specifically, the second switching transistor Q2 should meet the following operating conditions:

[0035] V A ≥|V THP |,V THN ≤V EN ≤|V max | (1)

[0036] The first switching transistor Q1 should meet the following operating conditions:

[0037] V A +V THN ≤V EN ≤|V max | (2)

[0038] Among them, V A express Figure 1 The voltage at point A in the middle;

[0039] V THP This represents the threshold voltage of the second switch Q2;

[0040] V THN This represents the threshold voltage of the NMOS transistor; specifically, when... Figure 1 In the circuit shown, when the first inverter NOT1 does not contain an NMOS transistor, V THNThis represents the threshold voltage of the first switch Q1; when the first inverter NOT1 contains an NMOS transistor, V THN This represents the maximum threshold voltage of the first switch Q1 and the NMOS transistor in the first inverter NOT1;

[0041] V EN Indicates the transmission gate control voltage;

[0042] |V max | represents the breakdown voltage between any two ports of a MOSFET, as defined by the semiconductor process. Here, it is assumed that the breakdown voltage between any two ports of a MOSFET is the same.

[0043] One method currently in use is to generate the transmission gate control voltage V. EN circuits such as Figure 2 As shown, the power supply voltage VDD is first divided by the third resistor R3 and the fourth resistor R4 to obtain the proportional voltage Vin, where Vin = m * VDD, and m is the voltage division ratio. Then, the proportional voltage Vin is input to the buffer 500 to enhance the driving capability before outputting the transmission gate control voltage V. EN .

[0044] Figure 2 The circuit shown may not be suitable for applications with a large fluctuation range in the power supply voltage VDD. That is, regardless of the voltage divider ratio m, it is difficult to guarantee the reliable operation of the subsequent transmission gate. For example, if the power supply voltage VDD fluctuates from 1.25V to 3.63V... Figure 1 V in A =0.5V, |V is limited by process specifications max |=1.98V. To prevent irreversible breakdown of the switching element, m can be taken to a maximum of 0.54, resulting in V EN The voltage range is 0.675V to 1.9602V, which is less than the maximum withstand voltage of 1.98V, providing a safety margin of approximately 0.02V. At this point, V EN The lower limit of 0.675V is insufficient to reliably turn on the second switch Q2, nor can it reliably turn on the first switch Q1, potentially leading to the transmission gate being turned off. Specifically, according to the conduction condition of MN1 defined by formula (2), V is required to... THN A voltage less than 0.175V is required to ensure conduction, which is obviously difficult to achieve in terms of manufacturing process. According to the conduction condition of the second switch Q2 defined by formula (1), although theoretically V... ENIt's possible that the conduction condition is just met, but in actual production, process factors can affect the actual parameters of the device, and some process factors are difficult to control artificially. For example, there may be significant fluctuations between different batches of wafers and between different wafers within the same batch, and the threshold voltage is usually the parameter with the greatest fluctuation due to process variations. Therefore, even considering the impact of actual process factors, it is difficult to guarantee the reliable conduction of the second switch Q2.

[0045] To meet the driving voltage requirements of switching elements in integrated circuits, while also taking into account the process sensitivity of integrated circuit manufacturing, such as Figure 3 As shown, in one embodiment, this application provides a voltage conversion circuit, which includes a voltage divider circuit 100 and a voltage offset circuit 600 connected to the voltage divider circuit 100. The voltage divider circuit 100 divides a first floating voltage VDD_1 to generate a second floating voltage VDD_2, and the voltage offset circuit offsets the second floating voltage VDD_2 to generate a third floating voltage VDD_3. The voltage offset circuit 600 includes at least one voltage offset unit, such as... Figure 4 As shown, the voltage offset unit includes a current source 200, a first branch 300, and a second branch 400. The current source 200 generates a constant current I0. A portion of the constant current I0 flows through the first branch 300 to form a first branch current I1, and the other portion of the constant current I0 flows through the second branch 400 to form a second branch current I2. The first branch 300 includes a first field-effect transistor 310 and a first load 320 connected in series. The second branch 400 includes a second field-effect transistor 410 and a second load 420 connected in series. The source 1 of the first field-effect transistor 310 and the source 2 of the second field-effect transistor 410 are connected. The width-to-length ratio of the conductive channels of the first field-effect transistor 310 and the second field-effect transistor 410 is different to form a current difference between the first branch current I1 and the second branch current I2. The gate 1 of the first field-effect transistor 310 is connected to a second floating voltage VDD_2, and the gate 2 of the second field-effect transistor 410 is connected to a third floating voltage VDD_3.

[0046] It should be noted that in this embodiment, the source of the first field-effect transistor 310 and the source of the second field-effect transistor 410 can be directly connected or indirectly connected through an intermediate component.

[0047] Furthermore, this embodiment does not limit the connection order of the first field-effect transistor 310 and the first load 320 in the first branch 300. Along the positive current direction, the first branch current I1 can flow through the first field-effect transistor 310 before flowing through the first load 320, or vice versa. Similarly, along the positive current direction, the second branch current I2 can flow through the second field-effect transistor 410 before flowing through the second load 420, or vice versa.

[0048] Furthermore, this embodiment does not limit the direction of the constant current I0. The direction of the constant current I0 can be from the current source 200 to the first branch 300, or it can be from the first branch 300 to the current source 200. Similarly, the direction of the constant current I0 can be from the current source 200 to the second branch 400, or it can be from the second branch 400 to the current source 200.

[0049] The working principle of this embodiment is as follows: First, the voltage divider circuit 100 is used to divide the first floating voltage VDD_1 to obtain the second floating voltage VDD_2. The floating range of the second floating voltage VDD_2 is smaller than the floating range of the first floating voltage VDD_1, and it is ensured that the second floating voltage VDD_2 will not cause breakdown. However, at this time, the second floating voltage VDD_2 does not need to ensure that the first field-effect transistor 310 is in a strong inversion state, that is, the first field-effect transistor 310 can work in the subthreshold region.

[0050] The second floating voltage VDD_2 is input to the gate Gate1 of the first field-effect transistor 310, causing the first field-effect transistor 310 to be in a strong inversion or weak inversion state, thereby controlling the magnitude of the first branch current I1. The magnitude of the second branch current I2 is determined by the difference between the constant current I0 and the first branch current I1.

[0051] Since the source voltages of the first field-effect transistor 310 and the second field-effect transistor 410 are equal or the voltage difference is fixed, the voltage difference between the third floating voltage VDD_3 and the second floating voltage VDD_2 depends on the gate-source voltage V of the first field-effect transistor 310. gs1 The gate-source voltage V of the second field-effect transistor 410 gs2In this embodiment, the voltage divider circuit 100 first reduces the floating range of the first floating voltage VDD_1 to obtain the second floating voltage VDD_2; then, the first field-effect transistor 310 and the second field-effect transistor 410 are configured as conductive channels with different aspect ratios (only the design value is limited here), causing the gate-source voltages of the first field-effect transistor 310 and the second field-effect transistor 410 to be asymmetrical, thereby causing the third floating voltage VDD_3 to shift relative to the second floating voltage VDD_2, so that the three floating voltages VDD_3 can be stably within the floating range allowed by the driving voltage.

[0052] This embodiment also uses a current source 200 to output a constant current I0, thereby stabilizing the voltage difference between the third floating voltage VDD_3 and the second floating voltage VDD_2, and avoiding the influence of fluctuations in the first floating voltage VDD_1. This can be understood as meaning that although the MOSFET process may change, VDD_2 can still undergo a large level shift when the first floating voltage VDD_1 is relatively low, thus improving VDD_2's stability. EN The lower limit of V, but when the first floating voltage VDD_1 is relatively high, no larger level shift occurs, limiting V EN The upper limit.

[0053] Regarding process sensitivity, since the effects of process factors on the threshold voltage of the first field-effect transistor 310 and the threshold voltage of the second field-effect transistor 410 are synchronous and can largely cancel each other out, the impact on the third floating voltage VDD_3 is relatively small.

[0054] To further reduce the impact of process factors on the third floating voltage VDD_3, in this embodiment, the difference between the threshold voltage of the first field-effect transistor 310 and the threshold voltage of the second field-effect transistor 410 is less than or equal to 1.5mV.

[0055] In this embodiment, the first field-effect transistor 310 and the second field-effect transistor 410 are PMOS transistors. The width-to-length ratio of the conductive channel of the second field-effect transistor 410 is q times the width-to-length ratio of the conductive channel of the first field-effect transistor 310, where 1.5 ≤ q ≤ 30.

[0056] If the aspect ratio of the conductive channel is set too small, it will limit the offset of the third floating voltage VDD_3 relative to the second floating voltage VDD_2, making it difficult to cope with situations where the first floating voltage VDD_1 has an excessively large fluctuation range. If the aspect ratio of the conductive channel is set too large, it will increase the chip area.

[0057] In this embodiment, the impedance of the second load 420 is k times the impedance of the first load 320, where 1.5 ≤ k ≤ 30.

[0058] In this embodiment, the impedances of the first load 320 and the second load 420 are set differently, causing an asymmetry between the first branch current I1 and the second branch current I2. Then, the gate-source voltage V of the first field-effect transistor 310 is increased by utilizing the positive correlation between the source-drain current and the gate-source voltage. gs1 The gate-source voltage V of the second field-effect transistor 410 gs2 The asymmetry ensures that the resulting third floating voltage VDD_3 meets the requirements of the switching elements in the integrated circuit for the drive voltage.

[0059] By adjusting the relative sizes of the first load 320 and the second load 420, the magnitudes of the first branch current I1 and the second branch current I2 can be changed. Specifically, the smaller the first load 320 is relative to the second load 420, the larger the first branch current I1, and the larger the gate-source voltage V of the first field-effect transistor. gs1 The larger the value, the lower the gate-source voltage V of the second field-effect transistor. Since the sum of the first branch current I1 and the second branch current I2 is fixed, the smaller the second branch current I2 received, the lower the gate-source voltage V of the second field-effect transistor. gs2 The smaller the value, the greater the offset of the third floating voltage VDD_3 relative to the second floating voltage VDD_2.

[0060] To facilitate integrated circuit manufacturing, in this embodiment, the first load 320 and the second load 420 are NMOS transistors. The aspect ratio of the conductive channel of the first load 320 is k times that of the conductive channel of the second load 420, where 1.5 ≤ k ≤ 30.

[0061] To further reduce the difference in threshold voltage between the first field-effect transistor 310 and the second field-effect transistor 410 due to process factors, and to reduce the process sensitivity of the integrated circuit, in this embodiment, the second field-effect transistor 410 includes multiple PMOS device units connected in parallel. Each PMOS device unit is arranged around the first field-effect transistor 310, and the center of each PMOS device unit coincides with the center of the first field-effect transistor 310. Taking a rectangular arrangement of PMOS device units as an example, the center of each PMOS device unit is the center of symmetry of the rectangle. The first load 320 includes multiple NMOS device units connected in parallel. Each NMOS device unit is arranged around the second load 420, and the center of each NMOS device unit coincides with the center of the second load 420.

[0062] To further reduce the impact of process factors, the number of NMOS device units is greater than 4, and the number of PMOS device units is greater than 16.

[0063] Specifically, such as Figure 5 As shown, in this embodiment, the voltage divider circuit 100 includes a fifth voltage divider resistor R5 and a sixth voltage divider resistor R6 connected in series. The intermediate node of the fifth voltage divider resistor R5 and the sixth voltage divider resistor R6 outputs a second floating voltage VDD_2.

[0064] like Figure 5 As shown, both the first field-effect transistor 310 and the second field-effect transistor 410 are PMOS transistors, and both the first load 320 and the second load 420 are NMOS transistors. The source of the first field-effect transistor 310 is connected to the current source 200, the drain of the first field-effect transistor 310 is connected to the drain of the first load 320, the source of the first load 320 is grounded, and the gate and drain of the first load 320 are connected. The source of the second load 420 is grounded, the gate of the second load 420 is connected to the gate of the first load 320, the source of the second field-effect transistor 410 is connected to the current source 200, the drain of the second field-effect transistor 410 is connected to the drain of the second load 420, and the gate of the second field-effect transistor 410 is connected to the drain of the second load 420.

[0065] The current formation process in the first branch 300 and the second branch 400 is as follows: the second floating voltage VDD_2 is less than the source voltage of the first field-effect transistor 310, and the voltage difference is greater than or close to the threshold voltage of the first field-effect transistor 310, causing the first field-effect transistor 310 to be in a strong inversion or weak inversion state. The gate of the first load 320 is connected to the first floating voltage VDD_1 through the first field-effect transistor 310 and the current source. The gate-source voltage of the first load 320 is greater than the threshold voltage of the first load 320, causing the first load 320 to be in a strong inversion or weak inversion state. The drain voltage of the first field-effect transistor 310 also turns on the second load 420. The gate of the second field-effect transistor 410 is grounded through the second load 420, and the source of the second field-effect transistor 410 is connected to the first floating voltage VDD_1 through the current source. The second field-effect transistor 410 is in a strong inversion or weak inversion state, and the gate of the second field-effect transistor 410 is connected to the third floating voltage VDD_3.

[0066] When the first field-effect transistor 310 or the second field-effect transistor 410 is operating in the saturation region, the gate-source voltage difference ΔV between the two is... gs It can be represented as:

[0067]

[0068] When the first field-effect transistor 310 or the second field-effect transistor 410 operates in the subthreshold region, then ΔV gs It can be represented as:

[0069] ΔV gs =nV T *ln(kq)+(|V THP,0 |-|V THP,1 |) (4)

[0070] Where, μ p The hole mobility of the PMOS.

[0071] Cox is the capacitance per unit area of ​​the gate insulating layer of the MOSFET.

[0072] (W / L)p is the width-to-length ratio of the conductive channel of the first field-effect transistor 310;

[0073] V T Thermoelectric voltage;

[0074] V THP,0 The threshold voltage of the first field-effect transistor 310;

[0075] V THP,1 This is the threshold voltage of the second field-effect transistor 410.

[0076] As can be seen, the temperature characteristic of the voltage conversion circuit in this embodiment is that the third floating voltage VDD_3 gradually increases with the increase of ambient temperature. This temperature characteristic is beneficial for applications where the driving voltage is used as a switching element, and can, to a certain extent, offset the voltage drop (IR drop) on the power lines of digital circuits at high temperatures.

[0077] like Figure 5 As shown, in this embodiment, the voltage conversion circuit further includes a buffer 500 for increasing the drive current of the third floating voltage VDD_3, and the input terminal of the buffer 500 is connected to the gate of the second field-effect transistor 410.

[0078] like Figure 5 As shown, in order to further enhance the conversion capability of the first floating voltage VDD_1, in this embodiment, the voltage conversion circuit includes a voltage divider circuit 100, a multi-stage interconnected voltage offset unit, and a buffer 500.

[0079] like Figure 6 As shown in this embodiment, each voltage offset unit has a voltage input terminal, a voltage output terminal, and a power supply terminal. The power supply terminal of each voltage offset unit is used to connect to the first floating voltage VDD_1, and the output terminal of the previous stage voltage offset unit is connected to the input terminal of the next stage voltage offset unit. The voltage input terminal of the first stage voltage offset unit 610 in each voltage offset unit receives the second floating voltage VDD_2, and the voltage output terminal of the last stage voltage offset unit 620 outputs the third floating voltage VDD_3.

[0080] Specifically, in this embodiment, the number of voltage offset units is 2 to 5. Too few units will not meet the offset requirements for the second floating voltage, while too many units may cause the current source to be pinched off.

[0081] In this embodiment, the aspect ratio of the conductive channel of the first field-effect transistor 310 is 8, the aspect ratio of the conductive channel of the second field-effect transistor 410 is 64, the aspect ratio of the conductive channel of the second load 420 is 0.5, the aspect ratio of the conductive channel of the first load 320 is 4, and the resistance ratio of the fifth voltage divider resistor R5 and the sixth voltage divider resistor R6 is 0.37. When the floating range of the first floating voltage VDD_1 is 1.25V to 3.63V, the number of voltage offset units is 3, resulting in the third floating voltage V EN The voltage fluctuation range is 0.813V to 1.962V. Compared with the lower limit of 0.675V obtained by the prior art, the lower limit of this embodiment is significantly improved, which can ensure the reliable conduction of the switching element. At the same time, the upper limit of this embodiment is still within the safe range of the withstand voltage limit, which solves the contradiction between circuit function and withstand voltage when the power supply voltage fluctuates too much.

[0082] Consider the duality between PMOS and NMOS transistors, such as Figure 7 As shown in another embodiment, the first field-effect transistor 310 and the second field-effect transistor 410 are NMOS transistors, and the width-to-length ratio of the conductive channel of the first field-effect transistor 310 is q times the width-to-length ratio of the conductive channel of the second field-effect transistor 410, where 1.5 ≤ q ≤ 30.

[0083] In this embodiment, the impedance of the first load 320 is k times the impedance of the second load 420, where 1.5 ≤ k ≤ 30.

[0084] In this embodiment, the first load 320 and the second load 420 are PMOS transistors. The aspect ratio of the conductive channel of the second load 420 is k times that of the conductive channel of the first load 320, where 1.5 ≤ k ≤ 30.

[0085] In this embodiment, the first field-effect transistor 310 includes multiple NMOS device units connected in parallel, each NMOS device unit being arranged around the second field-effect transistor 410, with the center of each NMOS device unit coinciding with the center of the second field-effect transistor 410. The second load 420 includes multiple PMOS device units connected in parallel, each PMOS device unit being arranged around the first load 320, with the center of each PMOS device unit coinciding with the center of the first load 320.

[0086] like Figure 8 Specifically, in this embodiment, the number of voltage offset units is 2 to 5.

[0087] Voltage divider circuit 100 divides the first floating voltage VDD_1 to generate a second floating voltage VDD_2.

[0088] Each voltage offset unit has a voltage input terminal, a voltage output terminal, and a power supply terminal. The power supply terminal of each voltage offset unit is used to connect to the first floating voltage VDD_1. The voltage input terminal of the first-stage voltage offset unit 610 in the multi-stage voltage offset unit receives the second floating voltage VDD_2, and the voltage output terminal of the last-stage voltage offset unit 620 outputs the third floating voltage VDD_3.

[0089] and Figure 4 , Figure 6 Compared to the circuit shown, Figure 7 , Figure 8 The circuit shown can also obtain a third floating voltage that varies little with the process and the first floating voltage VDD_1 and is positively correlated with temperature changes simply by adjusting the voltage division ratio of the voltage divider circuit.

[0090] In summary, the voltage conversion circuit of this application can resolve the contradiction between the switching logic and withstand voltage value of the digital circuit section when the power supply voltage fluctuation range is too large. Furthermore, it can operate in the subthreshold region and has the advantages of simple structure, low power consumption, and low process sensitivity. This application can also flexibly match the driving voltage requirements of different scenarios by adjusting the width-to-length ratio of each MOSFET and the number of voltage offset units.

[0091] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A voltage conversion circuit, characterized in that, The voltage conversion circuit includes a voltage divider circuit and a voltage offset circuit connected to the voltage divider circuit. The voltage divider circuit divides a first floating voltage to generate a second floating voltage, and the voltage offset circuit offsets the second floating voltage to generate a third floating voltage. The voltage offset circuit includes at least one voltage offset unit, which includes a current source, a first branch, and a second branch. The current source generates a constant current. A portion of the constant current flows through the first branch to form a first branch current, and another portion of the constant current flows through the second branch to form a second branch current. The first branch includes a first field-effect transistor and a first load connected in series. The second branch includes a second field-effect transistor and a second load connected in series. The sources of the first field-effect transistor and the second field-effect transistor are connected together. The conductive channels of the field-effect transistors have different aspect ratios to form a current difference between the first branch current and the second branch current. The gate of the first field-effect transistor is connected to the second floating voltage, and the gate of the second field-effect transistor is connected to the third floating voltage. The first and second field-effect transistors are PMOS transistors, and the first and second loads are NMOS transistors. The second field-effect transistor includes multiple PMOS device units connected in parallel, each PMOS device unit is arranged around the first field-effect transistor, and the center of each PMOS device unit coincides with the center of the first field-effect transistor. The first load includes multiple NMOS device units connected in parallel, each NMOS device unit is arranged around the second load, and the center of each NMOS device unit coincides with the center of the second load.

2. The voltage conversion circuit according to claim 1, characterized in that, The width-to-length ratio of the conductive channel of the second field-effect transistor is q times the width-to-length ratio of the conductive channel of the first field-effect transistor, where 1.5 ≤ q ≤ 30.

3. The voltage conversion circuit according to claim 2, characterized in that, The impedance of the second load is k times the impedance of the first load, where 1.5 ≤ k ≤ 30.

4. The voltage conversion circuit according to claim 3, characterized in that, The aspect ratio of the conductive channel of the first load is k times that of the conductive channel of the second load, where 1.5 ≤ k ≤ 30.

5. The voltage conversion circuit according to any one of claims 1 to 4, characterized in that, The sources of the first field-effect transistor and the second field-effect transistor are connected to the current source; the gate and drain of the second field-effect transistor are connected; the gates of the first load and the second load are connected to the drain of the first field-effect transistor.

6. A voltage conversion circuit, characterized in that, The voltage conversion circuit includes a voltage divider circuit and a voltage offset circuit connected to the voltage divider circuit. The voltage divider circuit divides a first floating voltage to generate a second floating voltage, and the voltage offset circuit offsets the second floating voltage to generate a third floating voltage. The voltage offset circuit includes at least one voltage offset unit, which includes a current source, a first branch, and a second branch. The current source generates a constant current. A portion of the constant current flows through the first branch to form a first branch current, and another portion of the constant current flows through the second branch to form a second branch current. The first branch includes a first field-effect transistor and a first load connected in series. The second branch includes a second field-effect transistor and a second load connected in series. The sources of the first field-effect transistor and the second field-effect transistor are connected together. The conductive channels of the field-effect transistors have different aspect ratios to form a current difference between the first branch current and the second branch current. The gate of the first field-effect transistor is connected to the second floating voltage, and the gate of the second field-effect transistor is connected to the third floating voltage. The first and second field-effect transistors are NMOS transistors, and the first and second loads are PMOS transistors. The first field-effect transistor includes multiple NMOS device units connected in parallel, each NMOS device unit is arranged around the second field-effect transistor, and the center of each NMOS device unit coincides with the center of the second field-effect transistor. The second load includes multiple PMOS device units connected in parallel, each PMOS device unit is arranged around the first load, and the center of each PMOS device unit coincides with the center of the first load.

7. The voltage conversion circuit according to claim 6, characterized in that, The width-to-length ratio of the conductive channel of the first field-effect transistor is q times the width-to-length ratio of the conductive channel of the second field-effect transistor, where 1.5 ≤ q ≤ 30.

8. The voltage conversion circuit according to claim 7, characterized in that, The impedance of the first load is k times the impedance of the second load, where 1.5 ≤ k ≤ 30.

9. The voltage conversion circuit according to claim 8, characterized in that, The aspect ratio of the conductive channel of the second load is k times that of the conductive channel of the first load, where 1.5 ≤ k ≤ 30.

10. The voltage conversion circuit according to any one of claims 6 to 9, characterized in that, The sources of the first field-effect transistor and the second field-effect transistor are connected to the current source; the gate and drain of the second field-effect transistor are connected; the gates of the first load and the second load are connected to the drain of the first field-effect transistor.

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